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lxdream.org :: lxdream/src/sh4/timer.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/timer.c
changeset 30:89b30313d757
prev23:1ec3acd0594d
next53:f2981805b929
author nkeynes
date Sun Dec 25 05:57:00 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Change timeslice to nanoseconds (was microseconds)
Generize single step (now steps through active CPU)
Add lots of header blocks
file annotate diff log raw
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/**
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 * $Id: timer.c,v 1.2 2005-12-25 05:57:00 nkeynes Exp $
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 * 
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 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
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 * keep things simple (they intertwine a bit).
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include "dream.h"
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#include "mem.h"
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#include "clock.h"
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#include "sh4core.h"
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#include "sh4mmio.h"
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/********************************* CPG *************************************/
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int32_t mmio_region_CPG_read( uint32_t reg )
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{
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    return MMIO_READ( CPG, reg );
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}
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void mmio_region_CPG_write( uint32_t reg, uint32_t val )
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{
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    MMIO_WRITE( CPG, reg, val );
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}
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/********************************** RTC *************************************/
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int32_t mmio_region_RTC_read( uint32_t reg )
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{
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    return MMIO_READ( RTC, reg );
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}
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void mmio_region_RTC_write( uint32_t reg, uint32_t val )
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{
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    MMIO_WRITE( RTC, reg, val );
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}
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/********************************** TMU *************************************/
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int timer_divider[3] = {16,16,16};
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int32_t mmio_region_TMU_read( uint32_t reg )
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{
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    return MMIO_READ( TMU, reg );
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}
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int get_timer_div( int val )
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{
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    switch( val & 0x07 ) {
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        case 0: return 16; /* assume peripheral clock is IC/4 */
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        case 1: return 64;
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        case 2: return 256;
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        case 3: return 1024;
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        case 4: return 4096;
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    }
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    return 1;
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}
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void mmio_region_TMU_write( uint32_t reg, uint32_t val )
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{
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    switch( reg ) {
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        case TCR0:
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            timer_divider[0] = get_timer_div(val);
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            break;
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        case TCR1:
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            timer_divider[1] = get_timer_div(val);
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            break;
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        case TCR2:
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            timer_divider[2] = get_timer_div(val);
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            break;
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    }
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    MMIO_WRITE( TMU, reg, val );
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}
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void TMU_run_slice( uint32_t nanosecs )
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{
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    int tcr = MMIO_READ( TMU, TSTR );
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    int cycles = nanosecs / sh4_peripheral_period;
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    if( tcr & 0x01 ) {
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        int count = cycles / timer_divider[0];
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        int *val = MMIO_REG( TMU, TCNT0 );
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        if( *val < count ) {
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            MMIO_READ( TMU, TCR0 ) |= 0x100;
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            /* interrupt goes here */
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            count -= *val;
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            *val = MMIO_READ( TMU, TCOR0 ) - count;
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        } else {
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            *val -= count;
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        }
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    }
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    if( tcr & 0x02 ) {
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        int count = cycles / timer_divider[1];
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        int *val = MMIO_REG( TMU, TCNT1 );
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        if( *val < count ) {
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            MMIO_READ( TMU, TCR1 ) |= 0x100;
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            /* interrupt goes here */
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            count -= *val;
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            *val = MMIO_READ( TMU, TCOR1 ) - count;
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        } else {
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            *val -= count;
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        }
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    }
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    if( tcr & 0x04 ) {
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        int count = cycles / timer_divider[2];
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        int *val = MMIO_REG( TMU, TCNT2 );
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        if( *val < count ) {
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            MMIO_READ( TMU, TCR2 ) |= 0x100;
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            /* interrupt goes here */
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            count -= *val;
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            *val = MMIO_READ( TMU, TCOR2 ) - count;
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        } else {
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            *val -= count;
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        }
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    }
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}
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