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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 374:8f80a795513e
prev368:36fac4c42322
next375:4627600f7f8e
author nkeynes
date Tue Sep 11 02:14:46 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Cache the pointer to the last FR bank (speeds fp ops up by about 10%)
Implement experimental fix for FLOAT/FTRC
Make read/write sr functions non-static (share with translator)
Much more translator WIP
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.4 2007-09-11 02:14:46 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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#ifndef NDEBUG
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#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(x,n)
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#define CHECK_JMP(x)
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#endif
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_spreg( int x86reg, int regoffset )
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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static inline void load_xf_bank( int bankreg )
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{
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    load_spreg( bankreg, R_FPSCR );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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static inline void push_dr( int bankreg, int frm )
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{
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    if( frm&1 ) { 
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	// this is technically undefined, but it seems to work consistently - high 32 bits
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	// loaded from FRm (32-bits), low 32bits are 0.
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	OP(0xFF); OP(0x70 + bankreg); OP((frm^1)<<2); // PUSH [bankreg + frm^1]
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	PUSH_imm32(0);
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    } else {
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	OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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    }
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    if( frm&1 ) {
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    } else {
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	OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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    }
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() 
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{
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    PUSH_r32(R_EBP);
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    PUSH_r32(R_EDI);
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    PUSH_r32(R_ESI);
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    sh4_x86.in_delay_slot = FALSE;
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    sh4_x86.priv_checked = FALSE;
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    sh4_x86.fpuen_checked = FALSE;
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    sh4_x86.backpatch_posn = 0;
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}
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/**
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 * Exit the block early (ie branch out), conditionally or otherwise
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 */
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void exit_block( )
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{
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    store_spreg( R_EDI, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    MUL_r32( R_ESI );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    XOR_r32_r32( R_EAX, R_EAX );
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    POP_r32(R_ESI);
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    POP_r32(R_EDI);
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    POP_r32(R_EBP);
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    RET();
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}
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/**
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 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
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 */
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void sh4_translate_end_block( sh4addr_t pc ) {
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    assert( !sh4_x86.in_delay_slot ); // should never stop here
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    // Normal termination - save PC, cycle count
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    exit_block( );
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    uint8_t *end_ptr = xlat_output;
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    // Exception termination. Jump block for various exception codes:
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    PUSH_imm32( EXC_DATA_ADDR_READ );
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    JMP_rel8( 33 );
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    PUSH_imm32( EXC_DATA_ADDR_WRITE );
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    JMP_rel8( 26 );
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    PUSH_imm32( EXC_ILLEGAL );
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    JMP_rel8( 19 );
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    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
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    JMP_rel8( 12 );
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    PUSH_imm32( EXC_FPU_DISABLED ); 
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    JMP_rel8( 5 );                 
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    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
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    // target
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    load_spreg( R_ECX, REG_OFFSET(pc) );
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    ADD_r32_r32( R_ESI, R_ECX );
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    ADD_r32_r32( R_ESI, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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   347
    MUL_r32( R_ESI );
nkeynes@368
   348
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   349
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   350
nkeynes@368
   351
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   352
    CALL_r32( R_EAX ); // 2
nkeynes@368
   353
    POP_r32(R_EBP);
nkeynes@368
   354
    RET();
nkeynes@368
   355
nkeynes@368
   356
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   357
}
nkeynes@359
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   361
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   362
 * 
nkeynes@359
   363
 *
nkeynes@359
   364
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   365
 * (eg a branch or 
nkeynes@359
   366
 */
nkeynes@359
   367
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   368
{
nkeynes@361
   369
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   370
    
nkeynes@359
   371
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   372
            case 0x0:
nkeynes@359
   373
                switch( ir&0xF ) {
nkeynes@359
   374
                    case 0x2:
nkeynes@359
   375
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   376
                            case 0x0:
nkeynes@359
   377
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   378
                                    case 0x0:
nkeynes@359
   379
                                        { /* STC SR, Rn */
nkeynes@359
   380
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   381
                                        call_func0(sh4_read_sr);
nkeynes@368
   382
                                        store_reg( R_EAX, Rn );
nkeynes@359
   383
                                        }
nkeynes@359
   384
                                        break;
nkeynes@359
   385
                                    case 0x1:
nkeynes@359
   386
                                        { /* STC GBR, Rn */
nkeynes@359
   387
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   388
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   389
                                        store_reg( R_EAX, Rn );
nkeynes@359
   390
                                        }
nkeynes@359
   391
                                        break;
nkeynes@359
   392
                                    case 0x2:
nkeynes@359
   393
                                        { /* STC VBR, Rn */
nkeynes@359
   394
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   395
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   396
                                        store_reg( R_EAX, Rn );
nkeynes@359
   397
                                        }
nkeynes@359
   398
                                        break;
nkeynes@359
   399
                                    case 0x3:
nkeynes@359
   400
                                        { /* STC SSR, Rn */
nkeynes@359
   401
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   402
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   403
                                        store_reg( R_EAX, Rn );
nkeynes@359
   404
                                        }
nkeynes@359
   405
                                        break;
nkeynes@359
   406
                                    case 0x4:
nkeynes@359
   407
                                        { /* STC SPC, Rn */
nkeynes@359
   408
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   409
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   410
                                        store_reg( R_EAX, Rn );
nkeynes@359
   411
                                        }
nkeynes@359
   412
                                        break;
nkeynes@359
   413
                                    default:
nkeynes@359
   414
                                        UNDEF();
nkeynes@359
   415
                                        break;
nkeynes@359
   416
                                }
nkeynes@359
   417
                                break;
nkeynes@359
   418
                            case 0x1:
nkeynes@359
   419
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   420
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
   421
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   422
                                store_reg( R_EAX, Rn );
nkeynes@359
   423
                                }
nkeynes@359
   424
                                break;
nkeynes@359
   425
                        }
nkeynes@359
   426
                        break;
nkeynes@359
   427
                    case 0x3:
nkeynes@359
   428
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   429
                            case 0x0:
nkeynes@359
   430
                                { /* BSRF Rn */
nkeynes@359
   431
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   432
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   433
                            	SLOTILLEGAL();
nkeynes@374
   434
                                } else {
nkeynes@374
   435
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
   436
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
   437
                            	load_reg( R_EDI, Rn );
nkeynes@374
   438
                            	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
   439
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   440
                            	INC_r32(R_ESI);
nkeynes@374
   441
                            	return 0;
nkeynes@374
   442
                                }
nkeynes@359
   443
                                }
nkeynes@359
   444
                                break;
nkeynes@359
   445
                            case 0x2:
nkeynes@359
   446
                                { /* BRAF Rn */
nkeynes@359
   447
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   448
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   449
                            	SLOTILLEGAL();
nkeynes@374
   450
                                } else {
nkeynes@374
   451
                            	load_reg( R_EDI, Rn );
nkeynes@374
   452
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   453
                            	INC_r32(R_ESI);
nkeynes@374
   454
                            	return 0;
nkeynes@374
   455
                                }
nkeynes@359
   456
                                }
nkeynes@359
   457
                                break;
nkeynes@359
   458
                            case 0x8:
nkeynes@359
   459
                                { /* PREF @Rn */
nkeynes@359
   460
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   461
                                load_reg( R_EAX, Rn );
nkeynes@374
   462
                                PUSH_r32( R_EAX );
nkeynes@374
   463
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   464
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@374
   465
                                JNE_rel8(8);
nkeynes@374
   466
                                call_func0( sh4_flush_store_queue );
nkeynes@374
   467
                                ADD_imm8s_r32( -4, R_ESP );
nkeynes@359
   468
                                }
nkeynes@359
   469
                                break;
nkeynes@359
   470
                            case 0x9:
nkeynes@359
   471
                                { /* OCBI @Rn */
nkeynes@359
   472
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   473
                                }
nkeynes@359
   474
                                break;
nkeynes@359
   475
                            case 0xA:
nkeynes@359
   476
                                { /* OCBP @Rn */
nkeynes@359
   477
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   478
                                }
nkeynes@359
   479
                                break;
nkeynes@359
   480
                            case 0xB:
nkeynes@359
   481
                                { /* OCBWB @Rn */
nkeynes@359
   482
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   483
                                }
nkeynes@359
   484
                                break;
nkeynes@359
   485
                            case 0xC:
nkeynes@359
   486
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   487
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   488
                                load_reg( R_EAX, 0 );
nkeynes@361
   489
                                load_reg( R_ECX, Rn );
nkeynes@374
   490
                                check_walign32( R_ECX );
nkeynes@361
   491
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   492
                                }
nkeynes@359
   493
                                break;
nkeynes@359
   494
                            default:
nkeynes@359
   495
                                UNDEF();
nkeynes@359
   496
                                break;
nkeynes@359
   497
                        }
nkeynes@359
   498
                        break;
nkeynes@359
   499
                    case 0x4:
nkeynes@359
   500
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   501
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   502
                        load_reg( R_EAX, 0 );
nkeynes@359
   503
                        load_reg( R_ECX, Rn );
nkeynes@359
   504
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   505
                        load_reg( R_EAX, Rm );
nkeynes@359
   506
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   507
                        }
nkeynes@359
   508
                        break;
nkeynes@359
   509
                    case 0x5:
nkeynes@359
   510
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   511
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   512
                        load_reg( R_EAX, 0 );
nkeynes@361
   513
                        load_reg( R_ECX, Rn );
nkeynes@361
   514
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   515
                        check_walign16( R_ECX );
nkeynes@361
   516
                        load_reg( R_EAX, Rm );
nkeynes@361
   517
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   518
                        }
nkeynes@359
   519
                        break;
nkeynes@359
   520
                    case 0x6:
nkeynes@359
   521
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   522
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   523
                        load_reg( R_EAX, 0 );
nkeynes@361
   524
                        load_reg( R_ECX, Rn );
nkeynes@361
   525
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   526
                        check_walign32( R_ECX );
nkeynes@361
   527
                        load_reg( R_EAX, Rm );
nkeynes@361
   528
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   529
                        }
nkeynes@359
   530
                        break;
nkeynes@359
   531
                    case 0x7:
nkeynes@359
   532
                        { /* MUL.L Rm, Rn */
nkeynes@359
   533
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   534
                        load_reg( R_EAX, Rm );
nkeynes@361
   535
                        load_reg( R_ECX, Rn );
nkeynes@361
   536
                        MUL_r32( R_ECX );
nkeynes@361
   537
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   538
                        }
nkeynes@359
   539
                        break;
nkeynes@359
   540
                    case 0x8:
nkeynes@359
   541
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   542
                            case 0x0:
nkeynes@359
   543
                                { /* CLRT */
nkeynes@374
   544
                                CLC();
nkeynes@374
   545
                                SETC_t();
nkeynes@359
   546
                                }
nkeynes@359
   547
                                break;
nkeynes@359
   548
                            case 0x1:
nkeynes@359
   549
                                { /* SETT */
nkeynes@374
   550
                                STC();
nkeynes@374
   551
                                SETC_t();
nkeynes@359
   552
                                }
nkeynes@359
   553
                                break;
nkeynes@359
   554
                            case 0x2:
nkeynes@359
   555
                                { /* CLRMAC */
nkeynes@374
   556
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   557
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   558
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   559
                                }
nkeynes@359
   560
                                break;
nkeynes@359
   561
                            case 0x3:
nkeynes@359
   562
                                { /* LDTLB */
nkeynes@359
   563
                                }
nkeynes@359
   564
                                break;
nkeynes@359
   565
                            case 0x4:
nkeynes@359
   566
                                { /* CLRS */
nkeynes@374
   567
                                CLC();
nkeynes@374
   568
                                SETC_sh4r(R_S);
nkeynes@359
   569
                                }
nkeynes@359
   570
                                break;
nkeynes@359
   571
                            case 0x5:
nkeynes@359
   572
                                { /* SETS */
nkeynes@374
   573
                                STC();
nkeynes@374
   574
                                SETC_sh4r(R_S);
nkeynes@359
   575
                                }
nkeynes@359
   576
                                break;
nkeynes@359
   577
                            default:
nkeynes@359
   578
                                UNDEF();
nkeynes@359
   579
                                break;
nkeynes@359
   580
                        }
nkeynes@359
   581
                        break;
nkeynes@359
   582
                    case 0x9:
nkeynes@359
   583
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   584
                            case 0x0:
nkeynes@359
   585
                                { /* NOP */
nkeynes@359
   586
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   587
                                }
nkeynes@359
   588
                                break;
nkeynes@359
   589
                            case 0x1:
nkeynes@359
   590
                                { /* DIV0U */
nkeynes@361
   591
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   592
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   593
                                store_spreg( R_EAX, R_M );
nkeynes@361
   594
                                store_spreg( R_EAX, R_T );
nkeynes@359
   595
                                }
nkeynes@359
   596
                                break;
nkeynes@359
   597
                            case 0x2:
nkeynes@359
   598
                                { /* MOVT Rn */
nkeynes@359
   599
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   600
                                load_spreg( R_EAX, R_T );
nkeynes@359
   601
                                store_reg( R_EAX, Rn );
nkeynes@359
   602
                                }
nkeynes@359
   603
                                break;
nkeynes@359
   604
                            default:
nkeynes@359
   605
                                UNDEF();
nkeynes@359
   606
                                break;
nkeynes@359
   607
                        }
nkeynes@359
   608
                        break;
nkeynes@359
   609
                    case 0xA:
nkeynes@359
   610
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   611
                            case 0x0:
nkeynes@359
   612
                                { /* STS MACH, Rn */
nkeynes@359
   613
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   614
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   615
                                store_reg( R_EAX, Rn );
nkeynes@359
   616
                                }
nkeynes@359
   617
                                break;
nkeynes@359
   618
                            case 0x1:
nkeynes@359
   619
                                { /* STS MACL, Rn */
nkeynes@359
   620
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   621
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   622
                                store_reg( R_EAX, Rn );
nkeynes@359
   623
                                }
nkeynes@359
   624
                                break;
nkeynes@359
   625
                            case 0x2:
nkeynes@359
   626
                                { /* STS PR, Rn */
nkeynes@359
   627
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   628
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   629
                                store_reg( R_EAX, Rn );
nkeynes@359
   630
                                }
nkeynes@359
   631
                                break;
nkeynes@359
   632
                            case 0x3:
nkeynes@359
   633
                                { /* STC SGR, Rn */
nkeynes@359
   634
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   635
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   636
                                store_reg( R_EAX, Rn );
nkeynes@359
   637
                                }
nkeynes@359
   638
                                break;
nkeynes@359
   639
                            case 0x5:
nkeynes@359
   640
                                { /* STS FPUL, Rn */
nkeynes@359
   641
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   642
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   643
                                store_reg( R_EAX, Rn );
nkeynes@359
   644
                                }
nkeynes@359
   645
                                break;
nkeynes@359
   646
                            case 0x6:
nkeynes@359
   647
                                { /* STS FPSCR, Rn */
nkeynes@359
   648
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   649
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   650
                                store_reg( R_EAX, Rn );
nkeynes@359
   651
                                }
nkeynes@359
   652
                                break;
nkeynes@359
   653
                            case 0xF:
nkeynes@359
   654
                                { /* STC DBR, Rn */
nkeynes@359
   655
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   656
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   657
                                store_reg( R_EAX, Rn );
nkeynes@359
   658
                                }
nkeynes@359
   659
                                break;
nkeynes@359
   660
                            default:
nkeynes@359
   661
                                UNDEF();
nkeynes@359
   662
                                break;
nkeynes@359
   663
                        }
nkeynes@359
   664
                        break;
nkeynes@359
   665
                    case 0xB:
nkeynes@359
   666
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   667
                            case 0x0:
nkeynes@359
   668
                                { /* RTS */
nkeynes@374
   669
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   670
                            	SLOTILLEGAL();
nkeynes@374
   671
                                } else {
nkeynes@374
   672
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   673
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   674
                            	INC_r32(R_ESI);
nkeynes@374
   675
                            	return 0;
nkeynes@374
   676
                                }
nkeynes@359
   677
                                }
nkeynes@359
   678
                                break;
nkeynes@359
   679
                            case 0x1:
nkeynes@359
   680
                                { /* SLEEP */
nkeynes@374
   681
                                /* TODO */
nkeynes@359
   682
                                }
nkeynes@359
   683
                                break;
nkeynes@359
   684
                            case 0x2:
nkeynes@359
   685
                                { /* RTE */
nkeynes@374
   686
                                check_priv();
nkeynes@374
   687
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   688
                            	SLOTILLEGAL();
nkeynes@374
   689
                                } else {
nkeynes@374
   690
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   691
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   692
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   693
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   694
                            	INC_r32(R_ESI);
nkeynes@374
   695
                            	return 0;
nkeynes@374
   696
                                }
nkeynes@359
   697
                                }
nkeynes@359
   698
                                break;
nkeynes@359
   699
                            default:
nkeynes@359
   700
                                UNDEF();
nkeynes@359
   701
                                break;
nkeynes@359
   702
                        }
nkeynes@359
   703
                        break;
nkeynes@359
   704
                    case 0xC:
nkeynes@359
   705
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   706
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   707
                        load_reg( R_EAX, 0 );
nkeynes@359
   708
                        load_reg( R_ECX, Rm );
nkeynes@359
   709
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   710
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   711
                        store_reg( R_EAX, Rn );
nkeynes@359
   712
                        }
nkeynes@359
   713
                        break;
nkeynes@359
   714
                    case 0xD:
nkeynes@359
   715
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   716
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   717
                        load_reg( R_EAX, 0 );
nkeynes@361
   718
                        load_reg( R_ECX, Rm );
nkeynes@361
   719
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   720
                        check_ralign16( R_ECX );
nkeynes@361
   721
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   722
                        store_reg( R_EAX, Rn );
nkeynes@359
   723
                        }
nkeynes@359
   724
                        break;
nkeynes@359
   725
                    case 0xE:
nkeynes@359
   726
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   727
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   728
                        load_reg( R_EAX, 0 );
nkeynes@361
   729
                        load_reg( R_ECX, Rm );
nkeynes@361
   730
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   731
                        check_ralign32( R_ECX );
nkeynes@361
   732
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   733
                        store_reg( R_EAX, Rn );
nkeynes@359
   734
                        }
nkeynes@359
   735
                        break;
nkeynes@359
   736
                    case 0xF:
nkeynes@359
   737
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   738
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   739
                        }
nkeynes@359
   740
                        break;
nkeynes@359
   741
                    default:
nkeynes@359
   742
                        UNDEF();
nkeynes@359
   743
                        break;
nkeynes@359
   744
                }
nkeynes@359
   745
                break;
nkeynes@359
   746
            case 0x1:
nkeynes@359
   747
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   748
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   749
                load_reg( R_ECX, Rn );
nkeynes@361
   750
                load_reg( R_EAX, Rm );
nkeynes@361
   751
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   752
                check_walign32( R_ECX );
nkeynes@361
   753
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   754
                }
nkeynes@359
   755
                break;
nkeynes@359
   756
            case 0x2:
nkeynes@359
   757
                switch( ir&0xF ) {
nkeynes@359
   758
                    case 0x0:
nkeynes@359
   759
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   760
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   761
                        load_reg( R_EAX, Rm );
nkeynes@359
   762
                        load_reg( R_ECX, Rn );
nkeynes@359
   763
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   764
                        }
nkeynes@359
   765
                        break;
nkeynes@359
   766
                    case 0x1:
nkeynes@359
   767
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   768
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   769
                        load_reg( R_ECX, Rn );
nkeynes@374
   770
                        check_walign16( R_ECX );
nkeynes@361
   771
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   772
                        store_reg( R_EAX, Rn );
nkeynes@359
   773
                        }
nkeynes@359
   774
                        break;
nkeynes@359
   775
                    case 0x2:
nkeynes@359
   776
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   777
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   778
                        load_reg( R_EAX, Rm );
nkeynes@361
   779
                        load_reg( R_ECX, Rn );
nkeynes@374
   780
                        check_walign32(R_ECX);
nkeynes@361
   781
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   782
                        }
nkeynes@359
   783
                        break;
nkeynes@359
   784
                    case 0x4:
nkeynes@359
   785
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   786
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   787
                        load_reg( R_EAX, Rm );
nkeynes@359
   788
                        load_reg( R_ECX, Rn );
nkeynes@359
   789
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   790
                        store_reg( R_ECX, Rn );
nkeynes@359
   791
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   792
                        }
nkeynes@359
   793
                        break;
nkeynes@359
   794
                    case 0x5:
nkeynes@359
   795
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   796
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   797
                        load_reg( R_ECX, Rn );
nkeynes@374
   798
                        check_walign16( R_ECX );
nkeynes@361
   799
                        load_reg( R_EAX, Rm );
nkeynes@361
   800
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   801
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   802
                        }
nkeynes@359
   803
                        break;
nkeynes@359
   804
                    case 0x6:
nkeynes@359
   805
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   806
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   807
                        load_reg( R_EAX, Rm );
nkeynes@361
   808
                        load_reg( R_ECX, Rn );
nkeynes@374
   809
                        check_walign32( R_ECX );
nkeynes@361
   810
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   811
                        store_reg( R_ECX, Rn );
nkeynes@361
   812
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   813
                        }
nkeynes@359
   814
                        break;
nkeynes@359
   815
                    case 0x7:
nkeynes@359
   816
                        { /* DIV0S Rm, Rn */
nkeynes@359
   817
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   818
                        load_reg( R_EAX, Rm );
nkeynes@361
   819
                        load_reg( R_ECX, Rm );
nkeynes@361
   820
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   821
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   822
                        store_spreg( R_EAX, R_M );
nkeynes@361
   823
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   824
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   825
                        SETE_t();
nkeynes@359
   826
                        }
nkeynes@359
   827
                        break;
nkeynes@359
   828
                    case 0x8:
nkeynes@359
   829
                        { /* TST Rm, Rn */
nkeynes@359
   830
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   831
                        load_reg( R_EAX, Rm );
nkeynes@361
   832
                        load_reg( R_ECX, Rn );
nkeynes@361
   833
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   834
                        SETE_t();
nkeynes@359
   835
                        }
nkeynes@359
   836
                        break;
nkeynes@359
   837
                    case 0x9:
nkeynes@359
   838
                        { /* AND Rm, Rn */
nkeynes@359
   839
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   840
                        load_reg( R_EAX, Rm );
nkeynes@359
   841
                        load_reg( R_ECX, Rn );
nkeynes@359
   842
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   843
                        store_reg( R_ECX, Rn );
nkeynes@359
   844
                        }
nkeynes@359
   845
                        break;
nkeynes@359
   846
                    case 0xA:
nkeynes@359
   847
                        { /* XOR Rm, Rn */
nkeynes@359
   848
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   849
                        load_reg( R_EAX, Rm );
nkeynes@359
   850
                        load_reg( R_ECX, Rn );
nkeynes@359
   851
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   852
                        store_reg( R_ECX, Rn );
nkeynes@359
   853
                        }
nkeynes@359
   854
                        break;
nkeynes@359
   855
                    case 0xB:
nkeynes@359
   856
                        { /* OR Rm, Rn */
nkeynes@359
   857
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   858
                        load_reg( R_EAX, Rm );
nkeynes@359
   859
                        load_reg( R_ECX, Rn );
nkeynes@359
   860
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   861
                        store_reg( R_ECX, Rn );
nkeynes@359
   862
                        }
nkeynes@359
   863
                        break;
nkeynes@359
   864
                    case 0xC:
nkeynes@359
   865
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   866
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   867
                        load_reg( R_EAX, Rm );
nkeynes@368
   868
                        load_reg( R_ECX, Rn );
nkeynes@368
   869
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   870
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   871
                        JE_rel8(13);
nkeynes@368
   872
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   873
                        JE_rel8(9);
nkeynes@368
   874
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   875
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   876
                        JE_rel8(2);
nkeynes@368
   877
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   878
                        SETE_t();
nkeynes@359
   879
                        }
nkeynes@359
   880
                        break;
nkeynes@359
   881
                    case 0xD:
nkeynes@359
   882
                        { /* XTRCT Rm, Rn */
nkeynes@359
   883
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   884
                        load_reg( R_EAX, Rm );
nkeynes@361
   885
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   886
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   887
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   888
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   889
                        store_reg( R_ECX, Rn );
nkeynes@359
   890
                        }
nkeynes@359
   891
                        break;
nkeynes@359
   892
                    case 0xE:
nkeynes@359
   893
                        { /* MULU.W Rm, Rn */
nkeynes@359
   894
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   895
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   896
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   897
                        MUL_r32( R_ECX );
nkeynes@374
   898
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   899
                        }
nkeynes@359
   900
                        break;
nkeynes@359
   901
                    case 0xF:
nkeynes@359
   902
                        { /* MULS.W Rm, Rn */
nkeynes@359
   903
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   904
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   905
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   906
                        MUL_r32( R_ECX );
nkeynes@374
   907
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   908
                        }
nkeynes@359
   909
                        break;
nkeynes@359
   910
                    default:
nkeynes@359
   911
                        UNDEF();
nkeynes@359
   912
                        break;
nkeynes@359
   913
                }
nkeynes@359
   914
                break;
nkeynes@359
   915
            case 0x3:
nkeynes@359
   916
                switch( ir&0xF ) {
nkeynes@359
   917
                    case 0x0:
nkeynes@359
   918
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   919
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   920
                        load_reg( R_EAX, Rm );
nkeynes@359
   921
                        load_reg( R_ECX, Rn );
nkeynes@359
   922
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   923
                        SETE_t();
nkeynes@359
   924
                        }
nkeynes@359
   925
                        break;
nkeynes@359
   926
                    case 0x2:
nkeynes@359
   927
                        { /* CMP/HS Rm, Rn */
nkeynes@359
   928
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   929
                        load_reg( R_EAX, Rm );
nkeynes@359
   930
                        load_reg( R_ECX, Rn );
nkeynes@359
   931
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   932
                        SETAE_t();
nkeynes@359
   933
                        }
nkeynes@359
   934
                        break;
nkeynes@359
   935
                    case 0x3:
nkeynes@359
   936
                        { /* CMP/GE Rm, Rn */
nkeynes@359
   937
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   938
                        load_reg( R_EAX, Rm );
nkeynes@359
   939
                        load_reg( R_ECX, Rn );
nkeynes@359
   940
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   941
                        SETGE_t();
nkeynes@359
   942
                        }
nkeynes@359
   943
                        break;
nkeynes@359
   944
                    case 0x4:
nkeynes@359
   945
                        { /* DIV1 Rm, Rn */
nkeynes@359
   946
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   947
                        load_reg( R_ECX, Rn );
nkeynes@374
   948
                        LDC_t();
nkeynes@374
   949
                        RCL1_r32( R_ECX ); // OP2
nkeynes@374
   950
                        SETC_r32( R_EDX ); // Q
nkeynes@374
   951
                        load_spreg( R_EAX, R_Q );
nkeynes@374
   952
                        CMP_sh4r_r32( R_M, R_EAX );
nkeynes@374
   953
                        JE_rel8(8);
nkeynes@374
   954
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   955
                        JMP_rel8(3);
nkeynes@374
   956
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   957
                        // TODO
nkeynes@359
   958
                        }
nkeynes@359
   959
                        break;
nkeynes@359
   960
                    case 0x5:
nkeynes@359
   961
                        { /* DMULU.L Rm, Rn */
nkeynes@359
   962
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   963
                        load_reg( R_EAX, Rm );
nkeynes@361
   964
                        load_reg( R_ECX, Rn );
nkeynes@361
   965
                        MUL_r32(R_ECX);
nkeynes@361
   966
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
   967
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   968
                        }
nkeynes@359
   969
                        break;
nkeynes@359
   970
                    case 0x6:
nkeynes@359
   971
                        { /* CMP/HI Rm, Rn */
nkeynes@359
   972
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   973
                        load_reg( R_EAX, Rm );
nkeynes@359
   974
                        load_reg( R_ECX, Rn );
nkeynes@359
   975
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   976
                        SETA_t();
nkeynes@359
   977
                        }
nkeynes@359
   978
                        break;
nkeynes@359
   979
                    case 0x7:
nkeynes@359
   980
                        { /* CMP/GT Rm, Rn */
nkeynes@359
   981
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   982
                        load_reg( R_EAX, Rm );
nkeynes@359
   983
                        load_reg( R_ECX, Rn );
nkeynes@359
   984
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   985
                        SETG_t();
nkeynes@359
   986
                        }
nkeynes@359
   987
                        break;
nkeynes@359
   988
                    case 0x8:
nkeynes@359
   989
                        { /* SUB Rm, Rn */
nkeynes@359
   990
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   991
                        load_reg( R_EAX, Rm );
nkeynes@359
   992
                        load_reg( R_ECX, Rn );
nkeynes@359
   993
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
                        store_reg( R_ECX, Rn );
nkeynes@359
   995
                        }
nkeynes@359
   996
                        break;
nkeynes@359
   997
                    case 0xA:
nkeynes@359
   998
                        { /* SUBC Rm, Rn */
nkeynes@359
   999
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1000
                        load_reg( R_EAX, Rm );
nkeynes@359
  1001
                        load_reg( R_ECX, Rn );
nkeynes@359
  1002
                        LDC_t();
nkeynes@359
  1003
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
                        store_reg( R_ECX, Rn );
nkeynes@359
  1005
                        }
nkeynes@359
  1006
                        break;
nkeynes@359
  1007
                    case 0xB:
nkeynes@359
  1008
                        { /* SUBV Rm, Rn */
nkeynes@359
  1009
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1010
                        load_reg( R_EAX, Rm );
nkeynes@359
  1011
                        load_reg( R_ECX, Rn );
nkeynes@359
  1012
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1013
                        store_reg( R_ECX, Rn );
nkeynes@359
  1014
                        SETO_t();
nkeynes@359
  1015
                        }
nkeynes@359
  1016
                        break;
nkeynes@359
  1017
                    case 0xC:
nkeynes@359
  1018
                        { /* ADD Rm, Rn */
nkeynes@359
  1019
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1020
                        load_reg( R_EAX, Rm );
nkeynes@359
  1021
                        load_reg( R_ECX, Rn );
nkeynes@359
  1022
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1023
                        store_reg( R_ECX, Rn );
nkeynes@359
  1024
                        }
nkeynes@359
  1025
                        break;
nkeynes@359
  1026
                    case 0xD:
nkeynes@359
  1027
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1028
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1029
                        load_reg( R_EAX, Rm );
nkeynes@361
  1030
                        load_reg( R_ECX, Rn );
nkeynes@361
  1031
                        IMUL_r32(R_ECX);
nkeynes@361
  1032
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1033
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1034
                        }
nkeynes@359
  1035
                        break;
nkeynes@359
  1036
                    case 0xE:
nkeynes@359
  1037
                        { /* ADDC Rm, Rn */
nkeynes@359
  1038
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1039
                        load_reg( R_EAX, Rm );
nkeynes@359
  1040
                        load_reg( R_ECX, Rn );
nkeynes@359
  1041
                        LDC_t();
nkeynes@359
  1042
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1043
                        store_reg( R_ECX, Rn );
nkeynes@359
  1044
                        SETC_t();
nkeynes@359
  1045
                        }
nkeynes@359
  1046
                        break;
nkeynes@359
  1047
                    case 0xF:
nkeynes@359
  1048
                        { /* ADDV Rm, Rn */
nkeynes@359
  1049
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1050
                        load_reg( R_EAX, Rm );
nkeynes@359
  1051
                        load_reg( R_ECX, Rn );
nkeynes@359
  1052
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1053
                        store_reg( R_ECX, Rn );
nkeynes@359
  1054
                        SETO_t();
nkeynes@359
  1055
                        }
nkeynes@359
  1056
                        break;
nkeynes@359
  1057
                    default:
nkeynes@359
  1058
                        UNDEF();
nkeynes@359
  1059
                        break;
nkeynes@359
  1060
                }
nkeynes@359
  1061
                break;
nkeynes@359
  1062
            case 0x4:
nkeynes@359
  1063
                switch( ir&0xF ) {
nkeynes@359
  1064
                    case 0x0:
nkeynes@359
  1065
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1066
                            case 0x0:
nkeynes@359
  1067
                                { /* SHLL Rn */
nkeynes@359
  1068
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1069
                                load_reg( R_EAX, Rn );
nkeynes@359
  1070
                                SHL1_r32( R_EAX );
nkeynes@359
  1071
                                store_reg( R_EAX, Rn );
nkeynes@359
  1072
                                }
nkeynes@359
  1073
                                break;
nkeynes@359
  1074
                            case 0x1:
nkeynes@359
  1075
                                { /* DT Rn */
nkeynes@359
  1076
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1077
                                load_reg( R_EAX, Rn );
nkeynes@359
  1078
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
  1079
                                store_reg( R_EAX, Rn );
nkeynes@359
  1080
                                SETE_t();
nkeynes@359
  1081
                                }
nkeynes@359
  1082
                                break;
nkeynes@359
  1083
                            case 0x2:
nkeynes@359
  1084
                                { /* SHAL Rn */
nkeynes@359
  1085
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1086
                                load_reg( R_EAX, Rn );
nkeynes@359
  1087
                                SHL1_r32( R_EAX );
nkeynes@359
  1088
                                store_reg( R_EAX, Rn );
nkeynes@359
  1089
                                }
nkeynes@359
  1090
                                break;
nkeynes@359
  1091
                            default:
nkeynes@359
  1092
                                UNDEF();
nkeynes@359
  1093
                                break;
nkeynes@359
  1094
                        }
nkeynes@359
  1095
                        break;
nkeynes@359
  1096
                    case 0x1:
nkeynes@359
  1097
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1098
                            case 0x0:
nkeynes@359
  1099
                                { /* SHLR Rn */
nkeynes@359
  1100
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1101
                                load_reg( R_EAX, Rn );
nkeynes@359
  1102
                                SHR1_r32( R_EAX );
nkeynes@359
  1103
                                store_reg( R_EAX, Rn );
nkeynes@359
  1104
                                }
nkeynes@359
  1105
                                break;
nkeynes@359
  1106
                            case 0x1:
nkeynes@359
  1107
                                { /* CMP/PZ Rn */
nkeynes@359
  1108
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1109
                                load_reg( R_EAX, Rn );
nkeynes@359
  1110
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1111
                                SETGE_t();
nkeynes@359
  1112
                                }
nkeynes@359
  1113
                                break;
nkeynes@359
  1114
                            case 0x2:
nkeynes@359
  1115
                                { /* SHAR Rn */
nkeynes@359
  1116
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1117
                                load_reg( R_EAX, Rn );
nkeynes@359
  1118
                                SAR1_r32( R_EAX );
nkeynes@359
  1119
                                store_reg( R_EAX, Rn );
nkeynes@359
  1120
                                }
nkeynes@359
  1121
                                break;
nkeynes@359
  1122
                            default:
nkeynes@359
  1123
                                UNDEF();
nkeynes@359
  1124
                                break;
nkeynes@359
  1125
                        }
nkeynes@359
  1126
                        break;
nkeynes@359
  1127
                    case 0x2:
nkeynes@359
  1128
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1129
                            case 0x0:
nkeynes@359
  1130
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1131
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1132
                                load_reg( R_ECX, Rn );
nkeynes@359
  1133
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1134
                                store_reg( R_ECX, Rn );
nkeynes@359
  1135
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1136
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1137
                                }
nkeynes@359
  1138
                                break;
nkeynes@359
  1139
                            case 0x1:
nkeynes@359
  1140
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1141
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1142
                                load_reg( R_ECX, Rn );
nkeynes@359
  1143
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1144
                                store_reg( R_ECX, Rn );
nkeynes@359
  1145
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1146
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1147
                                }
nkeynes@359
  1148
                                break;
nkeynes@359
  1149
                            case 0x2:
nkeynes@359
  1150
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1151
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1152
                                load_reg( R_ECX, Rn );
nkeynes@359
  1153
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1154
                                store_reg( R_ECX, Rn );
nkeynes@359
  1155
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1156
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1157
                                }
nkeynes@359
  1158
                                break;
nkeynes@359
  1159
                            case 0x3:
nkeynes@359
  1160
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1161
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1162
                                load_reg( R_ECX, Rn );
nkeynes@359
  1163
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1164
                                store_reg( R_ECX, Rn );
nkeynes@359
  1165
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1166
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1167
                                }
nkeynes@359
  1168
                                break;
nkeynes@359
  1169
                            case 0x5:
nkeynes@359
  1170
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1171
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1172
                                load_reg( R_ECX, Rn );
nkeynes@359
  1173
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1174
                                store_reg( R_ECX, Rn );
nkeynes@359
  1175
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1176
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1177
                                }
nkeynes@359
  1178
                                break;
nkeynes@359
  1179
                            case 0x6:
nkeynes@359
  1180
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1181
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1182
                                load_reg( R_ECX, Rn );
nkeynes@359
  1183
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1184
                                store_reg( R_ECX, Rn );
nkeynes@359
  1185
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1186
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1187
                                }
nkeynes@359
  1188
                                break;
nkeynes@359
  1189
                            case 0xF:
nkeynes@359
  1190
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1191
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1192
                                load_reg( R_ECX, Rn );
nkeynes@359
  1193
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1194
                                store_reg( R_ECX, Rn );
nkeynes@359
  1195
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1196
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1197
                                }
nkeynes@359
  1198
                                break;
nkeynes@359
  1199
                            default:
nkeynes@359
  1200
                                UNDEF();
nkeynes@359
  1201
                                break;
nkeynes@359
  1202
                        }
nkeynes@359
  1203
                        break;
nkeynes@359
  1204
                    case 0x3:
nkeynes@359
  1205
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1206
                            case 0x0:
nkeynes@359
  1207
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1208
                                    case 0x0:
nkeynes@359
  1209
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1210
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1211
                                        load_reg( R_ECX, Rn );
nkeynes@374
  1212
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1213
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1214
                                        call_func0( sh4_read_sr );
nkeynes@374
  1215
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1216
                                        }
nkeynes@359
  1217
                                        break;
nkeynes@359
  1218
                                    case 0x1:
nkeynes@359
  1219
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1220
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1221
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1222
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1223
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1224
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1225
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1226
                                        }
nkeynes@359
  1227
                                        break;
nkeynes@359
  1228
                                    case 0x2:
nkeynes@359
  1229
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1230
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1231
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1232
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1233
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1234
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1235
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1236
                                        }
nkeynes@359
  1237
                                        break;
nkeynes@359
  1238
                                    case 0x3:
nkeynes@359
  1239
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1240
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1241
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1242
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1243
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1244
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1245
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1246
                                        }
nkeynes@359
  1247
                                        break;
nkeynes@359
  1248
                                    case 0x4:
nkeynes@359
  1249
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1250
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1251
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1252
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1253
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1254
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1255
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1256
                                        }
nkeynes@359
  1257
                                        break;
nkeynes@359
  1258
                                    default:
nkeynes@359
  1259
                                        UNDEF();
nkeynes@359
  1260
                                        break;
nkeynes@359
  1261
                                }
nkeynes@359
  1262
                                break;
nkeynes@359
  1263
                            case 0x1:
nkeynes@359
  1264
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1265
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1266
                                load_reg( R_ECX, Rn );
nkeynes@374
  1267
                                ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1268
                                store_reg( R_ECX, Rn );
nkeynes@374
  1269
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1270
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1271
                                }
nkeynes@359
  1272
                                break;
nkeynes@359
  1273
                        }
nkeynes@359
  1274
                        break;
nkeynes@359
  1275
                    case 0x4:
nkeynes@359
  1276
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1277
                            case 0x0:
nkeynes@359
  1278
                                { /* ROTL Rn */
nkeynes@359
  1279
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1280
                                load_reg( R_EAX, Rn );
nkeynes@359
  1281
                                ROL1_r32( R_EAX );
nkeynes@359
  1282
                                store_reg( R_EAX, Rn );
nkeynes@359
  1283
                                SETC_t();
nkeynes@359
  1284
                                }
nkeynes@359
  1285
                                break;
nkeynes@359
  1286
                            case 0x2:
nkeynes@359
  1287
                                { /* ROTCL Rn */
nkeynes@359
  1288
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1289
                                load_reg( R_EAX, Rn );
nkeynes@359
  1290
                                LDC_t();
nkeynes@359
  1291
                                RCL1_r32( R_EAX );
nkeynes@359
  1292
                                store_reg( R_EAX, Rn );
nkeynes@359
  1293
                                SETC_t();
nkeynes@359
  1294
                                }
nkeynes@359
  1295
                                break;
nkeynes@359
  1296
                            default:
nkeynes@359
  1297
                                UNDEF();
nkeynes@359
  1298
                                break;
nkeynes@359
  1299
                        }
nkeynes@359
  1300
                        break;
nkeynes@359
  1301
                    case 0x5:
nkeynes@359
  1302
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1303
                            case 0x0:
nkeynes@359
  1304
                                { /* ROTR Rn */
nkeynes@359
  1305
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1306
                                load_reg( R_EAX, Rn );
nkeynes@359
  1307
                                ROR1_r32( R_EAX );
nkeynes@359
  1308
                                store_reg( R_EAX, Rn );
nkeynes@359
  1309
                                SETC_t();
nkeynes@359
  1310
                                }
nkeynes@359
  1311
                                break;
nkeynes@359
  1312
                            case 0x1:
nkeynes@359
  1313
                                { /* CMP/PL Rn */
nkeynes@359
  1314
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1315
                                load_reg( R_EAX, Rn );
nkeynes@359
  1316
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1317
                                SETG_t();
nkeynes@359
  1318
                                }
nkeynes@359
  1319
                                break;
nkeynes@359
  1320
                            case 0x2:
nkeynes@359
  1321
                                { /* ROTCR Rn */
nkeynes@359
  1322
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1323
                                load_reg( R_EAX, Rn );
nkeynes@359
  1324
                                LDC_t();
nkeynes@359
  1325
                                RCR1_r32( R_EAX );
nkeynes@359
  1326
                                store_reg( R_EAX, Rn );
nkeynes@359
  1327
                                SETC_t();
nkeynes@359
  1328
                                }
nkeynes@359
  1329
                                break;
nkeynes@359
  1330
                            default:
nkeynes@359
  1331
                                UNDEF();
nkeynes@359
  1332
                                break;
nkeynes@359
  1333
                        }
nkeynes@359
  1334
                        break;
nkeynes@359
  1335
                    case 0x6:
nkeynes@359
  1336
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1337
                            case 0x0:
nkeynes@359
  1338
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1339
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1340
                                load_reg( R_EAX, Rm );
nkeynes@359
  1341
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1342
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1343
                                store_reg( R_EAX, Rm );
nkeynes@359
  1344
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1345
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1346
                                }
nkeynes@359
  1347
                                break;
nkeynes@359
  1348
                            case 0x1:
nkeynes@359
  1349
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1350
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1351
                                load_reg( R_EAX, Rm );
nkeynes@359
  1352
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1353
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1354
                                store_reg( R_EAX, Rm );
nkeynes@359
  1355
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1356
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1357
                                }
nkeynes@359
  1358
                                break;
nkeynes@359
  1359
                            case 0x2:
nkeynes@359
  1360
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1361
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1362
                                load_reg( R_EAX, Rm );
nkeynes@359
  1363
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1364
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1365
                                store_reg( R_EAX, Rm );
nkeynes@359
  1366
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1367
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1368
                                }
nkeynes@359
  1369
                                break;
nkeynes@359
  1370
                            case 0x3:
nkeynes@359
  1371
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1372
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1373
                                load_reg( R_EAX, Rm );
nkeynes@359
  1374
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1375
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1376
                                store_reg( R_EAX, Rm );
nkeynes@359
  1377
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1378
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1379
                                }
nkeynes@359
  1380
                                break;
nkeynes@359
  1381
                            case 0x5:
nkeynes@359
  1382
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1383
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1384
                                load_reg( R_EAX, Rm );
nkeynes@359
  1385
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1386
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1387
                                store_reg( R_EAX, Rm );
nkeynes@359
  1388
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1389
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1390
                                }
nkeynes@359
  1391
                                break;
nkeynes@359
  1392
                            case 0x6:
nkeynes@359
  1393
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1394
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1395
                                load_reg( R_EAX, Rm );
nkeynes@359
  1396
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1397
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1398
                                store_reg( R_EAX, Rm );
nkeynes@359
  1399
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1400
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1401
                                }
nkeynes@359
  1402
                                break;
nkeynes@359
  1403
                            case 0xF:
nkeynes@359
  1404
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1405
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1406
                                load_reg( R_EAX, Rm );
nkeynes@359
  1407
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1408
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1409
                                store_reg( R_EAX, Rm );
nkeynes@359
  1410
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1411
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1412
                                }
nkeynes@359
  1413
                                break;
nkeynes@359
  1414
                            default:
nkeynes@359
  1415
                                UNDEF();
nkeynes@359
  1416
                                break;
nkeynes@359
  1417
                        }
nkeynes@359
  1418
                        break;
nkeynes@359
  1419
                    case 0x7:
nkeynes@359
  1420
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1421
                            case 0x0:
nkeynes@359
  1422
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1423
                                    case 0x0:
nkeynes@359
  1424
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1425
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1426
                                        load_reg( R_EAX, Rm );
nkeynes@368
  1427
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1428
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1429
                                        store_reg( R_EAX, Rm );
nkeynes@368
  1430
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1431
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@359
  1432
                                        }
nkeynes@359
  1433
                                        break;
nkeynes@359
  1434
                                    case 0x1:
nkeynes@359
  1435
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1436
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1437
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1438
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1439
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1440
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1441
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1442
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1443
                                        }
nkeynes@359
  1444
                                        break;
nkeynes@359
  1445
                                    case 0x2:
nkeynes@359
  1446
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1447
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1448
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1449
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1450
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1451
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1452
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1453
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1454
                                        }
nkeynes@359
  1455
                                        break;
nkeynes@359
  1456
                                    case 0x3:
nkeynes@359
  1457
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1458
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1459
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1460
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1461
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1462
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1463
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1464
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1465
                                        }
nkeynes@359
  1466
                                        break;
nkeynes@359
  1467
                                    case 0x4:
nkeynes@359
  1468
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1469
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1470
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1471
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1472
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1473
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1474
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1475
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1476
                                        }
nkeynes@359
  1477
                                        break;
nkeynes@359
  1478
                                    default:
nkeynes@359
  1479
                                        UNDEF();
nkeynes@359
  1480
                                        break;
nkeynes@359
  1481
                                }
nkeynes@359
  1482
                                break;
nkeynes@359
  1483
                            case 0x1:
nkeynes@359
  1484
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1485
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1486
                                load_reg( R_EAX, Rm );
nkeynes@374
  1487
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1488
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1489
                                store_reg( R_EAX, Rm );
nkeynes@374
  1490
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1491
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1492
                                }
nkeynes@359
  1493
                                break;
nkeynes@359
  1494
                        }
nkeynes@359
  1495
                        break;
nkeynes@359
  1496
                    case 0x8:
nkeynes@359
  1497
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1498
                            case 0x0:
nkeynes@359
  1499
                                { /* SHLL2 Rn */
nkeynes@359
  1500
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1501
                                load_reg( R_EAX, Rn );
nkeynes@359
  1502
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1503
                                store_reg( R_EAX, Rn );
nkeynes@359
  1504
                                }
nkeynes@359
  1505
                                break;
nkeynes@359
  1506
                            case 0x1:
nkeynes@359
  1507
                                { /* SHLL8 Rn */
nkeynes@359
  1508
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1509
                                load_reg( R_EAX, Rn );
nkeynes@359
  1510
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1511
                                store_reg( R_EAX, Rn );
nkeynes@359
  1512
                                }
nkeynes@359
  1513
                                break;
nkeynes@359
  1514
                            case 0x2:
nkeynes@359
  1515
                                { /* SHLL16 Rn */
nkeynes@359
  1516
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1517
                                load_reg( R_EAX, Rn );
nkeynes@359
  1518
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1519
                                store_reg( R_EAX, Rn );
nkeynes@359
  1520
                                }
nkeynes@359
  1521
                                break;
nkeynes@359
  1522
                            default:
nkeynes@359
  1523
                                UNDEF();
nkeynes@359
  1524
                                break;
nkeynes@359
  1525
                        }
nkeynes@359
  1526
                        break;
nkeynes@359
  1527
                    case 0x9:
nkeynes@359
  1528
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1529
                            case 0x0:
nkeynes@359
  1530
                                { /* SHLR2 Rn */
nkeynes@359
  1531
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1532
                                load_reg( R_EAX, Rn );
nkeynes@359
  1533
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1534
                                store_reg( R_EAX, Rn );
nkeynes@359
  1535
                                }
nkeynes@359
  1536
                                break;
nkeynes@359
  1537
                            case 0x1:
nkeynes@359
  1538
                                { /* SHLR8 Rn */
nkeynes@359
  1539
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1540
                                load_reg( R_EAX, Rn );
nkeynes@359
  1541
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1542
                                store_reg( R_EAX, Rn );
nkeynes@359
  1543
                                }
nkeynes@359
  1544
                                break;
nkeynes@359
  1545
                            case 0x2:
nkeynes@359
  1546
                                { /* SHLR16 Rn */
nkeynes@359
  1547
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1548
                                load_reg( R_EAX, Rn );
nkeynes@359
  1549
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1550
                                store_reg( R_EAX, Rn );
nkeynes@359
  1551
                                }
nkeynes@359
  1552
                                break;
nkeynes@359
  1553
                            default:
nkeynes@359
  1554
                                UNDEF();
nkeynes@359
  1555
                                break;
nkeynes@359
  1556
                        }
nkeynes@359
  1557
                        break;
nkeynes@359
  1558
                    case 0xA:
nkeynes@359
  1559
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1560
                            case 0x0:
nkeynes@359
  1561
                                { /* LDS Rm, MACH */
nkeynes@359
  1562
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1563
                                load_reg( R_EAX, Rm );
nkeynes@359
  1564
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1565
                                }
nkeynes@359
  1566
                                break;
nkeynes@359
  1567
                            case 0x1:
nkeynes@359
  1568
                                { /* LDS Rm, MACL */
nkeynes@359
  1569
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1570
                                load_reg( R_EAX, Rm );
nkeynes@359
  1571
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1572
                                }
nkeynes@359
  1573
                                break;
nkeynes@359
  1574
                            case 0x2:
nkeynes@359
  1575
                                { /* LDS Rm, PR */
nkeynes@359
  1576
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1577
                                load_reg( R_EAX, Rm );
nkeynes@359
  1578
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1579
                                }
nkeynes@359
  1580
                                break;
nkeynes@359
  1581
                            case 0x3:
nkeynes@359
  1582
                                { /* LDC Rm, SGR */
nkeynes@359
  1583
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1584
                                load_reg( R_EAX, Rm );
nkeynes@359
  1585
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1586
                                }
nkeynes@359
  1587
                                break;
nkeynes@359
  1588
                            case 0x5:
nkeynes@359
  1589
                                { /* LDS Rm, FPUL */
nkeynes@359
  1590
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1591
                                load_reg( R_EAX, Rm );
nkeynes@359
  1592
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1593
                                }
nkeynes@359
  1594
                                break;
nkeynes@359
  1595
                            case 0x6:
nkeynes@359
  1596
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1597
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1598
                                load_reg( R_EAX, Rm );
nkeynes@359
  1599
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1600
                                }
nkeynes@359
  1601
                                break;
nkeynes@359
  1602
                            case 0xF:
nkeynes@359
  1603
                                { /* LDC Rm, DBR */
nkeynes@359
  1604
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1605
                                load_reg( R_EAX, Rm );
nkeynes@359
  1606
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1607
                                }
nkeynes@359
  1608
                                break;
nkeynes@359
  1609
                            default:
nkeynes@359
  1610
                                UNDEF();
nkeynes@359
  1611
                                break;
nkeynes@359
  1612
                        }
nkeynes@359
  1613
                        break;
nkeynes@359
  1614
                    case 0xB:
nkeynes@359
  1615
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1616
                            case 0x0:
nkeynes@359
  1617
                                { /* JSR @Rn */
nkeynes@359
  1618
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1619
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1620
                            	SLOTILLEGAL();
nkeynes@374
  1621
                                } else {
nkeynes@374
  1622
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1623
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
  1624
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1625
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1626
                            	INC_r32(R_ESI);
nkeynes@374
  1627
                            	return 0;
nkeynes@374
  1628
                                }
nkeynes@359
  1629
                                }
nkeynes@359
  1630
                                break;
nkeynes@359
  1631
                            case 0x1:
nkeynes@359
  1632
                                { /* TAS.B @Rn */
nkeynes@359
  1633
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1634
                                load_reg( R_ECX, Rn );
nkeynes@361
  1635
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1636
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1637
                                SETE_t();
nkeynes@361
  1638
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@361
  1639
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1640
                                }
nkeynes@359
  1641
                                break;
nkeynes@359
  1642
                            case 0x2:
nkeynes@359
  1643
                                { /* JMP @Rn */
nkeynes@359
  1644
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1645
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1646
                            	SLOTILLEGAL();
nkeynes@374
  1647
                                } else {
nkeynes@374
  1648
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1649
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1650
                            	INC_r32(R_ESI);
nkeynes@374
  1651
                            	return 0;
nkeynes@374
  1652
                                }
nkeynes@359
  1653
                                }
nkeynes@359
  1654
                                break;
nkeynes@359
  1655
                            default:
nkeynes@359
  1656
                                UNDEF();
nkeynes@359
  1657
                                break;
nkeynes@359
  1658
                        }
nkeynes@359
  1659
                        break;
nkeynes@359
  1660
                    case 0xC:
nkeynes@359
  1661
                        { /* SHAD Rm, Rn */
nkeynes@359
  1662
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1663
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1664
                        load_reg( R_EAX, Rn );
nkeynes@361
  1665
                        load_reg( R_ECX, Rm );
nkeynes@361
  1666
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@361
  1667
                        JAE_rel8(9);
nkeynes@361
  1668
                                        
nkeynes@361
  1669
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1670
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1671
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@361
  1672
                        JMP_rel8(5);               // 2
nkeynes@361
  1673
                        
nkeynes@361
  1674
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1675
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@361
  1676
                                        
nkeynes@361
  1677
                        store_reg( R_EAX, Rn );
nkeynes@359
  1678
                        }
nkeynes@359
  1679
                        break;
nkeynes@359
  1680
                    case 0xD:
nkeynes@359
  1681
                        { /* SHLD Rm, Rn */
nkeynes@359
  1682
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1683
                        load_reg( R_EAX, Rn );
nkeynes@368
  1684
                        load_reg( R_ECX, Rm );
nkeynes@368
  1685
                    
nkeynes@368
  1686
                        MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
  1687
                        SHL_r32_CL( R_EAX );
nkeynes@368
  1688
                        NEG_r32( R_ECX );
nkeynes@368
  1689
                        SHR_r32_CL( R_EDX );
nkeynes@368
  1690
                        CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
  1691
                        CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
  1692
                        store_reg( R_EAX, Rn );
nkeynes@359
  1693
                        }
nkeynes@359
  1694
                        break;
nkeynes@359
  1695
                    case 0xE:
nkeynes@359
  1696
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1697
                            case 0x0:
nkeynes@359
  1698
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1699
                                    case 0x0:
nkeynes@359
  1700
                                        { /* LDC Rm, SR */
nkeynes@359
  1701
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1702
                                        load_reg( R_EAX, Rm );
nkeynes@374
  1703
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@359
  1704
                                        }
nkeynes@359
  1705
                                        break;
nkeynes@359
  1706
                                    case 0x1:
nkeynes@359
  1707
                                        { /* LDC Rm, GBR */
nkeynes@359
  1708
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1709
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1710
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1711
                                        }
nkeynes@359
  1712
                                        break;
nkeynes@359
  1713
                                    case 0x2:
nkeynes@359
  1714
                                        { /* LDC Rm, VBR */
nkeynes@359
  1715
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1716
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1717
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1718
                                        }
nkeynes@359
  1719
                                        break;
nkeynes@359
  1720
                                    case 0x3:
nkeynes@359
  1721
                                        { /* LDC Rm, SSR */
nkeynes@359
  1722
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1723
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1724
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1725
                                        }
nkeynes@359
  1726
                                        break;
nkeynes@359
  1727
                                    case 0x4:
nkeynes@359
  1728
                                        { /* LDC Rm, SPC */
nkeynes@359
  1729
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1730
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1731
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1732
                                        }
nkeynes@359
  1733
                                        break;
nkeynes@359
  1734
                                    default:
nkeynes@359
  1735
                                        UNDEF();
nkeynes@359
  1736
                                        break;
nkeynes@359
  1737
                                }
nkeynes@359
  1738
                                break;
nkeynes@359
  1739
                            case 0x1:
nkeynes@359
  1740
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1741
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1742
                                load_reg( R_EAX, Rm );
nkeynes@374
  1743
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1744
                                }
nkeynes@359
  1745
                                break;
nkeynes@359
  1746
                        }
nkeynes@359
  1747
                        break;
nkeynes@359
  1748
                    case 0xF:
nkeynes@359
  1749
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1750
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1751
                        }
nkeynes@359
  1752
                        break;
nkeynes@359
  1753
                }
nkeynes@359
  1754
                break;
nkeynes@359
  1755
            case 0x5:
nkeynes@359
  1756
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1757
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1758
                load_reg( R_ECX, Rm );
nkeynes@361
  1759
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1760
                check_ralign32( R_ECX );
nkeynes@361
  1761
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1762
                store_reg( R_EAX, Rn );
nkeynes@359
  1763
                }
nkeynes@359
  1764
                break;
nkeynes@359
  1765
            case 0x6:
nkeynes@359
  1766
                switch( ir&0xF ) {
nkeynes@359
  1767
                    case 0x0:
nkeynes@359
  1768
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1769
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1770
                        load_reg( R_ECX, Rm );
nkeynes@359
  1771
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1772
                        store_reg( R_ECX, Rn );
nkeynes@359
  1773
                        }
nkeynes@359
  1774
                        break;
nkeynes@359
  1775
                    case 0x1:
nkeynes@359
  1776
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1777
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1778
                        load_reg( R_ECX, Rm );
nkeynes@374
  1779
                        check_ralign16( R_ECX );
nkeynes@361
  1780
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1781
                        store_reg( R_EAX, Rn );
nkeynes@359
  1782
                        }
nkeynes@359
  1783
                        break;
nkeynes@359
  1784
                    case 0x2:
nkeynes@359
  1785
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1786
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1787
                        load_reg( R_ECX, Rm );
nkeynes@374
  1788
                        check_ralign32( R_ECX );
nkeynes@361
  1789
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1790
                        store_reg( R_EAX, Rn );
nkeynes@359
  1791
                        }
nkeynes@359
  1792
                        break;
nkeynes@359
  1793
                    case 0x3:
nkeynes@359
  1794
                        { /* MOV Rm, Rn */
nkeynes@359
  1795
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1796
                        load_reg( R_EAX, Rm );
nkeynes@359
  1797
                        store_reg( R_EAX, Rn );
nkeynes@359
  1798
                        }
nkeynes@359
  1799
                        break;
nkeynes@359
  1800
                    case 0x4:
nkeynes@359
  1801
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1802
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1803
                        load_reg( R_ECX, Rm );
nkeynes@359
  1804
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1805
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1806
                        store_reg( R_EAX, Rm );
nkeynes@359
  1807
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1808
                        store_reg( R_EAX, Rn );
nkeynes@359
  1809
                        }
nkeynes@359
  1810
                        break;
nkeynes@359
  1811
                    case 0x5:
nkeynes@359
  1812
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1813
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1814
                        load_reg( R_EAX, Rm );
nkeynes@374
  1815
                        check_ralign16( R_EAX );
nkeynes@361
  1816
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1817
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1818
                        store_reg( R_EAX, Rm );
nkeynes@361
  1819
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1820
                        store_reg( R_EAX, Rn );
nkeynes@359
  1821
                        }
nkeynes@359
  1822
                        break;
nkeynes@359
  1823
                    case 0x6:
nkeynes@359
  1824
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1825
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1826
                        load_reg( R_EAX, Rm );
nkeynes@374
  1827
                        check_ralign32( R_ECX );
nkeynes@361
  1828
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1829
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1830
                        store_reg( R_EAX, Rm );
nkeynes@361
  1831
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1832
                        store_reg( R_EAX, Rn );
nkeynes@359
  1833
                        }
nkeynes@359
  1834
                        break;
nkeynes@359
  1835
                    case 0x7:
nkeynes@359
  1836
                        { /* NOT Rm, Rn */
nkeynes@359
  1837
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1838
                        load_reg( R_EAX, Rm );
nkeynes@359
  1839
                        NOT_r32( R_EAX );
nkeynes@359
  1840
                        store_reg( R_EAX, Rn );
nkeynes@359
  1841
                        }
nkeynes@359
  1842
                        break;
nkeynes@359
  1843
                    case 0x8:
nkeynes@359
  1844
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1845
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1846
                        load_reg( R_EAX, Rm );
nkeynes@359
  1847
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1848
                        store_reg( R_EAX, Rn );
nkeynes@359
  1849
                        }
nkeynes@359
  1850
                        break;
nkeynes@359
  1851
                    case 0x9:
nkeynes@359
  1852
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1853
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1854
                        load_reg( R_EAX, Rm );
nkeynes@359
  1855
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1856
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1857
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1858
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1859
                        store_reg( R_ECX, Rn );
nkeynes@359
  1860
                        }
nkeynes@359
  1861
                        break;
nkeynes@359
  1862
                    case 0xA:
nkeynes@359
  1863
                        { /* NEGC Rm, Rn */
nkeynes@359
  1864
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1865
                        load_reg( R_EAX, Rm );
nkeynes@359
  1866
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1867
                        LDC_t();
nkeynes@359
  1868
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1869
                        store_reg( R_ECX, Rn );
nkeynes@359
  1870
                        SETC_t();
nkeynes@359
  1871
                        }
nkeynes@359
  1872
                        break;
nkeynes@359
  1873
                    case 0xB:
nkeynes@359
  1874
                        { /* NEG Rm, Rn */
nkeynes@359
  1875
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1876
                        load_reg( R_EAX, Rm );
nkeynes@359
  1877
                        NEG_r32( R_EAX );
nkeynes@359
  1878
                        store_reg( R_EAX, Rn );
nkeynes@359
  1879
                        }
nkeynes@359
  1880
                        break;
nkeynes@359
  1881
                    case 0xC:
nkeynes@359
  1882
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1883
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1884
                        load_reg( R_EAX, Rm );
nkeynes@361
  1885
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  1886
                        store_reg( R_EAX, Rn );
nkeynes@359
  1887
                        }
nkeynes@359
  1888
                        break;
nkeynes@359
  1889
                    case 0xD:
nkeynes@359
  1890
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1891
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1892
                        load_reg( R_EAX, Rm );
nkeynes@361
  1893
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1894
                        store_reg( R_EAX, Rn );
nkeynes@359
  1895
                        }
nkeynes@359
  1896
                        break;
nkeynes@359
  1897
                    case 0xE:
nkeynes@359
  1898
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1899
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1900
                        load_reg( R_EAX, Rm );
nkeynes@359
  1901
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1902
                        store_reg( R_EAX, Rn );
nkeynes@359
  1903
                        }
nkeynes@359
  1904
                        break;
nkeynes@359
  1905
                    case 0xF:
nkeynes@359
  1906
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1907
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1908
                        load_reg( R_EAX, Rm );
nkeynes@361
  1909
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1910
                        store_reg( R_EAX, Rn );
nkeynes@359
  1911
                        }
nkeynes@359
  1912
                        break;
nkeynes@359
  1913
                }
nkeynes@359
  1914
                break;
nkeynes@359
  1915
            case 0x7:
nkeynes@359
  1916
                { /* ADD #imm, Rn */
nkeynes@359
  1917
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1918
                load_reg( R_EAX, Rn );
nkeynes@359
  1919
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  1920
                store_reg( R_EAX, Rn );
nkeynes@359
  1921
                }
nkeynes@359
  1922
                break;
nkeynes@359
  1923
            case 0x8:
nkeynes@359
  1924
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1925
                    case 0x0:
nkeynes@359
  1926
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  1927
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1928
                        load_reg( R_EAX, 0 );
nkeynes@359
  1929
                        load_reg( R_ECX, Rn );
nkeynes@359
  1930
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1931
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1932
                        }
nkeynes@359
  1933
                        break;
nkeynes@359
  1934
                    case 0x1:
nkeynes@359
  1935
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  1936
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1937
                        load_reg( R_ECX, Rn );
nkeynes@361
  1938
                        load_reg( R_EAX, 0 );
nkeynes@361
  1939
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1940
                        check_walign16( R_ECX );
nkeynes@361
  1941
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  1942
                        }
nkeynes@359
  1943
                        break;
nkeynes@359
  1944
                    case 0x4:
nkeynes@359
  1945
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  1946
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1947
                        load_reg( R_ECX, Rm );
nkeynes@359
  1948
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1949
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1950
                        store_reg( R_EAX, 0 );
nkeynes@359
  1951
                        }
nkeynes@359
  1952
                        break;
nkeynes@359
  1953
                    case 0x5:
nkeynes@359
  1954
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  1955
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1956
                        load_reg( R_ECX, Rm );
nkeynes@361
  1957
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1958
                        check_ralign16( R_ECX );
nkeynes@361
  1959
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1960
                        store_reg( R_EAX, 0 );
nkeynes@359
  1961
                        }
nkeynes@359
  1962
                        break;
nkeynes@359
  1963
                    case 0x8:
nkeynes@359
  1964
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  1965
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1966
                        load_reg( R_EAX, 0 );
nkeynes@359
  1967
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  1968
                        SETE_t();
nkeynes@359
  1969
                        }
nkeynes@359
  1970
                        break;
nkeynes@359
  1971
                    case 0x9:
nkeynes@359
  1972
                        { /* BT disp */
nkeynes@359
  1973
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  1974
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1975
                    	SLOTILLEGAL();
nkeynes@374
  1976
                        } else {
nkeynes@374
  1977
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1978
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1979
                    	JE_rel8( 5 );
nkeynes@374
  1980
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1981
                    	INC_r32(R_ESI);
nkeynes@374
  1982
                    	return 1;
nkeynes@374
  1983
                        }
nkeynes@359
  1984
                        }
nkeynes@359
  1985
                        break;
nkeynes@359
  1986
                    case 0xB:
nkeynes@359
  1987
                        { /* BF disp */
nkeynes@359
  1988
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  1989
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1990
                    	SLOTILLEGAL();
nkeynes@374
  1991
                        } else {
nkeynes@374
  1992
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1993
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1994
                    	JNE_rel8( 5 );
nkeynes@374
  1995
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1996
                    	INC_r32(R_ESI);
nkeynes@374
  1997
                    	return 1;
nkeynes@374
  1998
                        }
nkeynes@359
  1999
                        }
nkeynes@359
  2000
                        break;
nkeynes@359
  2001
                    case 0xD:
nkeynes@359
  2002
                        { /* BT/S disp */
nkeynes@359
  2003
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2004
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2005
                    	SLOTILLEGAL();
nkeynes@374
  2006
                        } else {
nkeynes@374
  2007
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2008
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2009
                    	JE_rel8( 5 );
nkeynes@374
  2010
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2011
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2012
                    	INC_r32(R_ESI);
nkeynes@374
  2013
                    	return 0;
nkeynes@374
  2014
                        }
nkeynes@359
  2015
                        }
nkeynes@359
  2016
                        break;
nkeynes@359
  2017
                    case 0xF:
nkeynes@359
  2018
                        { /* BF/S disp */
nkeynes@359
  2019
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2020
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2021
                    	SLOTILLEGAL();
nkeynes@374
  2022
                        } else {
nkeynes@374
  2023
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2024
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2025
                    	JNE_rel8( 5 );
nkeynes@374
  2026
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2027
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2028
                    	INC_r32(R_ESI);
nkeynes@374
  2029
                    	return 0;
nkeynes@374
  2030
                        }
nkeynes@359
  2031
                        }
nkeynes@359
  2032
                        break;
nkeynes@359
  2033
                    default:
nkeynes@359
  2034
                        UNDEF();
nkeynes@359
  2035
                        break;
nkeynes@359
  2036
                }
nkeynes@359
  2037
                break;
nkeynes@359
  2038
            case 0x9:
nkeynes@359
  2039
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2040
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2041
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2042
            	SLOTILLEGAL();
nkeynes@374
  2043
                } else {
nkeynes@374
  2044
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2045
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2046
            	store_reg( R_EAX, Rn );
nkeynes@374
  2047
                }
nkeynes@359
  2048
                }
nkeynes@359
  2049
                break;
nkeynes@359
  2050
            case 0xA:
nkeynes@359
  2051
                { /* BRA disp */
nkeynes@359
  2052
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2053
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2054
            	SLOTILLEGAL();
nkeynes@374
  2055
                } else {
nkeynes@374
  2056
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2057
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2058
            	INC_r32(R_ESI);
nkeynes@374
  2059
            	return 0;
nkeynes@374
  2060
                }
nkeynes@359
  2061
                }
nkeynes@359
  2062
                break;
nkeynes@359
  2063
            case 0xB:
nkeynes@359
  2064
                { /* BSR disp */
nkeynes@359
  2065
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2066
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2067
            	SLOTILLEGAL();
nkeynes@374
  2068
                } else {
nkeynes@374
  2069
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2070
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2071
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2072
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2073
            	INC_r32(R_ESI);
nkeynes@374
  2074
            	return 0;
nkeynes@374
  2075
                }
nkeynes@359
  2076
                }
nkeynes@359
  2077
                break;
nkeynes@359
  2078
            case 0xC:
nkeynes@359
  2079
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2080
                    case 0x0:
nkeynes@359
  2081
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2082
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2083
                        load_reg( R_EAX, 0 );
nkeynes@359
  2084
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2085
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2086
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2087
                        }
nkeynes@359
  2088
                        break;
nkeynes@359
  2089
                    case 0x1:
nkeynes@359
  2090
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2091
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2092
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2093
                        load_reg( R_EAX, 0 );
nkeynes@361
  2094
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2095
                        check_walign16( R_ECX );
nkeynes@361
  2096
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2097
                        }
nkeynes@359
  2098
                        break;
nkeynes@359
  2099
                    case 0x2:
nkeynes@359
  2100
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2101
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2102
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2103
                        load_reg( R_EAX, 0 );
nkeynes@361
  2104
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2105
                        check_walign32( R_ECX );
nkeynes@361
  2106
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2107
                        }
nkeynes@359
  2108
                        break;
nkeynes@359
  2109
                    case 0x3:
nkeynes@359
  2110
                        { /* TRAPA #imm */
nkeynes@359
  2111
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2112
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2113
                    	SLOTILLEGAL();
nkeynes@374
  2114
                        } else {
nkeynes@374
  2115
                    	// TODO: Write TRA 
nkeynes@374
  2116
                    	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  2117
                        }
nkeynes@359
  2118
                        }
nkeynes@359
  2119
                        break;
nkeynes@359
  2120
                    case 0x4:
nkeynes@359
  2121
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2122
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2123
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2124
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2125
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2126
                        store_reg( R_EAX, 0 );
nkeynes@359
  2127
                        }
nkeynes@359
  2128
                        break;
nkeynes@359
  2129
                    case 0x5:
nkeynes@359
  2130
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2131
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2132
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2133
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2134
                        check_ralign16( R_ECX );
nkeynes@361
  2135
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2136
                        store_reg( R_EAX, 0 );
nkeynes@359
  2137
                        }
nkeynes@359
  2138
                        break;
nkeynes@359
  2139
                    case 0x6:
nkeynes@359
  2140
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2141
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2142
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2143
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2144
                        check_ralign32( R_ECX );
nkeynes@361
  2145
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2146
                        store_reg( R_EAX, 0 );
nkeynes@359
  2147
                        }
nkeynes@359
  2148
                        break;
nkeynes@359
  2149
                    case 0x7:
nkeynes@359
  2150
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2151
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2152
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2153
                    	SLOTILLEGAL();
nkeynes@374
  2154
                        } else {
nkeynes@374
  2155
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2156
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2157
                        }
nkeynes@359
  2158
                        }
nkeynes@359
  2159
                        break;
nkeynes@359
  2160
                    case 0x8:
nkeynes@359
  2161
                        { /* TST #imm, R0 */
nkeynes@359
  2162
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2163
                        load_reg( R_EAX, 0 );
nkeynes@368
  2164
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2165
                        SETE_t();
nkeynes@359
  2166
                        }
nkeynes@359
  2167
                        break;
nkeynes@359
  2168
                    case 0x9:
nkeynes@359
  2169
                        { /* AND #imm, R0 */
nkeynes@359
  2170
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2171
                        load_reg( R_EAX, 0 );
nkeynes@359
  2172
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2173
                        store_reg( R_EAX, 0 );
nkeynes@359
  2174
                        }
nkeynes@359
  2175
                        break;
nkeynes@359
  2176
                    case 0xA:
nkeynes@359
  2177
                        { /* XOR #imm, R0 */
nkeynes@359
  2178
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2179
                        load_reg( R_EAX, 0 );
nkeynes@359
  2180
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2181
                        store_reg( R_EAX, 0 );
nkeynes@359
  2182
                        }
nkeynes@359
  2183
                        break;
nkeynes@359
  2184
                    case 0xB:
nkeynes@359
  2185
                        { /* OR #imm, R0 */
nkeynes@359
  2186
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2187
                        load_reg( R_EAX, 0 );
nkeynes@359
  2188
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2189
                        store_reg( R_EAX, 0 );
nkeynes@359
  2190
                        }
nkeynes@359
  2191
                        break;
nkeynes@359
  2192
                    case 0xC:
nkeynes@359
  2193
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2194
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2195
                        load_reg( R_EAX, 0);
nkeynes@368
  2196
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2197
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2198
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  2199
                        TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  2200
                        SETE_t();
nkeynes@359
  2201
                        }
nkeynes@359
  2202
                        break;
nkeynes@359
  2203
                    case 0xD:
nkeynes@359
  2204
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2205
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2206
                        load_reg( R_EAX, 0 );
nkeynes@359
  2207
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2208
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2209
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2210
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  2211
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2212
                        }
nkeynes@359
  2213
                        break;
nkeynes@359
  2214
                    case 0xE:
nkeynes@359
  2215
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2216
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2217
                        load_reg( R_EAX, 0 );
nkeynes@359
  2218
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2219
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2220
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2221
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2222
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2223
                        }
nkeynes@359
  2224
                        break;
nkeynes@359
  2225
                    case 0xF:
nkeynes@359
  2226
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2227
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2228
                        load_reg( R_EAX, 0 );
nkeynes@374
  2229
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2230
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2231
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
  2232
                        OR_imm32_r32(imm, R_ECX );
nkeynes@374
  2233
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2234
                        }
nkeynes@359
  2235
                        break;
nkeynes@359
  2236
                }
nkeynes@359
  2237
                break;
nkeynes@359
  2238
            case 0xD:
nkeynes@359
  2239
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2240
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2241
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2242
            	SLOTILLEGAL();
nkeynes@374
  2243
                } else {
nkeynes@374
  2244
            	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2245
            	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2246
            	store_reg( R_EAX, 0 );
nkeynes@374
  2247
                }
nkeynes@359
  2248
                }
nkeynes@359
  2249
                break;
nkeynes@359
  2250
            case 0xE:
nkeynes@359
  2251
                { /* MOV #imm, Rn */
nkeynes@359
  2252
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2253
                load_imm32( R_EAX, imm );
nkeynes@359
  2254
                store_reg( R_EAX, Rn );
nkeynes@359
  2255
                }
nkeynes@359
  2256
                break;
nkeynes@359
  2257
            case 0xF:
nkeynes@359
  2258
                switch( ir&0xF ) {
nkeynes@359
  2259
                    case 0x0:
nkeynes@359
  2260
                        { /* FADD FRm, FRn */
nkeynes@359
  2261
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2262
                        }
nkeynes@359
  2263
                        break;
nkeynes@359
  2264
                    case 0x1:
nkeynes@359
  2265
                        { /* FSUB FRm, FRn */
nkeynes@359
  2266
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2267
                        }
nkeynes@359
  2268
                        break;
nkeynes@359
  2269
                    case 0x2:
nkeynes@359
  2270
                        { /* FMUL FRm, FRn */
nkeynes@359
  2271
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2272
                        }
nkeynes@359
  2273
                        break;
nkeynes@359
  2274
                    case 0x3:
nkeynes@359
  2275
                        { /* FDIV FRm, FRn */
nkeynes@359
  2276
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2277
                        }
nkeynes@359
  2278
                        break;
nkeynes@359
  2279
                    case 0x4:
nkeynes@359
  2280
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2281
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2282
                        }
nkeynes@359
  2283
                        break;
nkeynes@359
  2284
                    case 0x5:
nkeynes@359
  2285
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2286
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2287
                        }
nkeynes@359
  2288
                        break;
nkeynes@359
  2289
                    case 0x6:
nkeynes@359
  2290
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2291
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2292
                        }
nkeynes@359
  2293
                        break;
nkeynes@359
  2294
                    case 0x7:
nkeynes@359
  2295
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@359
  2296
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2297
                        }
nkeynes@359
  2298
                        break;
nkeynes@359
  2299
                    case 0x8:
nkeynes@359
  2300
                        { /* FMOV @Rm, FRn */
nkeynes@359
  2301
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2302
                        }
nkeynes@359
  2303
                        break;
nkeynes@359
  2304
                    case 0x9:
nkeynes@359
  2305
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  2306
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2307
                        }
nkeynes@359
  2308
                        break;
nkeynes@359
  2309
                    case 0xA:
nkeynes@359
  2310
                        { /* FMOV FRm, @Rn */
nkeynes@359
  2311
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2312
                        }
nkeynes@359
  2313
                        break;
nkeynes@359
  2314
                    case 0xB:
nkeynes@359
  2315
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  2316
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2317
                        }
nkeynes@359
  2318
                        break;
nkeynes@359
  2319
                    case 0xC:
nkeynes@359
  2320
                        { /* FMOV FRm, FRn */
nkeynes@359
  2321
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2322
                        }
nkeynes@359
  2323
                        break;
nkeynes@359
  2324
                    case 0xD:
nkeynes@359
  2325
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2326
                            case 0x0:
nkeynes@359
  2327
                                { /* FSTS FPUL, FRn */
nkeynes@359
  2328
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2329
                                }
nkeynes@359
  2330
                                break;
nkeynes@359
  2331
                            case 0x1:
nkeynes@359
  2332
                                { /* FLDS FRm, FPUL */
nkeynes@359
  2333
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2334
                                }
nkeynes@359
  2335
                                break;
nkeynes@359
  2336
                            case 0x2:
nkeynes@359
  2337
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  2338
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2339
                                }
nkeynes@359
  2340
                                break;
nkeynes@359
  2341
                            case 0x3:
nkeynes@359
  2342
                                { /* FTRC FRm, FPUL */
nkeynes@359
  2343
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2344
                                }
nkeynes@359
  2345
                                break;
nkeynes@359
  2346
                            case 0x4:
nkeynes@359
  2347
                                { /* FNEG FRn */
nkeynes@359
  2348
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2349
                                }
nkeynes@359
  2350
                                break;
nkeynes@359
  2351
                            case 0x5:
nkeynes@359
  2352
                                { /* FABS FRn */
nkeynes@359
  2353
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@374
  2354
                                load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  2355
                                load_spreg( R_EDX, REG_OFFSET(fr_bank) );
nkeynes@374
  2356
                                TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@374
  2357
                                JNE_rel8(10);
nkeynes@374
  2358
                                push_fr(R_EDX, FRn); // 3
nkeynes@374
  2359
                                FABS_st0(); // 2
nkeynes@374
  2360
                                pop_fr( R_EDX, FRn); //3
nkeynes@374
  2361
                                JMP_rel8(8); // 2
nkeynes@374
  2362
                                push_dr(R_EDX, FRn);
nkeynes@374
  2363
                                FABS_st0();
nkeynes@374
  2364
                                pop_dr(R_EDX, FRn);
nkeynes@359
  2365
                                }
nkeynes@359
  2366
                                break;
nkeynes@359
  2367
                            case 0x6:
nkeynes@359
  2368
                                { /* FSQRT FRn */
nkeynes@359
  2369
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2370
                                }
nkeynes@359
  2371
                                break;
nkeynes@359
  2372
                            case 0x7:
nkeynes@359
  2373
                                { /* FSRRA FRn */
nkeynes@359
  2374
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2375
                                }
nkeynes@359
  2376
                                break;
nkeynes@359
  2377
                            case 0x8:
nkeynes@359
  2378
                                { /* FLDI0 FRn */
nkeynes@359
  2379
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2380
                                }
nkeynes@359
  2381
                                break;
nkeynes@359
  2382
                            case 0x9:
nkeynes@359
  2383
                                { /* FLDI1 FRn */
nkeynes@359
  2384
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2385
                                }
nkeynes@359
  2386
                                break;
nkeynes@359
  2387
                            case 0xA:
nkeynes@359
  2388
                                { /* FCNVSD FPUL, FRn */
nkeynes@359
  2389
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2390
                                }
nkeynes@359
  2391
                                break;
nkeynes@359
  2392
                            case 0xB:
nkeynes@359
  2393
                                { /* FCNVDS FRm, FPUL */
nkeynes@359
  2394
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2395
                                }
nkeynes@359
  2396
                                break;
nkeynes@359
  2397
                            case 0xE:
nkeynes@359
  2398
                                { /* FIPR FVm, FVn */
nkeynes@359
  2399
                                uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
nkeynes@359
  2400
                                }
nkeynes@359
  2401
                                break;
nkeynes@359
  2402
                            case 0xF:
nkeynes@359
  2403
                                switch( (ir&0x100) >> 8 ) {
nkeynes@359
  2404
                                    case 0x0:
nkeynes@359
  2405
                                        { /* FSCA FPUL, FRn */
nkeynes@359
  2406
                                        uint32_t FRn = ((ir>>9)&0x7)<<1; 
nkeynes@359
  2407
                                        }
nkeynes@359
  2408
                                        break;
nkeynes@359
  2409
                                    case 0x1:
nkeynes@359
  2410
                                        switch( (ir&0x200) >> 9 ) {
nkeynes@359
  2411
                                            case 0x0:
nkeynes@359
  2412
                                                { /* FTRV XMTRX, FVn */
nkeynes@359
  2413
                                                uint32_t FVn = ((ir>>10)&0x3); 
nkeynes@359
  2414
                                                }
nkeynes@359
  2415
                                                break;
nkeynes@359
  2416
                                            case 0x1:
nkeynes@359
  2417
                                                switch( (ir&0xC00) >> 10 ) {
nkeynes@359
  2418
                                                    case 0x0:
nkeynes@359
  2419
                                                        { /* FSCHG */
nkeynes@359
  2420
                                                        }
nkeynes@359
  2421
                                                        break;
nkeynes@359
  2422
                                                    case 0x2:
nkeynes@359
  2423
                                                        { /* FRCHG */
nkeynes@359
  2424
                                                        }
nkeynes@359
  2425
                                                        break;
nkeynes@359
  2426
                                                    case 0x3:
nkeynes@359
  2427
                                                        { /* UNDEF */
nkeynes@374
  2428
                                                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2429
                                                    	RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
nkeynes@374
  2430
                                                        } else {
nkeynes@374
  2431
                                                    	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@374
  2432
                                                        }
nkeynes@374
  2433
                                                        return 1;
nkeynes@359
  2434
                                                        }
nkeynes@359
  2435
                                                        break;
nkeynes@359
  2436
                                                    default:
nkeynes@359
  2437
                                                        UNDEF();
nkeynes@359
  2438
                                                        break;
nkeynes@359
  2439
                                                }
nkeynes@359
  2440
                                                break;
nkeynes@359
  2441
                                        }
nkeynes@359
  2442
                                        break;
nkeynes@359
  2443
                                }
nkeynes@359
  2444
                                break;
nkeynes@359
  2445
                            default:
nkeynes@359
  2446
                                UNDEF();
nkeynes@359
  2447
                                break;
nkeynes@359
  2448
                        }
nkeynes@359
  2449
                        break;
nkeynes@359
  2450
                    case 0xE:
nkeynes@359
  2451
                        { /* FMAC FR0, FRm, FRn */
nkeynes@359
  2452
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2453
                        }
nkeynes@359
  2454
                        break;
nkeynes@359
  2455
                    default:
nkeynes@359
  2456
                        UNDEF();
nkeynes@359
  2457
                        break;
nkeynes@359
  2458
                }
nkeynes@359
  2459
                break;
nkeynes@359
  2460
        }
nkeynes@359
  2461
nkeynes@368
  2462
    INC_r32(R_ESI);
nkeynes@374
  2463
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2464
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2465
	return 1;
nkeynes@374
  2466
    }
nkeynes@359
  2467
    return 0;
nkeynes@359
  2468
}
.