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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 374:8f80a795513e
prev368:36fac4c42322
next375:4627600f7f8e
author nkeynes
date Tue Sep 11 02:14:46 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Cache the pointer to the last FR bank (speeds fp ops up by about 10%)
Implement experimental fix for FLOAT/FTRC
Make read/write sr functions non-static (share with translator)
Much more translator WIP
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.4 2007-09-11 02:14:46 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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#ifndef NDEBUG
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#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(x,n)
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#define CHECK_JMP(x)
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#endif
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_spreg( int x86reg, int regoffset )
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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static inline void load_xf_bank( int bankreg )
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{
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    load_spreg( bankreg, R_FPSCR );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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static inline void push_dr( int bankreg, int frm )
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{
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    if( frm&1 ) { 
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	// this is technically undefined, but it seems to work consistently - high 32 bits
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	// loaded from FRm (32-bits), low 32bits are 0.
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	OP(0xFF); OP(0x70 + bankreg); OP((frm^1)<<2); // PUSH [bankreg + frm^1]
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	PUSH_imm32(0);
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    } else {
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	OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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    }
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    if( frm&1 ) {
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    } else {
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	OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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    }
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() 
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{
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    PUSH_r32(R_EBP);
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    PUSH_r32(R_EDI);
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    PUSH_r32(R_ESI);
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    sh4_x86.in_delay_slot = FALSE;
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    sh4_x86.priv_checked = FALSE;
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    sh4_x86.fpuen_checked = FALSE;
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    sh4_x86.backpatch_posn = 0;
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}
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/**
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 * Exit the block early (ie branch out), conditionally or otherwise
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 */
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void exit_block( )
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{
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    store_spreg( R_EDI, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    MUL_r32( R_ESI );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    XOR_r32_r32( R_EAX, R_EAX );
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    POP_r32(R_ESI);
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    POP_r32(R_EDI);
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    POP_r32(R_EBP);
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    RET();
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}
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/**
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 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
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 */
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void sh4_translate_end_block( sh4addr_t pc ) {
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    assert( !sh4_x86.in_delay_slot ); // should never stop here
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    // Normal termination - save PC, cycle count
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    exit_block( );
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    uint8_t *end_ptr = xlat_output;
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    // Exception termination. Jump block for various exception codes:
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    PUSH_imm32( EXC_DATA_ADDR_READ );
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    JMP_rel8( 33 );
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    PUSH_imm32( EXC_DATA_ADDR_WRITE );
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    JMP_rel8( 26 );
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    PUSH_imm32( EXC_ILLEGAL );
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    JMP_rel8( 19 );
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    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
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    JMP_rel8( 12 );
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    PUSH_imm32( EXC_FPU_DISABLED ); 
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    JMP_rel8( 5 );                 
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    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
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    // target
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    load_spreg( R_ECX, REG_OFFSET(pc) );
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    ADD_r32_r32( R_ESI, R_ECX );
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    ADD_r32_r32( R_ESI, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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   347
    MUL_r32( R_ESI );
nkeynes@368
   348
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   349
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   350
nkeynes@368
   351
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   352
    CALL_r32( R_EAX ); // 2
nkeynes@368
   353
    POP_r32(R_EBP);
nkeynes@368
   354
    RET();
nkeynes@368
   355
nkeynes@368
   356
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   357
}
nkeynes@359
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   361
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   362
 * 
nkeynes@359
   363
 *
nkeynes@359
   364
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   365
 * (eg a branch or 
nkeynes@359
   366
 */
nkeynes@359
   367
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   368
{
nkeynes@361
   369
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   370
    
nkeynes@359
   371
%%
nkeynes@359
   372
/* ALU operations */
nkeynes@359
   373
ADD Rm, Rn {:
nkeynes@359
   374
    load_reg( R_EAX, Rm );
nkeynes@359
   375
    load_reg( R_ECX, Rn );
nkeynes@359
   376
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   377
    store_reg( R_ECX, Rn );
nkeynes@359
   378
:}
nkeynes@359
   379
ADD #imm, Rn {:  
nkeynes@359
   380
    load_reg( R_EAX, Rn );
nkeynes@359
   381
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   382
    store_reg( R_EAX, Rn );
nkeynes@359
   383
:}
nkeynes@359
   384
ADDC Rm, Rn {:
nkeynes@359
   385
    load_reg( R_EAX, Rm );
nkeynes@359
   386
    load_reg( R_ECX, Rn );
nkeynes@359
   387
    LDC_t();
nkeynes@359
   388
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   389
    store_reg( R_ECX, Rn );
nkeynes@359
   390
    SETC_t();
nkeynes@359
   391
:}
nkeynes@359
   392
ADDV Rm, Rn {:
nkeynes@359
   393
    load_reg( R_EAX, Rm );
nkeynes@359
   394
    load_reg( R_ECX, Rn );
nkeynes@359
   395
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   396
    store_reg( R_ECX, Rn );
nkeynes@359
   397
    SETO_t();
nkeynes@359
   398
:}
nkeynes@359
   399
AND Rm, Rn {:
nkeynes@359
   400
    load_reg( R_EAX, Rm );
nkeynes@359
   401
    load_reg( R_ECX, Rn );
nkeynes@359
   402
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   403
    store_reg( R_ECX, Rn );
nkeynes@359
   404
:}
nkeynes@359
   405
AND #imm, R0 {:  
nkeynes@359
   406
    load_reg( R_EAX, 0 );
nkeynes@359
   407
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   408
    store_reg( R_EAX, 0 );
nkeynes@359
   409
:}
nkeynes@359
   410
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   411
    load_reg( R_EAX, 0 );
nkeynes@359
   412
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   413
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   414
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   415
    AND_imm32_r32(imm, R_ECX );
nkeynes@359
   416
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   417
:}
nkeynes@359
   418
CMP/EQ Rm, Rn {:  
nkeynes@359
   419
    load_reg( R_EAX, Rm );
nkeynes@359
   420
    load_reg( R_ECX, Rn );
nkeynes@359
   421
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   422
    SETE_t();
nkeynes@359
   423
:}
nkeynes@359
   424
CMP/EQ #imm, R0 {:  
nkeynes@359
   425
    load_reg( R_EAX, 0 );
nkeynes@359
   426
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   427
    SETE_t();
nkeynes@359
   428
:}
nkeynes@359
   429
CMP/GE Rm, Rn {:  
nkeynes@359
   430
    load_reg( R_EAX, Rm );
nkeynes@359
   431
    load_reg( R_ECX, Rn );
nkeynes@359
   432
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   433
    SETGE_t();
nkeynes@359
   434
:}
nkeynes@359
   435
CMP/GT Rm, Rn {: 
nkeynes@359
   436
    load_reg( R_EAX, Rm );
nkeynes@359
   437
    load_reg( R_ECX, Rn );
nkeynes@359
   438
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   439
    SETG_t();
nkeynes@359
   440
:}
nkeynes@359
   441
CMP/HI Rm, Rn {:  
nkeynes@359
   442
    load_reg( R_EAX, Rm );
nkeynes@359
   443
    load_reg( R_ECX, Rn );
nkeynes@359
   444
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   445
    SETA_t();
nkeynes@359
   446
:}
nkeynes@359
   447
CMP/HS Rm, Rn {: 
nkeynes@359
   448
    load_reg( R_EAX, Rm );
nkeynes@359
   449
    load_reg( R_ECX, Rn );
nkeynes@359
   450
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   451
    SETAE_t();
nkeynes@359
   452
 :}
nkeynes@359
   453
CMP/PL Rn {: 
nkeynes@359
   454
    load_reg( R_EAX, Rn );
nkeynes@359
   455
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   456
    SETG_t();
nkeynes@359
   457
:}
nkeynes@359
   458
CMP/PZ Rn {:  
nkeynes@359
   459
    load_reg( R_EAX, Rn );
nkeynes@359
   460
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   461
    SETGE_t();
nkeynes@359
   462
:}
nkeynes@361
   463
CMP/STR Rm, Rn {:  
nkeynes@368
   464
    load_reg( R_EAX, Rm );
nkeynes@368
   465
    load_reg( R_ECX, Rn );
nkeynes@368
   466
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   467
    TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   468
    JE_rel8(13);
nkeynes@368
   469
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   470
    JE_rel8(9);
nkeynes@368
   471
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   472
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   473
    JE_rel8(2);
nkeynes@368
   474
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   475
    SETE_t();
nkeynes@361
   476
:}
nkeynes@361
   477
DIV0S Rm, Rn {:
nkeynes@361
   478
    load_reg( R_EAX, Rm );
nkeynes@361
   479
    load_reg( R_ECX, Rm );
nkeynes@361
   480
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   481
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   482
    store_spreg( R_EAX, R_M );
nkeynes@361
   483
    store_spreg( R_ECX, R_Q );
nkeynes@361
   484
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   485
    SETE_t();
nkeynes@361
   486
:}
nkeynes@361
   487
DIV0U {:  
nkeynes@361
   488
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   489
    store_spreg( R_EAX, R_Q );
nkeynes@361
   490
    store_spreg( R_EAX, R_M );
nkeynes@361
   491
    store_spreg( R_EAX, R_T );
nkeynes@361
   492
:}
nkeynes@374
   493
DIV1 Rm, Rn {:  
nkeynes@374
   494
    load_reg( R_ECX, Rn );
nkeynes@374
   495
    LDC_t();
nkeynes@374
   496
    RCL1_r32( R_ECX ); // OP2
nkeynes@374
   497
    SETC_r32( R_EDX ); // Q
nkeynes@374
   498
    load_spreg( R_EAX, R_Q );
nkeynes@374
   499
    CMP_sh4r_r32( R_M, R_EAX );
nkeynes@374
   500
    JE_rel8(8);
nkeynes@374
   501
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   502
    JMP_rel8(3);
nkeynes@374
   503
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   504
    // TODO
nkeynes@374
   505
:}
nkeynes@361
   506
DMULS.L Rm, Rn {:  
nkeynes@361
   507
    load_reg( R_EAX, Rm );
nkeynes@361
   508
    load_reg( R_ECX, Rn );
nkeynes@361
   509
    IMUL_r32(R_ECX);
nkeynes@361
   510
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   511
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   512
:}
nkeynes@361
   513
DMULU.L Rm, Rn {:  
nkeynes@361
   514
    load_reg( R_EAX, Rm );
nkeynes@361
   515
    load_reg( R_ECX, Rn );
nkeynes@361
   516
    MUL_r32(R_ECX);
nkeynes@361
   517
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   518
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   519
:}
nkeynes@359
   520
DT Rn {:  
nkeynes@359
   521
    load_reg( R_EAX, Rn );
nkeynes@359
   522
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   523
    store_reg( R_EAX, Rn );
nkeynes@359
   524
    SETE_t();
nkeynes@359
   525
:}
nkeynes@359
   526
EXTS.B Rm, Rn {:  
nkeynes@359
   527
    load_reg( R_EAX, Rm );
nkeynes@359
   528
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   529
    store_reg( R_EAX, Rn );
nkeynes@359
   530
:}
nkeynes@361
   531
EXTS.W Rm, Rn {:  
nkeynes@361
   532
    load_reg( R_EAX, Rm );
nkeynes@361
   533
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   534
    store_reg( R_EAX, Rn );
nkeynes@361
   535
:}
nkeynes@361
   536
EXTU.B Rm, Rn {:  
nkeynes@361
   537
    load_reg( R_EAX, Rm );
nkeynes@361
   538
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   539
    store_reg( R_EAX, Rn );
nkeynes@361
   540
:}
nkeynes@361
   541
EXTU.W Rm, Rn {:  
nkeynes@361
   542
    load_reg( R_EAX, Rm );
nkeynes@361
   543
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   544
    store_reg( R_EAX, Rn );
nkeynes@361
   545
:}
nkeynes@359
   546
MAC.L @Rm+, @Rn+ {:  :}
nkeynes@359
   547
MAC.W @Rm+, @Rn+ {:  :}
nkeynes@359
   548
MOVT Rn {:  
nkeynes@359
   549
    load_spreg( R_EAX, R_T );
nkeynes@359
   550
    store_reg( R_EAX, Rn );
nkeynes@359
   551
:}
nkeynes@361
   552
MUL.L Rm, Rn {:  
nkeynes@361
   553
    load_reg( R_EAX, Rm );
nkeynes@361
   554
    load_reg( R_ECX, Rn );
nkeynes@361
   555
    MUL_r32( R_ECX );
nkeynes@361
   556
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   557
:}
nkeynes@374
   558
MULS.W Rm, Rn {:
nkeynes@374
   559
    load_reg16s( R_EAX, Rm );
nkeynes@374
   560
    load_reg16s( R_ECX, Rn );
nkeynes@374
   561
    MUL_r32( R_ECX );
nkeynes@374
   562
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   563
:}
nkeynes@374
   564
MULU.W Rm, Rn {:  
nkeynes@374
   565
    load_reg16u( R_EAX, Rm );
nkeynes@374
   566
    load_reg16u( R_ECX, Rn );
nkeynes@374
   567
    MUL_r32( R_ECX );
nkeynes@374
   568
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   569
:}
nkeynes@359
   570
NEG Rm, Rn {:
nkeynes@359
   571
    load_reg( R_EAX, Rm );
nkeynes@359
   572
    NEG_r32( R_EAX );
nkeynes@359
   573
    store_reg( R_EAX, Rn );
nkeynes@359
   574
:}
nkeynes@359
   575
NEGC Rm, Rn {:  
nkeynes@359
   576
    load_reg( R_EAX, Rm );
nkeynes@359
   577
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   578
    LDC_t();
nkeynes@359
   579
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   580
    store_reg( R_ECX, Rn );
nkeynes@359
   581
    SETC_t();
nkeynes@359
   582
:}
nkeynes@359
   583
NOT Rm, Rn {:  
nkeynes@359
   584
    load_reg( R_EAX, Rm );
nkeynes@359
   585
    NOT_r32( R_EAX );
nkeynes@359
   586
    store_reg( R_EAX, Rn );
nkeynes@359
   587
:}
nkeynes@359
   588
OR Rm, Rn {:  
nkeynes@359
   589
    load_reg( R_EAX, Rm );
nkeynes@359
   590
    load_reg( R_ECX, Rn );
nkeynes@359
   591
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   592
    store_reg( R_ECX, Rn );
nkeynes@359
   593
:}
nkeynes@359
   594
OR #imm, R0 {:
nkeynes@359
   595
    load_reg( R_EAX, 0 );
nkeynes@359
   596
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   597
    store_reg( R_EAX, 0 );
nkeynes@359
   598
:}
nkeynes@374
   599
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   600
    load_reg( R_EAX, 0 );
nkeynes@374
   601
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   602
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   603
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
   604
    OR_imm32_r32(imm, R_ECX );
nkeynes@374
   605
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   606
:}
nkeynes@359
   607
ROTCL Rn {:
nkeynes@359
   608
    load_reg( R_EAX, Rn );
nkeynes@359
   609
    LDC_t();
nkeynes@359
   610
    RCL1_r32( R_EAX );
nkeynes@359
   611
    store_reg( R_EAX, Rn );
nkeynes@359
   612
    SETC_t();
nkeynes@359
   613
:}
nkeynes@359
   614
ROTCR Rn {:  
nkeynes@359
   615
    load_reg( R_EAX, Rn );
nkeynes@359
   616
    LDC_t();
nkeynes@359
   617
    RCR1_r32( R_EAX );
nkeynes@359
   618
    store_reg( R_EAX, Rn );
nkeynes@359
   619
    SETC_t();
nkeynes@359
   620
:}
nkeynes@359
   621
ROTL Rn {:  
nkeynes@359
   622
    load_reg( R_EAX, Rn );
nkeynes@359
   623
    ROL1_r32( R_EAX );
nkeynes@359
   624
    store_reg( R_EAX, Rn );
nkeynes@359
   625
    SETC_t();
nkeynes@359
   626
:}
nkeynes@359
   627
ROTR Rn {:  
nkeynes@359
   628
    load_reg( R_EAX, Rn );
nkeynes@359
   629
    ROR1_r32( R_EAX );
nkeynes@359
   630
    store_reg( R_EAX, Rn );
nkeynes@359
   631
    SETC_t();
nkeynes@359
   632
:}
nkeynes@359
   633
SHAD Rm, Rn {:
nkeynes@359
   634
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   635
    load_reg( R_EAX, Rn );
nkeynes@361
   636
    load_reg( R_ECX, Rm );
nkeynes@361
   637
    CMP_imm32_r32( 0, R_ECX );
nkeynes@361
   638
    JAE_rel8(9);
nkeynes@361
   639
                    
nkeynes@361
   640
    NEG_r32( R_ECX );      // 2
nkeynes@361
   641
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   642
    SAR_r32_CL( R_EAX );       // 2
nkeynes@361
   643
    JMP_rel8(5);               // 2
nkeynes@361
   644
    
nkeynes@361
   645
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   646
    SHL_r32_CL( R_EAX );       // 2
nkeynes@361
   647
                    
nkeynes@361
   648
    store_reg( R_EAX, Rn );
nkeynes@359
   649
:}
nkeynes@359
   650
SHLD Rm, Rn {:  
nkeynes@368
   651
    load_reg( R_EAX, Rn );
nkeynes@368
   652
    load_reg( R_ECX, Rm );
nkeynes@368
   653
nkeynes@368
   654
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
   655
    SHL_r32_CL( R_EAX );
nkeynes@368
   656
    NEG_r32( R_ECX );
nkeynes@368
   657
    SHR_r32_CL( R_EDX );
nkeynes@368
   658
    CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
   659
    CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
   660
    store_reg( R_EAX, Rn );
nkeynes@359
   661
:}
nkeynes@359
   662
SHAL Rn {: 
nkeynes@359
   663
    load_reg( R_EAX, Rn );
nkeynes@359
   664
    SHL1_r32( R_EAX );
nkeynes@359
   665
    store_reg( R_EAX, Rn );
nkeynes@359
   666
:}
nkeynes@359
   667
SHAR Rn {:  
nkeynes@359
   668
    load_reg( R_EAX, Rn );
nkeynes@359
   669
    SAR1_r32( R_EAX );
nkeynes@359
   670
    store_reg( R_EAX, Rn );
nkeynes@359
   671
:}
nkeynes@359
   672
SHLL Rn {:  
nkeynes@359
   673
    load_reg( R_EAX, Rn );
nkeynes@359
   674
    SHL1_r32( R_EAX );
nkeynes@359
   675
    store_reg( R_EAX, Rn );
nkeynes@359
   676
:}
nkeynes@359
   677
SHLL2 Rn {:
nkeynes@359
   678
    load_reg( R_EAX, Rn );
nkeynes@359
   679
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   680
    store_reg( R_EAX, Rn );
nkeynes@359
   681
:}
nkeynes@359
   682
SHLL8 Rn {:  
nkeynes@359
   683
    load_reg( R_EAX, Rn );
nkeynes@359
   684
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   685
    store_reg( R_EAX, Rn );
nkeynes@359
   686
:}
nkeynes@359
   687
SHLL16 Rn {:  
nkeynes@359
   688
    load_reg( R_EAX, Rn );
nkeynes@359
   689
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   690
    store_reg( R_EAX, Rn );
nkeynes@359
   691
:}
nkeynes@359
   692
SHLR Rn {:  
nkeynes@359
   693
    load_reg( R_EAX, Rn );
nkeynes@359
   694
    SHR1_r32( R_EAX );
nkeynes@359
   695
    store_reg( R_EAX, Rn );
nkeynes@359
   696
:}
nkeynes@359
   697
SHLR2 Rn {:  
nkeynes@359
   698
    load_reg( R_EAX, Rn );
nkeynes@359
   699
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   700
    store_reg( R_EAX, Rn );
nkeynes@359
   701
:}
nkeynes@359
   702
SHLR8 Rn {:  
nkeynes@359
   703
    load_reg( R_EAX, Rn );
nkeynes@359
   704
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   705
    store_reg( R_EAX, Rn );
nkeynes@359
   706
:}
nkeynes@359
   707
SHLR16 Rn {:  
nkeynes@359
   708
    load_reg( R_EAX, Rn );
nkeynes@359
   709
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   710
    store_reg( R_EAX, Rn );
nkeynes@359
   711
:}
nkeynes@359
   712
SUB Rm, Rn {:  
nkeynes@359
   713
    load_reg( R_EAX, Rm );
nkeynes@359
   714
    load_reg( R_ECX, Rn );
nkeynes@359
   715
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   716
    store_reg( R_ECX, Rn );
nkeynes@359
   717
:}
nkeynes@359
   718
SUBC Rm, Rn {:  
nkeynes@359
   719
    load_reg( R_EAX, Rm );
nkeynes@359
   720
    load_reg( R_ECX, Rn );
nkeynes@359
   721
    LDC_t();
nkeynes@359
   722
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   723
    store_reg( R_ECX, Rn );
nkeynes@359
   724
:}
nkeynes@359
   725
SUBV Rm, Rn {:  
nkeynes@359
   726
    load_reg( R_EAX, Rm );
nkeynes@359
   727
    load_reg( R_ECX, Rn );
nkeynes@359
   728
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   729
    store_reg( R_ECX, Rn );
nkeynes@359
   730
    SETO_t();
nkeynes@359
   731
:}
nkeynes@359
   732
SWAP.B Rm, Rn {:  
nkeynes@359
   733
    load_reg( R_EAX, Rm );
nkeynes@359
   734
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   735
    store_reg( R_EAX, Rn );
nkeynes@359
   736
:}
nkeynes@359
   737
SWAP.W Rm, Rn {:  
nkeynes@359
   738
    load_reg( R_EAX, Rm );
nkeynes@359
   739
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   740
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   741
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   742
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   743
    store_reg( R_ECX, Rn );
nkeynes@359
   744
:}
nkeynes@361
   745
TAS.B @Rn {:  
nkeynes@361
   746
    load_reg( R_ECX, Rn );
nkeynes@361
   747
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   748
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   749
    SETE_t();
nkeynes@361
   750
    OR_imm8_r8( 0x80, R_AL );
nkeynes@361
   751
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   752
:}
nkeynes@361
   753
TST Rm, Rn {:  
nkeynes@361
   754
    load_reg( R_EAX, Rm );
nkeynes@361
   755
    load_reg( R_ECX, Rn );
nkeynes@361
   756
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   757
    SETE_t();
nkeynes@361
   758
:}
nkeynes@368
   759
TST #imm, R0 {:  
nkeynes@368
   760
    load_reg( R_EAX, 0 );
nkeynes@368
   761
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   762
    SETE_t();
nkeynes@368
   763
:}
nkeynes@368
   764
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   765
    load_reg( R_EAX, 0);
nkeynes@368
   766
    load_reg( R_ECX, R_GBR);
nkeynes@368
   767
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   768
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
   769
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
   770
    SETE_t();
nkeynes@368
   771
:}
nkeynes@359
   772
XOR Rm, Rn {:  
nkeynes@359
   773
    load_reg( R_EAX, Rm );
nkeynes@359
   774
    load_reg( R_ECX, Rn );
nkeynes@359
   775
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   776
    store_reg( R_ECX, Rn );
nkeynes@359
   777
:}
nkeynes@359
   778
XOR #imm, R0 {:  
nkeynes@359
   779
    load_reg( R_EAX, 0 );
nkeynes@359
   780
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   781
    store_reg( R_EAX, 0 );
nkeynes@359
   782
:}
nkeynes@359
   783
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   784
    load_reg( R_EAX, 0 );
nkeynes@359
   785
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   786
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   787
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   788
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   789
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   790
:}
nkeynes@361
   791
XTRCT Rm, Rn {:
nkeynes@361
   792
    load_reg( R_EAX, Rm );
nkeynes@361
   793
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   794
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   795
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   796
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   797
    store_reg( R_ECX, Rn );
nkeynes@359
   798
:}
nkeynes@359
   799
nkeynes@359
   800
/* Data move instructions */
nkeynes@359
   801
MOV Rm, Rn {:  
nkeynes@359
   802
    load_reg( R_EAX, Rm );
nkeynes@359
   803
    store_reg( R_EAX, Rn );
nkeynes@359
   804
:}
nkeynes@359
   805
MOV #imm, Rn {:  
nkeynes@359
   806
    load_imm32( R_EAX, imm );
nkeynes@359
   807
    store_reg( R_EAX, Rn );
nkeynes@359
   808
:}
nkeynes@359
   809
MOV.B Rm, @Rn {:  
nkeynes@359
   810
    load_reg( R_EAX, Rm );
nkeynes@359
   811
    load_reg( R_ECX, Rn );
nkeynes@359
   812
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   813
:}
nkeynes@359
   814
MOV.B Rm, @-Rn {:  
nkeynes@359
   815
    load_reg( R_EAX, Rm );
nkeynes@359
   816
    load_reg( R_ECX, Rn );
nkeynes@359
   817
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   818
    store_reg( R_ECX, Rn );
nkeynes@359
   819
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   820
:}
nkeynes@359
   821
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   822
    load_reg( R_EAX, 0 );
nkeynes@359
   823
    load_reg( R_ECX, Rn );
nkeynes@359
   824
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   825
    load_reg( R_EAX, Rm );
nkeynes@359
   826
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   827
:}
nkeynes@359
   828
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   829
    load_reg( R_EAX, 0 );
nkeynes@359
   830
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   831
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   832
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   833
:}
nkeynes@359
   834
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   835
    load_reg( R_EAX, 0 );
nkeynes@359
   836
    load_reg( R_ECX, Rn );
nkeynes@359
   837
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   838
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   839
:}
nkeynes@359
   840
MOV.B @Rm, Rn {:  
nkeynes@359
   841
    load_reg( R_ECX, Rm );
nkeynes@359
   842
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   843
    store_reg( R_ECX, Rn );
nkeynes@359
   844
:}
nkeynes@359
   845
MOV.B @Rm+, Rn {:  
nkeynes@359
   846
    load_reg( R_ECX, Rm );
nkeynes@359
   847
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
   848
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
   849
    store_reg( R_EAX, Rm );
nkeynes@359
   850
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   851
    store_reg( R_EAX, Rn );
nkeynes@359
   852
:}
nkeynes@359
   853
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
   854
    load_reg( R_EAX, 0 );
nkeynes@359
   855
    load_reg( R_ECX, Rm );
nkeynes@359
   856
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   857
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, Rn );
nkeynes@359
   859
:}
nkeynes@359
   860
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
   861
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   862
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   863
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   864
    store_reg( R_EAX, 0 );
nkeynes@359
   865
:}
nkeynes@359
   866
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
   867
    load_reg( R_ECX, Rm );
nkeynes@359
   868
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   869
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   870
    store_reg( R_EAX, 0 );
nkeynes@359
   871
:}
nkeynes@374
   872
MOV.L Rm, @Rn {:
nkeynes@361
   873
    load_reg( R_EAX, Rm );
nkeynes@361
   874
    load_reg( R_ECX, Rn );
nkeynes@374
   875
    check_walign32(R_ECX);
nkeynes@361
   876
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   877
:}
nkeynes@361
   878
MOV.L Rm, @-Rn {:  
nkeynes@361
   879
    load_reg( R_EAX, Rm );
nkeynes@361
   880
    load_reg( R_ECX, Rn );
nkeynes@374
   881
    check_walign32( R_ECX );
nkeynes@361
   882
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   883
    store_reg( R_ECX, Rn );
nkeynes@361
   884
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   885
:}
nkeynes@361
   886
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
   887
    load_reg( R_EAX, 0 );
nkeynes@361
   888
    load_reg( R_ECX, Rn );
nkeynes@361
   889
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   890
    check_walign32( R_ECX );
nkeynes@361
   891
    load_reg( R_EAX, Rm );
nkeynes@361
   892
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   893
:}
nkeynes@361
   894
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
   895
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   896
    load_reg( R_EAX, 0 );
nkeynes@361
   897
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   898
    check_walign32( R_ECX );
nkeynes@361
   899
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   900
:}
nkeynes@361
   901
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
   902
    load_reg( R_ECX, Rn );
nkeynes@361
   903
    load_reg( R_EAX, Rm );
nkeynes@361
   904
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   905
    check_walign32( R_ECX );
nkeynes@361
   906
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   907
:}
nkeynes@361
   908
MOV.L @Rm, Rn {:  
nkeynes@361
   909
    load_reg( R_ECX, Rm );
nkeynes@374
   910
    check_ralign32( R_ECX );
nkeynes@361
   911
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   912
    store_reg( R_EAX, Rn );
nkeynes@361
   913
:}
nkeynes@361
   914
MOV.L @Rm+, Rn {:  
nkeynes@361
   915
    load_reg( R_EAX, Rm );
nkeynes@374
   916
    check_ralign32( R_ECX );
nkeynes@361
   917
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   918
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
   919
    store_reg( R_EAX, Rm );
nkeynes@361
   920
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   921
    store_reg( R_EAX, Rn );
nkeynes@361
   922
:}
nkeynes@361
   923
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
   924
    load_reg( R_EAX, 0 );
nkeynes@361
   925
    load_reg( R_ECX, Rm );
nkeynes@361
   926
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   927
    check_ralign32( R_ECX );
nkeynes@361
   928
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   929
    store_reg( R_EAX, Rn );
nkeynes@361
   930
:}
nkeynes@361
   931
MOV.L @(disp, GBR), R0 {:
nkeynes@361
   932
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   933
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   934
    check_ralign32( R_ECX );
nkeynes@361
   935
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   936
    store_reg( R_EAX, 0 );
nkeynes@361
   937
:}
nkeynes@361
   938
MOV.L @(disp, PC), Rn {:  
nkeynes@374
   939
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
   940
	SLOTILLEGAL();
nkeynes@374
   941
    } else {
nkeynes@374
   942
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
   943
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
   944
	store_reg( R_EAX, 0 );
nkeynes@374
   945
    }
nkeynes@361
   946
:}
nkeynes@361
   947
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
   948
    load_reg( R_ECX, Rm );
nkeynes@361
   949
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
   950
    check_ralign32( R_ECX );
nkeynes@361
   951
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   952
    store_reg( R_EAX, Rn );
nkeynes@361
   953
:}
nkeynes@361
   954
MOV.W Rm, @Rn {:  
nkeynes@361
   955
    load_reg( R_ECX, Rn );
nkeynes@374
   956
    check_walign16( R_ECX );
nkeynes@361
   957
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   958
    store_reg( R_EAX, Rn );
nkeynes@361
   959
:}
nkeynes@361
   960
MOV.W Rm, @-Rn {:  
nkeynes@361
   961
    load_reg( R_ECX, Rn );
nkeynes@374
   962
    check_walign16( R_ECX );
nkeynes@361
   963
    load_reg( R_EAX, Rm );
nkeynes@361
   964
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   965
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   966
:}
nkeynes@361
   967
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
   968
    load_reg( R_EAX, 0 );
nkeynes@361
   969
    load_reg( R_ECX, Rn );
nkeynes@361
   970
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   971
    check_walign16( R_ECX );
nkeynes@361
   972
    load_reg( R_EAX, Rm );
nkeynes@361
   973
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   974
:}
nkeynes@361
   975
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
   976
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   977
    load_reg( R_EAX, 0 );
nkeynes@361
   978
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   979
    check_walign16( R_ECX );
nkeynes@361
   980
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   981
:}
nkeynes@361
   982
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
   983
    load_reg( R_ECX, Rn );
nkeynes@361
   984
    load_reg( R_EAX, 0 );
nkeynes@361
   985
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   986
    check_walign16( R_ECX );
nkeynes@361
   987
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   988
:}
nkeynes@361
   989
MOV.W @Rm, Rn {:  
nkeynes@361
   990
    load_reg( R_ECX, Rm );
nkeynes@374
   991
    check_ralign16( R_ECX );
nkeynes@361
   992
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   993
    store_reg( R_EAX, Rn );
nkeynes@361
   994
:}
nkeynes@361
   995
MOV.W @Rm+, Rn {:  
nkeynes@361
   996
    load_reg( R_EAX, Rm );
nkeynes@374
   997
    check_ralign16( R_EAX );
nkeynes@361
   998
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   999
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1000
    store_reg( R_EAX, Rm );
nkeynes@361
  1001
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1002
    store_reg( R_EAX, Rn );
nkeynes@361
  1003
:}
nkeynes@361
  1004
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1005
    load_reg( R_EAX, 0 );
nkeynes@361
  1006
    load_reg( R_ECX, Rm );
nkeynes@361
  1007
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1008
    check_ralign16( R_ECX );
nkeynes@361
  1009
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1010
    store_reg( R_EAX, Rn );
nkeynes@361
  1011
:}
nkeynes@361
  1012
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1013
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1014
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1015
    check_ralign16( R_ECX );
nkeynes@361
  1016
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1017
    store_reg( R_EAX, 0 );
nkeynes@361
  1018
:}
nkeynes@361
  1019
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1020
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1021
	SLOTILLEGAL();
nkeynes@374
  1022
    } else {
nkeynes@374
  1023
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1024
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1025
	store_reg( R_EAX, Rn );
nkeynes@374
  1026
    }
nkeynes@361
  1027
:}
nkeynes@361
  1028
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1029
    load_reg( R_ECX, Rm );
nkeynes@361
  1030
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1031
    check_ralign16( R_ECX );
nkeynes@361
  1032
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1033
    store_reg( R_EAX, 0 );
nkeynes@361
  1034
:}
nkeynes@361
  1035
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1036
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1037
	SLOTILLEGAL();
nkeynes@374
  1038
    } else {
nkeynes@374
  1039
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1040
	store_reg( R_ECX, 0 );
nkeynes@374
  1041
    }
nkeynes@361
  1042
:}
nkeynes@361
  1043
MOVCA.L R0, @Rn {:  
nkeynes@361
  1044
    load_reg( R_EAX, 0 );
nkeynes@361
  1045
    load_reg( R_ECX, Rn );
nkeynes@374
  1046
    check_walign32( R_ECX );
nkeynes@361
  1047
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1048
:}
nkeynes@359
  1049
nkeynes@359
  1050
/* Control transfer instructions */
nkeynes@374
  1051
BF disp {:
nkeynes@374
  1052
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1053
	SLOTILLEGAL();
nkeynes@374
  1054
    } else {
nkeynes@374
  1055
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1056
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1057
	JNE_rel8( 5 );
nkeynes@374
  1058
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1059
	INC_r32(R_ESI);
nkeynes@374
  1060
	return 1;
nkeynes@374
  1061
    }
nkeynes@374
  1062
:}
nkeynes@374
  1063
BF/S disp {:
nkeynes@374
  1064
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1065
	SLOTILLEGAL();
nkeynes@374
  1066
    } else {
nkeynes@374
  1067
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1068
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1069
	JNE_rel8( 5 );
nkeynes@374
  1070
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1071
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1072
	INC_r32(R_ESI);
nkeynes@374
  1073
	return 0;
nkeynes@374
  1074
    }
nkeynes@374
  1075
:}
nkeynes@374
  1076
BRA disp {:  
nkeynes@374
  1077
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1078
	SLOTILLEGAL();
nkeynes@374
  1079
    } else {
nkeynes@374
  1080
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1081
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1082
	INC_r32(R_ESI);
nkeynes@374
  1083
	return 0;
nkeynes@374
  1084
    }
nkeynes@374
  1085
:}
nkeynes@374
  1086
BRAF Rn {:  
nkeynes@374
  1087
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1088
	SLOTILLEGAL();
nkeynes@374
  1089
    } else {
nkeynes@374
  1090
	load_reg( R_EDI, Rn );
nkeynes@374
  1091
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1092
	INC_r32(R_ESI);
nkeynes@374
  1093
	return 0;
nkeynes@374
  1094
    }
nkeynes@374
  1095
:}
nkeynes@374
  1096
BSR disp {:  
nkeynes@374
  1097
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1098
	SLOTILLEGAL();
nkeynes@374
  1099
    } else {
nkeynes@374
  1100
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1101
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1102
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1103
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1104
	INC_r32(R_ESI);
nkeynes@374
  1105
	return 0;
nkeynes@374
  1106
    }
nkeynes@374
  1107
:}
nkeynes@374
  1108
BSRF Rn {:  
nkeynes@374
  1109
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1110
	SLOTILLEGAL();
nkeynes@374
  1111
    } else {
nkeynes@374
  1112
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1113
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1114
	load_reg( R_EDI, Rn );
nkeynes@374
  1115
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1116
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1117
	INC_r32(R_ESI);
nkeynes@374
  1118
	return 0;
nkeynes@374
  1119
    }
nkeynes@374
  1120
:}
nkeynes@374
  1121
BT disp {:
nkeynes@374
  1122
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1123
	SLOTILLEGAL();
nkeynes@374
  1124
    } else {
nkeynes@374
  1125
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1126
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1127
	JE_rel8( 5 );
nkeynes@374
  1128
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1129
	INC_r32(R_ESI);
nkeynes@374
  1130
	return 1;
nkeynes@374
  1131
    }
nkeynes@374
  1132
:}
nkeynes@374
  1133
BT/S disp {:
nkeynes@374
  1134
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1135
	SLOTILLEGAL();
nkeynes@374
  1136
    } else {
nkeynes@374
  1137
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1138
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1139
	JE_rel8( 5 );
nkeynes@374
  1140
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1141
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1142
	INC_r32(R_ESI);
nkeynes@374
  1143
	return 0;
nkeynes@374
  1144
    }
nkeynes@374
  1145
:}
nkeynes@374
  1146
JMP @Rn {:  
nkeynes@374
  1147
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1148
	SLOTILLEGAL();
nkeynes@374
  1149
    } else {
nkeynes@374
  1150
	load_reg( R_EDI, Rn );
nkeynes@374
  1151
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1152
	INC_r32(R_ESI);
nkeynes@374
  1153
	return 0;
nkeynes@374
  1154
    }
nkeynes@374
  1155
:}
nkeynes@374
  1156
JSR @Rn {:  
nkeynes@374
  1157
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1158
	SLOTILLEGAL();
nkeynes@374
  1159
    } else {
nkeynes@374
  1160
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1161
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1162
	load_reg( R_EDI, Rn );
nkeynes@374
  1163
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1164
	INC_r32(R_ESI);
nkeynes@374
  1165
	return 0;
nkeynes@374
  1166
    }
nkeynes@374
  1167
:}
nkeynes@374
  1168
RTE {:  
nkeynes@374
  1169
    check_priv();
nkeynes@374
  1170
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1171
	SLOTILLEGAL();
nkeynes@374
  1172
    } else {
nkeynes@374
  1173
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1174
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1175
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1176
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1177
	INC_r32(R_ESI);
nkeynes@374
  1178
	return 0;
nkeynes@374
  1179
    }
nkeynes@374
  1180
:}
nkeynes@374
  1181
RTS {:  
nkeynes@374
  1182
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1183
	SLOTILLEGAL();
nkeynes@374
  1184
    } else {
nkeynes@374
  1185
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1186
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1187
	INC_r32(R_ESI);
nkeynes@374
  1188
	return 0;
nkeynes@374
  1189
    }
nkeynes@374
  1190
:}
nkeynes@374
  1191
TRAPA #imm {:  
nkeynes@374
  1192
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1193
	SLOTILLEGAL();
nkeynes@374
  1194
    } else {
nkeynes@374
  1195
	// TODO: Write TRA 
nkeynes@374
  1196
	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  1197
    }
nkeynes@374
  1198
:}
nkeynes@374
  1199
UNDEF {:  
nkeynes@374
  1200
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1201
	RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
nkeynes@374
  1202
    } else {
nkeynes@374
  1203
	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@374
  1204
    }
nkeynes@368
  1205
    return 1;
nkeynes@368
  1206
:}
nkeynes@374
  1207
nkeynes@374
  1208
CLRMAC {:  
nkeynes@374
  1209
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1210
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1211
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1212
:}
nkeynes@374
  1213
CLRS {:
nkeynes@374
  1214
    CLC();
nkeynes@374
  1215
    SETC_sh4r(R_S);
nkeynes@368
  1216
:}
nkeynes@374
  1217
CLRT {:  
nkeynes@374
  1218
    CLC();
nkeynes@374
  1219
    SETC_t();
nkeynes@359
  1220
:}
nkeynes@374
  1221
SETS {:  
nkeynes@374
  1222
    STC();
nkeynes@374
  1223
    SETC_sh4r(R_S);
nkeynes@359
  1224
:}
nkeynes@374
  1225
SETT {:  
nkeynes@374
  1226
    STC();
nkeynes@374
  1227
    SETC_t();
nkeynes@374
  1228
:}
nkeynes@359
  1229
nkeynes@359
  1230
/* Floating point instructions */
nkeynes@374
  1231
FABS FRn {:  
nkeynes@374
  1232
    load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  1233
    load_spreg( R_EDX, REG_OFFSET(fr_bank) );
nkeynes@374
  1234
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@374
  1235
    JNE_rel8(10);
nkeynes@374
  1236
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1237
    FABS_st0(); // 2
nkeynes@374
  1238
    pop_fr( R_EDX, FRn); //3
nkeynes@374
  1239
    JMP_rel8(8); // 2
nkeynes@374
  1240
    push_dr(R_EDX, FRn);
nkeynes@374
  1241
    FABS_st0();
nkeynes@374
  1242
    pop_dr(R_EDX, FRn);
nkeynes@374
  1243
:}
nkeynes@359
  1244
FADD FRm, FRn {:  :}
nkeynes@359
  1245
FCMP/EQ FRm, FRn {:  :}
nkeynes@359
  1246
FCMP/GT FRm, FRn {:  :}
nkeynes@359
  1247
FCNVDS FRm, FPUL {:  :}
nkeynes@359
  1248
FCNVSD FPUL, FRn {:  :}
nkeynes@359
  1249
FDIV FRm, FRn {:  :}
nkeynes@359
  1250
FIPR FVm, FVn {:  :}
nkeynes@359
  1251
FLDS FRm, FPUL {:  :}
nkeynes@359
  1252
FLDI0 FRn {:  :}
nkeynes@359
  1253
FLDI1 FRn {:  :}
nkeynes@359
  1254
FLOAT FPUL, FRn {:  :}
nkeynes@359
  1255
FMAC FR0, FRm, FRn {:  :}
nkeynes@359
  1256
FMOV FRm, FRn {:  :}
nkeynes@359
  1257
FMOV FRm, @Rn {:  :}
nkeynes@359
  1258
FMOV FRm, @-Rn {:  :}
nkeynes@359
  1259
FMOV FRm, @(R0, Rn) {:  :}
nkeynes@359
  1260
FMOV @Rm, FRn {:  :}
nkeynes@359
  1261
FMOV @Rm+, FRn {:  :}
nkeynes@359
  1262
FMOV @(R0, Rm), FRn {:  :}
nkeynes@359
  1263
FMUL FRm, FRn {:  :}
nkeynes@359
  1264
FNEG FRn {:  :}
nkeynes@359
  1265
FRCHG {:  :}
nkeynes@359
  1266
FSCA FPUL, FRn {:  :}
nkeynes@359
  1267
FSCHG {:  :}
nkeynes@359
  1268
FSQRT FRn {:  :}
nkeynes@359
  1269
FSRRA FRn {:  :}
nkeynes@359
  1270
FSTS FPUL, FRn {:  :}
nkeynes@359
  1271
FSUB FRm, FRn {:  :}
nkeynes@359
  1272
FTRC FRm, FPUL {:  :}
nkeynes@359
  1273
FTRV XMTRX, FVn {:  :}
nkeynes@359
  1274
nkeynes@359
  1275
/* Processor control instructions */
nkeynes@368
  1276
LDC Rm, SR {:
nkeynes@368
  1277
    load_reg( R_EAX, Rm );
nkeynes@374
  1278
    call_func1( sh4_write_sr, R_EAX );
nkeynes@368
  1279
:}
nkeynes@359
  1280
LDC Rm, GBR {: 
nkeynes@359
  1281
    load_reg( R_EAX, Rm );
nkeynes@359
  1282
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1283
:}
nkeynes@359
  1284
LDC Rm, VBR {:  
nkeynes@359
  1285
    load_reg( R_EAX, Rm );
nkeynes@359
  1286
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1287
:}
nkeynes@359
  1288
LDC Rm, SSR {:  
nkeynes@359
  1289
    load_reg( R_EAX, Rm );
nkeynes@359
  1290
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1291
:}
nkeynes@359
  1292
LDC Rm, SGR {:  
nkeynes@359
  1293
    load_reg( R_EAX, Rm );
nkeynes@359
  1294
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1295
:}
nkeynes@359
  1296
LDC Rm, SPC {:  
nkeynes@359
  1297
    load_reg( R_EAX, Rm );
nkeynes@359
  1298
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1299
:}
nkeynes@359
  1300
LDC Rm, DBR {:  
nkeynes@359
  1301
    load_reg( R_EAX, Rm );
nkeynes@359
  1302
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1303
:}
nkeynes@374
  1304
LDC Rm, Rn_BANK {:  
nkeynes@374
  1305
    load_reg( R_EAX, Rm );
nkeynes@374
  1306
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  1307
:}
nkeynes@359
  1308
LDC.L @Rm+, GBR {:  
nkeynes@359
  1309
    load_reg( R_EAX, Rm );
nkeynes@359
  1310
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1311
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1312
    store_reg( R_EAX, Rm );
nkeynes@359
  1313
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1314
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1315
:}
nkeynes@368
  1316
LDC.L @Rm+, SR {:
nkeynes@368
  1317
    load_reg( R_EAX, Rm );
nkeynes@368
  1318
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1319
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1320
    store_reg( R_EAX, Rm );
nkeynes@368
  1321
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1322
    call_func1( sh4_write_sr, R_EAX );
nkeynes@359
  1323
:}
nkeynes@359
  1324
LDC.L @Rm+, VBR {:  
nkeynes@359
  1325
    load_reg( R_EAX, Rm );
nkeynes@359
  1326
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1327
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1328
    store_reg( R_EAX, Rm );
nkeynes@359
  1329
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1330
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1331
:}
nkeynes@359
  1332
LDC.L @Rm+, SSR {:
nkeynes@359
  1333
    load_reg( R_EAX, Rm );
nkeynes@359
  1334
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1335
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1336
    store_reg( R_EAX, Rm );
nkeynes@359
  1337
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1338
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1339
:}
nkeynes@359
  1340
LDC.L @Rm+, SGR {:  
nkeynes@359
  1341
    load_reg( R_EAX, Rm );
nkeynes@359
  1342
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1343
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1344
    store_reg( R_EAX, Rm );
nkeynes@359
  1345
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1346
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1347
:}
nkeynes@359
  1348
LDC.L @Rm+, SPC {:  
nkeynes@359
  1349
    load_reg( R_EAX, Rm );
nkeynes@359
  1350
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1351
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1352
    store_reg( R_EAX, Rm );
nkeynes@359
  1353
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1354
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1355
:}
nkeynes@359
  1356
LDC.L @Rm+, DBR {:  
nkeynes@359
  1357
    load_reg( R_EAX, Rm );
nkeynes@359
  1358
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1359
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1360
    store_reg( R_EAX, Rm );
nkeynes@359
  1361
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1362
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1363
:}
nkeynes@359
  1364
LDC.L @Rm+, Rn_BANK {:  
nkeynes@374
  1365
    load_reg( R_EAX, Rm );
nkeynes@374
  1366
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1367
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1368
    store_reg( R_EAX, Rm );
nkeynes@374
  1369
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1370
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1371
:}
nkeynes@359
  1372
LDS Rm, FPSCR {:  
nkeynes@359
  1373
    load_reg( R_EAX, Rm );
nkeynes@359
  1374
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1375
:}
nkeynes@359
  1376
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  1377
    load_reg( R_EAX, Rm );
nkeynes@359
  1378
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1379
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1380
    store_reg( R_EAX, Rm );
nkeynes@359
  1381
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1382
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1383
:}
nkeynes@359
  1384
LDS Rm, FPUL {:  
nkeynes@359
  1385
    load_reg( R_EAX, Rm );
nkeynes@359
  1386
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1387
:}
nkeynes@359
  1388
LDS.L @Rm+, FPUL {:  
nkeynes@359
  1389
    load_reg( R_EAX, Rm );
nkeynes@359
  1390
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1391
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1392
    store_reg( R_EAX, Rm );
nkeynes@359
  1393
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1394
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1395
:}
nkeynes@359
  1396
LDS Rm, MACH {: 
nkeynes@359
  1397
    load_reg( R_EAX, Rm );
nkeynes@359
  1398
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1399
:}
nkeynes@359
  1400
LDS.L @Rm+, MACH {:  
nkeynes@359
  1401
    load_reg( R_EAX, Rm );
nkeynes@359
  1402
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1403
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1404
    store_reg( R_EAX, Rm );
nkeynes@359
  1405
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1406
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1407
:}
nkeynes@359
  1408
LDS Rm, MACL {:  
nkeynes@359
  1409
    load_reg( R_EAX, Rm );
nkeynes@359
  1410
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1411
:}
nkeynes@359
  1412
LDS.L @Rm+, MACL {:  
nkeynes@359
  1413
    load_reg( R_EAX, Rm );
nkeynes@359
  1414
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1415
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1416
    store_reg( R_EAX, Rm );
nkeynes@359
  1417
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1418
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1419
:}
nkeynes@359
  1420
LDS Rm, PR {:  
nkeynes@359
  1421
    load_reg( R_EAX, Rm );
nkeynes@359
  1422
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1423
:}
nkeynes@359
  1424
LDS.L @Rm+, PR {:  
nkeynes@359
  1425
    load_reg( R_EAX, Rm );
nkeynes@359
  1426
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1427
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1428
    store_reg( R_EAX, Rm );
nkeynes@359
  1429
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1430
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1431
:}
nkeynes@359
  1432
LDTLB {:  :}
nkeynes@359
  1433
OCBI @Rn {:  :}
nkeynes@359
  1434
OCBP @Rn {:  :}
nkeynes@359
  1435
OCBWB @Rn {:  :}
nkeynes@374
  1436
PREF @Rn {:
nkeynes@374
  1437
    load_reg( R_EAX, Rn );
nkeynes@374
  1438
    PUSH_r32( R_EAX );
nkeynes@374
  1439
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  1440
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@374
  1441
    JNE_rel8(8);
nkeynes@374
  1442
    call_func0( sh4_flush_store_queue );
nkeynes@374
  1443
    ADD_imm8s_r32( -4, R_ESP );
nkeynes@374
  1444
:}
nkeynes@374
  1445
 SLEEP {: /* TODO */ :}
nkeynes@368
  1446
 STC SR, Rn {:
nkeynes@374
  1447
     call_func0(sh4_read_sr);
nkeynes@368
  1448
     store_reg( R_EAX, Rn );
nkeynes@359
  1449
:}
nkeynes@359
  1450
STC GBR, Rn {:  
nkeynes@359
  1451
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  1452
    store_reg( R_EAX, Rn );
nkeynes@359
  1453
:}
nkeynes@359
  1454
STC VBR, Rn {:  
nkeynes@359
  1455
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  1456
    store_reg( R_EAX, Rn );
nkeynes@359
  1457
:}
nkeynes@359
  1458
STC SSR, Rn {:  
nkeynes@359
  1459
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  1460
    store_reg( R_EAX, Rn );
nkeynes@359
  1461
:}
nkeynes@359
  1462
STC SPC, Rn {:  
nkeynes@359
  1463
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  1464
    store_reg( R_EAX, Rn );
nkeynes@359
  1465
:}
nkeynes@359
  1466
STC SGR, Rn {:  
nkeynes@359
  1467
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  1468
    store_reg( R_EAX, Rn );
nkeynes@359
  1469
:}
nkeynes@359
  1470
STC DBR, Rn {:  
nkeynes@359
  1471
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  1472
    store_reg( R_EAX, Rn );
nkeynes@359
  1473
:}
nkeynes@374
  1474
STC Rm_BANK, Rn {:
nkeynes@374
  1475
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1476
    store_reg( R_EAX, Rn );
nkeynes@359
  1477
:}
nkeynes@374
  1478
STC.L SR, @-Rn {:
nkeynes@368
  1479
    load_reg( R_ECX, Rn );
nkeynes@368
  1480
    ADD_imm8s_r32( -4, Rn );
nkeynes@368
  1481
    store_reg( R_ECX, Rn );
nkeynes@374
  1482
    call_func0( sh4_read_sr );
nkeynes@368
  1483
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1484
:}
nkeynes@359
  1485
STC.L VBR, @-Rn {:  
nkeynes@359
  1486
    load_reg( R_ECX, Rn );
nkeynes@359
  1487
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1488
    store_reg( R_ECX, Rn );
nkeynes@359
  1489
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  1490
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1491
:}
nkeynes@359
  1492
STC.L SSR, @-Rn {:  
nkeynes@359
  1493
    load_reg( R_ECX, Rn );
nkeynes@359
  1494
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1495
    store_reg( R_ECX, Rn );
nkeynes@359
  1496
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  1497
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1498
:}
nkeynes@359
  1499
STC.L SPC, @-Rn {:  
nkeynes@359
  1500
    load_reg( R_ECX, Rn );
nkeynes@359
  1501
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1502
    store_reg( R_ECX, Rn );
nkeynes@359
  1503
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  1504
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1505
:}
nkeynes@359
  1506
STC.L SGR, @-Rn {:  
nkeynes@359
  1507
    load_reg( R_ECX, Rn );
nkeynes@359
  1508
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1509
    store_reg( R_ECX, Rn );
nkeynes@359
  1510
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  1511
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1512
:}
nkeynes@359
  1513
STC.L DBR, @-Rn {:  
nkeynes@359
  1514
    load_reg( R_ECX, Rn );
nkeynes@359
  1515
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1516
    store_reg( R_ECX, Rn );
nkeynes@359
  1517
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  1518
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1519
:}
nkeynes@374
  1520
STC.L Rm_BANK, @-Rn {:  
nkeynes@374
  1521
    load_reg( R_ECX, Rn );
nkeynes@374
  1522
    ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1523
    store_reg( R_ECX, Rn );
nkeynes@374
  1524
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1525
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  1526
:}
nkeynes@359
  1527
STC.L GBR, @-Rn {:  
nkeynes@359
  1528
    load_reg( R_ECX, Rn );
nkeynes@359
  1529
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1530
    store_reg( R_ECX, Rn );
nkeynes@359
  1531
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  1532
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1533
:}
nkeynes@359
  1534
STS FPSCR, Rn {:  
nkeynes@359
  1535
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1536
    store_reg( R_EAX, Rn );
nkeynes@359
  1537
:}
nkeynes@359
  1538
STS.L FPSCR, @-Rn {:  
nkeynes@359
  1539
    load_reg( R_ECX, Rn );
nkeynes@359
  1540
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1541
    store_reg( R_ECX, Rn );
nkeynes@359
  1542
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1543
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1544
:}
nkeynes@359
  1545
STS FPUL, Rn {:  
nkeynes@359
  1546
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1547
    store_reg( R_EAX, Rn );
nkeynes@359
  1548
:}
nkeynes@359
  1549
STS.L FPUL, @-Rn {:  
nkeynes@359
  1550
    load_reg( R_ECX, Rn );
nkeynes@359
  1551
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1552
    store_reg( R_ECX, Rn );
nkeynes@359
  1553
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1554
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1555
:}
nkeynes@359
  1556
STS MACH, Rn {:  
nkeynes@359
  1557
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  1558
    store_reg( R_EAX, Rn );
nkeynes@359
  1559
:}
nkeynes@359
  1560
STS.L MACH, @-Rn {:  
nkeynes@359
  1561
    load_reg( R_ECX, Rn );
nkeynes@359
  1562
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1563
    store_reg( R_ECX, Rn );
nkeynes@359
  1564
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  1565
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1566
:}
nkeynes@359
  1567
STS MACL, Rn {:  
nkeynes@359
  1568
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  1569
    store_reg( R_EAX, Rn );
nkeynes@359
  1570
:}
nkeynes@359
  1571
STS.L MACL, @-Rn {:  
nkeynes@359
  1572
    load_reg( R_ECX, Rn );
nkeynes@359
  1573
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1574
    store_reg( R_ECX, Rn );
nkeynes@359
  1575
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  1576
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1577
:}
nkeynes@359
  1578
STS PR, Rn {:  
nkeynes@359
  1579
    load_spreg( R_EAX, R_PR );
nkeynes@359
  1580
    store_reg( R_EAX, Rn );
nkeynes@359
  1581
:}
nkeynes@359
  1582
STS.L PR, @-Rn {:  
nkeynes@359
  1583
    load_reg( R_ECX, Rn );
nkeynes@359
  1584
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1585
    store_reg( R_ECX, Rn );
nkeynes@359
  1586
    load_spreg( R_EAX, R_PR );
nkeynes@359
  1587
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1588
:}
nkeynes@359
  1589
nkeynes@359
  1590
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  1591
%%
nkeynes@368
  1592
    INC_r32(R_ESI);
nkeynes@374
  1593
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1594
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  1595
	return 1;
nkeynes@374
  1596
    }
nkeynes@359
  1597
    return 0;
nkeynes@359
  1598
}
.