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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 106:9048bac046c3
prev103:9b9cfc5855e0
next107:e576dd36073a
author nkeynes
date Tue Mar 14 12:45:53 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Move driver selection out to main at long last. Add video NULL driver for
headless operation
Make dcload exit() actually exit
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.18 2006-03-14 12:45:53 nkeynes Exp $
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 *
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 * PVR2 (Video) Core MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "video.h"
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#include "mem.h"
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#include "asic.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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void pvr2_init( void );
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uint32_t pvr2_run_slice( uint32_t );
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void pvr2_display_frame( void );
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/**
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 * Current PVR2 ram address of the data (if any) currently held in the 
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 * OpenGL buffers.
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 */
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video_driver_t video_driver = NULL;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int display_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 575, 32000 };
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struct video_timing ntsc_timing= { 60, 525, 480, 31746 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
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					pvr2_run_slice, NULL,
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					NULL, NULL };
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void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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}
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void video_set_driver( video_driver_t driver )
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{
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    if( video_driver != NULL && video_driver->shutdown_driver != NULL )
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	video_driver->shutdown_driver();
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    video_driver = driver;
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    if( driver->init_driver != NULL )
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	driver->init_driver();
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    driver->set_display_format( 640, 480, COLFMT_RGB32 );
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}
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uint32_t pvr2_line_count = 0;
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uint32_t pvr2_line_remainder = 0;
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uint32_t pvr2_irq_vpos1 = 0;
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uint32_t pvr2_irq_vpos2 = 0;
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struct video_timing *pvr2_timing = &ntsc_timing;
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uint32_t pvr2_time_counter = 0;
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uint32_t pvr2_frame_counter = 0;
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uint32_t pvr2_time_per_frame = 20000000;
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uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_line_remainder += nanosecs;
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    while( pvr2_line_remainder >= pvr2_timing->line_time_ns ) {
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	pvr2_line_remainder -= pvr2_timing->line_time_ns;
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	pvr2_line_count++;
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	if( pvr2_line_count == pvr2_irq_vpos1 ) {
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	    asic_event( EVENT_SCANLINE1 );
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	} 
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	if( pvr2_line_count == pvr2_irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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	}
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	if( pvr2_line_count == pvr2_timing->display_lines ) {
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	    asic_event( EVENT_RETRACE );
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	} else if( pvr2_line_count == pvr2_timing->total_lines ) {
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	    pvr2_display_frame();
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	    pvr2_line_count = 0;
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	}
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    }
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    return nanosecs;
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}
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uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
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int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
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char *frame_start; /* current video start address (in real memory) */
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISPSIZE );
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    int dispmode = MMIO_READ( PVR2, DISPMODE );
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    int vidcfg = MMIO_READ( PVR2, DISPCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    if( bEnabled ) {
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	video_buffer_t buffer = &video_buffer[video_buffer_idx];
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	video_buffer_idx = !video_buffer_idx;
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	video_buffer_t last = &video_buffer[video_buffer_idx];
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	buffer->rowstride = (vid_ppl + vid_stride) << 2;
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	buffer->data = frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
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	buffer->vres = vid_lpf;
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	if( interlaced ) buffer->vres <<= 1;
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	switch( (dispmode & DISPMODE_COL) >> 2 ) {
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	case 0: 
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	    buffer->colour_format = COLFMT_ARGB1555;
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	    buffer->hres = vid_ppl << 1; 
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	    break;
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	case 1: 
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	    buffer->colour_format = COLFMT_RGB565;
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	    buffer->hres = vid_ppl << 1; 
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	    break;
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	case 2:
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	    buffer->colour_format = COLFMT_RGB888;
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	    buffer->hres = (vid_ppl << 2) / 3; 
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	    break;
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	case 3: 
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	    buffer->colour_format = COLFMT_ARGB8888;
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	    buffer->hres = vid_ppl; 
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	    break;
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	}
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	if( video_driver != NULL ) {
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	    if( buffer->hres != last->hres ||
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		buffer->vres != last->vres ||
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		buffer->colour_format != last->colour_format) {
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		video_driver->set_display_format( buffer->hres, buffer->vres,
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						  buffer->colour_format );
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	    }
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	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
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		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
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		video_driver->display_blank_frame( colour );
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	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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		video_driver->display_frame( buffer );
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	    }
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	}
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    } else {
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	video_buffer_idx = 0;
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	video_buffer[0].hres = video_buffer[0].vres = 0;
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    }
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    pvr2_frame_counter++;
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    asic_event( EVENT_SCANLINE1 );
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    asic_event( EVENT_SCANLINE2 );
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    asic_event( EVENT_RETRACE );
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}
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        /* I don't want to hear about these */
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        return;
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    }
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    INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
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          MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
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    switch(reg) {
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    case VPOS_IRQ:
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	pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
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	pvr2_irq_vpos2 = val & 0x03FF;
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	break;
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    case TAINIT:
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	if( val & 0x80000000 )
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	    pvr2_ta_init();
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	break;
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    case RENDSTART:
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	if( val == 0xFFFFFFFF )
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	    pvr2_render_scene();
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	break;
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    }
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    MMIO_WRITE( PVR2, reg, val );
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}
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MMIO_REGION_READ_FN( PVR2, reg )
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{
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    switch( reg ) {
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        case BEAMPOS:
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            return sh4r.icount&0x20 ? 0x2000 : 1;
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        default:
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            return MMIO_READ( PVR2, reg );
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    }
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}
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MMIO_REGION_DEFFNS( PVR2PAL )
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void pvr2_set_base_address( uint32_t base ) 
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{
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    mmio_region_PVR2_write( DISPADDR1, base );
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}
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int32_t mmio_region_PVR2TA_read( uint32_t reg )
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{
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    return 0xFFFFFFFF;
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}
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void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
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{
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    pvr2_ta_write( &val, sizeof(uint32_t) );
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}
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void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
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{
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    int bank_flag = (destaddr & 0x04) >> 2;
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    uint32_t *banks[2];
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    uint32_t *dwsrc;
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    int i;
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    destaddr = destaddr & 0x7FFFFF;
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    if( destaddr + length > 0x800000 ) {
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	length = 0x800000 - destaddr;
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    }
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    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
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	texcache_invalidate_page( i );
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    }
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    banks[0] = ((uint32_t *)(video_base + (destaddr>>3)));
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    banks[1] = banks[0] + 0x100000;
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    /* Handle non-aligned start of source */
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    if( destaddr & 0x03 ) {
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	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
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	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
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	    *dest++ = *src++;
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	}
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	bank_flag = !bank_flag;
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    }
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    dwsrc = (uint32_t *)src;
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    while( length >= 4 ) {
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	*banks[bank_flag]++ = *dwsrc++;
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	bank_flag = !bank_flag;
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	length -= 4;
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    }
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    /* Handle non-aligned end of source */
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    if( length ) {
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	src = (char *)dwsrc;
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	char *dest = (char *)banks[bank_flag];
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   278
	while( length-- > 0 ) {
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	    *dest++ = *src++;
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	}
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    }  
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}
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void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
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{
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    int bank_flag = (srcaddr & 0x04) >> 2;
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    uint32_t *banks[2];
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    uint32_t *dwdest;
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    int i;
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    srcaddr = srcaddr & 0x7FFFFF;
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    if( srcaddr + length > 0x800000 )
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	length = 0x800000 - srcaddr;
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   295
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    banks[0] = ((uint32_t *)(video_base + (srcaddr>>3)));
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    banks[1] = banks[0] + 0x100000;
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    /* Handle non-aligned start of source */
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    if( srcaddr & 0x03 ) {
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	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
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   302
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
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   303
	    *dest++ = *src++;
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	}
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	bank_flag = !bank_flag;
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    }
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   307
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    dwdest = (uint32_t *)dest;
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   309
    while( length >= 4 ) {
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	*dwdest++ = *banks[bank_flag]++;
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	bank_flag = !bank_flag;
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   312
	length -= 4;
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   313
    }
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   314
    
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   315
    /* Handle non-aligned end of source */
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   316
    if( length ) {
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   317
	dest = (char *)dwdest;
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   318
	char *src = (char *)banks[bank_flag];
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   319
	while( length-- > 0 ) {
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	    *dest++ = *src++;
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	}
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   322
    }
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}
.