Search
lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/asic.c
changeset 188:91ee93613faa
prev186:79bfebd5e0ff
next240:9ae4bd697292
author nkeynes
date Tue Aug 01 21:56:48 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change Remove no-longer-needed logging
file annotate diff log raw
nkeynes@31
     1
/**
nkeynes@188
     2
 * $Id: asic.c,v 1.19 2006-08-01 21:56:48 nkeynes Exp $
nkeynes@31
     3
 *
nkeynes@31
     4
 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
nkeynes@31
     5
 * and DMA). 
nkeynes@31
     6
 *
nkeynes@31
     7
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@31
     8
 *
nkeynes@31
     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@31
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@31
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@31
    12
 * (at your option) any later version.
nkeynes@31
    13
 *
nkeynes@31
    14
 * This program is distributed in the hope that it will be useful,
nkeynes@31
    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@31
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@31
    17
 * GNU General Public License for more details.
nkeynes@31
    18
 */
nkeynes@35
    19
nkeynes@35
    20
#define MODULE asic_module
nkeynes@35
    21
nkeynes@1
    22
#include <assert.h>
nkeynes@137
    23
#include <stdlib.h>
nkeynes@1
    24
#include "dream.h"
nkeynes@1
    25
#include "mem.h"
nkeynes@1
    26
#include "sh4/intc.h"
nkeynes@56
    27
#include "sh4/dmac.h"
nkeynes@2
    28
#include "dreamcast.h"
nkeynes@25
    29
#include "maple/maple.h"
nkeynes@25
    30
#include "gdrom/ide.h"
nkeynes@15
    31
#include "asic.h"
nkeynes@1
    32
#define MMIO_IMPL
nkeynes@1
    33
#include "asic.h"
nkeynes@1
    34
/*
nkeynes@1
    35
 * Open questions:
nkeynes@1
    36
 *   1) Does changing the mask after event occurance result in the
nkeynes@1
    37
 *      interrupt being delivered immediately?
nkeynes@1
    38
 * TODO: Logic diagram of ASIC event/interrupt logic.
nkeynes@1
    39
 *
nkeynes@1
    40
 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
nkeynes@1
    41
 * practically nothing is publicly known...
nkeynes@1
    42
 */
nkeynes@1
    43
nkeynes@155
    44
static void asic_check_cleared_events( void );
nkeynes@155
    45
static void asic_init( void );
nkeynes@155
    46
static void asic_reset( void );
nkeynes@155
    47
static void asic_save_state( FILE *f );
nkeynes@155
    48
static int asic_load_state( FILE *f );
nkeynes@155
    49
nkeynes@155
    50
struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
nkeynes@155
    51
					NULL, asic_save_state, asic_load_state };
nkeynes@15
    52
nkeynes@137
    53
#define G2_BIT5_TICKS 8
nkeynes@137
    54
#define G2_BIT4_TICKS 16
nkeynes@137
    55
#define G2_BIT0_ON_TICKS 24
nkeynes@137
    56
#define G2_BIT0_OFF_TICKS 24
nkeynes@137
    57
nkeynes@137
    58
struct asic_g2_state {
nkeynes@163
    59
    unsigned int last_update_time;
nkeynes@137
    60
    unsigned int bit5_off_timer;
nkeynes@137
    61
    unsigned int bit4_on_timer;
nkeynes@137
    62
    unsigned int bit4_off_timer;
nkeynes@137
    63
    unsigned int bit0_on_timer;
nkeynes@137
    64
    unsigned int bit0_off_timer;
nkeynes@155
    65
};
nkeynes@155
    66
nkeynes@155
    67
static struct asic_g2_state g2_state;
nkeynes@155
    68
nkeynes@155
    69
static void asic_init( void )
nkeynes@155
    70
{
nkeynes@155
    71
    register_io_region( &mmio_region_ASIC );
nkeynes@155
    72
    register_io_region( &mmio_region_EXTDMA );
nkeynes@155
    73
    asic_reset();
nkeynes@155
    74
}
nkeynes@155
    75
nkeynes@155
    76
static void asic_reset( void )
nkeynes@155
    77
{
nkeynes@155
    78
    memset( &g2_state, 0, sizeof(g2_state) );
nkeynes@155
    79
}    
nkeynes@155
    80
nkeynes@155
    81
static void asic_save_state( FILE *f )
nkeynes@155
    82
{
nkeynes@155
    83
    fwrite( &g2_state, sizeof(g2_state), 1, f );
nkeynes@155
    84
}
nkeynes@155
    85
nkeynes@155
    86
static int asic_load_state( FILE *f )
nkeynes@155
    87
{
nkeynes@155
    88
    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
nkeynes@155
    89
	return 1;
nkeynes@155
    90
    else
nkeynes@155
    91
	return 0;
nkeynes@155
    92
}
nkeynes@155
    93
nkeynes@137
    94
nkeynes@137
    95
/* FIXME: Handle rollover */
nkeynes@137
    96
void asic_g2_write_word()
nkeynes@137
    97
{
nkeynes@163
    98
    g2_state.last_update_time = sh4r.icount;
nkeynes@137
    99
    g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
nkeynes@137
   100
    if( g2_state.bit4_off_timer < sh4r.icount )
nkeynes@137
   101
	g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
nkeynes@137
   102
    g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
nkeynes@137
   103
    if( g2_state.bit0_off_timer < sh4r.icount ) {
nkeynes@137
   104
	g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
nkeynes@137
   105
	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
nkeynes@137
   106
    } else {
nkeynes@137
   107
	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
nkeynes@137
   108
    }
nkeynes@137
   109
    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
nkeynes@137
   110
}
nkeynes@137
   111
nkeynes@137
   112
static uint32_t g2_read_status()
nkeynes@137
   113
{
nkeynes@163
   114
    if( sh4r.icount < g2_state.last_update_time ) {
nkeynes@163
   115
	/* Rollover */
nkeynes@163
   116
	if( g2_state.last_update_time < g2_state.bit5_off_timer )
nkeynes@163
   117
	    g2_state.bit5_off_timer = 0;
nkeynes@163
   118
	if( g2_state.last_update_time < g2_state.bit4_off_timer )
nkeynes@163
   119
	    g2_state.bit4_off_timer = 0;
nkeynes@163
   120
	if( g2_state.last_update_time < g2_state.bit4_on_timer )
nkeynes@163
   121
	    g2_state.bit4_on_timer = 0;
nkeynes@163
   122
	if( g2_state.last_update_time < g2_state.bit0_off_timer )
nkeynes@163
   123
	    g2_state.bit0_off_timer = 0;
nkeynes@163
   124
	if( g2_state.last_update_time < g2_state.bit0_on_timer )
nkeynes@163
   125
	    g2_state.bit0_on_timer = 0;
nkeynes@163
   126
    }
nkeynes@137
   127
    uint32_t val = MMIO_READ( ASIC, G2STATUS );
nkeynes@137
   128
    if( g2_state.bit5_off_timer <= sh4r.icount )
nkeynes@137
   129
	val = val & (~0x20);
nkeynes@163
   130
    if( g2_state.bit4_off_timer <= sh4r.icount ||
nkeynes@163
   131
	(sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
nkeynes@137
   132
	val = val & (~0x10);
nkeynes@137
   133
    else if( g2_state.bit4_on_timer <= sh4r.icount )
nkeynes@137
   134
	val = val | 0x10;
nkeynes@137
   135
    if( g2_state.bit0_off_timer <= sh4r.icount )
nkeynes@137
   136
	val = val & (~0x01);
nkeynes@137
   137
    else if( g2_state.bit0_on_timer <= sh4r.icount )
nkeynes@137
   138
	val = val | 0x01;
nkeynes@137
   139
    return val | 0x0E;
nkeynes@137
   140
}   
nkeynes@137
   141
nkeynes@20
   142
nkeynes@155
   143
void asic_event( int event )
nkeynes@1
   144
{
nkeynes@155
   145
    int offset = ((event&0x60)>>3);
nkeynes@155
   146
    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
nkeynes@155
   147
nkeynes@155
   148
    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
nkeynes@155
   149
        intc_raise_interrupt( INT_IRQ13 );
nkeynes@155
   150
    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
nkeynes@155
   151
        intc_raise_interrupt( INT_IRQ11 );
nkeynes@155
   152
    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
nkeynes@155
   153
        intc_raise_interrupt( INT_IRQ9 );
nkeynes@1
   154
}
nkeynes@1
   155
nkeynes@155
   156
void asic_clear_event( int event ) {
nkeynes@155
   157
    int offset = ((event&0x60)>>3);
nkeynes@155
   158
    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
nkeynes@155
   159
    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
nkeynes@155
   160
nkeynes@155
   161
    asic_check_cleared_events();
nkeynes@155
   162
}
nkeynes@155
   163
nkeynes@155
   164
void asic_check_cleared_events( )
nkeynes@155
   165
{
nkeynes@155
   166
    int i, setA = 0, setB = 0, setC = 0;
nkeynes@155
   167
    uint32_t bits;
nkeynes@155
   168
    for( i=0; i<3; i++ ) {
nkeynes@155
   169
	bits = MMIO_READ( ASIC, PIRQ0 + i );
nkeynes@155
   170
	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
nkeynes@155
   171
	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
nkeynes@155
   172
	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
nkeynes@155
   173
    }
nkeynes@155
   174
    if( setA == 0 )
nkeynes@155
   175
	intc_clear_interrupt( INT_IRQ13 );
nkeynes@155
   176
    if( setB == 0 )
nkeynes@155
   177
	intc_clear_interrupt( INT_IRQ11 );
nkeynes@155
   178
    if( setC == 0 )
nkeynes@155
   179
	intc_clear_interrupt( INT_IRQ9 );
nkeynes@155
   180
}
nkeynes@155
   181
nkeynes@155
   182
nkeynes@155
   183
void asic_ide_dma_transfer( )
nkeynes@155
   184
{	
nkeynes@158
   185
    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
nkeynes@158
   186
	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
nkeynes@158
   187
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
nkeynes@158
   188
	    
nkeynes@158
   189
	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
nkeynes@158
   190
	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
nkeynes@158
   191
	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
nkeynes@158
   192
	    
nkeynes@158
   193
	    uint32_t xfer = ide_read_data_dma( addr, length );
nkeynes@158
   194
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
nkeynes@158
   195
	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
nkeynes@158
   196
	} else { /* 0 */
nkeynes@158
   197
	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
nkeynes@155
   198
	}
nkeynes@155
   199
    }
nkeynes@155
   200
nkeynes@155
   201
}
nkeynes@155
   202
nkeynes@155
   203
nkeynes@1
   204
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
nkeynes@1
   205
{
nkeynes@1
   206
    switch( reg ) {
nkeynes@125
   207
    case PIRQ1:
nkeynes@125
   208
	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
nkeynes@125
   209
	/* fallthrough */
nkeynes@56
   210
    case PIRQ0:
nkeynes@56
   211
    case PIRQ2:
nkeynes@56
   212
	/* Clear any interrupts */
nkeynes@56
   213
	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
nkeynes@56
   214
	asic_check_cleared_events();
nkeynes@56
   215
	break;
nkeynes@56
   216
    case MAPLE_STATE:
nkeynes@56
   217
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   218
	if( val & 1 ) {
nkeynes@56
   219
	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@56
   220
	    maple_handle_buffer( maple_addr );
nkeynes@56
   221
	    MMIO_WRITE( ASIC, reg, 0 );
nkeynes@56
   222
	}
nkeynes@56
   223
	break;
nkeynes@56
   224
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@94
   225
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   226
	if( val & 1 ) {
nkeynes@56
   227
	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
nkeynes@56
   228
	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@56
   229
	    char *data = alloca( count );
nkeynes@56
   230
	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@56
   231
	    if( rcount != count )
nkeynes@56
   232
		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@100
   233
	    mem_copy_to_sh4( dest_addr, data, rcount );
nkeynes@56
   234
	    asic_event( EVENT_PVR_DMA );
nkeynes@186
   235
	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@186
   236
	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@56
   237
	}
nkeynes@56
   238
	break;
nkeynes@158
   239
    case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
nkeynes@158
   240
	MMIO_WRITE( ASIC, reg, val );
nkeynes@158
   241
	break;
nkeynes@56
   242
    default:
nkeynes@56
   243
	MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   244
    }
nkeynes@1
   245
}
nkeynes@1
   246
nkeynes@1
   247
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   248
{
nkeynes@1
   249
    int32_t val;
nkeynes@1
   250
    switch( reg ) {
nkeynes@2
   251
        /*
nkeynes@2
   252
        case 0x89C:
nkeynes@2
   253
            sh4_stop();
nkeynes@2
   254
            return 0x000000B;
nkeynes@2
   255
        */     
nkeynes@94
   256
    case PIRQ0:
nkeynes@94
   257
    case PIRQ1:
nkeynes@94
   258
    case PIRQ2:
nkeynes@94
   259
    case IRQA0:
nkeynes@94
   260
    case IRQA1:
nkeynes@94
   261
    case IRQA2:
nkeynes@94
   262
    case IRQB0:
nkeynes@94
   263
    case IRQB1:
nkeynes@94
   264
    case IRQB2:
nkeynes@94
   265
    case IRQC0:
nkeynes@94
   266
    case IRQC1:
nkeynes@94
   267
    case IRQC2:
nkeynes@158
   268
    case MAPLE_STATE:
nkeynes@94
   269
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   270
	return val;            
nkeynes@94
   271
    case G2STATUS:
nkeynes@137
   272
	return g2_read_status();
nkeynes@94
   273
    default:
nkeynes@94
   274
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   275
	return val;
nkeynes@1
   276
    }
nkeynes@94
   277
    
nkeynes@1
   278
}
nkeynes@1
   279
nkeynes@1
   280
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   281
{
nkeynes@2
   282
    switch( reg ) {
nkeynes@125
   283
    case IDEALTSTATUS: /* Device control */
nkeynes@125
   284
	ide_write_control( val );
nkeynes@125
   285
	break;
nkeynes@125
   286
    case IDEDATA:
nkeynes@125
   287
	ide_write_data_pio( val );
nkeynes@125
   288
	break;
nkeynes@125
   289
    case IDEFEAT:
nkeynes@125
   290
	if( ide_can_write_regs() )
nkeynes@125
   291
	    idereg.feature = (uint8_t)val;
nkeynes@125
   292
	break;
nkeynes@125
   293
    case IDECOUNT:
nkeynes@125
   294
	if( ide_can_write_regs() )
nkeynes@125
   295
	    idereg.count = (uint8_t)val;
nkeynes@125
   296
	break;
nkeynes@125
   297
    case IDELBA0:
nkeynes@125
   298
	if( ide_can_write_regs() )
nkeynes@125
   299
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   300
	break;
nkeynes@125
   301
    case IDELBA1:
nkeynes@125
   302
	if( ide_can_write_regs() )
nkeynes@125
   303
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   304
	break;
nkeynes@125
   305
    case IDELBA2:
nkeynes@125
   306
	if( ide_can_write_regs() )
nkeynes@125
   307
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   308
	break;
nkeynes@125
   309
    case IDEDEV:
nkeynes@125
   310
	if( ide_can_write_regs() )
nkeynes@125
   311
	    idereg.device = (uint8_t)val;
nkeynes@125
   312
	break;
nkeynes@125
   313
    case IDECMD:
nkeynes@125
   314
	if( ide_can_write_regs() ) {
nkeynes@125
   315
	    ide_write_command( (uint8_t)val );
nkeynes@125
   316
	}
nkeynes@125
   317
	break;
nkeynes@125
   318
    case IDEDMACTL1:
nkeynes@155
   319
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@125
   320
    case IDEDMACTL2:
nkeynes@125
   321
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@155
   322
	asic_ide_dma_transfer( );
nkeynes@125
   323
	break;
nkeynes@125
   324
    default:
nkeynes@2
   325
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   326
    }
nkeynes@1
   327
}
nkeynes@1
   328
nkeynes@1
   329
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   330
{
nkeynes@56
   331
    uint32_t val;
nkeynes@1
   332
    switch( reg ) {
nkeynes@158
   333
    case IDEALTSTATUS: 
nkeynes@158
   334
	val = idereg.status;
nkeynes@158
   335
	return val;
nkeynes@158
   336
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   337
    case IDEFEAT: return idereg.error;
nkeynes@158
   338
    case IDECOUNT:return idereg.count;
nkeynes@158
   339
    case IDELBA0: return idereg.disc;
nkeynes@158
   340
    case IDELBA1: return idereg.lba1;
nkeynes@158
   341
    case IDELBA2: return idereg.lba2;
nkeynes@158
   342
    case IDEDEV: return idereg.device;
nkeynes@158
   343
    case IDECMD:
nkeynes@158
   344
	val = ide_read_status();
nkeynes@158
   345
	return val;
nkeynes@158
   346
    default:
nkeynes@158
   347
	val = MMIO_READ( EXTDMA, reg );
nkeynes@158
   348
	return val;
nkeynes@1
   349
    }
nkeynes@1
   350
}
nkeynes@1
   351
.