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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 261:93fdb2a70e18
prev218:cbad5a3f8387
next265:5daf59b7f31b
author nkeynes
date Wed Jan 03 09:01:51 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Implement the main CRTC registers, along with the sync status register.
Timings are now pretty close to the real thing.
file annotate diff log raw
nkeynes@31
     1
/**
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 * $Id: pvr2.c,v 1.34 2007-01-03 09:01:51 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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    26
#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 31945 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gboolean retrace;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    gboolean interlaced;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_state.dot_clock = 27069;
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    pvr2_state.total_lines = pal_timing.total_lines;
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    pvr2_state.line_time_ns = pal_timing.line_time_ns;
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    pvr2_state.front_porch_ns = 12000;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.hsync_width_ns = 4000;
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    pvr2_state.vsync_lines = 5;
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    pvr2_reset();
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    pvr2_ta_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.retrace = FALSE;
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    pvr2_state.timing = ntsc_timing;
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return pvr2_ta_load_state(f);
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_state.line_remainder += nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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	pvr2_state.line_count++;
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	if( pvr2_state.line_count == pvr2_state.total_lines ) {
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	    asic_event( EVENT_RETRACE );
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	    pvr2_state.line_count = 0;
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	    pvr2_state.retrace = TRUE;
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	}
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	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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	    asic_event( EVENT_SCANLINE1 );
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	} 
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	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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	}
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	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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	    if( pvr2_state.retrace ) {
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		pvr2_display_frame();
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		pvr2_state.retrace = FALSE;
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	    }
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	}
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    }
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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						buffer->colour_format );
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	}
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	if( !bEnabled ) {
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	    display_driver->display_blank_frame( 0 );
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	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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	    display_driver->display_blank_frame( colour );
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	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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	    display_driver->display_frame( buffer );
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	}
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    }
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    pvr2_state.frame_count++;
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}
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/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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 */
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        return;
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    }
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    switch(reg) {
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    case PVRID:
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    case PVRVER:
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    case GUNPOS: /* Read only registers */
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	break;
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    case PVRRESET:
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	val &= 0x00000007; /* Do stuff? */
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	MMIO_WRITE( PVR2, reg, val );
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	break;
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    case RENDER_START:
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	if( val == 0xFFFFFFFF || val == 0x00000001 )
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	    pvr2_render_scene();
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	break;
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    case RENDER_POLYBASE:
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    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
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    	break;
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    case RENDER_TSPCFG:
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    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
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    	break;
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   261
    case DISP_BORDER:
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   262
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
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    	break;
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   264
    case DISP_MODE:
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    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
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    	break;
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   267
    case RENDER_MODE:
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    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
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    	break;
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   270
    case RENDER_SIZE:
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   271
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
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    	break;
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   273
    case DISP_ADDR1:
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   274
	val &= 0x00FFFFFC;
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   275
	MMIO_WRITE( PVR2, reg, val );
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   276
	if( pvr2_state.retrace ) {
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   277
	    pvr2_display_frame();
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	    pvr2_state.retrace = FALSE;
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   279
	}
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   280
	break;
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   281
    case DISP_ADDR2:
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   282
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
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   283
    	break;
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   284
    case DISP_SIZE:
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   285
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
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   286
    	break;
nkeynes@191
   287
    case RENDER_ADDR1:
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   288
    case RENDER_ADDR2:
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   289
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   290
    	break;
nkeynes@191
   291
    case RENDER_HCLIP:
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   292
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   293
	break;
nkeynes@191
   294
    case RENDER_VCLIP:
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   295
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   296
	break;
nkeynes@197
   297
    case DISP_HPOSIRQ:
nkeynes@191
   298
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   299
	break;
nkeynes@197
   300
    case DISP_VPOSIRQ:
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   301
	val = val & 0x03FF03FF;
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   302
	pvr2_state.irq_vpos1 = (val >> 16);
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   303
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@189
   304
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   305
	break;
nkeynes@197
   306
    case RENDER_NEARCLIP:
nkeynes@197
   307
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   308
	break;
nkeynes@191
   309
    case RENDER_SHADOW:
nkeynes@191
   310
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   311
	break;
nkeynes@191
   312
    case RENDER_OBJCFG:
nkeynes@191
   313
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   314
    	break;
nkeynes@191
   315
    case RENDER_TSPCLIP:
nkeynes@191
   316
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   317
    	break;
nkeynes@197
   318
    case RENDER_FARCLIP:
nkeynes@197
   319
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   320
	break;
nkeynes@191
   321
    case RENDER_BGPLANE:
nkeynes@191
   322
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   323
    	break;
nkeynes@191
   324
    case RENDER_ISPCFG:
nkeynes@191
   325
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   326
    	break;
nkeynes@197
   327
    case VRAM_CFG1:
nkeynes@197
   328
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   329
	break;
nkeynes@197
   330
    case VRAM_CFG2:
nkeynes@197
   331
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   332
	break;
nkeynes@197
   333
    case VRAM_CFG3:
nkeynes@197
   334
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   335
	break;
nkeynes@197
   336
    case RENDER_FOGTBLCOL:
nkeynes@197
   337
    case RENDER_FOGVRTCOL:
nkeynes@197
   338
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   339
	break;
nkeynes@197
   340
    case RENDER_FOGCOEFF:
nkeynes@197
   341
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   342
	break;
nkeynes@197
   343
    case RENDER_CLAMPHI:
nkeynes@197
   344
    case RENDER_CLAMPLO:
nkeynes@197
   345
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   346
	break;
nkeynes@261
   347
    case RENDER_TEXSIZE:
nkeynes@261
   348
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   349
	break;
nkeynes@261
   350
    case RENDER_PALETTE:
nkeynes@261
   351
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   352
	break;
nkeynes@261
   353
nkeynes@261
   354
	/********** CRTC registers *************/
nkeynes@197
   355
    case DISP_HBORDER:
nkeynes@197
   356
    case DISP_VBORDER:
nkeynes@197
   357
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   358
	break;
nkeynes@261
   359
    case DISP_TOTAL:
nkeynes@261
   360
	val = val & 0x03FF03FF;
nkeynes@261
   361
	MMIO_WRITE( PVR2, reg, val );
nkeynes@261
   362
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   363
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   364
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@261
   365
	break;
nkeynes@261
   366
    case DISP_SYNCCFG:
nkeynes@261
   367
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   368
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   369
	break;
nkeynes@261
   370
    case DISP_SYNCTIME:
nkeynes@261
   371
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@261
   372
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@197
   373
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   374
	break;
nkeynes@197
   375
    case DISP_CFG2:
nkeynes@197
   376
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   377
	break;
nkeynes@197
   378
    case DISP_HPOS:
nkeynes@261
   379
	val = val & 0x03FF;
nkeynes@261
   380
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   381
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   382
	break;
nkeynes@197
   383
    case DISP_VPOS:
nkeynes@197
   384
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   385
	break;
nkeynes@261
   386
nkeynes@261
   387
	/*********** Tile accelerator registers ***********/
nkeynes@261
   388
    case TA_POLYPOS:
nkeynes@261
   389
    case TA_LISTPOS:
nkeynes@261
   390
	/* Readonly registers */
nkeynes@197
   391
	break;
nkeynes@189
   392
    case TA_TILEBASE:
nkeynes@193
   393
    case TA_LISTEND:
nkeynes@189
   394
    case TA_LISTBASE:
nkeynes@191
   395
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   396
	break;
nkeynes@191
   397
    case RENDER_TILEBASE:
nkeynes@189
   398
    case TA_POLYBASE:
nkeynes@189
   399
    case TA_POLYEND:
nkeynes@191
   400
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   401
	break;
nkeynes@189
   402
    case TA_TILESIZE:
nkeynes@191
   403
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   404
	break;
nkeynes@189
   405
    case TA_TILECFG:
nkeynes@191
   406
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   407
	break;
nkeynes@261
   408
    case TA_INIT:
nkeynes@261
   409
	if( val & 0x80000000 )
nkeynes@261
   410
	    pvr2_ta_init();
nkeynes@261
   411
	break;
nkeynes@261
   412
    case TA_REINIT:
nkeynes@261
   413
	break;
nkeynes@261
   414
	/**************** Scaler registers? ****************/
nkeynes@261
   415
    case SCALERCFG:
nkeynes@261
   416
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   417
	break;
nkeynes@261
   418
nkeynes@197
   419
    case YUV_ADDR:
nkeynes@197
   420
	MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
nkeynes@197
   421
	break;
nkeynes@197
   422
    case YUV_CFG:
nkeynes@197
   423
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@197
   424
	break;
nkeynes@261
   425
nkeynes@261
   426
nkeynes@261
   427
	/**************** Unknowns ***************/
nkeynes@261
   428
    case PVRUNK1:
nkeynes@261
   429
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   430
    	break;
nkeynes@261
   431
    case PVRUNK2:
nkeynes@261
   432
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   433
	break;
nkeynes@261
   434
    case PVRUNK3:
nkeynes@261
   435
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   436
	break;
nkeynes@261
   437
    case PVRUNK5:
nkeynes@261
   438
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   439
	break;
nkeynes@261
   440
    case PVRUNK6:
nkeynes@261
   441
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   442
	break;
nkeynes@197
   443
    case PVRUNK7:
nkeynes@197
   444
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   445
	break;
nkeynes@1
   446
    }
nkeynes@1
   447
}
nkeynes@1
   448
nkeynes@261
   449
/**
nkeynes@261
   450
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   451
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   452
 * The register reads (LSB to MSB) as:
nkeynes@261
   453
 *     0..9  Current scan line
nkeynes@261
   454
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   455
 *     11    Display active (including border and overscan)
nkeynes@261
   456
 *     12    Horizontal sync off
nkeynes@261
   457
 *     13    Vertical sync off
nkeynes@261
   458
 * Note this method is probably incorrect for anything other than straight
nkeynes@261
   459
 * interlaced PAL, and needs further testing.
nkeynes@261
   460
 */
nkeynes@261
   461
uint32_t pvr2_get_sync_status()
nkeynes@261
   462
{
nkeynes@261
   463
    uint32_t tmp = pvr2_state.line_remainder + sh4r.slice_cycle;
nkeynes@261
   464
    uint32_t line = pvr2_state.line_count + (tmp / pvr2_state.line_time_ns);
nkeynes@261
   465
    uint32_t remainder = tmp % pvr2_state.line_time_ns;
nkeynes@261
   466
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@261
   467
    uint32_t result;
nkeynes@261
   468
nkeynes@261
   469
    if( line >= pvr2_state.total_lines ) {
nkeynes@261
   470
	line -= pvr2_state.total_lines;
nkeynes@261
   471
	if( pvr2_state.interlaced ) {
nkeynes@261
   472
	    field == 1 ? 0 : 1;
nkeynes@261
   473
	}
nkeynes@261
   474
    }
nkeynes@261
   475
nkeynes@261
   476
    result = line;
nkeynes@261
   477
nkeynes@261
   478
    if( field ) {
nkeynes@261
   479
	result |= 0x0400;
nkeynes@261
   480
    }
nkeynes@261
   481
    if( (line & 0x01) == field ) {
nkeynes@261
   482
	if( remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   483
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   484
	}
nkeynes@261
   485
	if( line >= pvr2_state.vsync_lines ) {
nkeynes@261
   486
	    if( remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   487
		result |= 0x2800; /* Display active */
nkeynes@261
   488
	    } else {
nkeynes@261
   489
		result |= 0x2000; /* Front porch */
nkeynes@261
   490
	    }
nkeynes@261
   491
	}
nkeynes@261
   492
    } else {
nkeynes@261
   493
	if( remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns) &&
nkeynes@261
   494
	    line >= pvr2_state.vsync_lines ) {
nkeynes@261
   495
	    result |= 0x3800; /* Display active */
nkeynes@261
   496
	} else {
nkeynes@261
   497
	    result |= 0x1000; /* Back porch */
nkeynes@261
   498
	}
nkeynes@261
   499
    }
nkeynes@261
   500
    return result;
nkeynes@261
   501
}
nkeynes@261
   502
nkeynes@1
   503
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   504
{
nkeynes@1
   505
    switch( reg ) {
nkeynes@261
   506
        case DISP_SYNCSTAT:
nkeynes@261
   507
            return pvr2_get_sync_status();
nkeynes@1
   508
        default:
nkeynes@1
   509
            return MMIO_READ( PVR2, reg );
nkeynes@1
   510
    }
nkeynes@1
   511
}
nkeynes@19
   512
nkeynes@85
   513
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   514
nkeynes@19
   515
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   516
{
nkeynes@197
   517
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   518
}
nkeynes@56
   519
nkeynes@56
   520
nkeynes@65
   521
nkeynes@98
   522
nkeynes@56
   523
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   524
{
nkeynes@56
   525
    return 0xFFFFFFFF;
nkeynes@56
   526
}
nkeynes@56
   527
nkeynes@56
   528
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   529
{
nkeynes@189
   530
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   531
}
nkeynes@56
   532
nkeynes@85
   533
nkeynes@103
   534
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   535
{
nkeynes@103
   536
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   537
    uint32_t *banks[2];
nkeynes@103
   538
    uint32_t *dwsrc;
nkeynes@103
   539
    int i;
nkeynes@65
   540
nkeynes@103
   541
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   542
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   543
	length = 0x800000 - destaddr;
nkeynes@103
   544
    }
nkeynes@103
   545
nkeynes@103
   546
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   547
	texcache_invalidate_page( i );
nkeynes@103
   548
    }
nkeynes@103
   549
nkeynes@108
   550
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
nkeynes@103
   551
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   552
    if( bank_flag ) 
nkeynes@108
   553
	banks[0]++;
nkeynes@103
   554
    
nkeynes@103
   555
    /* Handle non-aligned start of source */
nkeynes@103
   556
    if( destaddr & 0x03 ) {
nkeynes@103
   557
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   558
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   559
	    *dest++ = *src++;
nkeynes@103
   560
	}
nkeynes@103
   561
	bank_flag = !bank_flag;
nkeynes@103
   562
    }
nkeynes@103
   563
nkeynes@103
   564
    dwsrc = (uint32_t *)src;
nkeynes@103
   565
    while( length >= 4 ) {
nkeynes@103
   566
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   567
	bank_flag = !bank_flag;
nkeynes@103
   568
	length -= 4;
nkeynes@103
   569
    }
nkeynes@103
   570
    
nkeynes@103
   571
    /* Handle non-aligned end of source */
nkeynes@103
   572
    if( length ) {
nkeynes@103
   573
	src = (char *)dwsrc;
nkeynes@103
   574
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   575
	while( length-- > 0 ) {
nkeynes@103
   576
	    *dest++ = *src++;
nkeynes@103
   577
	}
nkeynes@103
   578
    }  
nkeynes@218
   579
}
nkeynes@103
   580
nkeynes@218
   581
void pvr2_vram_write_invert( sh4addr_t destaddr, char *src, uint32_t length, uint32_t line_length )
nkeynes@218
   582
{
nkeynes@218
   583
    char *dest = video_base + (destaddr & 0x007FFFFF);
nkeynes@218
   584
    char *p = src + length - line_length;
nkeynes@218
   585
    while( p >= src ) {
nkeynes@218
   586
	memcpy( dest, p, line_length );
nkeynes@218
   587
	p -= line_length;
nkeynes@218
   588
	dest += line_length;
nkeynes@218
   589
    }
nkeynes@103
   590
}
nkeynes@103
   591
nkeynes@103
   592
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   593
{
nkeynes@103
   594
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   595
    uint32_t *banks[2];
nkeynes@103
   596
    uint32_t *dwdest;
nkeynes@103
   597
    int i;
nkeynes@103
   598
nkeynes@103
   599
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   600
    if( srcaddr + length > 0x800000 )
nkeynes@103
   601
	length = 0x800000 - srcaddr;
nkeynes@103
   602
nkeynes@108
   603
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   604
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   605
    if( bank_flag )
nkeynes@108
   606
	banks[0]++;
nkeynes@103
   607
    
nkeynes@103
   608
    /* Handle non-aligned start of source */
nkeynes@103
   609
    if( srcaddr & 0x03 ) {
nkeynes@103
   610
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   611
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   612
	    *dest++ = *src++;
nkeynes@103
   613
	}
nkeynes@103
   614
	bank_flag = !bank_flag;
nkeynes@103
   615
    }
nkeynes@103
   616
nkeynes@103
   617
    dwdest = (uint32_t *)dest;
nkeynes@103
   618
    while( length >= 4 ) {
nkeynes@103
   619
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   620
	bank_flag = !bank_flag;
nkeynes@103
   621
	length -= 4;
nkeynes@103
   622
    }
nkeynes@103
   623
    
nkeynes@103
   624
    /* Handle non-aligned end of source */
nkeynes@103
   625
    if( length ) {
nkeynes@103
   626
	dest = (char *)dwdest;
nkeynes@103
   627
	char *src = (char *)banks[bank_flag];
nkeynes@103
   628
	while( length-- > 0 ) {
nkeynes@103
   629
	    *dest++ = *src++;
nkeynes@103
   630
	}
nkeynes@103
   631
    }
nkeynes@103
   632
}
nkeynes@127
   633
nkeynes@127
   634
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   635
{
nkeynes@127
   636
    char tmp[length];
nkeynes@127
   637
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   638
    fwrite_dump( tmp, length, f );
nkeynes@127
   639
}
.