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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 302:96b5cc24309c
prev279:7bb759c23271
next305:1191085c5988
author nkeynes
date Wed Jan 17 21:27:20 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Rename SPUDMA to G2DMA (following KOS's lead)
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
file annotate diff log raw
nkeynes@31
     1
/**
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 * $Id: asic.c,v 1.24 2007-01-17 21:27:20 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static uint32_t asic_run_slice( uint32_t nanosecs );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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					NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 60
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#define G2_BIT4_TICKS 160
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#define G2_BIT0_ON_TICKS 120
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#define G2_BIT0_OFF_TICKS 420
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struct asic_g2_state {
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    int bit5_off_timer;
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    int bit4_on_timer;
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    int bit4_off_timer;
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    int bit0_on_timer;
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    int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static uint32_t asic_run_slice( uint32_t nanosecs )
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{
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    g2_update_fifo_status(nanosecs);
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    if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit5_off_timer = -1;
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    } else {
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	g2_state.bit5_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_off_timer = -1;
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    } else {
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	g2_state.bit4_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_on_timer = -1;
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    } else {
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	g2_state.bit4_on_timer -= nanosecs;
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    }
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    if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_off_timer = -1;
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    } else {
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	g2_state.bit0_off_timer -= nanosecs;
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    }
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    if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_on_timer = -1;
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    } else {
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	g2_state.bit0_on_timer -= nanosecs;
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    }
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    return nanosecs;
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}
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0xFF, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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	return 1;
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    else
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	return 0;
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}
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/**
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 * Setup the timers for the 3 FIFO status bits following a write through the G2
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 * bus from the SH4 side. The timing is roughly as follows: (times are
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 * approximate based on software readings - I wouldn't take this as gospel but
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 * it seems to be enough to fool most programs). 
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 *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
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 *   40ns: Bit 5 goes low and bit 4 goes high
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 *  120ns: Bit 4 goes low, bit 0 goes high
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 *  240ns: Bit 0 goes low.
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 *
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 * Additional writes while the FIFO is in operation extend the time that the
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 * bits remain high as one might expect, without altering the time at which
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 * they initially go high.
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 */
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void asic_g2_write_word()
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{
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    if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    } else {
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	g2_state.bit5_off_timer += G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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    } else {
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	g2_state.bit4_off_timer += G2_BIT4_TICKS;
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    }
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    if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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    }
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    if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_update_fifo_status( uint32_t nanos )
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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	val = val & (~0x20);
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	g2_state.bit5_off_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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	val = val | 0x10;
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	g2_state.bit4_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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	val = val & (~0x10);
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	g2_state.bit4_off_timer = -1;
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    } 
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    if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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	val = val | 0x01;
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	g2_state.bit0_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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	val = val & (~0x01);
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	g2_state.bit0_off_timer = -1;
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    } 
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    MMIO_WRITE( ASIC, G2STATUS, val );
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    return val;
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}   
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static int g2_read_status() {
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    return g2_update_fifo_status( sh4r.slice_cycle );
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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{
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    uint32_t offset = channel << 5;
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    if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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	if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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	    uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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	    uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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	    uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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	    uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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	    uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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	    char buf[length];
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	    if( dir == 0 ) { /* SH4 to device */
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		mem_copy_from_sh4( buf, sh4addr, length );
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		mem_copy_to_sh4( extaddr, buf, length );
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	    } else { /* Device to SH4 */
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		mem_copy_from_sh4( buf, extaddr, length );
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		mem_copy_to_sh4( sh4addr, buf, length );
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	    }
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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	    asic_event( EVENT_G2_DMA0 + channel );
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	} else {
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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   271
	}
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    }
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   273
}
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void asic_ide_dma_transfer( )
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{	
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   277
    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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   278
	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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   279
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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   280
	    
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	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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   283
	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
nkeynes@158
   284
	    
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	    uint32_t xfer = ide_read_data_dma( addr, length );
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   286
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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	} else { /* 0 */
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	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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	}
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   291
    }
nkeynes@155
   292
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   293
}
nkeynes@155
   294
nkeynes@155
   295
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   296
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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   297
{
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   298
    switch( reg ) {
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   299
    case PIRQ1:
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   300
	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
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	/* fallthrough */
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    case PIRQ0:
nkeynes@56
   303
    case PIRQ2:
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	/* Clear any interrupts */
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   305
	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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   306
	asic_check_cleared_events();
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   307
	break;
nkeynes@244
   308
    case SYSRESET:
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   309
	if( val == 0x7611 ) {
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   310
	    dreamcast_reset();
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   311
	    sh4r.new_pc = sh4r.pc;
nkeynes@244
   312
	} else {
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   313
	    WARN( "Unknown value %08X written to SYSRESET port", val );
nkeynes@244
   314
	}
nkeynes@244
   315
	break;
nkeynes@56
   316
    case MAPLE_STATE:
nkeynes@56
   317
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   318
	if( val & 1 ) {
nkeynes@56
   319
	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@56
   320
	    maple_handle_buffer( maple_addr );
nkeynes@56
   321
	    MMIO_WRITE( ASIC, reg, 0 );
nkeynes@56
   322
	}
nkeynes@56
   323
	break;
nkeynes@56
   324
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@94
   325
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   326
	if( val & 1 ) {
nkeynes@56
   327
	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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   328
	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@56
   329
	    char *data = alloca( count );
nkeynes@56
   330
	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@56
   331
	    if( rcount != count )
nkeynes@56
   332
		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@100
   333
	    mem_copy_to_sh4( dest_addr, data, rcount );
nkeynes@56
   334
	    asic_event( EVENT_PVR_DMA );
nkeynes@186
   335
	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@186
   336
	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@56
   337
	}
nkeynes@56
   338
	break;
nkeynes@158
   339
    case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
nkeynes@158
   340
	MMIO_WRITE( ASIC, reg, val );
nkeynes@158
   341
	break;
nkeynes@56
   342
    default:
nkeynes@56
   343
	MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   344
    }
nkeynes@1
   345
}
nkeynes@1
   346
nkeynes@1
   347
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   348
{
nkeynes@1
   349
    int32_t val;
nkeynes@1
   350
    switch( reg ) {
nkeynes@2
   351
        /*
nkeynes@2
   352
        case 0x89C:
nkeynes@2
   353
            sh4_stop();
nkeynes@2
   354
            return 0x000000B;
nkeynes@2
   355
        */     
nkeynes@94
   356
    case PIRQ0:
nkeynes@94
   357
    case PIRQ1:
nkeynes@94
   358
    case PIRQ2:
nkeynes@94
   359
    case IRQA0:
nkeynes@94
   360
    case IRQA1:
nkeynes@94
   361
    case IRQA2:
nkeynes@94
   362
    case IRQB0:
nkeynes@94
   363
    case IRQB1:
nkeynes@94
   364
    case IRQB2:
nkeynes@94
   365
    case IRQC0:
nkeynes@94
   366
    case IRQC1:
nkeynes@94
   367
    case IRQC2:
nkeynes@158
   368
    case MAPLE_STATE:
nkeynes@94
   369
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   370
	return val;            
nkeynes@94
   371
    case G2STATUS:
nkeynes@137
   372
	return g2_read_status();
nkeynes@94
   373
    default:
nkeynes@94
   374
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   375
	return val;
nkeynes@1
   376
    }
nkeynes@94
   377
    
nkeynes@1
   378
}
nkeynes@1
   379
nkeynes@1
   380
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   381
{
nkeynes@244
   382
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   383
	return; /* disabled */
nkeynes@244
   384
    }
nkeynes@244
   385
nkeynes@2
   386
    switch( reg ) {
nkeynes@125
   387
    case IDEALTSTATUS: /* Device control */
nkeynes@125
   388
	ide_write_control( val );
nkeynes@125
   389
	break;
nkeynes@125
   390
    case IDEDATA:
nkeynes@125
   391
	ide_write_data_pio( val );
nkeynes@125
   392
	break;
nkeynes@125
   393
    case IDEFEAT:
nkeynes@125
   394
	if( ide_can_write_regs() )
nkeynes@125
   395
	    idereg.feature = (uint8_t)val;
nkeynes@125
   396
	break;
nkeynes@125
   397
    case IDECOUNT:
nkeynes@125
   398
	if( ide_can_write_regs() )
nkeynes@125
   399
	    idereg.count = (uint8_t)val;
nkeynes@125
   400
	break;
nkeynes@125
   401
    case IDELBA0:
nkeynes@125
   402
	if( ide_can_write_regs() )
nkeynes@125
   403
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   404
	break;
nkeynes@125
   405
    case IDELBA1:
nkeynes@125
   406
	if( ide_can_write_regs() )
nkeynes@125
   407
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   408
	break;
nkeynes@125
   409
    case IDELBA2:
nkeynes@125
   410
	if( ide_can_write_regs() )
nkeynes@125
   411
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   412
	break;
nkeynes@125
   413
    case IDEDEV:
nkeynes@125
   414
	if( ide_can_write_regs() )
nkeynes@125
   415
	    idereg.device = (uint8_t)val;
nkeynes@125
   416
	break;
nkeynes@125
   417
    case IDECMD:
nkeynes@240
   418
	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@125
   419
	    ide_write_command( (uint8_t)val );
nkeynes@125
   420
	}
nkeynes@125
   421
	break;
nkeynes@125
   422
    case IDEDMACTL1:
nkeynes@125
   423
    case IDEDMACTL2:
nkeynes@125
   424
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@155
   425
	asic_ide_dma_transfer( );
nkeynes@125
   426
	break;
nkeynes@244
   427
    case IDEACTIVATE:
nkeynes@244
   428
	if( val == 0x001FFFFF ) {
nkeynes@244
   429
	    idereg.interface_enabled = TRUE;
nkeynes@244
   430
	    /* Conventional wisdom says that this is necessary but not
nkeynes@244
   431
	     * sufficient to enable the IDE interface.
nkeynes@244
   432
	     */
nkeynes@244
   433
	} else if( val == 0x000042FE ) {
nkeynes@244
   434
	    idereg.interface_enabled = FALSE;
nkeynes@244
   435
	}
nkeynes@279
   436
	break;
nkeynes@302
   437
    case G2DMA0CTL1:
nkeynes@302
   438
    case G2DMA0CTL2:
nkeynes@279
   439
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   440
	g2_dma_transfer( 0 );
nkeynes@279
   441
	break;
nkeynes@302
   442
    case G2DMA0STOP:
nkeynes@279
   443
	break;
nkeynes@302
   444
    case G2DMA1CTL1:
nkeynes@302
   445
    case G2DMA1CTL2:
nkeynes@279
   446
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   447
	g2_dma_transfer( 1 );
nkeynes@279
   448
	break;
nkeynes@279
   449
nkeynes@302
   450
    case G2DMA1STOP:
nkeynes@279
   451
	break;
nkeynes@302
   452
    case G2DMA2CTL1:
nkeynes@302
   453
    case G2DMA2CTL2:
nkeynes@279
   454
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   455
	g2_dma_transfer( 2 );
nkeynes@279
   456
	break;
nkeynes@302
   457
    case G2DMA2STOP:
nkeynes@279
   458
	break;
nkeynes@302
   459
    case G2DMA3CTL1:
nkeynes@302
   460
    case G2DMA3CTL2:
nkeynes@279
   461
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   462
	g2_dma_transfer( 3 );
nkeynes@279
   463
	break;
nkeynes@302
   464
    case G2DMA3STOP:
nkeynes@279
   465
	break;
nkeynes@279
   466
    case PVRDMA2CTL1:
nkeynes@279
   467
    case PVRDMA2CTL2:
nkeynes@279
   468
	if( val != 0 ) {
nkeynes@279
   469
	    ERROR( "Write to unimplemented DMA control register %08X", reg );
nkeynes@279
   470
	    //dreamcast_stop();
nkeynes@279
   471
	    //sh4_stop();
nkeynes@279
   472
	}
nkeynes@279
   473
	break;
nkeynes@125
   474
    default:
nkeynes@2
   475
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   476
    }
nkeynes@1
   477
}
nkeynes@1
   478
nkeynes@1
   479
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   480
{
nkeynes@56
   481
    uint32_t val;
nkeynes@244
   482
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   483
	return 0xFFFFFFFF; /* disabled */
nkeynes@244
   484
    }
nkeynes@244
   485
nkeynes@1
   486
    switch( reg ) {
nkeynes@158
   487
    case IDEALTSTATUS: 
nkeynes@158
   488
	val = idereg.status;
nkeynes@158
   489
	return val;
nkeynes@158
   490
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   491
    case IDEFEAT: return idereg.error;
nkeynes@158
   492
    case IDECOUNT:return idereg.count;
nkeynes@158
   493
    case IDELBA0: return idereg.disc;
nkeynes@158
   494
    case IDELBA1: return idereg.lba1;
nkeynes@158
   495
    case IDELBA2: return idereg.lba2;
nkeynes@158
   496
    case IDEDEV: return idereg.device;
nkeynes@158
   497
    case IDECMD:
nkeynes@158
   498
	val = ide_read_status();
nkeynes@158
   499
	return val;
nkeynes@158
   500
    default:
nkeynes@158
   501
	val = MMIO_READ( EXTDMA, reg );
nkeynes@158
   502
	return val;
nkeynes@1
   503
    }
nkeynes@1
   504
}
nkeynes@1
   505
.