Search
lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.h
changeset 302:96b5cc24309c
prev265:5daf59b7f31b
next312:2c34bdc36cbd
author nkeynes
date Wed Jan 17 21:27:20 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Rename SPUDMA to G2DMA (following KOS's lead)
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
file annotate diff log raw
nkeynes@10
     1
/**
nkeynes@302
     2
 * $Id: sh4core.h,v 1.17 2007-01-17 21:27:20 nkeynes Exp $
nkeynes@10
     3
 * 
nkeynes@54
     4
 * This file defines the internal functions exported/used by the SH4 core, 
nkeynes@54
     5
 * except for disassembly functions defined in sh4dasm.h
nkeynes@10
     6
 *
nkeynes@10
     7
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@10
     8
 *
nkeynes@10
     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@10
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@10
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@10
    12
 * (at your option) any later version.
nkeynes@10
    13
 *
nkeynes@10
    14
 * This program is distributed in the hope that it will be useful,
nkeynes@10
    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@10
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@10
    17
 * GNU General Public License for more details.
nkeynes@1
    18
 */
nkeynes@30
    19
nkeynes@1
    20
#ifndef sh4core_H
nkeynes@1
    21
#define sh4core_H 1
nkeynes@1
    22
nkeynes@27
    23
#include <glib/gtypes.h>
nkeynes@1
    24
#include <stdint.h>
nkeynes@23
    25
#include <stdio.h>
nkeynes@1
    26
nkeynes@1
    27
#ifdef __cplusplus
nkeynes@1
    28
extern "C" {
nkeynes@1
    29
#if 0
nkeynes@1
    30
}
nkeynes@1
    31
#endif
nkeynes@1
    32
#endif
nkeynes@1
    33
nkeynes@27
    34
nkeynes@27
    35
/**
nkeynes@27
    36
 * SH4 is running normally 
nkeynes@27
    37
 */
nkeynes@27
    38
#define SH4_STATE_RUNNING 1
nkeynes@27
    39
/**
nkeynes@27
    40
 * SH4 is not executing instructions but all peripheral modules are still
nkeynes@27
    41
 * running
nkeynes@27
    42
 */
nkeynes@27
    43
#define SH4_STATE_SLEEP 2
nkeynes@27
    44
/**
nkeynes@27
    45
 * SH4 is not executing instructions, DMAC is halted, but all other peripheral
nkeynes@27
    46
 * modules are still running
nkeynes@27
    47
 */
nkeynes@27
    48
#define SH4_STATE_DEEP_SLEEP 3
nkeynes@27
    49
/**
nkeynes@27
    50
 * SH4 is not executing instructions and all peripheral modules are also
nkeynes@27
    51
 * stopped. As close as you can get to powered-off without actually being
nkeynes@27
    52
 * off.
nkeynes@27
    53
 */
nkeynes@27
    54
#define SH4_STATE_STANDBY 4
nkeynes@27
    55
nkeynes@265
    56
#define PENDING_IRQ 1
nkeynes@265
    57
#define PENDING_EVENT 2
nkeynes@265
    58
nkeynes@1
    59
struct sh4_registers {
nkeynes@1
    60
    uint32_t r[16];
nkeynes@1
    61
    uint32_t r_bank[8]; /* hidden banked registers */
nkeynes@1
    62
    uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
nkeynes@84
    63
    uint32_t pr, pc, fpscr;
nkeynes@84
    64
    int32_t fpul;
nkeynes@1
    65
    uint64_t mac;
nkeynes@1
    66
    uint32_t m, q, s, t; /* really boolean - 0 or 1 */
nkeynes@1
    67
    float fr[2][16];
nkeynes@1
    68
nkeynes@2
    69
    int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
nkeynes@2
    70
    
nkeynes@1
    71
    uint32_t new_pc; /* Not a real register, but used to handle delay slots */
nkeynes@265
    72
    uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
nkeynes@265
    73
                             when no events are pending */
nkeynes@265
    74
    uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
nkeynes@2
    75
    int in_delay_slot; /* flag to indicate the current instruction is in
nkeynes@2
    76
                             * a delay slot (certain rules apply) */
nkeynes@302
    77
    uint32_t slice_cycle; /* Current nanosecond within the timeslice */
nkeynes@27
    78
    int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
nkeynes@1
    79
};
nkeynes@1
    80
nkeynes@1
    81
extern struct sh4_registers sh4r;
nkeynes@1
    82
nkeynes@1
    83
/* Public functions */
nkeynes@1
    84
nkeynes@1
    85
void sh4_init( void );
nkeynes@1
    86
void sh4_reset( void );
nkeynes@1
    87
void sh4_run( void );
nkeynes@1
    88
void sh4_runto( uint32_t pc, uint32_t count );
nkeynes@1
    89
void sh4_runfor( uint32_t count );
nkeynes@1
    90
int sh4_isrunning( void );
nkeynes@1
    91
void sh4_stop( void );
nkeynes@1
    92
void sh4_set_pc( int );
nkeynes@27
    93
gboolean sh4_execute_instruction( void );
nkeynes@246
    94
gboolean sh4_raise_exception( int );
nkeynes@246
    95
gboolean sh4_raise_slot_exception( int, int );
nkeynes@246
    96
gboolean sh4_raise_tlb_exception( int );
nkeynes@23
    97
void sh4_set_breakpoint( uint32_t pc, int type );
nkeynes@43
    98
gboolean sh4_clear_breakpoint( uint32_t pc, int type );
nkeynes@43
    99
int sh4_get_breakpoint( uint32_t pc );
nkeynes@23
   100
nkeynes@23
   101
#define BREAK_ONESHOT 1
nkeynes@23
   102
#define BREAK_PERM 2
nkeynes@1
   103
nkeynes@10
   104
/* SH4 Memory */
nkeynes@10
   105
int32_t sh4_read_long( uint32_t addr );
nkeynes@10
   106
int32_t sh4_read_word( uint32_t addr );
nkeynes@10
   107
int32_t sh4_read_byte( uint32_t addr );
nkeynes@10
   108
void sh4_write_long( uint32_t addr, uint32_t val );
nkeynes@10
   109
void sh4_write_word( uint32_t addr, uint32_t val );
nkeynes@10
   110
void sh4_write_byte( uint32_t addr, uint32_t val );
nkeynes@10
   111
int32_t sh4_read_phys_word( uint32_t addr );
nkeynes@10
   112
nkeynes@23
   113
/* Peripheral functions */
nkeynes@260
   114
void CPG_reset( void );
nkeynes@30
   115
void TMU_run_slice( uint32_t );
nkeynes@53
   116
void TMU_update_clocks( void );
nkeynes@53
   117
void TMU_reset( void );
nkeynes@53
   118
void TMU_save_state( FILE * );
nkeynes@53
   119
int TMU_load_state( FILE * );
nkeynes@54
   120
void DMAC_reset( void );
nkeynes@54
   121
void DMAC_run_slice( uint32_t );
nkeynes@54
   122
void DMAC_save_state( FILE * );
nkeynes@54
   123
int DMAC_load_state( FILE * );
nkeynes@32
   124
void SCIF_reset( void );
nkeynes@30
   125
void SCIF_run_slice( uint32_t );
nkeynes@23
   126
void SCIF_save_state( FILE *f );
nkeynes@23
   127
int SCIF_load_state( FILE *f );
nkeynes@157
   128
void INTC_reset( void );
nkeynes@157
   129
void INTC_save_state( FILE *f );
nkeynes@157
   130
int INTC_load_state( FILE *f );
nkeynes@1
   131
nkeynes@1
   132
#define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
nkeynes@1
   133
#define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
nkeynes@1
   134
#define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
nkeynes@1
   135
#define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
nkeynes@1
   136
#define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
nkeynes@1
   137
#define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
nkeynes@1
   138
nkeynes@1
   139
/* Status Register (SR) bits */
nkeynes@1
   140
#define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
nkeynes@1
   141
#define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
nkeynes@1
   142
#define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
nkeynes@1
   143
#define SR_FD    0x00008000 /* FPU disable */
nkeynes@1
   144
#define SR_M     0x00000200
nkeynes@1
   145
#define SR_Q     0x00000100
nkeynes@1
   146
#define SR_IMASK 0x000000F0 /* Interrupt mask level */
nkeynes@1
   147
#define SR_S     0x00000002 /* Saturation operation for MAC instructions */
nkeynes@1
   148
#define SR_T     0x00000001 /* True/false or carry/borrow */
nkeynes@1
   149
#define SR_MASK  0x700083F3
nkeynes@1
   150
#define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
nkeynes@1
   151
nkeynes@1
   152
#define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
nkeynes@1
   153
#define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
nkeynes@265
   154
#define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
nkeynes@1
   155
nkeynes@1
   156
#define FPSCR_FR     0x00200000 /* FPU register bank */
nkeynes@1
   157
#define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
nkeynes@1
   158
#define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
nkeynes@1
   159
#define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
nkeynes@1
   160
#define FPSCR_CAUSE  0x0003F000
nkeynes@1
   161
#define FPSCR_ENABLE 0x00000F80
nkeynes@1
   162
#define FPSCR_FLAG   0x0000007C
nkeynes@1
   163
#define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
nkeynes@1
   164
nkeynes@1
   165
#define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
nkeynes@1
   166
#define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
nkeynes@1
   167
#define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
nkeynes@1
   168
nkeynes@84
   169
#define FR(x) sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][(x)^1]
nkeynes@84
   170
#define DR(x) ((double *)(sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]))[x]
nkeynes@84
   171
#define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
nkeynes@95
   172
#define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
nkeynes@95
   173
#define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
nkeynes@1
   174
/* Exceptions (for use with sh4_raise_exception) */
nkeynes@1
   175
nkeynes@1
   176
#define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
nkeynes@1
   177
#define EX_SLOT_ILLEGAL        0x1A0, 0x100
nkeynes@1
   178
#define EX_TLB_MISS_READ       0x040, 0x400
nkeynes@1
   179
#define EX_TLB_MISS_WRITE      0x060, 0x400
nkeynes@1
   180
#define EX_INIT_PAGE_WRITE     0x080, 0x100
nkeynes@1
   181
#define EX_TLB_PROT_READ       0x0A0, 0x100
nkeynes@1
   182
#define EX_TLB_PROT_WRITE      0x0C0, 0x100
nkeynes@1
   183
#define EX_DATA_ADDR_READ      0x0E0, 0x100
nkeynes@1
   184
#define EX_DATA_ADDR_WRITE     0x100, 0x100
nkeynes@1
   185
#define EX_FPU_EXCEPTION       0x120, 0x100
nkeynes@1
   186
#define EX_TRAPA               0x160, 0x100
nkeynes@1
   187
#define EX_BREAKPOINT          0x1E0, 0x100
nkeynes@1
   188
#define EX_FPU_DISABLED        0x800, 0x100
nkeynes@1
   189
#define EX_SLOT_FPU_DISABLED   0x820, 0x100
nkeynes@1
   190
nkeynes@2
   191
#define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
nkeynes@1
   192
nkeynes@1
   193
#ifdef __cplusplus
nkeynes@1
   194
}
nkeynes@1
   195
#endif
nkeynes@1
   196
#endif
.