Search
lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.c
changeset 571:9bc09948d0f2
prev570:d2893980fbf5
next577:a181aeacd6e8
author nkeynes
date Thu Jan 10 08:28:37 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change More MMU work in progess. Much better now...
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@561
     2
 * $Id$
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359
    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359
    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@368
    21
#include <assert.h>
nkeynes@388
    22
#include <math.h>
nkeynes@368
    23
nkeynes@380
    24
#ifndef NDEBUG
nkeynes@380
    25
#define DEBUG_JUMPS 1
nkeynes@380
    26
#endif
nkeynes@380
    27
nkeynes@417
    28
#include "sh4/xltcache.h"
nkeynes@368
    29
#include "sh4/sh4core.h"
nkeynes@368
    30
#include "sh4/sh4trans.h"
nkeynes@388
    31
#include "sh4/sh4mmio.h"
nkeynes@368
    32
#include "sh4/x86op.h"
nkeynes@368
    33
#include "clock.h"
nkeynes@368
    34
nkeynes@368
    35
#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368
    36
nkeynes@559
    37
struct backpatch_record {
nkeynes@559
    38
    uint32_t *fixup_addr;
nkeynes@559
    39
    uint32_t fixup_icount;
nkeynes@559
    40
    uint32_t exc_code;
nkeynes@559
    41
};
nkeynes@559
    42
nkeynes@571
    43
#define MAX_RECOVERY_SIZE 2048
nkeynes@571
    44
nkeynes@368
    45
/** 
nkeynes@368
    46
 * Struct to manage internal translation state. This state is not saved -
nkeynes@368
    47
 * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368
    48
 * sh4_translate_end_block()
nkeynes@368
    49
 */
nkeynes@368
    50
struct sh4_x86_state {
nkeynes@368
    51
    gboolean in_delay_slot;
nkeynes@368
    52
    gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368
    53
    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409
    54
    gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@408
    55
    uint32_t block_start_pc;
nkeynes@547
    56
    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
nkeynes@417
    57
    int tstate;
nkeynes@368
    58
nkeynes@570
    59
    /* mode flags */
nkeynes@570
    60
    gboolean tlb_on; /* True if tlb translation is active */
nkeynes@570
    61
nkeynes@368
    62
    /* Allocated memory for the (block-wide) back-patch list */
nkeynes@559
    63
    struct backpatch_record *backpatch_list;
nkeynes@368
    64
    uint32_t backpatch_posn;
nkeynes@368
    65
    uint32_t backpatch_size;
nkeynes@571
    66
    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
nkeynes@571
    67
    uint32_t recovery_posn;
nkeynes@368
    68
};
nkeynes@368
    69
nkeynes@417
    70
#define TSTATE_NONE -1
nkeynes@417
    71
#define TSTATE_O    0
nkeynes@417
    72
#define TSTATE_C    2
nkeynes@417
    73
#define TSTATE_E    4
nkeynes@417
    74
#define TSTATE_NE   5
nkeynes@417
    75
#define TSTATE_G    0xF
nkeynes@417
    76
#define TSTATE_GE   0xD
nkeynes@417
    77
#define TSTATE_A    7
nkeynes@417
    78
#define TSTATE_AE   3
nkeynes@417
    79
nkeynes@417
    80
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@417
    81
#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    82
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    83
    OP(0x70+sh4_x86.tstate); OP(rel8); \
nkeynes@417
    84
    MARK_JMP(rel8,label)
nkeynes@417
    85
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@417
    86
#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417
    87
	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417
    88
    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
nkeynes@417
    89
    MARK_JMP(rel8, label)
nkeynes@417
    90
nkeynes@368
    91
static struct sh4_x86_state sh4_x86;
nkeynes@368
    92
nkeynes@388
    93
static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388
    94
static uint32_t min_int = 0x80000000;
nkeynes@394
    95
static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394
    96
static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386
    97
nkeynes@368
    98
void sh4_x86_init()
nkeynes@368
    99
{
nkeynes@368
   100
    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@559
   101
    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@368
   102
}
nkeynes@368
   103
nkeynes@368
   104
nkeynes@559
   105
static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368
   106
{
nkeynes@368
   107
    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368
   108
	sh4_x86.backpatch_size <<= 1;
nkeynes@559
   109
	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
nkeynes@559
   110
					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368
   111
	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368
   112
    }
nkeynes@559
   113
    if( sh4_x86.in_delay_slot ) {
nkeynes@559
   114
	fixup_pc -= 2;
nkeynes@368
   115
    }
nkeynes@559
   116
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
nkeynes@559
   117
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@559
   118
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@559
   119
    sh4_x86.backpatch_posn++;
nkeynes@368
   120
}
nkeynes@368
   121
nkeynes@571
   122
void sh4_x86_add_recovery( uint32_t pc )
nkeynes@571
   123
{
nkeynes@571
   124
    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
nkeynes@571
   125
    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
nkeynes@571
   126
    xlat_recovery_posn++;
nkeynes@571
   127
}
nkeynes@571
   128
    
nkeynes@359
   129
/**
nkeynes@359
   130
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
   131
 */
nkeynes@359
   132
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
   133
{
nkeynes@359
   134
    /* mov [bp+n], reg */
nkeynes@361
   135
    OP(0x8B);
nkeynes@361
   136
    OP(0x45 + (x86reg<<3));
nkeynes@359
   137
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   138
}
nkeynes@359
   139
nkeynes@374
   140
static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368
   141
{
nkeynes@374
   142
    OP(0x0F);
nkeynes@374
   143
    OP(0xBF);
nkeynes@374
   144
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368
   145
}
nkeynes@368
   146
nkeynes@374
   147
static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368
   148
{
nkeynes@374
   149
    OP(0x0F);
nkeynes@374
   150
    OP(0xB7);
nkeynes@374
   151
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374
   152
nkeynes@368
   153
}
nkeynes@368
   154
nkeynes@380
   155
#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380
   156
#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359
   157
/**
nkeynes@359
   158
 * Emit an instruction to load an immediate value into a register
nkeynes@359
   159
 */
nkeynes@359
   160
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
   161
    /* mov #value, reg */
nkeynes@359
   162
    OP(0xB8 + x86reg);
nkeynes@359
   163
    OP32(value);
nkeynes@359
   164
}
nkeynes@359
   165
nkeynes@359
   166
/**
nkeynes@527
   167
 * Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527
   168
 */
nkeynes@527
   169
static inline void load_imm64( int x86reg, uint32_t value ) {
nkeynes@527
   170
    /* mov #value, reg */
nkeynes@527
   171
    REXW();
nkeynes@527
   172
    OP(0xB8 + x86reg);
nkeynes@527
   173
    OP64(value);
nkeynes@527
   174
}
nkeynes@527
   175
nkeynes@527
   176
nkeynes@527
   177
/**
nkeynes@359
   178
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
   179
 */
nkeynes@359
   180
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
   181
    /* mov reg, [bp+n] */
nkeynes@361
   182
    OP(0x89);
nkeynes@361
   183
    OP(0x45 + (x86reg<<3));
nkeynes@359
   184
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   185
}
nkeynes@374
   186
nkeynes@374
   187
#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374
   188
nkeynes@375
   189
/**
nkeynes@375
   190
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   191
 * register (eg for register-to-register moves)
nkeynes@375
   192
 */
nkeynes@375
   193
void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375
   194
{
nkeynes@375
   195
    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375
   196
}
nkeynes@375
   197
nkeynes@375
   198
/**
nkeynes@375
   199
 * Store an FR register (single-precision floating point) into an integer x86
nkeynes@375
   200
 * register (eg for register-to-register moves)
nkeynes@375
   201
 */
nkeynes@375
   202
void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375
   203
{
nkeynes@375
   204
    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375
   205
}
nkeynes@375
   206
nkeynes@375
   207
nkeynes@375
   208
/**
nkeynes@375
   209
 * Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375
   210
 * bankreg must have been previously loaded with FPSCR.
nkeynes@388
   211
 * NB: 12 bytes
nkeynes@375
   212
 */
nkeynes@374
   213
static inline void load_xf_bank( int bankreg )
nkeynes@374
   214
{
nkeynes@386
   215
    NOT_r32( bankreg );
nkeynes@374
   216
    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374
   217
    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
nkeynes@374
   218
    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374
   219
}
nkeynes@374
   220
nkeynes@375
   221
/**
nkeynes@386
   222
 * Update the fr_bank pointer based on the current fpscr value.
nkeynes@386
   223
 */
nkeynes@386
   224
static inline void update_fr_bank( int fpscrreg )
nkeynes@386
   225
{
nkeynes@386
   226
    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386
   227
    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
nkeynes@386
   228
    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386
   229
    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386
   230
}
nkeynes@386
   231
/**
nkeynes@377
   232
 * Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377
   233
 */
nkeynes@377
   234
static inline void push_fpul( )
nkeynes@377
   235
{
nkeynes@377
   236
    OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377
   237
}
nkeynes@377
   238
nkeynes@377
   239
/**
nkeynes@377
   240
 * Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377
   241
 */
nkeynes@377
   242
static inline void pop_fpul( )
nkeynes@377
   243
{
nkeynes@377
   244
    OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377
   245
}
nkeynes@377
   246
nkeynes@377
   247
/**
nkeynes@375
   248
 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375
   249
 * with the location of the current fp bank.
nkeynes@375
   250
 */
nkeynes@374
   251
static inline void push_fr( int bankreg, int frm ) 
nkeynes@374
   252
{
nkeynes@374
   253
    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
nkeynes@374
   254
}
nkeynes@374
   255
nkeynes@375
   256
/**
nkeynes@375
   257
 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
nkeynes@375
   258
 * with bankreg previously loaded with the location of the current fp bank.
nkeynes@375
   259
 */
nkeynes@374
   260
static inline void pop_fr( int bankreg, int frm )
nkeynes@374
   261
{
nkeynes@374
   262
    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374
   263
}
nkeynes@374
   264
nkeynes@375
   265
/**
nkeynes@375
   266
 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375
   267
 * with the location of the current fp bank.
nkeynes@375
   268
 */
nkeynes@374
   269
static inline void push_dr( int bankreg, int frm )
nkeynes@374
   270
{
nkeynes@377
   271
    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374
   272
}
nkeynes@374
   273
nkeynes@374
   274
static inline void pop_dr( int bankreg, int frm )
nkeynes@374
   275
{
nkeynes@377
   276
    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374
   277
}
nkeynes@374
   278
nkeynes@368
   279
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   280
nkeynes@416
   281
#define check_priv( ) \
nkeynes@416
   282
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   283
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   284
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   285
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   286
	if( sh4_x86.in_delay_slot ) {\
nkeynes@559
   287
	    JE_exc( EXC_SLOT_ILLEGAL );\
nkeynes@416
   288
	} else {\
nkeynes@559
   289
	    JE_exc( EXC_ILLEGAL );\
nkeynes@416
   290
	}\
nkeynes@416
   291
    }\
nkeynes@416
   292
nkeynes@416
   293
#define check_fpuen( ) \
nkeynes@416
   294
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   295
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   296
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   297
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   298
	if( sh4_x86.in_delay_slot ) {\
nkeynes@559
   299
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   300
	} else {\
nkeynes@559
   301
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   302
	}\
nkeynes@416
   303
    }
nkeynes@416
   304
nkeynes@559
   305
#define check_ralign16( x86reg ) \
nkeynes@559
   306
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@559
   307
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   308
nkeynes@559
   309
#define check_walign16( x86reg ) \
nkeynes@559
   310
    TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@559
   311
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   312
nkeynes@559
   313
#define check_ralign32( x86reg ) \
nkeynes@559
   314
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@559
   315
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   316
nkeynes@559
   317
#define check_walign32( x86reg ) \
nkeynes@559
   318
    TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@559
   319
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   320
nkeynes@361
   321
#define UNDEF()
nkeynes@361
   322
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@571
   323
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@571
   324
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@571
   325
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@571
   326
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@571
   327
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@571
   328
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   329
nkeynes@571
   330
/**
nkeynes@571
   331
 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
nkeynes@571
   332
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@571
   333
 */
nkeynes@571
   334
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@571
   335
/**
nkeynes@571
   336
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@571
   337
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@571
   338
 */
nkeynes@571
   339
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@570
   340
nkeynes@571
   341
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@571
   342
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@571
   343
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@559
   344
nkeynes@559
   345
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   346
nkeynes@539
   347
/****** Import appropriate calling conventions ******/
nkeynes@539
   348
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   349
#include "sh4/ia64abi.h"
nkeynes@539
   350
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   351
#ifdef APPLE_BUILD
nkeynes@539
   352
#include "sh4/ia32mac.h"
nkeynes@539
   353
#else
nkeynes@539
   354
#include "sh4/ia32abi.h"
nkeynes@539
   355
#endif
nkeynes@539
   356
#endif
nkeynes@539
   357
nkeynes@539
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   361
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   362
 * 
nkeynes@359
   363
 *
nkeynes@359
   364
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   365
 * (eg a branch or 
nkeynes@359
   366
 */
nkeynes@526
   367
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   368
{
nkeynes@388
   369
    uint32_t ir;
nkeynes@388
   370
    /* Read instruction */
nkeynes@569
   371
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   372
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   373
    } else {
nkeynes@569
   374
	ir = sh4_read_word(pc);
nkeynes@388
   375
    }
nkeynes@571
   376
    if( !sh4_x86.in_delay_slot ) {
nkeynes@571
   377
	sh4_x86_add_recovery(pc);
nkeynes@571
   378
    }
nkeynes@359
   379
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   380
            case 0x0:
nkeynes@359
   381
                switch( ir&0xF ) {
nkeynes@359
   382
                    case 0x2:
nkeynes@359
   383
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   384
                            case 0x0:
nkeynes@359
   385
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   386
                                    case 0x0:
nkeynes@359
   387
                                        { /* STC SR, Rn */
nkeynes@359
   388
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   389
                                        check_priv();
nkeynes@374
   390
                                        call_func0(sh4_read_sr);
nkeynes@368
   391
                                        store_reg( R_EAX, Rn );
nkeynes@417
   392
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   393
                                        }
nkeynes@359
   394
                                        break;
nkeynes@359
   395
                                    case 0x1:
nkeynes@359
   396
                                        { /* STC GBR, Rn */
nkeynes@359
   397
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   398
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   399
                                        store_reg( R_EAX, Rn );
nkeynes@359
   400
                                        }
nkeynes@359
   401
                                        break;
nkeynes@359
   402
                                    case 0x2:
nkeynes@359
   403
                                        { /* STC VBR, Rn */
nkeynes@359
   404
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   405
                                        check_priv();
nkeynes@359
   406
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   407
                                        store_reg( R_EAX, Rn );
nkeynes@417
   408
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   409
                                        }
nkeynes@359
   410
                                        break;
nkeynes@359
   411
                                    case 0x3:
nkeynes@359
   412
                                        { /* STC SSR, Rn */
nkeynes@359
   413
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   414
                                        check_priv();
nkeynes@359
   415
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   416
                                        store_reg( R_EAX, Rn );
nkeynes@417
   417
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   418
                                        }
nkeynes@359
   419
                                        break;
nkeynes@359
   420
                                    case 0x4:
nkeynes@359
   421
                                        { /* STC SPC, Rn */
nkeynes@359
   422
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   423
                                        check_priv();
nkeynes@359
   424
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   425
                                        store_reg( R_EAX, Rn );
nkeynes@417
   426
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   427
                                        }
nkeynes@359
   428
                                        break;
nkeynes@359
   429
                                    default:
nkeynes@359
   430
                                        UNDEF();
nkeynes@359
   431
                                        break;
nkeynes@359
   432
                                }
nkeynes@359
   433
                                break;
nkeynes@359
   434
                            case 0x1:
nkeynes@359
   435
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   436
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   437
                                check_priv();
nkeynes@374
   438
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   439
                                store_reg( R_EAX, Rn );
nkeynes@417
   440
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   441
                                }
nkeynes@359
   442
                                break;
nkeynes@359
   443
                        }
nkeynes@359
   444
                        break;
nkeynes@359
   445
                    case 0x3:
nkeynes@359
   446
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   447
                            case 0x0:
nkeynes@359
   448
                                { /* BSRF Rn */
nkeynes@359
   449
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   450
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   451
                            	SLOTILLEGAL();
nkeynes@374
   452
                                } else {
nkeynes@408
   453
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   454
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   455
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   456
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   457
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   458
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   459
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   460
                            	exit_block_pcset(pc+2);
nkeynes@409
   461
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   462
                            	return 4;
nkeynes@374
   463
                                }
nkeynes@359
   464
                                }
nkeynes@359
   465
                                break;
nkeynes@359
   466
                            case 0x2:
nkeynes@359
   467
                                { /* BRAF Rn */
nkeynes@359
   468
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   469
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   470
                            	SLOTILLEGAL();
nkeynes@374
   471
                                } else {
nkeynes@408
   472
                            	load_reg( R_EAX, Rn );
nkeynes@408
   473
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   474
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   475
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   476
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   477
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   478
                            	exit_block_pcset(pc+2);
nkeynes@409
   479
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   480
                            	return 4;
nkeynes@374
   481
                                }
nkeynes@359
   482
                                }
nkeynes@359
   483
                                break;
nkeynes@359
   484
                            case 0x8:
nkeynes@359
   485
                                { /* PREF @Rn */
nkeynes@359
   486
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   487
                                load_reg( R_EAX, Rn );
nkeynes@532
   488
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   489
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   490
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
   491
                                JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
   492
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
   493
                                JMP_TARGET(end);
nkeynes@417
   494
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   495
                                }
nkeynes@359
   496
                                break;
nkeynes@359
   497
                            case 0x9:
nkeynes@359
   498
                                { /* OCBI @Rn */
nkeynes@359
   499
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   500
                                }
nkeynes@359
   501
                                break;
nkeynes@359
   502
                            case 0xA:
nkeynes@359
   503
                                { /* OCBP @Rn */
nkeynes@359
   504
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   505
                                }
nkeynes@359
   506
                                break;
nkeynes@359
   507
                            case 0xB:
nkeynes@359
   508
                                { /* OCBWB @Rn */
nkeynes@359
   509
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   510
                                }
nkeynes@359
   511
                                break;
nkeynes@359
   512
                            case 0xC:
nkeynes@359
   513
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   514
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
   515
                                load_reg( R_EAX, Rn );
nkeynes@571
   516
                                check_walign32( R_EAX );
nkeynes@571
   517
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   518
                                load_reg( R_EDX, 0 );
nkeynes@571
   519
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   520
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   521
                                }
nkeynes@359
   522
                                break;
nkeynes@359
   523
                            default:
nkeynes@359
   524
                                UNDEF();
nkeynes@359
   525
                                break;
nkeynes@359
   526
                        }
nkeynes@359
   527
                        break;
nkeynes@359
   528
                    case 0x4:
nkeynes@359
   529
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   530
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   531
                        load_reg( R_EAX, 0 );
nkeynes@359
   532
                        load_reg( R_ECX, Rn );
nkeynes@571
   533
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   534
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   535
                        load_reg( R_EDX, Rm );
nkeynes@571
   536
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   537
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   538
                        }
nkeynes@359
   539
                        break;
nkeynes@359
   540
                    case 0x5:
nkeynes@359
   541
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   542
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   543
                        load_reg( R_EAX, 0 );
nkeynes@361
   544
                        load_reg( R_ECX, Rn );
nkeynes@571
   545
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   546
                        check_walign16( R_EAX );
nkeynes@571
   547
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   548
                        load_reg( R_EDX, Rm );
nkeynes@571
   549
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   550
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   551
                        }
nkeynes@359
   552
                        break;
nkeynes@359
   553
                    case 0x6:
nkeynes@359
   554
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   555
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   556
                        load_reg( R_EAX, 0 );
nkeynes@361
   557
                        load_reg( R_ECX, Rn );
nkeynes@571
   558
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   559
                        check_walign32( R_EAX );
nkeynes@571
   560
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   561
                        load_reg( R_EDX, Rm );
nkeynes@571
   562
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   563
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   564
                        }
nkeynes@359
   565
                        break;
nkeynes@359
   566
                    case 0x7:
nkeynes@359
   567
                        { /* MUL.L Rm, Rn */
nkeynes@359
   568
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   569
                        load_reg( R_EAX, Rm );
nkeynes@361
   570
                        load_reg( R_ECX, Rn );
nkeynes@361
   571
                        MUL_r32( R_ECX );
nkeynes@361
   572
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   573
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   574
                        }
nkeynes@359
   575
                        break;
nkeynes@359
   576
                    case 0x8:
nkeynes@359
   577
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   578
                            case 0x0:
nkeynes@359
   579
                                { /* CLRT */
nkeynes@374
   580
                                CLC();
nkeynes@374
   581
                                SETC_t();
nkeynes@417
   582
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   583
                                }
nkeynes@359
   584
                                break;
nkeynes@359
   585
                            case 0x1:
nkeynes@359
   586
                                { /* SETT */
nkeynes@374
   587
                                STC();
nkeynes@374
   588
                                SETC_t();
nkeynes@417
   589
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   590
                                }
nkeynes@359
   591
                                break;
nkeynes@359
   592
                            case 0x2:
nkeynes@359
   593
                                { /* CLRMAC */
nkeynes@374
   594
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   595
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   596
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   597
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   598
                                }
nkeynes@359
   599
                                break;
nkeynes@359
   600
                            case 0x3:
nkeynes@359
   601
                                { /* LDTLB */
nkeynes@553
   602
                                call_func0( MMU_ldtlb );
nkeynes@359
   603
                                }
nkeynes@359
   604
                                break;
nkeynes@359
   605
                            case 0x4:
nkeynes@359
   606
                                { /* CLRS */
nkeynes@374
   607
                                CLC();
nkeynes@374
   608
                                SETC_sh4r(R_S);
nkeynes@417
   609
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   610
                                }
nkeynes@359
   611
                                break;
nkeynes@359
   612
                            case 0x5:
nkeynes@359
   613
                                { /* SETS */
nkeynes@374
   614
                                STC();
nkeynes@374
   615
                                SETC_sh4r(R_S);
nkeynes@417
   616
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   617
                                }
nkeynes@359
   618
                                break;
nkeynes@359
   619
                            default:
nkeynes@359
   620
                                UNDEF();
nkeynes@359
   621
                                break;
nkeynes@359
   622
                        }
nkeynes@359
   623
                        break;
nkeynes@359
   624
                    case 0x9:
nkeynes@359
   625
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   626
                            case 0x0:
nkeynes@359
   627
                                { /* NOP */
nkeynes@359
   628
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   629
                                }
nkeynes@359
   630
                                break;
nkeynes@359
   631
                            case 0x1:
nkeynes@359
   632
                                { /* DIV0U */
nkeynes@361
   633
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   634
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   635
                                store_spreg( R_EAX, R_M );
nkeynes@361
   636
                                store_spreg( R_EAX, R_T );
nkeynes@417
   637
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   638
                                }
nkeynes@359
   639
                                break;
nkeynes@359
   640
                            case 0x2:
nkeynes@359
   641
                                { /* MOVT Rn */
nkeynes@359
   642
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   643
                                load_spreg( R_EAX, R_T );
nkeynes@359
   644
                                store_reg( R_EAX, Rn );
nkeynes@359
   645
                                }
nkeynes@359
   646
                                break;
nkeynes@359
   647
                            default:
nkeynes@359
   648
                                UNDEF();
nkeynes@359
   649
                                break;
nkeynes@359
   650
                        }
nkeynes@359
   651
                        break;
nkeynes@359
   652
                    case 0xA:
nkeynes@359
   653
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   654
                            case 0x0:
nkeynes@359
   655
                                { /* STS MACH, Rn */
nkeynes@359
   656
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   657
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   658
                                store_reg( R_EAX, Rn );
nkeynes@359
   659
                                }
nkeynes@359
   660
                                break;
nkeynes@359
   661
                            case 0x1:
nkeynes@359
   662
                                { /* STS MACL, Rn */
nkeynes@359
   663
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   664
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   665
                                store_reg( R_EAX, Rn );
nkeynes@359
   666
                                }
nkeynes@359
   667
                                break;
nkeynes@359
   668
                            case 0x2:
nkeynes@359
   669
                                { /* STS PR, Rn */
nkeynes@359
   670
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   671
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   672
                                store_reg( R_EAX, Rn );
nkeynes@359
   673
                                }
nkeynes@359
   674
                                break;
nkeynes@359
   675
                            case 0x3:
nkeynes@359
   676
                                { /* STC SGR, Rn */
nkeynes@359
   677
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   678
                                check_priv();
nkeynes@359
   679
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   680
                                store_reg( R_EAX, Rn );
nkeynes@417
   681
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   682
                                }
nkeynes@359
   683
                                break;
nkeynes@359
   684
                            case 0x5:
nkeynes@359
   685
                                { /* STS FPUL, Rn */
nkeynes@359
   686
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   687
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   688
                                store_reg( R_EAX, Rn );
nkeynes@359
   689
                                }
nkeynes@359
   690
                                break;
nkeynes@359
   691
                            case 0x6:
nkeynes@359
   692
                                { /* STS FPSCR, Rn */
nkeynes@359
   693
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   694
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   695
                                store_reg( R_EAX, Rn );
nkeynes@359
   696
                                }
nkeynes@359
   697
                                break;
nkeynes@359
   698
                            case 0xF:
nkeynes@359
   699
                                { /* STC DBR, Rn */
nkeynes@359
   700
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   701
                                check_priv();
nkeynes@359
   702
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   703
                                store_reg( R_EAX, Rn );
nkeynes@417
   704
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   705
                                }
nkeynes@359
   706
                                break;
nkeynes@359
   707
                            default:
nkeynes@359
   708
                                UNDEF();
nkeynes@359
   709
                                break;
nkeynes@359
   710
                        }
nkeynes@359
   711
                        break;
nkeynes@359
   712
                    case 0xB:
nkeynes@359
   713
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   714
                            case 0x0:
nkeynes@359
   715
                                { /* RTS */
nkeynes@374
   716
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   717
                            	SLOTILLEGAL();
nkeynes@374
   718
                                } else {
nkeynes@408
   719
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
   720
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   721
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
   722
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   723
                            	exit_block_pcset(pc+2);
nkeynes@409
   724
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   725
                            	return 4;
nkeynes@374
   726
                                }
nkeynes@359
   727
                                }
nkeynes@359
   728
                                break;
nkeynes@359
   729
                            case 0x1:
nkeynes@359
   730
                                { /* SLEEP */
nkeynes@388
   731
                                check_priv();
nkeynes@388
   732
                                call_func0( sh4_sleep );
nkeynes@417
   733
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
   734
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
   735
                                return 2;
nkeynes@359
   736
                                }
nkeynes@359
   737
                                break;
nkeynes@359
   738
                            case 0x2:
nkeynes@359
   739
                                { /* RTE */
nkeynes@374
   740
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   741
                            	SLOTILLEGAL();
nkeynes@374
   742
                                } else {
nkeynes@408
   743
                            	check_priv();
nkeynes@408
   744
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
   745
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   746
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   747
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   748
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   749
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   750
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   751
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   752
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   753
                            	exit_block_pcset(pc+2);
nkeynes@409
   754
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   755
                            	return 4;
nkeynes@374
   756
                                }
nkeynes@359
   757
                                }
nkeynes@359
   758
                                break;
nkeynes@359
   759
                            default:
nkeynes@359
   760
                                UNDEF();
nkeynes@359
   761
                                break;
nkeynes@359
   762
                        }
nkeynes@359
   763
                        break;
nkeynes@359
   764
                    case 0xC:
nkeynes@359
   765
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   766
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   767
                        load_reg( R_EAX, 0 );
nkeynes@359
   768
                        load_reg( R_ECX, Rm );
nkeynes@571
   769
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   770
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@571
   771
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   772
                        store_reg( R_EAX, Rn );
nkeynes@417
   773
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   774
                        }
nkeynes@359
   775
                        break;
nkeynes@359
   776
                    case 0xD:
nkeynes@359
   777
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   778
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   779
                        load_reg( R_EAX, 0 );
nkeynes@361
   780
                        load_reg( R_ECX, Rm );
nkeynes@571
   781
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   782
                        check_ralign16( R_EAX );
nkeynes@571
   783
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   784
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   785
                        store_reg( R_EAX, Rn );
nkeynes@417
   786
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   787
                        }
nkeynes@359
   788
                        break;
nkeynes@359
   789
                    case 0xE:
nkeynes@359
   790
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   791
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   792
                        load_reg( R_EAX, 0 );
nkeynes@361
   793
                        load_reg( R_ECX, Rm );
nkeynes@571
   794
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   795
                        check_ralign32( R_EAX );
nkeynes@571
   796
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   797
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   798
                        store_reg( R_EAX, Rn );
nkeynes@417
   799
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   800
                        }
nkeynes@359
   801
                        break;
nkeynes@359
   802
                    case 0xF:
nkeynes@359
   803
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   804
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   805
                        if( Rm == Rn ) {
nkeynes@571
   806
                    	load_reg( R_EAX, Rm );
nkeynes@571
   807
                    	check_ralign32( R_EAX );
nkeynes@571
   808
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   809
                    	PUSH_realigned_r32( R_EAX );
nkeynes@571
   810
                    	load_reg( R_EAX, Rn );
nkeynes@571
   811
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@571
   812
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   813
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@571
   814
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   815
                    	// adding a page-boundary check to skip the second translation
nkeynes@571
   816
                        } else {
nkeynes@571
   817
                    	load_reg( R_EAX, Rm );
nkeynes@571
   818
                    	check_ralign32( R_EAX );
nkeynes@571
   819
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   820
                    	PUSH_realigned_r32( R_EAX );
nkeynes@571
   821
                    	load_reg( R_EAX, Rn );
nkeynes@571
   822
                    	check_ralign32( R_EAX );
nkeynes@571
   823
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   824
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   825
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
   826
                        }
nkeynes@571
   827
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@571
   828
                        POP_r32( R_ECX );
nkeynes@571
   829
                        PUSH_r32( R_EAX );
nkeynes@386
   830
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   831
                        POP_realigned_r32( R_ECX );
nkeynes@571
   832
                    
nkeynes@386
   833
                        IMUL_r32( R_ECX );
nkeynes@386
   834
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   835
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   836
                    
nkeynes@386
   837
                        load_spreg( R_ECX, R_S );
nkeynes@386
   838
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   839
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   840
                        call_func0( signsat48 );
nkeynes@386
   841
                        JMP_TARGET( nosat );
nkeynes@417
   842
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   843
                        }
nkeynes@359
   844
                        break;
nkeynes@359
   845
                    default:
nkeynes@359
   846
                        UNDEF();
nkeynes@359
   847
                        break;
nkeynes@359
   848
                }
nkeynes@359
   849
                break;
nkeynes@359
   850
            case 0x1:
nkeynes@359
   851
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   852
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@571
   853
                load_reg( R_EAX, Rn );
nkeynes@571
   854
                ADD_imm32_r32( disp, R_EAX );
nkeynes@571
   855
                check_walign32( R_EAX );
nkeynes@571
   856
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   857
                load_reg( R_EDX, Rm );
nkeynes@571
   858
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   859
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   860
                }
nkeynes@359
   861
                break;
nkeynes@359
   862
            case 0x2:
nkeynes@359
   863
                switch( ir&0xF ) {
nkeynes@359
   864
                    case 0x0:
nkeynes@359
   865
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   866
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   867
                        load_reg( R_EAX, Rn );
nkeynes@571
   868
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   869
                        load_reg( R_EDX, Rm );
nkeynes@571
   870
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   871
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   872
                        }
nkeynes@359
   873
                        break;
nkeynes@359
   874
                    case 0x1:
nkeynes@359
   875
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   876
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   877
                        load_reg( R_EAX, Rn );
nkeynes@571
   878
                        check_walign16( R_EAX );
nkeynes@571
   879
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@571
   880
                        load_reg( R_EDX, Rm );
nkeynes@571
   881
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   882
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   883
                        }
nkeynes@359
   884
                        break;
nkeynes@359
   885
                    case 0x2:
nkeynes@359
   886
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   887
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   888
                        load_reg( R_EAX, Rn );
nkeynes@571
   889
                        check_walign32(R_EAX);
nkeynes@571
   890
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   891
                        load_reg( R_EDX, Rm );
nkeynes@571
   892
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   893
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   894
                        }
nkeynes@359
   895
                        break;
nkeynes@359
   896
                    case 0x4:
nkeynes@359
   897
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   898
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   899
                        load_reg( R_EAX, Rn );
nkeynes@571
   900
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@571
   901
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   902
                        load_reg( R_EDX, Rm );
nkeynes@571
   903
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@571
   904
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   905
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   906
                        }
nkeynes@359
   907
                        break;
nkeynes@359
   908
                    case 0x5:
nkeynes@359
   909
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   910
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   911
                        load_reg( R_EAX, Rn );
nkeynes@571
   912
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@571
   913
                        check_walign16( R_EAX );
nkeynes@571
   914
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   915
                        load_reg( R_EDX, Rm );
nkeynes@571
   916
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@571
   917
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   918
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   919
                        }
nkeynes@359
   920
                        break;
nkeynes@359
   921
                    case 0x6:
nkeynes@359
   922
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   923
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
   924
                        load_reg( R_EAX, Rn );
nkeynes@571
   925
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
   926
                        check_walign32( R_EAX );
nkeynes@571
   927
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   928
                        load_reg( R_EDX, Rm );
nkeynes@571
   929
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
   930
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   931
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   932
                        }
nkeynes@359
   933
                        break;
nkeynes@359
   934
                    case 0x7:
nkeynes@359
   935
                        { /* DIV0S Rm, Rn */
nkeynes@359
   936
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   937
                        load_reg( R_EAX, Rm );
nkeynes@386
   938
                        load_reg( R_ECX, Rn );
nkeynes@361
   939
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   940
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   941
                        store_spreg( R_EAX, R_M );
nkeynes@361
   942
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   943
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   944
                        SETNE_t();
nkeynes@417
   945
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   946
                        }
nkeynes@359
   947
                        break;
nkeynes@359
   948
                    case 0x8:
nkeynes@359
   949
                        { /* TST Rm, Rn */
nkeynes@359
   950
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   951
                        load_reg( R_EAX, Rm );
nkeynes@361
   952
                        load_reg( R_ECX, Rn );
nkeynes@361
   953
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   954
                        SETE_t();
nkeynes@417
   955
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   956
                        }
nkeynes@359
   957
                        break;
nkeynes@359
   958
                    case 0x9:
nkeynes@359
   959
                        { /* AND Rm, Rn */
nkeynes@359
   960
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   961
                        load_reg( R_EAX, Rm );
nkeynes@359
   962
                        load_reg( R_ECX, Rn );
nkeynes@359
   963
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   964
                        store_reg( R_ECX, Rn );
nkeynes@417
   965
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   966
                        }
nkeynes@359
   967
                        break;
nkeynes@359
   968
                    case 0xA:
nkeynes@359
   969
                        { /* XOR Rm, Rn */
nkeynes@359
   970
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   971
                        load_reg( R_EAX, Rm );
nkeynes@359
   972
                        load_reg( R_ECX, Rn );
nkeynes@359
   973
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   974
                        store_reg( R_ECX, Rn );
nkeynes@417
   975
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   976
                        }
nkeynes@359
   977
                        break;
nkeynes@359
   978
                    case 0xB:
nkeynes@359
   979
                        { /* OR Rm, Rn */
nkeynes@359
   980
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   981
                        load_reg( R_EAX, Rm );
nkeynes@359
   982
                        load_reg( R_ECX, Rn );
nkeynes@359
   983
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   984
                        store_reg( R_ECX, Rn );
nkeynes@417
   985
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   986
                        }
nkeynes@359
   987
                        break;
nkeynes@359
   988
                    case 0xC:
nkeynes@359
   989
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   990
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   991
                        load_reg( R_EAX, Rm );
nkeynes@368
   992
                        load_reg( R_ECX, Rn );
nkeynes@368
   993
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   994
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   995
                        JE_rel8(13, target1);
nkeynes@368
   996
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   997
                        JE_rel8(9, target2);
nkeynes@368
   998
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   999
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1000
                        JE_rel8(2, target3);
nkeynes@368
  1001
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1002
                        JMP_TARGET(target1);
nkeynes@380
  1003
                        JMP_TARGET(target2);
nkeynes@380
  1004
                        JMP_TARGET(target3);
nkeynes@368
  1005
                        SETE_t();
nkeynes@417
  1006
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1007
                        }
nkeynes@359
  1008
                        break;
nkeynes@359
  1009
                    case 0xD:
nkeynes@359
  1010
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1011
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1012
                        load_reg( R_EAX, Rm );
nkeynes@394
  1013
                        load_reg( R_ECX, Rn );
nkeynes@394
  1014
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1015
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1016
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1017
                        store_reg( R_ECX, Rn );
nkeynes@417
  1018
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1019
                        }
nkeynes@359
  1020
                        break;
nkeynes@359
  1021
                    case 0xE:
nkeynes@359
  1022
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1023
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1024
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1025
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1026
                        MUL_r32( R_ECX );
nkeynes@374
  1027
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1028
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1029
                        }
nkeynes@359
  1030
                        break;
nkeynes@359
  1031
                    case 0xF:
nkeynes@359
  1032
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1033
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1034
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1035
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1036
                        MUL_r32( R_ECX );
nkeynes@374
  1037
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1038
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1039
                        }
nkeynes@359
  1040
                        break;
nkeynes@359
  1041
                    default:
nkeynes@359
  1042
                        UNDEF();
nkeynes@359
  1043
                        break;
nkeynes@359
  1044
                }
nkeynes@359
  1045
                break;
nkeynes@359
  1046
            case 0x3:
nkeynes@359
  1047
                switch( ir&0xF ) {
nkeynes@359
  1048
                    case 0x0:
nkeynes@359
  1049
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1050
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1051
                        load_reg( R_EAX, Rm );
nkeynes@359
  1052
                        load_reg( R_ECX, Rn );
nkeynes@359
  1053
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1054
                        SETE_t();
nkeynes@417
  1055
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1056
                        }
nkeynes@359
  1057
                        break;
nkeynes@359
  1058
                    case 0x2:
nkeynes@359
  1059
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1060
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1061
                        load_reg( R_EAX, Rm );
nkeynes@359
  1062
                        load_reg( R_ECX, Rn );
nkeynes@359
  1063
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1064
                        SETAE_t();
nkeynes@417
  1065
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1066
                        }
nkeynes@359
  1067
                        break;
nkeynes@359
  1068
                    case 0x3:
nkeynes@359
  1069
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1070
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1071
                        load_reg( R_EAX, Rm );
nkeynes@359
  1072
                        load_reg( R_ECX, Rn );
nkeynes@359
  1073
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1074
                        SETGE_t();
nkeynes@417
  1075
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1076
                        }
nkeynes@359
  1077
                        break;
nkeynes@359
  1078
                    case 0x4:
nkeynes@359
  1079
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1080
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1081
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1082
                        load_reg( R_EAX, Rn );
nkeynes@417
  1083
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1084
                    	LDC_t();
nkeynes@417
  1085
                        }
nkeynes@386
  1086
                        RCL1_r32( R_EAX );
nkeynes@386
  1087
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1088
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1089
                        JE_rel8(5, mqequal);
nkeynes@386
  1090
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1091
                        JMP_rel8(3, end);
nkeynes@380
  1092
                        JMP_TARGET(mqequal);
nkeynes@386
  1093
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1094
                        JMP_TARGET(end);
nkeynes@386
  1095
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1096
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1097
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1098
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1099
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1100
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1101
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1102
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1103
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1104
                        }
nkeynes@359
  1105
                        break;
nkeynes@359
  1106
                    case 0x5:
nkeynes@359
  1107
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1108
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1109
                        load_reg( R_EAX, Rm );
nkeynes@361
  1110
                        load_reg( R_ECX, Rn );
nkeynes@361
  1111
                        MUL_r32(R_ECX);
nkeynes@361
  1112
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1113
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1114
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
                        }
nkeynes@359
  1116
                        break;
nkeynes@359
  1117
                    case 0x6:
nkeynes@359
  1118
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1119
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1120
                        load_reg( R_EAX, Rm );
nkeynes@359
  1121
                        load_reg( R_ECX, Rn );
nkeynes@359
  1122
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1123
                        SETA_t();
nkeynes@417
  1124
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1125
                        }
nkeynes@359
  1126
                        break;
nkeynes@359
  1127
                    case 0x7:
nkeynes@359
  1128
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1129
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1130
                        load_reg( R_EAX, Rm );
nkeynes@359
  1131
                        load_reg( R_ECX, Rn );
nkeynes@359
  1132
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1133
                        SETG_t();
nkeynes@417
  1134
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1135
                        }
nkeynes@359
  1136
                        break;
nkeynes@359
  1137
                    case 0x8:
nkeynes@359
  1138
                        { /* SUB Rm, Rn */
nkeynes@359
  1139
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1140
                        load_reg( R_EAX, Rm );
nkeynes@359
  1141
                        load_reg( R_ECX, Rn );
nkeynes@359
  1142
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1143
                        store_reg( R_ECX, Rn );
nkeynes@417
  1144
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1145
                        }
nkeynes@359
  1146
                        break;
nkeynes@359
  1147
                    case 0xA:
nkeynes@359
  1148
                        { /* SUBC Rm, Rn */
nkeynes@359
  1149
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1150
                        load_reg( R_EAX, Rm );
nkeynes@359
  1151
                        load_reg( R_ECX, Rn );
nkeynes@417
  1152
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1153
                    	LDC_t();
nkeynes@417
  1154
                        }
nkeynes@359
  1155
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1156
                        store_reg( R_ECX, Rn );
nkeynes@394
  1157
                        SETC_t();
nkeynes@417
  1158
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1159
                        }
nkeynes@359
  1160
                        break;
nkeynes@359
  1161
                    case 0xB:
nkeynes@359
  1162
                        { /* SUBV Rm, Rn */
nkeynes@359
  1163
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1164
                        load_reg( R_EAX, Rm );
nkeynes@359
  1165
                        load_reg( R_ECX, Rn );
nkeynes@359
  1166
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1167
                        store_reg( R_ECX, Rn );
nkeynes@359
  1168
                        SETO_t();
nkeynes@417
  1169
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1170
                        }
nkeynes@359
  1171
                        break;
nkeynes@359
  1172
                    case 0xC:
nkeynes@359
  1173
                        { /* ADD Rm, Rn */
nkeynes@359
  1174
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1175
                        load_reg( R_EAX, Rm );
nkeynes@359
  1176
                        load_reg( R_ECX, Rn );
nkeynes@359
  1177
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1178
                        store_reg( R_ECX, Rn );
nkeynes@417
  1179
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1180
                        }
nkeynes@359
  1181
                        break;
nkeynes@359
  1182
                    case 0xD:
nkeynes@359
  1183
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1184
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1185
                        load_reg( R_EAX, Rm );
nkeynes@361
  1186
                        load_reg( R_ECX, Rn );
nkeynes@361
  1187
                        IMUL_r32(R_ECX);
nkeynes@361
  1188
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1189
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1190
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
                        }
nkeynes@359
  1192
                        break;
nkeynes@359
  1193
                    case 0xE:
nkeynes@359
  1194
                        { /* ADDC Rm, Rn */
nkeynes@359
  1195
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1196
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1197
                    	LDC_t();
nkeynes@417
  1198
                        }
nkeynes@359
  1199
                        load_reg( R_EAX, Rm );
nkeynes@359
  1200
                        load_reg( R_ECX, Rn );
nkeynes@359
  1201
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1202
                        store_reg( R_ECX, Rn );
nkeynes@359
  1203
                        SETC_t();
nkeynes@417
  1204
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1205
                        }
nkeynes@359
  1206
                        break;
nkeynes@359
  1207
                    case 0xF:
nkeynes@359
  1208
                        { /* ADDV Rm, Rn */
nkeynes@359
  1209
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1210
                        load_reg( R_EAX, Rm );
nkeynes@359
  1211
                        load_reg( R_ECX, Rn );
nkeynes@359
  1212
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1213
                        store_reg( R_ECX, Rn );
nkeynes@359
  1214
                        SETO_t();
nkeynes@417
  1215
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1216
                        }
nkeynes@359
  1217
                        break;
nkeynes@359
  1218
                    default:
nkeynes@359
  1219
                        UNDEF();
nkeynes@359
  1220
                        break;
nkeynes@359
  1221
                }
nkeynes@359
  1222
                break;
nkeynes@359
  1223
            case 0x4:
nkeynes@359
  1224
                switch( ir&0xF ) {
nkeynes@359
  1225
                    case 0x0:
nkeynes@359
  1226
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1227
                            case 0x0:
nkeynes@359
  1228
                                { /* SHLL Rn */
nkeynes@359
  1229
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1230
                                load_reg( R_EAX, Rn );
nkeynes@359
  1231
                                SHL1_r32( R_EAX );
nkeynes@397
  1232
                                SETC_t();
nkeynes@359
  1233
                                store_reg( R_EAX, Rn );
nkeynes@417
  1234
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1235
                                }
nkeynes@359
  1236
                                break;
nkeynes@359
  1237
                            case 0x1:
nkeynes@359
  1238
                                { /* DT Rn */
nkeynes@359
  1239
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1240
                                load_reg( R_EAX, Rn );
nkeynes@386
  1241
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1242
                                store_reg( R_EAX, Rn );
nkeynes@359
  1243
                                SETE_t();
nkeynes@417
  1244
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1245
                                }
nkeynes@359
  1246
                                break;
nkeynes@359
  1247
                            case 0x2:
nkeynes@359
  1248
                                { /* SHAL Rn */
nkeynes@359
  1249
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1250
                                load_reg( R_EAX, Rn );
nkeynes@359
  1251
                                SHL1_r32( R_EAX );
nkeynes@397
  1252
                                SETC_t();
nkeynes@359
  1253
                                store_reg( R_EAX, Rn );
nkeynes@417
  1254
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1255
                                }
nkeynes@359
  1256
                                break;
nkeynes@359
  1257
                            default:
nkeynes@359
  1258
                                UNDEF();
nkeynes@359
  1259
                                break;
nkeynes@359
  1260
                        }
nkeynes@359
  1261
                        break;
nkeynes@359
  1262
                    case 0x1:
nkeynes@359
  1263
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1264
                            case 0x0:
nkeynes@359
  1265
                                { /* SHLR Rn */
nkeynes@359
  1266
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1267
                                load_reg( R_EAX, Rn );
nkeynes@359
  1268
                                SHR1_r32( R_EAX );
nkeynes@397
  1269
                                SETC_t();
nkeynes@359
  1270
                                store_reg( R_EAX, Rn );
nkeynes@417
  1271
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1272
                                }
nkeynes@359
  1273
                                break;
nkeynes@359
  1274
                            case 0x1:
nkeynes@359
  1275
                                { /* CMP/PZ Rn */
nkeynes@359
  1276
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1277
                                load_reg( R_EAX, Rn );
nkeynes@359
  1278
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1279
                                SETGE_t();
nkeynes@417
  1280
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1281
                                }
nkeynes@359
  1282
                                break;
nkeynes@359
  1283
                            case 0x2:
nkeynes@359
  1284
                                { /* SHAR Rn */
nkeynes@359
  1285
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1286
                                load_reg( R_EAX, Rn );
nkeynes@359
  1287
                                SAR1_r32( R_EAX );
nkeynes@397
  1288
                                SETC_t();
nkeynes@359
  1289
                                store_reg( R_EAX, Rn );
nkeynes@417
  1290
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1291
                                }
nkeynes@359
  1292
                                break;
nkeynes@359
  1293
                            default:
nkeynes@359
  1294
                                UNDEF();
nkeynes@359
  1295
                                break;
nkeynes@359
  1296
                        }
nkeynes@359
  1297
                        break;
nkeynes@359
  1298
                    case 0x2:
nkeynes@359
  1299
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1300
                            case 0x0:
nkeynes@359
  1301
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1302
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1303
                                load_reg( R_EAX, Rn );
nkeynes@571
  1304
                                check_walign32( R_EAX );
nkeynes@571
  1305
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1306
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1307
                                load_spreg( R_EDX, R_MACH );
nkeynes@571
  1308
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1309
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1310
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1311
                                }
nkeynes@359
  1312
                                break;
nkeynes@359
  1313
                            case 0x1:
nkeynes@359
  1314
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1315
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1316
                                load_reg( R_EAX, Rn );
nkeynes@571
  1317
                                check_walign32( R_EAX );
nkeynes@571
  1318
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1319
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1320
                                load_spreg( R_EDX, R_MACL );
nkeynes@571
  1321
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1322
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1323
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1324
                                }
nkeynes@359
  1325
                                break;
nkeynes@359
  1326
                            case 0x2:
nkeynes@359
  1327
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1328
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1329
                                load_reg( R_EAX, Rn );
nkeynes@571
  1330
                                check_walign32( R_EAX );
nkeynes@571
  1331
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1332
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1333
                                load_spreg( R_EDX, R_PR );
nkeynes@571
  1334
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1335
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1336
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1337
                                }
nkeynes@359
  1338
                                break;
nkeynes@359
  1339
                            case 0x3:
nkeynes@359
  1340
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1341
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1342
                                check_priv();
nkeynes@571
  1343
                                load_reg( R_EAX, Rn );
nkeynes@571
  1344
                                check_walign32( R_EAX );
nkeynes@571
  1345
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1346
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1347
                                load_spreg( R_EDX, R_SGR );
nkeynes@571
  1348
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1349
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1350
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1351
                                }
nkeynes@359
  1352
                                break;
nkeynes@359
  1353
                            case 0x5:
nkeynes@359
  1354
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1355
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1356
                                load_reg( R_EAX, Rn );
nkeynes@571
  1357
                                check_walign32( R_EAX );
nkeynes@571
  1358
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1359
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1360
                                load_spreg( R_EDX, R_FPUL );
nkeynes@571
  1361
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1362
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1363
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1364
                                }
nkeynes@359
  1365
                                break;
nkeynes@359
  1366
                            case 0x6:
nkeynes@359
  1367
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1368
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1369
                                load_reg( R_EAX, Rn );
nkeynes@571
  1370
                                check_walign32( R_EAX );
nkeynes@571
  1371
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1372
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1373
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@571
  1374
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1375
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1376
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1377
                                }
nkeynes@359
  1378
                                break;
nkeynes@359
  1379
                            case 0xF:
nkeynes@359
  1380
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1381
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1382
                                check_priv();
nkeynes@571
  1383
                                load_reg( R_EAX, Rn );
nkeynes@571
  1384
                                check_walign32( R_EAX );
nkeynes@571
  1385
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1386
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1387
                                load_spreg( R_EDX, R_DBR );
nkeynes@571
  1388
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1389
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1390
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1391
                                }
nkeynes@359
  1392
                                break;
nkeynes@359
  1393
                            default:
nkeynes@359
  1394
                                UNDEF();
nkeynes@359
  1395
                                break;
nkeynes@359
  1396
                        }
nkeynes@359
  1397
                        break;
nkeynes@359
  1398
                    case 0x3:
nkeynes@359
  1399
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1400
                            case 0x0:
nkeynes@359
  1401
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1402
                                    case 0x0:
nkeynes@359
  1403
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1404
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1405
                                        check_priv();
nkeynes@571
  1406
                                        load_reg( R_EAX, Rn );
nkeynes@571
  1407
                                        check_walign32( R_EAX );
nkeynes@571
  1408
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1409
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1410
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1411
                                        call_func0( sh4_read_sr );
nkeynes@571
  1412
                                        POP_realigned_r32( R_ECX );
nkeynes@571
  1413
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1414
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1415
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1416
                                        }
nkeynes@359
  1417
                                        break;
nkeynes@359
  1418
                                    case 0x1:
nkeynes@359
  1419
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1420
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1421
                                        load_reg( R_EAX, Rn );
nkeynes@571
  1422
                                        check_walign32( R_EAX );
nkeynes@571
  1423
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1424
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1425
                                        load_spreg( R_EDX, R_GBR );
nkeynes@571
  1426
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1427
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1428
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1429
                                        }
nkeynes@359
  1430
                                        break;
nkeynes@359
  1431
                                    case 0x2:
nkeynes@359
  1432
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1433
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1434
                                        check_priv();
nkeynes@571
  1435
                                        load_reg( R_EAX, Rn );
nkeynes@571
  1436
                                        check_walign32( R_EAX );
nkeynes@571
  1437
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1438
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1439
                                        load_spreg( R_EDX, R_VBR );
nkeynes@571
  1440
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1441
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1442
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1443
                                        }
nkeynes@359
  1444
                                        break;
nkeynes@359
  1445
                                    case 0x3:
nkeynes@359
  1446
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1447
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1448
                                        check_priv();
nkeynes@571
  1449
                                        load_reg( R_EAX, Rn );
nkeynes@571
  1450
                                        check_walign32( R_EAX );
nkeynes@571
  1451
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1452
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1453
                                        load_spreg( R_EDX, R_SSR );
nkeynes@571
  1454
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1455
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1456
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1457
                                        }
nkeynes@359
  1458
                                        break;
nkeynes@359
  1459
                                    case 0x4:
nkeynes@359
  1460
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1461
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1462
                                        check_priv();
nkeynes@571
  1463
                                        load_reg( R_EAX, Rn );
nkeynes@571
  1464
                                        check_walign32( R_EAX );
nkeynes@571
  1465
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1466
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1467
                                        load_spreg( R_EDX, R_SPC );
nkeynes@571
  1468
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1469
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1470
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1471
                                        }
nkeynes@359
  1472
                                        break;
nkeynes@359
  1473
                                    default:
nkeynes@359
  1474
                                        UNDEF();
nkeynes@359
  1475
                                        break;
nkeynes@359
  1476
                                }
nkeynes@359
  1477
                                break;
nkeynes@359
  1478
                            case 0x1:
nkeynes@359
  1479
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1480
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1481
                                check_priv();
nkeynes@571
  1482
                                load_reg( R_EAX, Rn );
nkeynes@571
  1483
                                check_walign32( R_EAX );
nkeynes@571
  1484
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1485
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1486
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@571
  1487
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1488
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1489
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1490
                                }
nkeynes@359
  1491
                                break;
nkeynes@359
  1492
                        }
nkeynes@359
  1493
                        break;
nkeynes@359
  1494
                    case 0x4:
nkeynes@359
  1495
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1496
                            case 0x0:
nkeynes@359
  1497
                                { /* ROTL Rn */
nkeynes@359
  1498
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1499
                                load_reg( R_EAX, Rn );
nkeynes@359
  1500
                                ROL1_r32( R_EAX );
nkeynes@359
  1501
                                store_reg( R_EAX, Rn );
nkeynes@359
  1502
                                SETC_t();
nkeynes@417
  1503
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1504
                                }
nkeynes@359
  1505
                                break;
nkeynes@359
  1506
                            case 0x2:
nkeynes@359
  1507
                                { /* ROTCL Rn */
nkeynes@359
  1508
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1509
                                load_reg( R_EAX, Rn );
nkeynes@417
  1510
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1511
                            	LDC_t();
nkeynes@417
  1512
                                }
nkeynes@359
  1513
                                RCL1_r32( R_EAX );
nkeynes@359
  1514
                                store_reg( R_EAX, Rn );
nkeynes@359
  1515
                                SETC_t();
nkeynes@417
  1516
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1517
                                }
nkeynes@359
  1518
                                break;
nkeynes@359
  1519
                            default:
nkeynes@359
  1520
                                UNDEF();
nkeynes@359
  1521
                                break;
nkeynes@359
  1522
                        }
nkeynes@359
  1523
                        break;
nkeynes@359
  1524
                    case 0x5:
nkeynes@359
  1525
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1526
                            case 0x0:
nkeynes@359
  1527
                                { /* ROTR Rn */
nkeynes@359
  1528
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1529
                                load_reg( R_EAX, Rn );
nkeynes@359
  1530
                                ROR1_r32( R_EAX );
nkeynes@359
  1531
                                store_reg( R_EAX, Rn );
nkeynes@359
  1532
                                SETC_t();
nkeynes@417
  1533
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1534
                                }
nkeynes@359
  1535
                                break;
nkeynes@359
  1536
                            case 0x1:
nkeynes@359
  1537
                                { /* CMP/PL Rn */
nkeynes@359
  1538
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1539
                                load_reg( R_EAX, Rn );
nkeynes@359
  1540
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1541
                                SETG_t();
nkeynes@417
  1542
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1543
                                }
nkeynes@359
  1544
                                break;
nkeynes@359
  1545
                            case 0x2:
nkeynes@359
  1546
                                { /* ROTCR Rn */
nkeynes@359
  1547
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1548
                                load_reg( R_EAX, Rn );
nkeynes@417
  1549
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1550
                            	LDC_t();
nkeynes@417
  1551
                                }
nkeynes@359
  1552
                                RCR1_r32( R_EAX );
nkeynes@359
  1553
                                store_reg( R_EAX, Rn );
nkeynes@359
  1554
                                SETC_t();
nkeynes@417
  1555
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1556
                                }
nkeynes@359
  1557
                                break;
nkeynes@359
  1558
                            default:
nkeynes@359
  1559
                                UNDEF();
nkeynes@359
  1560
                                break;
nkeynes@359
  1561
                        }
nkeynes@359
  1562
                        break;
nkeynes@359
  1563
                    case 0x6:
nkeynes@359
  1564
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1565
                            case 0x0:
nkeynes@359
  1566
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1567
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1568
                                load_reg( R_EAX, Rm );
nkeynes@395
  1569
                                check_ralign32( R_EAX );
nkeynes@571
  1570
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1571
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1572
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1573
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1574
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1575
                                }
nkeynes@359
  1576
                                break;
nkeynes@359
  1577
                            case 0x1:
nkeynes@359
  1578
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1579
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1580
                                load_reg( R_EAX, Rm );
nkeynes@395
  1581
                                check_ralign32( R_EAX );
nkeynes@571
  1582
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1583
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1584
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1585
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1586
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1587
                                }
nkeynes@359
  1588
                                break;
nkeynes@359
  1589
                            case 0x2:
nkeynes@359
  1590
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1591
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1592
                                load_reg( R_EAX, Rm );
nkeynes@395
  1593
                                check_ralign32( R_EAX );
nkeynes@571
  1594
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1595
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1596
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1597
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1598
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1599
                                }
nkeynes@359
  1600
                                break;
nkeynes@359
  1601
                            case 0x3:
nkeynes@359
  1602
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1603
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1604
                                check_priv();
nkeynes@359
  1605
                                load_reg( R_EAX, Rm );
nkeynes@395
  1606
                                check_ralign32( R_EAX );
nkeynes@571
  1607
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1608
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1609
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1610
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1611
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1612
                                }
nkeynes@359
  1613
                                break;
nkeynes@359
  1614
                            case 0x5:
nkeynes@359
  1615
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1616
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1617
                                load_reg( R_EAX, Rm );
nkeynes@395
  1618
                                check_ralign32( R_EAX );
nkeynes@571
  1619
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1620
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1621
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1622
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1623
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1624
                                }
nkeynes@359
  1625
                                break;
nkeynes@359
  1626
                            case 0x6:
nkeynes@359
  1627
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1628
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1629
                                load_reg( R_EAX, Rm );
nkeynes@395
  1630
                                check_ralign32( R_EAX );
nkeynes@571
  1631
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1632
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1633
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1634
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1635
                                update_fr_bank( R_EAX );
nkeynes@417
  1636
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1637
                                }
nkeynes@359
  1638
                                break;
nkeynes@359
  1639
                            case 0xF:
nkeynes@359
  1640
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1641
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1642
                                check_priv();
nkeynes@359
  1643
                                load_reg( R_EAX, Rm );
nkeynes@395
  1644
                                check_ralign32( R_EAX );
nkeynes@571
  1645
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1646
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1647
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1648
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1649
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1650
                                }
nkeynes@359
  1651
                                break;
nkeynes@359
  1652
                            default:
nkeynes@359
  1653
                                UNDEF();
nkeynes@359
  1654
                                break;
nkeynes@359
  1655
                        }
nkeynes@359
  1656
                        break;
nkeynes@359
  1657
                    case 0x7:
nkeynes@359
  1658
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1659
                            case 0x0:
nkeynes@359
  1660
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1661
                                    case 0x0:
nkeynes@359
  1662
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1663
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1664
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1665
                                    	SLOTILLEGAL();
nkeynes@386
  1666
                                        } else {
nkeynes@559
  1667
                                    	check_priv();
nkeynes@386
  1668
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1669
                                    	check_ralign32( R_EAX );
nkeynes@571
  1670
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1671
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1672
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1673
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1674
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1675
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1676
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1677
                                        }
nkeynes@359
  1678
                                        }
nkeynes@359
  1679
                                        break;
nkeynes@359
  1680
                                    case 0x1:
nkeynes@359
  1681
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1682
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1683
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1684
                                        check_ralign32( R_EAX );
nkeynes@571
  1685
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1686
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1687
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1688
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1689
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1690
                                        }
nkeynes@359
  1691
                                        break;
nkeynes@359
  1692
                                    case 0x2:
nkeynes@359
  1693
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1694
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1695
                                        check_priv();
nkeynes@359
  1696
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1697
                                        check_ralign32( R_EAX );
nkeynes@571
  1698
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1699
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1700
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1701
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1702
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1703
                                        }
nkeynes@359
  1704
                                        break;
nkeynes@359
  1705
                                    case 0x3:
nkeynes@359
  1706
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1707
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1708
                                        check_priv();
nkeynes@359
  1709
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1710
                                        check_ralign32( R_EAX );
nkeynes@571
  1711
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1712
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1713
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1714
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1715
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1716
                                        }
nkeynes@359
  1717
                                        break;
nkeynes@359
  1718
                                    case 0x4:
nkeynes@359
  1719
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1720
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1721
                                        check_priv();
nkeynes@359
  1722
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1723
                                        check_ralign32( R_EAX );
nkeynes@571
  1724
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1725
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1726
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1727
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1728
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1729
                                        }
nkeynes@359
  1730
                                        break;
nkeynes@359
  1731
                                    default:
nkeynes@359
  1732
                                        UNDEF();
nkeynes@359
  1733
                                        break;
nkeynes@359
  1734
                                }
nkeynes@359
  1735
                                break;
nkeynes@359
  1736
                            case 0x1:
nkeynes@359
  1737
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1738
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1739
                                check_priv();
nkeynes@374
  1740
                                load_reg( R_EAX, Rm );
nkeynes@395
  1741
                                check_ralign32( R_EAX );
nkeynes@571
  1742
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1743
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1744
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1745
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1746
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1747
                                }
nkeynes@359
  1748
                                break;
nkeynes@359
  1749
                        }
nkeynes@359
  1750
                        break;
nkeynes@359
  1751
                    case 0x8:
nkeynes@359
  1752
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1753
                            case 0x0:
nkeynes@359
  1754
                                { /* SHLL2 Rn */
nkeynes@359
  1755
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1756
                                load_reg( R_EAX, Rn );
nkeynes@359
  1757
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1758
                                store_reg( R_EAX, Rn );
nkeynes@417
  1759
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1760
                                }
nkeynes@359
  1761
                                break;
nkeynes@359
  1762
                            case 0x1:
nkeynes@359
  1763
                                { /* SHLL8 Rn */
nkeynes@359
  1764
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1765
                                load_reg( R_EAX, Rn );
nkeynes@359
  1766
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1767
                                store_reg( R_EAX, Rn );
nkeynes@417
  1768
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1769
                                }
nkeynes@359
  1770
                                break;
nkeynes@359
  1771
                            case 0x2:
nkeynes@359
  1772
                                { /* SHLL16 Rn */
nkeynes@359
  1773
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1774
                                load_reg( R_EAX, Rn );
nkeynes@359
  1775
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1776
                                store_reg( R_EAX, Rn );
nkeynes@417
  1777
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1778
                                }
nkeynes@359
  1779
                                break;
nkeynes@359
  1780
                            default:
nkeynes@359
  1781
                                UNDEF();
nkeynes@359
  1782
                                break;
nkeynes@359
  1783
                        }
nkeynes@359
  1784
                        break;
nkeynes@359
  1785
                    case 0x9:
nkeynes@359
  1786
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1787
                            case 0x0:
nkeynes@359
  1788
                                { /* SHLR2 Rn */
nkeynes@359
  1789
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1790
                                load_reg( R_EAX, Rn );
nkeynes@359
  1791
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1792
                                store_reg( R_EAX, Rn );
nkeynes@417
  1793
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1794
                                }
nkeynes@359
  1795
                                break;
nkeynes@359
  1796
                            case 0x1:
nkeynes@359
  1797
                                { /* SHLR8 Rn */
nkeynes@359
  1798
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1799
                                load_reg( R_EAX, Rn );
nkeynes@359
  1800
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1801
                                store_reg( R_EAX, Rn );
nkeynes@417
  1802
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1803
                                }
nkeynes@359
  1804
                                break;
nkeynes@359
  1805
                            case 0x2:
nkeynes@359
  1806
                                { /* SHLR16 Rn */
nkeynes@359
  1807
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1808
                                load_reg( R_EAX, Rn );
nkeynes@359
  1809
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1810
                                store_reg( R_EAX, Rn );
nkeynes@417
  1811
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1812
                                }
nkeynes@359
  1813
                                break;
nkeynes@359
  1814
                            default:
nkeynes@359
  1815
                                UNDEF();
nkeynes@359
  1816
                                break;
nkeynes@359
  1817
                        }
nkeynes@359
  1818
                        break;
nkeynes@359
  1819
                    case 0xA:
nkeynes@359
  1820
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1821
                            case 0x0:
nkeynes@359
  1822
                                { /* LDS Rm, MACH */
nkeynes@359
  1823
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1824
                                load_reg( R_EAX, Rm );
nkeynes@359
  1825
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1826
                                }
nkeynes@359
  1827
                                break;
nkeynes@359
  1828
                            case 0x1:
nkeynes@359
  1829
                                { /* LDS Rm, MACL */
nkeynes@359
  1830
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1831
                                load_reg( R_EAX, Rm );
nkeynes@359
  1832
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1833
                                }
nkeynes@359
  1834
                                break;
nkeynes@359
  1835
                            case 0x2:
nkeynes@359
  1836
                                { /* LDS Rm, PR */
nkeynes@359
  1837
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1838
                                load_reg( R_EAX, Rm );
nkeynes@359
  1839
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1840
                                }
nkeynes@359
  1841
                                break;
nkeynes@359
  1842
                            case 0x3:
nkeynes@359
  1843
                                { /* LDC Rm, SGR */
nkeynes@359
  1844
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1845
                                check_priv();
nkeynes@359
  1846
                                load_reg( R_EAX, Rm );
nkeynes@359
  1847
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1848
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1849
                                }
nkeynes@359
  1850
                                break;
nkeynes@359
  1851
                            case 0x5:
nkeynes@359
  1852
                                { /* LDS Rm, FPUL */
nkeynes@359
  1853
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1854
                                load_reg( R_EAX, Rm );
nkeynes@359
  1855
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1856
                                }
nkeynes@359
  1857
                                break;
nkeynes@359
  1858
                            case 0x6:
nkeynes@359
  1859
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1860
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1861
                                load_reg( R_EAX, Rm );
nkeynes@359
  1862
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1863
                                update_fr_bank( R_EAX );
nkeynes@417
  1864
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1865
                                }
nkeynes@359
  1866
                                break;
nkeynes@359
  1867
                            case 0xF:
nkeynes@359
  1868
                                { /* LDC Rm, DBR */
nkeynes@359
  1869
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1870
                                check_priv();
nkeynes@359
  1871
                                load_reg( R_EAX, Rm );
nkeynes@359
  1872
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1873
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1874
                                }
nkeynes@359
  1875
                                break;
nkeynes@359
  1876
                            default:
nkeynes@359
  1877
                                UNDEF();
nkeynes@359
  1878
                                break;
nkeynes@359
  1879
                        }
nkeynes@359
  1880
                        break;
nkeynes@359
  1881
                    case 0xB:
nkeynes@359
  1882
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1883
                            case 0x0:
nkeynes@359
  1884
                                { /* JSR @Rn */
nkeynes@359
  1885
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1886
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1887
                            	SLOTILLEGAL();
nkeynes@374
  1888
                                } else {
nkeynes@374
  1889
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1890
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1891
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1892
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1893
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1894
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1895
                            	exit_block_pcset(pc+2);
nkeynes@409
  1896
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1897
                            	return 4;
nkeynes@374
  1898
                                }
nkeynes@359
  1899
                                }
nkeynes@359
  1900
                                break;
nkeynes@359
  1901
                            case 0x1:
nkeynes@359
  1902
                                { /* TAS.B @Rn */
nkeynes@359
  1903
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@571
  1904
                                load_reg( R_EAX, Rn );
nkeynes@571
  1905
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1906
                                PUSH_realigned_r32( R_EAX );
nkeynes@571
  1907
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1908
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1909
                                SETE_t();
nkeynes@361
  1910
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@571
  1911
                                POP_realigned_r32( R_ECX );
nkeynes@361
  1912
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1913
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1914
                                }
nkeynes@359
  1915
                                break;
nkeynes@359
  1916
                            case 0x2:
nkeynes@359
  1917
                                { /* JMP @Rn */
nkeynes@359
  1918
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1919
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1920
                            	SLOTILLEGAL();
nkeynes@374
  1921
                                } else {
nkeynes@408
  1922
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1923
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1924
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1925
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1926
                            	exit_block_pcset(pc+2);
nkeynes@409
  1927
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1928
                            	return 4;
nkeynes@374
  1929
                                }
nkeynes@359
  1930
                                }
nkeynes@359
  1931
                                break;
nkeynes@359
  1932
                            default:
nkeynes@359
  1933
                                UNDEF();
nkeynes@359
  1934
                                break;
nkeynes@359
  1935
                        }
nkeynes@359
  1936
                        break;
nkeynes@359
  1937
                    case 0xC:
nkeynes@359
  1938
                        { /* SHAD Rm, Rn */
nkeynes@359
  1939
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1940
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1941
                        load_reg( R_EAX, Rn );
nkeynes@361
  1942
                        load_reg( R_ECX, Rm );
nkeynes@361
  1943
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1944
                        JGE_rel8(16, doshl);
nkeynes@361
  1945
                                        
nkeynes@361
  1946
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1947
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1948
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1949
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1950
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1951
                    
nkeynes@386
  1952
                        JMP_TARGET(emptysar);
nkeynes@386
  1953
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1954
                        JMP_rel8(5, end2);
nkeynes@386
  1955
                    
nkeynes@380
  1956
                        JMP_TARGET(doshl);
nkeynes@361
  1957
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1958
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1959
                        JMP_TARGET(end);
nkeynes@386
  1960
                        JMP_TARGET(end2);
nkeynes@361
  1961
                        store_reg( R_EAX, Rn );
nkeynes@417
  1962
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1963
                        }
nkeynes@359
  1964
                        break;
nkeynes@359
  1965
                    case 0xD:
nkeynes@359
  1966
                        { /* SHLD Rm, Rn */
nkeynes@359
  1967
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1968
                        load_reg( R_EAX, Rn );
nkeynes@368
  1969
                        load_reg( R_ECX, Rm );
nkeynes@386
  1970
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1971
                        JGE_rel8(15, doshl);
nkeynes@368
  1972
                    
nkeynes@386
  1973
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1974
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1975
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1976
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1977
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1978
                    
nkeynes@386
  1979
                        JMP_TARGET(emptyshr);
nkeynes@386
  1980
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1981
                        JMP_rel8(5, end2);
nkeynes@386
  1982
                    
nkeynes@386
  1983
                        JMP_TARGET(doshl);
nkeynes@386
  1984
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1985
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1986
                        JMP_TARGET(end);
nkeynes@386
  1987
                        JMP_TARGET(end2);
nkeynes@368
  1988
                        store_reg( R_EAX, Rn );
nkeynes@417
  1989
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1990
                        }
nkeynes@359
  1991
                        break;
nkeynes@359
  1992
                    case 0xE:
nkeynes@359
  1993
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1994
                            case 0x0:
nkeynes@359
  1995
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1996
                                    case 0x0:
nkeynes@359
  1997
                                        { /* LDC Rm, SR */
nkeynes@359
  1998
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1999
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2000
                                    	SLOTILLEGAL();
nkeynes@386
  2001
                                        } else {
nkeynes@386
  2002
                                    	check_priv();
nkeynes@386
  2003
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2004
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2005
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2006
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2007
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2008
                                        }
nkeynes@359
  2009
                                        }
nkeynes@359
  2010
                                        break;
nkeynes@359
  2011
                                    case 0x1:
nkeynes@359
  2012
                                        { /* LDC Rm, GBR */
nkeynes@359
  2013
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2014
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2015
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2016
                                        }
nkeynes@359
  2017
                                        break;
nkeynes@359
  2018
                                    case 0x2:
nkeynes@359
  2019
                                        { /* LDC Rm, VBR */
nkeynes@359
  2020
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2021
                                        check_priv();
nkeynes@359
  2022
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2023
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2024
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2025
                                        }
nkeynes@359
  2026
                                        break;
nkeynes@359
  2027
                                    case 0x3:
nkeynes@359
  2028
                                        { /* LDC Rm, SSR */
nkeynes@359
  2029
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2030
                                        check_priv();
nkeynes@359
  2031
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2032
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2033
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2034
                                        }
nkeynes@359
  2035
                                        break;
nkeynes@359
  2036
                                    case 0x4:
nkeynes@359
  2037
                                        { /* LDC Rm, SPC */
nkeynes@359
  2038
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2039
                                        check_priv();
nkeynes@359
  2040
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2041
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2042
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2043
                                        }
nkeynes@359
  2044
                                        break;
nkeynes@359
  2045
                                    default:
nkeynes@359
  2046
                                        UNDEF();
nkeynes@359
  2047
                                        break;
nkeynes@359
  2048
                                }
nkeynes@359
  2049
                                break;
nkeynes@359
  2050
                            case 0x1:
nkeynes@359
  2051
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2052
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2053
                                check_priv();
nkeynes@374
  2054
                                load_reg( R_EAX, Rm );
nkeynes@374
  2055
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2056
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2057
                                }
nkeynes@359
  2058
                                break;
nkeynes@359
  2059
                        }
nkeynes@359
  2060
                        break;
nkeynes@359
  2061
                    case 0xF:
nkeynes@359
  2062
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2063
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
  2064
                        if( Rm == Rn ) {
nkeynes@571
  2065
                    	load_reg( R_EAX, Rm );
nkeynes@571
  2066
                    	check_ralign16( R_EAX );
nkeynes@571
  2067
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2068
                    	PUSH_realigned_r32( R_EAX );
nkeynes@571
  2069
                    	load_reg( R_EAX, Rn );
nkeynes@571
  2070
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@571
  2071
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2072
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2073
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
  2074
                    	// adding a page-boundary check to skip the second translation
nkeynes@571
  2075
                        } else {
nkeynes@571
  2076
                    	load_reg( R_EAX, Rm );
nkeynes@571
  2077
                    	check_ralign16( R_EAX );
nkeynes@571
  2078
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2079
                    	PUSH_realigned_r32( R_EAX );
nkeynes@571
  2080
                    	load_reg( R_EAX, Rn );
nkeynes@571
  2081
                    	check_ralign16( R_EAX );
nkeynes@571
  2082
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2083
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@571
  2084
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
  2085
                        }
nkeynes@571
  2086
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@571
  2087
                        POP_r32( R_ECX );
nkeynes@571
  2088
                        PUSH_r32( R_EAX );
nkeynes@386
  2089
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2090
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2091
                        IMUL_r32( R_ECX );
nkeynes@386
  2092
                    
nkeynes@386
  2093
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2094
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2095
                        JE_rel8( 47, nosat );
nkeynes@386
  2096
                    
nkeynes@386
  2097
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2098
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2099
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2100
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2101
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2102
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2103
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2104
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2105
                    
nkeynes@386
  2106
                        JMP_TARGET(positive);
nkeynes@386
  2107
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2108
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2109
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2110
                    
nkeynes@386
  2111
                        JMP_TARGET(nosat);
nkeynes@386
  2112
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2113
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2114
                        JMP_TARGET(end);
nkeynes@386
  2115
                        JMP_TARGET(end2);
nkeynes@386
  2116
                        JMP_TARGET(end3);
nkeynes@417
  2117
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2118
                        }
nkeynes@359
  2119
                        break;
nkeynes@359
  2120
                }
nkeynes@359
  2121
                break;
nkeynes@359
  2122
            case 0x5:
nkeynes@359
  2123
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2124
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@571
  2125
                load_reg( R_EAX, Rm );
nkeynes@571
  2126
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@571
  2127
                check_ralign32( R_EAX );
nkeynes@571
  2128
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2129
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2130
                store_reg( R_EAX, Rn );
nkeynes@417
  2131
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2132
                }
nkeynes@359
  2133
                break;
nkeynes@359
  2134
            case 0x6:
nkeynes@359
  2135
                switch( ir&0xF ) {
nkeynes@359
  2136
                    case 0x0:
nkeynes@359
  2137
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2138
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
  2139
                        load_reg( R_EAX, Rm );
nkeynes@571
  2140
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2141
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2142
                        store_reg( R_EAX, Rn );
nkeynes@417
  2143
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2144
                        }
nkeynes@359
  2145
                        break;
nkeynes@359
  2146
                    case 0x1:
nkeynes@359
  2147
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2148
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
  2149
                        load_reg( R_EAX, Rm );
nkeynes@571
  2150
                        check_ralign16( R_EAX );
nkeynes@571
  2151
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2152
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2153
                        store_reg( R_EAX, Rn );
nkeynes@417
  2154
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2155
                        }
nkeynes@359
  2156
                        break;
nkeynes@359
  2157
                    case 0x2:
nkeynes@359
  2158
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2159
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
  2160
                        load_reg( R_EAX, Rm );
nkeynes@571
  2161
                        check_ralign32( R_EAX );
nkeynes@571
  2162
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2163
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2164
                        store_reg( R_EAX, Rn );
nkeynes@417
  2165
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2166
                        }
nkeynes@359
  2167
                        break;
nkeynes@359
  2168
                    case 0x3:
nkeynes@359
  2169
                        { /* MOV Rm, Rn */
nkeynes@359
  2170
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2171
                        load_reg( R_EAX, Rm );
nkeynes@359
  2172
                        store_reg( R_EAX, Rn );
nkeynes@359
  2173
                        }
nkeynes@359
  2174
                        break;
nkeynes@359
  2175
                    case 0x4:
nkeynes@359
  2176
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2177
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@571
  2178
                        load_reg( R_EAX, Rm );
nkeynes@571
  2179
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2180
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@571
  2181
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2182
                        store_reg( R_EAX, Rn );
nkeynes@417
  2183
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2184
                        }
nkeynes@359
  2185
                        break;
nkeynes@359
  2186
                    case 0x5:
nkeynes@359
  2187
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2188
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2189
                        load_reg( R_EAX, Rm );
nkeynes@374
  2190
                        check_ralign16( R_EAX );
nkeynes@571
  2191
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2192
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
  2193
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2194
                        store_reg( R_EAX, Rn );
nkeynes@417
  2195
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2196
                        }
nkeynes@359
  2197
                        break;
nkeynes@359
  2198
                    case 0x6:
nkeynes@359
  2199
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2200
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2201
                        load_reg( R_EAX, Rm );
nkeynes@386
  2202
                        check_ralign32( R_EAX );
nkeynes@571
  2203
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2204
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2205
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2206
                        store_reg( R_EAX, Rn );
nkeynes@417
  2207
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2208
                        }
nkeynes@359
  2209
                        break;
nkeynes@359
  2210
                    case 0x7:
nkeynes@359
  2211
                        { /* NOT Rm, Rn */
nkeynes@359
  2212
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2213
                        load_reg( R_EAX, Rm );
nkeynes@359
  2214
                        NOT_r32( R_EAX );
nkeynes@359
  2215
                        store_reg( R_EAX, Rn );
nkeynes@417
  2216
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2217
                        }
nkeynes@359
  2218
                        break;
nkeynes@359
  2219
                    case 0x8:
nkeynes@359
  2220
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2221
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2222
                        load_reg( R_EAX, Rm );
nkeynes@359
  2223
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2224
                        store_reg( R_EAX, Rn );
nkeynes@359
  2225
                        }
nkeynes@359
  2226
                        break;
nkeynes@359
  2227
                    case 0x9:
nkeynes@359
  2228
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2229
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2230
                        load_reg( R_EAX, Rm );
nkeynes@359
  2231
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2232
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2233
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2234
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2235
                        store_reg( R_ECX, Rn );
nkeynes@417
  2236
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2237
                        }
nkeynes@359
  2238
                        break;
nkeynes@359
  2239
                    case 0xA:
nkeynes@359
  2240
                        { /* NEGC Rm, Rn */
nkeynes@359
  2241
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2242
                        load_reg( R_EAX, Rm );
nkeynes@359
  2243
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2244
                        LDC_t();
nkeynes@359
  2245
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2246
                        store_reg( R_ECX, Rn );
nkeynes@359
  2247
                        SETC_t();
nkeynes@417
  2248
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2249
                        }
nkeynes@359
  2250
                        break;
nkeynes@359
  2251
                    case 0xB:
nkeynes@359
  2252
                        { /* NEG Rm, Rn */
nkeynes@359
  2253
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2254
                        load_reg( R_EAX, Rm );
nkeynes@359
  2255
                        NEG_r32( R_EAX );
nkeynes@359
  2256
                        store_reg( R_EAX, Rn );
nkeynes@417
  2257
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2258
                        }
nkeynes@359
  2259
                        break;
nkeynes@359
  2260
                    case 0xC:
nkeynes@359
  2261
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2262
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2263
                        load_reg( R_EAX, Rm );
nkeynes@361
  2264
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2265
                        store_reg( R_EAX, Rn );
nkeynes@359
  2266
                        }
nkeynes@359
  2267
                        break;
nkeynes@359
  2268
                    case 0xD:
nkeynes@359
  2269
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2270
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2271
                        load_reg( R_EAX, Rm );
nkeynes@361
  2272
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2273
                        store_reg( R_EAX, Rn );
nkeynes@359
  2274
                        }
nkeynes@359
  2275
                        break;
nkeynes@359
  2276
                    case 0xE:
nkeynes@359
  2277
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2278
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2279
                        load_reg( R_EAX, Rm );
nkeynes@359
  2280
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2281
                        store_reg( R_EAX, Rn );
nkeynes@359
  2282
                        }
nkeynes@359
  2283
                        break;
nkeynes@359
  2284
                    case 0xF:
nkeynes@359
  2285
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2286
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2287
                        load_reg( R_EAX, Rm );
nkeynes@361
  2288
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2289
                        store_reg( R_EAX, Rn );
nkeynes@359
  2290
                        }
nkeynes@359
  2291
                        break;
nkeynes@359
  2292
                }
nkeynes@359
  2293
                break;
nkeynes@359
  2294
            case 0x7:
nkeynes@359
  2295
                { /* ADD #imm, Rn */
nkeynes@359
  2296
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2297
                load_reg( R_EAX, Rn );
nkeynes@359
  2298
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2299
                store_reg( R_EAX, Rn );
nkeynes@417
  2300
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2301
                }
nkeynes@359
  2302
                break;
nkeynes@359
  2303
            case 0x8:
nkeynes@359
  2304
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2305
                    case 0x0:
nkeynes@359
  2306
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2307
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@571
  2308
                        load_reg( R_EAX, Rn );
nkeynes@571
  2309
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2310
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2311
                        load_reg( R_EDX, 0 );
nkeynes@571
  2312
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2313
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2314
                        }
nkeynes@359
  2315
                        break;
nkeynes@359
  2316
                    case 0x1:
nkeynes@359
  2317
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2318
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@571
  2319
                        load_reg( R_EAX, Rn );
nkeynes@571
  2320
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2321
                        check_walign16( R_EAX );
nkeynes@571
  2322
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2323
                        load_reg( R_EDX, 0 );
nkeynes@571
  2324
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2325
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2326
                        }
nkeynes@359
  2327
                        break;
nkeynes@359
  2328
                    case 0x4:
nkeynes@359
  2329
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2330
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@571
  2331
                        load_reg( R_EAX, Rm );
nkeynes@571
  2332
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2333
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2334
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2335
                        store_reg( R_EAX, 0 );
nkeynes@417
  2336
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2337
                        }
nkeynes@359
  2338
                        break;
nkeynes@359
  2339
                    case 0x5:
nkeynes@359
  2340
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2341
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@571
  2342
                        load_reg( R_EAX, Rm );
nkeynes@571
  2343
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2344
                        check_ralign16( R_EAX );
nkeynes@571
  2345
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2346
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2347
                        store_reg( R_EAX, 0 );
nkeynes@417
  2348
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2349
                        }
nkeynes@359
  2350
                        break;
nkeynes@359
  2351
                    case 0x8:
nkeynes@359
  2352
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2353
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2354
                        load_reg( R_EAX, 0 );
nkeynes@359
  2355
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2356
                        SETE_t();
nkeynes@417
  2357
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2358
                        }
nkeynes@359
  2359
                        break;
nkeynes@359
  2360
                    case 0x9:
nkeynes@359
  2361
                        { /* BT disp */
nkeynes@359
  2362
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2363
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2364
                    	SLOTILLEGAL();
nkeynes@374
  2365
                        } else {
nkeynes@571
  2366
                    	sh4vma_t target = disp + pc + 4;
nkeynes@571
  2367
                    	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  2368
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2369
                    	JMP_TARGET(nottaken);
nkeynes@408
  2370
                    	return 2;
nkeynes@374
  2371
                        }
nkeynes@359
  2372
                        }
nkeynes@359
  2373
                        break;
nkeynes@359
  2374
                    case 0xB:
nkeynes@359
  2375
                        { /* BF disp */
nkeynes@359
  2376
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2377
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2378
                    	SLOTILLEGAL();
nkeynes@374
  2379
                        } else {
nkeynes@571
  2380
                    	sh4vma_t target = disp + pc + 4;
nkeynes@571
  2381
                    	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  2382
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2383
                    	JMP_TARGET(nottaken);
nkeynes@408
  2384
                    	return 2;
nkeynes@374
  2385
                        }
nkeynes@359
  2386
                        }
nkeynes@359
  2387
                        break;
nkeynes@359
  2388
                    case 0xD:
nkeynes@359
  2389
                        { /* BT/S disp */
nkeynes@359
  2390
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2391
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2392
                    	SLOTILLEGAL();
nkeynes@374
  2393
                        } else {
nkeynes@408
  2394
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2395
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2396
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2397
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2398
                    	}
nkeynes@417
  2399
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2400
                    	sh4_translate_instruction(pc+2);
nkeynes@571
  2401
                    	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  2402
                    	// not taken
nkeynes@408
  2403
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2404
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2405
                    	return 4;
nkeynes@374
  2406
                        }
nkeynes@359
  2407
                        }
nkeynes@359
  2408
                        break;
nkeynes@359
  2409
                    case 0xF:
nkeynes@359
  2410
                        { /* BF/S disp */
nkeynes@359
  2411
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2412
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2413
                    	SLOTILLEGAL();
nkeynes@374
  2414
                        } else {
nkeynes@571
  2415
                    	sh4vma_t target = disp + pc + 4;
nkeynes@408
  2416
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2417
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2418
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2419
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2420
                    	}
nkeynes@417
  2421
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2422
                    	sh4_translate_instruction(pc+2);
nkeynes@571
  2423
                    	exit_block_rel( target, pc+4 );
nkeynes@408
  2424
                    	// not taken
nkeynes@408
  2425
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2426
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2427
                    	return 4;
nkeynes@374
  2428
                        }
nkeynes@359
  2429
                        }
nkeynes@359
  2430
                        break;
nkeynes@359
  2431
                    default:
nkeynes@359
  2432
                        UNDEF();
nkeynes@359
  2433
                        break;
nkeynes@359
  2434
                }
nkeynes@359
  2435
                break;
nkeynes@359
  2436
            case 0x9:
nkeynes@359
  2437
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2438
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2439
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2440
            	SLOTILLEGAL();
nkeynes@374
  2441
                } else {
nkeynes@569
  2442
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  2443
            	uint32_t target = pc + disp + 4;
nkeynes@569
  2444
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2445
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  2446
            	    MOV_moff32_EAX( ptr );
nkeynes@569
  2447
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  2448
            	} else {
nkeynes@571
  2449
            	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@571
  2450
            	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@571
  2451
            	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2452
            	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@569
  2453
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  2454
            	}
nkeynes@374
  2455
            	store_reg( R_EAX, Rn );
nkeynes@374
  2456
                }
nkeynes@359
  2457
                }
nkeynes@359
  2458
                break;
nkeynes@359
  2459
            case 0xA:
nkeynes@359
  2460
                { /* BRA disp */
nkeynes@359
  2461
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2462
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2463
            	SLOTILLEGAL();
nkeynes@374
  2464
                } else {
nkeynes@374
  2465
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2466
            	sh4_translate_instruction( pc + 2 );
nkeynes@571
  2467
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2468
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2469
            	return 4;
nkeynes@374
  2470
                }
nkeynes@359
  2471
                }
nkeynes@359
  2472
                break;
nkeynes@359
  2473
            case 0xB:
nkeynes@359
  2474
                { /* BSR disp */
nkeynes@359
  2475
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2476
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2477
            	SLOTILLEGAL();
nkeynes@374
  2478
                } else {
nkeynes@374
  2479
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2480
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2481
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2482
            	sh4_translate_instruction( pc + 2 );
nkeynes@571
  2483
            	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  2484
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2485
            	return 4;
nkeynes@374
  2486
                }
nkeynes@359
  2487
                }
nkeynes@359
  2488
                break;
nkeynes@359
  2489
            case 0xC:
nkeynes@359
  2490
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2491
                    case 0x0:
nkeynes@359
  2492
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2493
                        uint32_t disp = (ir&0xFF); 
nkeynes@571
  2494
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2495
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2496
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2497
                        load_reg( R_EDX, 0 );
nkeynes@571
  2498
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2499
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2500
                        }
nkeynes@359
  2501
                        break;
nkeynes@359
  2502
                    case 0x1:
nkeynes@359
  2503
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2504
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@571
  2505
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2506
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2507
                        check_walign16( R_EAX );
nkeynes@571
  2508
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2509
                        load_reg( R_EDX, 0 );
nkeynes@571
  2510
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2511
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2512
                        }
nkeynes@359
  2513
                        break;
nkeynes@359
  2514
                    case 0x2:
nkeynes@359
  2515
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2516
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@571
  2517
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2518
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2519
                        check_walign32( R_EAX );
nkeynes@571
  2520
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2521
                        load_reg( R_EDX, 0 );
nkeynes@571
  2522
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2523
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2524
                        }
nkeynes@359
  2525
                        break;
nkeynes@359
  2526
                    case 0x3:
nkeynes@359
  2527
                        { /* TRAPA #imm */
nkeynes@359
  2528
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2529
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2530
                    	SLOTILLEGAL();
nkeynes@374
  2531
                        } else {
nkeynes@533
  2532
                    	load_imm32( R_ECX, pc+2 );
nkeynes@533
  2533
                    	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  2534
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2535
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2536
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2537
                    	exit_block_pcset(pc);
nkeynes@409
  2538
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2539
                    	return 2;
nkeynes@374
  2540
                        }
nkeynes@359
  2541
                        }
nkeynes@359
  2542
                        break;
nkeynes@359
  2543
                    case 0x4:
nkeynes@359
  2544
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2545
                        uint32_t disp = (ir&0xFF); 
nkeynes@571
  2546
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2547
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2548
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2549
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2550
                        store_reg( R_EAX, 0 );
nkeynes@417
  2551
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2552
                        }
nkeynes@359
  2553
                        break;
nkeynes@359
  2554
                    case 0x5:
nkeynes@359
  2555
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2556
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@571
  2557
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2558
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2559
                        check_ralign16( R_EAX );
nkeynes@571
  2560
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2561
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2562
                        store_reg( R_EAX, 0 );
nkeynes@417
  2563
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2564
                        }
nkeynes@359
  2565
                        break;
nkeynes@359
  2566
                    case 0x6:
nkeynes@359
  2567
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2568
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@571
  2569
                        load_spreg( R_EAX, R_GBR );
nkeynes@571
  2570
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  2571
                        check_ralign32( R_EAX );
nkeynes@571
  2572
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2573
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2574
                        store_reg( R_EAX, 0 );
nkeynes@417
  2575
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2576
                        }
nkeynes@359
  2577
                        break;
nkeynes@359
  2578
                    case 0x7:
nkeynes@359
  2579
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2580
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2581
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2582
                    	SLOTILLEGAL();
nkeynes@374
  2583
                        } else {
nkeynes@569
  2584
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  2585
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2586
                    	store_reg( R_ECX, 0 );
nkeynes@571
  2587
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2588
                        }
nkeynes@359
  2589
                        }
nkeynes@359
  2590
                        break;
nkeynes@359
  2591
                    case 0x8:
nkeynes@359
  2592
                        { /* TST #imm, R0 */
nkeynes@359
  2593
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2594
                        load_reg( R_EAX, 0 );
nkeynes@368
  2595
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2596
                        SETE_t();
nkeynes@417
  2597
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2598
                        }
nkeynes@359
  2599
                        break;
nkeynes@359
  2600
                    case 0x9:
nkeynes@359
  2601
                        { /* AND #imm, R0 */
nkeynes@359
  2602
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2603
                        load_reg( R_EAX, 0 );
nkeynes@359
  2604
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2605
                        store_reg( R_EAX, 0 );
nkeynes@417
  2606
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2607
                        }
nkeynes@359
  2608
                        break;
nkeynes@359
  2609
                    case 0xA:
nkeynes@359
  2610
                        { /* XOR #imm, R0 */
nkeynes@359
  2611
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2612
                        load_reg( R_EAX, 0 );
nkeynes@359
  2613
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2614
                        store_reg( R_EAX, 0 );
nkeynes@417
  2615
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
                        }
nkeynes@359
  2617
                        break;
nkeynes@359
  2618
                    case 0xB:
nkeynes@359
  2619
                        { /* OR #imm, R0 */
nkeynes@359
  2620
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2621
                        load_reg( R_EAX, 0 );
nkeynes@359
  2622
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2623
                        store_reg( R_EAX, 0 );
nkeynes@417
  2624
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2625
                        }
nkeynes@359
  2626
                        break;
nkeynes@359
  2627
                    case 0xC:
nkeynes@359
  2628
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2629
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2630
                        load_reg( R_EAX, 0);
nkeynes@368
  2631
                        load_reg( R_ECX, R_GBR);
nkeynes@571
  2632
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  2633
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2634
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  2635
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2636
                        SETE_t();
nkeynes@417
  2637
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2638
                        }
nkeynes@359
  2639
                        break;
nkeynes@359
  2640
                    case 0xD:
nkeynes@359
  2641
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2642
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2643
                        load_reg( R_EAX, 0 );
nkeynes@359
  2644
                        load_spreg( R_ECX, R_GBR );
nkeynes@571
  2645
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  2646
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2647
                        PUSH_realigned_r32(R_EAX);
nkeynes@571
  2648
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
  2649
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2650
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2651
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2652
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2653
                        }
nkeynes@359
  2654
                        break;
nkeynes@359
  2655
                    case 0xE:
nkeynes@359
  2656
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2657
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2658
                        load_reg( R_EAX, 0 );
nkeynes@359
  2659
                        load_spreg( R_ECX, R_GBR );
nkeynes@571
  2660
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  2661
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2662
                        PUSH_realigned_r32(R_EAX);
nkeynes@571
  2663
                        MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  2664
                        POP_realigned_r32(R_ECX);
nkeynes@359
  2665
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2666
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2667
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2668
                        }
nkeynes@359
  2669
                        break;
nkeynes@359
  2670
                    case 0xF:
nkeynes@359
  2671
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2672
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2673
                        load_reg( R_EAX, 0 );
nkeynes@374
  2674
                        load_spreg( R_ECX, R_GBR );
nkeynes@571
  2675
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  2676
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2677
                        PUSH_realigned_r32(R_EAX);
nkeynes@571
  2678
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
  2679
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2680
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2681
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2682
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2683
                        }
nkeynes@359
  2684
                        break;
nkeynes@359
  2685
                }
nkeynes@359
  2686
                break;
nkeynes@359
  2687
            case 0xD:
nkeynes@359
  2688
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2689
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2690
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2691
            	SLOTILLEGAL();
nkeynes@374
  2692
                } else {
nkeynes@388
  2693
            	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  2694
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2695
            	    // If the target address is in the same page as the code, it's
nkeynes@569
  2696
            	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  2697
            	    // memory subsystem. (this is a big performance win)
nkeynes@569
  2698
            
nkeynes@569
  2699
            	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  2700
            	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  2701
            	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  2702
            	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  2703
            	    // behaviour though.
nkeynes@56