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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 571:9bc09948d0f2
prev570:d2893980fbf5
next577:a181aeacd6e8
author nkeynes
date Thu Jan 10 08:28:37 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change More MMU work in progess. Much better now...
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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    uint32_t recovery_posn;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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void sh4_x86_add_recovery( uint32_t pc )
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{
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    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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    xlat_recovery_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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   334
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@571
   335
/**
nkeynes@571
   336
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@571
   337
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@571
   338
 */
nkeynes@571
   339
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@570
   340
nkeynes@571
   341
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@571
   342
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@571
   343
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@559
   344
nkeynes@559
   345
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   346
nkeynes@539
   347
/****** Import appropriate calling conventions ******/
nkeynes@539
   348
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   349
#include "sh4/ia64abi.h"
nkeynes@539
   350
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   351
#ifdef APPLE_BUILD
nkeynes@539
   352
#include "sh4/ia32mac.h"
nkeynes@539
   353
#else
nkeynes@539
   354
#include "sh4/ia32abi.h"
nkeynes@539
   355
#endif
nkeynes@539
   356
#endif
nkeynes@539
   357
nkeynes@539
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   361
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   362
 * 
nkeynes@359
   363
 *
nkeynes@359
   364
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   365
 * (eg a branch or 
nkeynes@359
   366
 */
nkeynes@526
   367
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   368
{
nkeynes@388
   369
    uint32_t ir;
nkeynes@388
   370
    /* Read instruction */
nkeynes@569
   371
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   372
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   373
    } else {
nkeynes@569
   374
	ir = sh4_read_word(pc);
nkeynes@388
   375
    }
nkeynes@571
   376
    if( !sh4_x86.in_delay_slot ) {
nkeynes@571
   377
	sh4_x86_add_recovery(pc);
nkeynes@571
   378
    }
nkeynes@359
   379
%%
nkeynes@359
   380
/* ALU operations */
nkeynes@359
   381
ADD Rm, Rn {:
nkeynes@359
   382
    load_reg( R_EAX, Rm );
nkeynes@359
   383
    load_reg( R_ECX, Rn );
nkeynes@359
   384
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   385
    store_reg( R_ECX, Rn );
nkeynes@417
   386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   387
:}
nkeynes@359
   388
ADD #imm, Rn {:  
nkeynes@359
   389
    load_reg( R_EAX, Rn );
nkeynes@359
   390
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   391
    store_reg( R_EAX, Rn );
nkeynes@417
   392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   393
:}
nkeynes@359
   394
ADDC Rm, Rn {:
nkeynes@417
   395
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   396
	LDC_t();
nkeynes@417
   397
    }
nkeynes@359
   398
    load_reg( R_EAX, Rm );
nkeynes@359
   399
    load_reg( R_ECX, Rn );
nkeynes@359
   400
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   401
    store_reg( R_ECX, Rn );
nkeynes@359
   402
    SETC_t();
nkeynes@417
   403
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   404
:}
nkeynes@359
   405
ADDV Rm, Rn {:
nkeynes@359
   406
    load_reg( R_EAX, Rm );
nkeynes@359
   407
    load_reg( R_ECX, Rn );
nkeynes@359
   408
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   409
    store_reg( R_ECX, Rn );
nkeynes@359
   410
    SETO_t();
nkeynes@417
   411
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   412
:}
nkeynes@359
   413
AND Rm, Rn {:
nkeynes@359
   414
    load_reg( R_EAX, Rm );
nkeynes@359
   415
    load_reg( R_ECX, Rn );
nkeynes@359
   416
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   417
    store_reg( R_ECX, Rn );
nkeynes@417
   418
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   419
:}
nkeynes@359
   420
AND #imm, R0 {:  
nkeynes@359
   421
    load_reg( R_EAX, 0 );
nkeynes@359
   422
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   423
    store_reg( R_EAX, 0 );
nkeynes@417
   424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   425
:}
nkeynes@359
   426
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   427
    load_reg( R_EAX, 0 );
nkeynes@359
   428
    load_spreg( R_ECX, R_GBR );
nkeynes@571
   429
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   430
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   431
    PUSH_realigned_r32(R_EAX);
nkeynes@571
   432
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   433
    POP_realigned_r32(R_ECX);
nkeynes@386
   434
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   435
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   437
:}
nkeynes@359
   438
CMP/EQ Rm, Rn {:  
nkeynes@359
   439
    load_reg( R_EAX, Rm );
nkeynes@359
   440
    load_reg( R_ECX, Rn );
nkeynes@359
   441
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   442
    SETE_t();
nkeynes@417
   443
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   444
:}
nkeynes@359
   445
CMP/EQ #imm, R0 {:  
nkeynes@359
   446
    load_reg( R_EAX, 0 );
nkeynes@359
   447
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   448
    SETE_t();
nkeynes@417
   449
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   450
:}
nkeynes@359
   451
CMP/GE Rm, Rn {:  
nkeynes@359
   452
    load_reg( R_EAX, Rm );
nkeynes@359
   453
    load_reg( R_ECX, Rn );
nkeynes@359
   454
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   455
    SETGE_t();
nkeynes@417
   456
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   457
:}
nkeynes@359
   458
CMP/GT Rm, Rn {: 
nkeynes@359
   459
    load_reg( R_EAX, Rm );
nkeynes@359
   460
    load_reg( R_ECX, Rn );
nkeynes@359
   461
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   462
    SETG_t();
nkeynes@417
   463
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   464
:}
nkeynes@359
   465
CMP/HI Rm, Rn {:  
nkeynes@359
   466
    load_reg( R_EAX, Rm );
nkeynes@359
   467
    load_reg( R_ECX, Rn );
nkeynes@359
   468
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   469
    SETA_t();
nkeynes@417
   470
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   471
:}
nkeynes@359
   472
CMP/HS Rm, Rn {: 
nkeynes@359
   473
    load_reg( R_EAX, Rm );
nkeynes@359
   474
    load_reg( R_ECX, Rn );
nkeynes@359
   475
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   476
    SETAE_t();
nkeynes@417
   477
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   478
 :}
nkeynes@359
   479
CMP/PL Rn {: 
nkeynes@359
   480
    load_reg( R_EAX, Rn );
nkeynes@359
   481
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   482
    SETG_t();
nkeynes@417
   483
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   484
:}
nkeynes@359
   485
CMP/PZ Rn {:  
nkeynes@359
   486
    load_reg( R_EAX, Rn );
nkeynes@359
   487
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   488
    SETGE_t();
nkeynes@417
   489
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   490
:}
nkeynes@361
   491
CMP/STR Rm, Rn {:  
nkeynes@368
   492
    load_reg( R_EAX, Rm );
nkeynes@368
   493
    load_reg( R_ECX, Rn );
nkeynes@368
   494
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   495
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   496
    JE_rel8(13, target1);
nkeynes@368
   497
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   498
    JE_rel8(9, target2);
nkeynes@368
   499
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   500
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   501
    JE_rel8(2, target3);
nkeynes@368
   502
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   503
    JMP_TARGET(target1);
nkeynes@380
   504
    JMP_TARGET(target2);
nkeynes@380
   505
    JMP_TARGET(target3);
nkeynes@368
   506
    SETE_t();
nkeynes@417
   507
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   508
:}
nkeynes@361
   509
DIV0S Rm, Rn {:
nkeynes@361
   510
    load_reg( R_EAX, Rm );
nkeynes@386
   511
    load_reg( R_ECX, Rn );
nkeynes@361
   512
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   513
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   514
    store_spreg( R_EAX, R_M );
nkeynes@361
   515
    store_spreg( R_ECX, R_Q );
nkeynes@361
   516
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   517
    SETNE_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   519
:}
nkeynes@361
   520
DIV0U {:  
nkeynes@361
   521
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   522
    store_spreg( R_EAX, R_Q );
nkeynes@361
   523
    store_spreg( R_EAX, R_M );
nkeynes@361
   524
    store_spreg( R_EAX, R_T );
nkeynes@417
   525
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   526
:}
nkeynes@386
   527
DIV1 Rm, Rn {:
nkeynes@386
   528
    load_spreg( R_ECX, R_M );
nkeynes@386
   529
    load_reg( R_EAX, Rn );
nkeynes@417
   530
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   531
	LDC_t();
nkeynes@417
   532
    }
nkeynes@386
   533
    RCL1_r32( R_EAX );
nkeynes@386
   534
    SETC_r8( R_DL ); // Q'
nkeynes@386
   535
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   536
    JE_rel8(5, mqequal);
nkeynes@386
   537
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   538
    JMP_rel8(3, end);
nkeynes@380
   539
    JMP_TARGET(mqequal);
nkeynes@386
   540
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   541
    JMP_TARGET(end);
nkeynes@386
   542
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   543
    SETC_r8(R_AL); // tmp1
nkeynes@386
   544
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   545
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   546
    store_spreg( R_ECX, R_Q );
nkeynes@386
   547
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   548
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   549
    store_spreg( R_EAX, R_T );
nkeynes@417
   550
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   551
:}
nkeynes@361
   552
DMULS.L Rm, Rn {:  
nkeynes@361
   553
    load_reg( R_EAX, Rm );
nkeynes@361
   554
    load_reg( R_ECX, Rn );
nkeynes@361
   555
    IMUL_r32(R_ECX);
nkeynes@361
   556
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   557
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   558
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   559
:}
nkeynes@361
   560
DMULU.L Rm, Rn {:  
nkeynes@361
   561
    load_reg( R_EAX, Rm );
nkeynes@361
   562
    load_reg( R_ECX, Rn );
nkeynes@361
   563
    MUL_r32(R_ECX);
nkeynes@361
   564
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   565
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   566
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   567
:}
nkeynes@359
   568
DT Rn {:  
nkeynes@359
   569
    load_reg( R_EAX, Rn );
nkeynes@382
   570
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   571
    store_reg( R_EAX, Rn );
nkeynes@359
   572
    SETE_t();
nkeynes@417
   573
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   574
:}
nkeynes@359
   575
EXTS.B Rm, Rn {:  
nkeynes@359
   576
    load_reg( R_EAX, Rm );
nkeynes@359
   577
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   578
    store_reg( R_EAX, Rn );
nkeynes@359
   579
:}
nkeynes@361
   580
EXTS.W Rm, Rn {:  
nkeynes@361
   581
    load_reg( R_EAX, Rm );
nkeynes@361
   582
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   583
    store_reg( R_EAX, Rn );
nkeynes@361
   584
:}
nkeynes@361
   585
EXTU.B Rm, Rn {:  
nkeynes@361
   586
    load_reg( R_EAX, Rm );
nkeynes@361
   587
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   588
    store_reg( R_EAX, Rn );
nkeynes@361
   589
:}
nkeynes@361
   590
EXTU.W Rm, Rn {:  
nkeynes@361
   591
    load_reg( R_EAX, Rm );
nkeynes@361
   592
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   593
    store_reg( R_EAX, Rn );
nkeynes@361
   594
:}
nkeynes@571
   595
MAC.L @Rm+, @Rn+ {:
nkeynes@571
   596
    if( Rm == Rn ) {
nkeynes@571
   597
	load_reg( R_EAX, Rm );
nkeynes@571
   598
	check_ralign32( R_EAX );
nkeynes@571
   599
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   600
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   601
	load_reg( R_EAX, Rn );
nkeynes@571
   602
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@571
   603
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   604
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@571
   605
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   606
	// adding a page-boundary check to skip the second translation
nkeynes@571
   607
    } else {
nkeynes@571
   608
	load_reg( R_EAX, Rm );
nkeynes@571
   609
	check_ralign32( R_EAX );
nkeynes@571
   610
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   611
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   612
	load_reg( R_EAX, Rn );
nkeynes@571
   613
	check_ralign32( R_EAX );
nkeynes@571
   614
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   615
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   616
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
   617
    }
nkeynes@571
   618
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@571
   619
    POP_r32( R_ECX );
nkeynes@571
   620
    PUSH_r32( R_EAX );
nkeynes@386
   621
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   622
    POP_realigned_r32( R_ECX );
nkeynes@571
   623
nkeynes@386
   624
    IMUL_r32( R_ECX );
nkeynes@386
   625
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   626
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   627
nkeynes@386
   628
    load_spreg( R_ECX, R_S );
nkeynes@386
   629
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   630
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   631
    call_func0( signsat48 );
nkeynes@386
   632
    JMP_TARGET( nosat );
nkeynes@417
   633
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   634
:}
nkeynes@386
   635
MAC.W @Rm+, @Rn+ {:  
nkeynes@571
   636
    if( Rm == Rn ) {
nkeynes@571
   637
	load_reg( R_EAX, Rm );
nkeynes@571
   638
	check_ralign16( R_EAX );
nkeynes@571
   639
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   640
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   641
	load_reg( R_EAX, Rn );
nkeynes@571
   642
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@571
   643
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   644
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   645
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   646
	// adding a page-boundary check to skip the second translation
nkeynes@571
   647
    } else {
nkeynes@571
   648
	load_reg( R_EAX, Rm );
nkeynes@571
   649
	check_ralign16( R_EAX );
nkeynes@571
   650
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   651
	PUSH_realigned_r32( R_EAX );
nkeynes@571
   652
	load_reg( R_EAX, Rn );
nkeynes@571
   653
	check_ralign16( R_EAX );
nkeynes@571
   654
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   655
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@571
   656
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
   657
    }
nkeynes@571
   658
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@571
   659
    POP_r32( R_ECX );
nkeynes@571
   660
    PUSH_r32( R_EAX );
nkeynes@386
   661
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   662
    POP_realigned_r32( R_ECX );
nkeynes@386
   663
    IMUL_r32( R_ECX );
nkeynes@386
   664
nkeynes@386
   665
    load_spreg( R_ECX, R_S );
nkeynes@386
   666
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   667
    JE_rel8( 47, nosat );
nkeynes@386
   668
nkeynes@386
   669
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   670
    JNO_rel8( 51, end );            // 2
nkeynes@386
   671
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   672
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   673
    JS_rel8( 13, positive );        // 2
nkeynes@386
   674
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   675
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   676
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   677
nkeynes@386
   678
    JMP_TARGET(positive);
nkeynes@386
   679
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   680
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   681
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   682
nkeynes@386
   683
    JMP_TARGET(nosat);
nkeynes@386
   684
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   685
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   686
    JMP_TARGET(end);
nkeynes@386
   687
    JMP_TARGET(end2);
nkeynes@386
   688
    JMP_TARGET(end3);
nkeynes@417
   689
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   690
:}
nkeynes@359
   691
MOVT Rn {:  
nkeynes@359
   692
    load_spreg( R_EAX, R_T );
nkeynes@359
   693
    store_reg( R_EAX, Rn );
nkeynes@359
   694
:}
nkeynes@361
   695
MUL.L Rm, Rn {:  
nkeynes@361
   696
    load_reg( R_EAX, Rm );
nkeynes@361
   697
    load_reg( R_ECX, Rn );
nkeynes@361
   698
    MUL_r32( R_ECX );
nkeynes@361
   699
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   700
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   701
:}
nkeynes@374
   702
MULS.W Rm, Rn {:
nkeynes@374
   703
    load_reg16s( R_EAX, Rm );
nkeynes@374
   704
    load_reg16s( R_ECX, Rn );
nkeynes@374
   705
    MUL_r32( R_ECX );
nkeynes@374
   706
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   707
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   708
:}
nkeynes@374
   709
MULU.W Rm, Rn {:  
nkeynes@374
   710
    load_reg16u( R_EAX, Rm );
nkeynes@374
   711
    load_reg16u( R_ECX, Rn );
nkeynes@374
   712
    MUL_r32( R_ECX );
nkeynes@374
   713
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   714
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   715
:}
nkeynes@359
   716
NEG Rm, Rn {:
nkeynes@359
   717
    load_reg( R_EAX, Rm );
nkeynes@359
   718
    NEG_r32( R_EAX );
nkeynes@359
   719
    store_reg( R_EAX, Rn );
nkeynes@417
   720
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   721
:}
nkeynes@359
   722
NEGC Rm, Rn {:  
nkeynes@359
   723
    load_reg( R_EAX, Rm );
nkeynes@359
   724
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   725
    LDC_t();
nkeynes@359
   726
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   727
    store_reg( R_ECX, Rn );
nkeynes@359
   728
    SETC_t();
nkeynes@417
   729
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   730
:}
nkeynes@359
   731
NOT Rm, Rn {:  
nkeynes@359
   732
    load_reg( R_EAX, Rm );
nkeynes@359
   733
    NOT_r32( R_EAX );
nkeynes@359
   734
    store_reg( R_EAX, Rn );
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   736
:}
nkeynes@359
   737
OR Rm, Rn {:  
nkeynes@359
   738
    load_reg( R_EAX, Rm );
nkeynes@359
   739
    load_reg( R_ECX, Rn );
nkeynes@359
   740
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   741
    store_reg( R_ECX, Rn );
nkeynes@417
   742
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   743
:}
nkeynes@359
   744
OR #imm, R0 {:
nkeynes@359
   745
    load_reg( R_EAX, 0 );
nkeynes@359
   746
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   747
    store_reg( R_EAX, 0 );
nkeynes@417
   748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   749
:}
nkeynes@374
   750
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   751
    load_reg( R_EAX, 0 );
nkeynes@374
   752
    load_spreg( R_ECX, R_GBR );
nkeynes@571
   753
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   754
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   755
    PUSH_realigned_r32(R_EAX);
nkeynes@571
   756
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   757
    POP_realigned_r32(R_ECX);
nkeynes@386
   758
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   759
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   760
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   761
:}
nkeynes@359
   762
ROTCL Rn {:
nkeynes@359
   763
    load_reg( R_EAX, Rn );
nkeynes@417
   764
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   765
	LDC_t();
nkeynes@417
   766
    }
nkeynes@359
   767
    RCL1_r32( R_EAX );
nkeynes@359
   768
    store_reg( R_EAX, Rn );
nkeynes@359
   769
    SETC_t();
nkeynes@417
   770
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   771
:}
nkeynes@359
   772
ROTCR Rn {:  
nkeynes@359
   773
    load_reg( R_EAX, Rn );
nkeynes@417
   774
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   775
	LDC_t();
nkeynes@417
   776
    }
nkeynes@359
   777
    RCR1_r32( R_EAX );
nkeynes@359
   778
    store_reg( R_EAX, Rn );
nkeynes@359
   779
    SETC_t();
nkeynes@417
   780
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   781
:}
nkeynes@359
   782
ROTL Rn {:  
nkeynes@359
   783
    load_reg( R_EAX, Rn );
nkeynes@359
   784
    ROL1_r32( R_EAX );
nkeynes@359
   785
    store_reg( R_EAX, Rn );
nkeynes@359
   786
    SETC_t();
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   788
:}
nkeynes@359
   789
ROTR Rn {:  
nkeynes@359
   790
    load_reg( R_EAX, Rn );
nkeynes@359
   791
    ROR1_r32( R_EAX );
nkeynes@359
   792
    store_reg( R_EAX, Rn );
nkeynes@359
   793
    SETC_t();
nkeynes@417
   794
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   795
:}
nkeynes@359
   796
SHAD Rm, Rn {:
nkeynes@359
   797
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   798
    load_reg( R_EAX, Rn );
nkeynes@361
   799
    load_reg( R_ECX, Rm );
nkeynes@361
   800
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   801
    JGE_rel8(16, doshl);
nkeynes@361
   802
                    
nkeynes@361
   803
    NEG_r32( R_ECX );      // 2
nkeynes@361
   804
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   805
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   806
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   807
    JMP_rel8(10, end);          // 2
nkeynes@386
   808
nkeynes@386
   809
    JMP_TARGET(emptysar);
nkeynes@386
   810
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   811
    JMP_rel8(5, end2);
nkeynes@382
   812
nkeynes@380
   813
    JMP_TARGET(doshl);
nkeynes@361
   814
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   815
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   816
    JMP_TARGET(end);
nkeynes@386
   817
    JMP_TARGET(end2);
nkeynes@361
   818
    store_reg( R_EAX, Rn );
nkeynes@417
   819
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   820
:}
nkeynes@359
   821
SHLD Rm, Rn {:  
nkeynes@368
   822
    load_reg( R_EAX, Rn );
nkeynes@368
   823
    load_reg( R_ECX, Rm );
nkeynes@382
   824
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   825
    JGE_rel8(15, doshl);
nkeynes@368
   826
nkeynes@382
   827
    NEG_r32( R_ECX );      // 2
nkeynes@382
   828
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   829
    JE_rel8( 4, emptyshr );
nkeynes@382
   830
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   831
    JMP_rel8(9, end);          // 2
nkeynes@386
   832
nkeynes@386
   833
    JMP_TARGET(emptyshr);
nkeynes@386
   834
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   835
    JMP_rel8(5, end2);
nkeynes@382
   836
nkeynes@382
   837
    JMP_TARGET(doshl);
nkeynes@382
   838
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   839
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   840
    JMP_TARGET(end);
nkeynes@386
   841
    JMP_TARGET(end2);
nkeynes@368
   842
    store_reg( R_EAX, Rn );
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   844
:}
nkeynes@359
   845
SHAL Rn {: 
nkeynes@359
   846
    load_reg( R_EAX, Rn );
nkeynes@359
   847
    SHL1_r32( R_EAX );
nkeynes@397
   848
    SETC_t();
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   851
:}
nkeynes@359
   852
SHAR Rn {:  
nkeynes@359
   853
    load_reg( R_EAX, Rn );
nkeynes@359
   854
    SAR1_r32( R_EAX );
nkeynes@397
   855
    SETC_t();
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   858
:}
nkeynes@359
   859
SHLL Rn {:  
nkeynes@359
   860
    load_reg( R_EAX, Rn );
nkeynes@359
   861
    SHL1_r32( R_EAX );
nkeynes@397
   862
    SETC_t();
nkeynes@359
   863
    store_reg( R_EAX, Rn );
nkeynes@417
   864
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   865
:}
nkeynes@359
   866
SHLL2 Rn {:
nkeynes@359
   867
    load_reg( R_EAX, Rn );
nkeynes@359
   868
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   869
    store_reg( R_EAX, Rn );
nkeynes@417
   870
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   871
:}
nkeynes@359
   872
SHLL8 Rn {:  
nkeynes@359
   873
    load_reg( R_EAX, Rn );
nkeynes@359
   874
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   875
    store_reg( R_EAX, Rn );
nkeynes@417
   876
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   877
:}
nkeynes@359
   878
SHLL16 Rn {:  
nkeynes@359
   879
    load_reg( R_EAX, Rn );
nkeynes@359
   880
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   881
    store_reg( R_EAX, Rn );
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   883
:}
nkeynes@359
   884
SHLR Rn {:  
nkeynes@359
   885
    load_reg( R_EAX, Rn );
nkeynes@359
   886
    SHR1_r32( R_EAX );
nkeynes@397
   887
    SETC_t();
nkeynes@359
   888
    store_reg( R_EAX, Rn );
nkeynes@417
   889
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   890
:}
nkeynes@359
   891
SHLR2 Rn {:  
nkeynes@359
   892
    load_reg( R_EAX, Rn );
nkeynes@359
   893
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   894
    store_reg( R_EAX, Rn );
nkeynes@417
   895
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   896
:}
nkeynes@359
   897
SHLR8 Rn {:  
nkeynes@359
   898
    load_reg( R_EAX, Rn );
nkeynes@359
   899
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   900
    store_reg( R_EAX, Rn );
nkeynes@417
   901
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   902
:}
nkeynes@359
   903
SHLR16 Rn {:  
nkeynes@359
   904
    load_reg( R_EAX, Rn );
nkeynes@359
   905
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   906
    store_reg( R_EAX, Rn );
nkeynes@417
   907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   908
:}
nkeynes@359
   909
SUB Rm, Rn {:  
nkeynes@359
   910
    load_reg( R_EAX, Rm );
nkeynes@359
   911
    load_reg( R_ECX, Rn );
nkeynes@359
   912
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   913
    store_reg( R_ECX, Rn );
nkeynes@417
   914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   915
:}
nkeynes@359
   916
SUBC Rm, Rn {:  
nkeynes@359
   917
    load_reg( R_EAX, Rm );
nkeynes@359
   918
    load_reg( R_ECX, Rn );
nkeynes@417
   919
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   920
	LDC_t();
nkeynes@417
   921
    }
nkeynes@359
   922
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   923
    store_reg( R_ECX, Rn );
nkeynes@394
   924
    SETC_t();
nkeynes@417
   925
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   926
:}
nkeynes@359
   927
SUBV Rm, Rn {:  
nkeynes@359
   928
    load_reg( R_EAX, Rm );
nkeynes@359
   929
    load_reg( R_ECX, Rn );
nkeynes@359
   930
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   931
    store_reg( R_ECX, Rn );
nkeynes@359
   932
    SETO_t();
nkeynes@417
   933
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   934
:}
nkeynes@359
   935
SWAP.B Rm, Rn {:  
nkeynes@359
   936
    load_reg( R_EAX, Rm );
nkeynes@359
   937
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   938
    store_reg( R_EAX, Rn );
nkeynes@359
   939
:}
nkeynes@359
   940
SWAP.W Rm, Rn {:  
nkeynes@359
   941
    load_reg( R_EAX, Rm );
nkeynes@359
   942
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   943
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   944
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   945
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   946
    store_reg( R_ECX, Rn );
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   948
:}
nkeynes@361
   949
TAS.B @Rn {:  
nkeynes@571
   950
    load_reg( R_EAX, Rn );
nkeynes@571
   951
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
   952
    PUSH_realigned_r32( R_EAX );
nkeynes@571
   953
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
   954
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   955
    SETE_t();
nkeynes@361
   956
    OR_imm8_r8( 0x80, R_AL );
nkeynes@571
   957
    POP_realigned_r32( R_ECX );
nkeynes@361
   958
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   959
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   960
:}
nkeynes@361
   961
TST Rm, Rn {:  
nkeynes@361
   962
    load_reg( R_EAX, Rm );
nkeynes@361
   963
    load_reg( R_ECX, Rn );
nkeynes@361
   964
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   965
    SETE_t();
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   967
:}
nkeynes@368
   968
TST #imm, R0 {:  
nkeynes@368
   969
    load_reg( R_EAX, 0 );
nkeynes@368
   970
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   971
    SETE_t();
nkeynes@417
   972
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   973
:}
nkeynes@368
   974
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   975
    load_reg( R_EAX, 0);
nkeynes@368
   976
    load_reg( R_ECX, R_GBR);
nkeynes@571
   977
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
   978
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
   979
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
   980
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   981
    SETE_t();
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   983
:}
nkeynes@359
   984
XOR Rm, Rn {:  
nkeynes@359
   985
    load_reg( R_EAX, Rm );
nkeynes@359
   986
    load_reg( R_ECX, Rn );
nkeynes@359
   987
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   988
    store_reg( R_ECX, Rn );
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   990
:}
nkeynes@359
   991
XOR #imm, R0 {:  
nkeynes@359
   992
    load_reg( R_EAX, 0 );
nkeynes@359
   993
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   994
    store_reg( R_EAX, 0 );
nkeynes@417
   995
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   996
:}
nkeynes@359
   997
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   998
    load_reg( R_EAX, 0 );
nkeynes@359
   999
    load_spreg( R_ECX, R_GBR );
nkeynes@571
  1000
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1001
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1002
    PUSH_realigned_r32(R_EAX);
nkeynes@571
  1003
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1004
    POP_realigned_r32(R_ECX);
nkeynes@359
  1005
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1006
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1008
:}
nkeynes@361
  1009
XTRCT Rm, Rn {:
nkeynes@361
  1010
    load_reg( R_EAX, Rm );
nkeynes@394
  1011
    load_reg( R_ECX, Rn );
nkeynes@394
  1012
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1013
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1014
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1015
    store_reg( R_ECX, Rn );
nkeynes@417
  1016
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1017
:}
nkeynes@359
  1018
nkeynes@359
  1019
/* Data move instructions */
nkeynes@359
  1020
MOV Rm, Rn {:  
nkeynes@359
  1021
    load_reg( R_EAX, Rm );
nkeynes@359
  1022
    store_reg( R_EAX, Rn );
nkeynes@359
  1023
:}
nkeynes@359
  1024
MOV #imm, Rn {:  
nkeynes@359
  1025
    load_imm32( R_EAX, imm );
nkeynes@359
  1026
    store_reg( R_EAX, Rn );
nkeynes@359
  1027
:}
nkeynes@359
  1028
MOV.B Rm, @Rn {:  
nkeynes@571
  1029
    load_reg( R_EAX, Rn );
nkeynes@571
  1030
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1031
    load_reg( R_EDX, Rm );
nkeynes@571
  1032
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1033
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1034
:}
nkeynes@359
  1035
MOV.B Rm, @-Rn {:  
nkeynes@571
  1036
    load_reg( R_EAX, Rn );
nkeynes@571
  1037
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@571
  1038
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1039
    load_reg( R_EDX, Rm );
nkeynes@571
  1040
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@571
  1041
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1043
:}
nkeynes@359
  1044
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1045
    load_reg( R_EAX, 0 );
nkeynes@359
  1046
    load_reg( R_ECX, Rn );
nkeynes@571
  1047
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1048
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1049
    load_reg( R_EDX, Rm );
nkeynes@571
  1050
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1052
:}
nkeynes@359
  1053
MOV.B R0, @(disp, GBR) {:  
nkeynes@571
  1054
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1055
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1056
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1057
    load_reg( R_EDX, 0 );
nkeynes@571
  1058
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1059
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1060
:}
nkeynes@359
  1061
MOV.B R0, @(disp, Rn) {:  
nkeynes@571
  1062
    load_reg( R_EAX, Rn );
nkeynes@571
  1063
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1064
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1065
    load_reg( R_EDX, 0 );
nkeynes@571
  1066
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1067
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1068
:}
nkeynes@359
  1069
MOV.B @Rm, Rn {:  
nkeynes@571
  1070
    load_reg( R_EAX, Rm );
nkeynes@571
  1071
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1072
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1073
    store_reg( R_EAX, Rn );
nkeynes@417
  1074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1075
:}
nkeynes@359
  1076
MOV.B @Rm+, Rn {:  
nkeynes@571
  1077
    load_reg( R_EAX, Rm );
nkeynes@571
  1078
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1079
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@571
  1080
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1081
    store_reg( R_EAX, Rn );
nkeynes@417
  1082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1083
:}
nkeynes@359
  1084
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1085
    load_reg( R_EAX, 0 );
nkeynes@359
  1086
    load_reg( R_ECX, Rm );
nkeynes@571
  1087
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1088
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@571
  1089
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1090
    store_reg( R_EAX, Rn );
nkeynes@417
  1091
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1092
:}
nkeynes@359
  1093
MOV.B @(disp, GBR), R0 {:  
nkeynes@571
  1094
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1095
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1096
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1097
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1098
    store_reg( R_EAX, 0 );
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1100
:}
nkeynes@359
  1101
MOV.B @(disp, Rm), R0 {:  
nkeynes@571
  1102
    load_reg( R_EAX, Rm );
nkeynes@571
  1103
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1104
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1105
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1106
    store_reg( R_EAX, 0 );
nkeynes@417
  1107
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1108
:}
nkeynes@374
  1109
MOV.L Rm, @Rn {:
nkeynes@571
  1110
    load_reg( R_EAX, Rn );
nkeynes@571
  1111
    check_walign32(R_EAX);
nkeynes@571
  1112
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1113
    load_reg( R_EDX, Rm );
nkeynes@571
  1114
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1116
:}
nkeynes@361
  1117
MOV.L Rm, @-Rn {:  
nkeynes@571
  1118
    load_reg( R_EAX, Rn );
nkeynes@571
  1119
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1120
    check_walign32( R_EAX );
nkeynes@571
  1121
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1122
    load_reg( R_EDX, Rm );
nkeynes@571
  1123
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  1124
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1125
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1126
:}
nkeynes@361
  1127
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1128
    load_reg( R_EAX, 0 );
nkeynes@361
  1129
    load_reg( R_ECX, Rn );
nkeynes@571
  1130
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1131
    check_walign32( R_EAX );
nkeynes@571
  1132
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1133
    load_reg( R_EDX, Rm );
nkeynes@571
  1134
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1136
:}
nkeynes@361
  1137
MOV.L R0, @(disp, GBR) {:  
nkeynes@571
  1138
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1139
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1140
    check_walign32( R_EAX );
nkeynes@571
  1141
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1142
    load_reg( R_EDX, 0 );
nkeynes@571
  1143
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1144
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1145
:}
nkeynes@361
  1146
MOV.L Rm, @(disp, Rn) {:  
nkeynes@571
  1147
    load_reg( R_EAX, Rn );
nkeynes@571
  1148
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1149
    check_walign32( R_EAX );
nkeynes@571
  1150
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1151
    load_reg( R_EDX, Rm );
nkeynes@571
  1152
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1154
:}
nkeynes@361
  1155
MOV.L @Rm, Rn {:  
nkeynes@571
  1156
    load_reg( R_EAX, Rm );
nkeynes@571
  1157
    check_ralign32( R_EAX );
nkeynes@571
  1158
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1159
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1160
    store_reg( R_EAX, Rn );
nkeynes@417
  1161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1162
:}
nkeynes@361
  1163
MOV.L @Rm+, Rn {:  
nkeynes@361
  1164
    load_reg( R_EAX, Rm );
nkeynes@382
  1165
    check_ralign32( R_EAX );
nkeynes@571
  1166
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1167
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1168
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1169
    store_reg( R_EAX, Rn );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1171
:}
nkeynes@361
  1172
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1173
    load_reg( R_EAX, 0 );
nkeynes@361
  1174
    load_reg( R_ECX, Rm );
nkeynes@571
  1175
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1176
    check_ralign32( R_EAX );
nkeynes@571
  1177
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1178
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1179
    store_reg( R_EAX, Rn );
nkeynes@417
  1180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1181
:}
nkeynes@361
  1182
MOV.L @(disp, GBR), R0 {:
nkeynes@571
  1183
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1184
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1185
    check_ralign32( R_EAX );
nkeynes@571
  1186
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1187
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1188
    store_reg( R_EAX, 0 );
nkeynes@417
  1189
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1190
:}
nkeynes@361
  1191
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1192
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1193
	SLOTILLEGAL();
nkeynes@374
  1194
    } else {
nkeynes@388
  1195
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  1196
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1197
	    // If the target address is in the same page as the code, it's
nkeynes@569
  1198
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  1199
	    // memory subsystem. (this is a big performance win)
nkeynes@569
  1200
nkeynes@569
  1201
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  1202
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  1203
	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  1204
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  1205
	    // behaviour though.
nkeynes@569
  1206
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1207
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1208
	} else {
nkeynes@569
  1209
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  1210
	    // different virtual address than the translation was done with,
nkeynes@569
  1211
	    // but we can safely assume that the low bits are the same.
nkeynes@571
  1212
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@571
  1213
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@571
  1214
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1215
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@569
  1216
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1217
	}
nkeynes@382
  1218
	store_reg( R_EAX, Rn );
nkeynes@374
  1219
    }
nkeynes@361
  1220
:}
nkeynes@361
  1221
MOV.L @(disp, Rm), Rn {:  
nkeynes@571
  1222
    load_reg( R_EAX, Rm );
nkeynes@571
  1223
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@571
  1224
    check_ralign32( R_EAX );
nkeynes@571
  1225
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1226
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1227
    store_reg( R_EAX, Rn );
nkeynes@417
  1228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1229
:}
nkeynes@361
  1230
MOV.W Rm, @Rn {:  
nkeynes@571
  1231
    load_reg( R_EAX, Rn );
nkeynes@571
  1232
    check_walign16( R_EAX );
nkeynes@571
  1233
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@571
  1234
    load_reg( R_EDX, Rm );
nkeynes@571
  1235
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1236
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1237
:}
nkeynes@361
  1238
MOV.W Rm, @-Rn {:  
nkeynes@571
  1239
    load_reg( R_EAX, Rn );
nkeynes@571
  1240
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@571
  1241
    check_walign16( R_EAX );
nkeynes@571
  1242
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1243
    load_reg( R_EDX, Rm );
nkeynes@571
  1244
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@571
  1245
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1246
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1247
:}
nkeynes@361
  1248
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1249
    load_reg( R_EAX, 0 );
nkeynes@361
  1250
    load_reg( R_ECX, Rn );
nkeynes@571
  1251
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1252
    check_walign16( R_EAX );
nkeynes@571
  1253
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1254
    load_reg( R_EDX, Rm );
nkeynes@571
  1255
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1256
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1257
:}
nkeynes@361
  1258
MOV.W R0, @(disp, GBR) {:  
nkeynes@571
  1259
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1260
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1261
    check_walign16( R_EAX );
nkeynes@571
  1262
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1263
    load_reg( R_EDX, 0 );
nkeynes@571
  1264
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1265
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1266
:}
nkeynes@361
  1267
MOV.W R0, @(disp, Rn) {:  
nkeynes@571
  1268
    load_reg( R_EAX, Rn );
nkeynes@571
  1269
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1270
    check_walign16( R_EAX );
nkeynes@571
  1271
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1272
    load_reg( R_EDX, 0 );
nkeynes@571
  1273
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1274
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1275
:}
nkeynes@361
  1276
MOV.W @Rm, Rn {:  
nkeynes@571
  1277
    load_reg( R_EAX, Rm );
nkeynes@571
  1278
    check_ralign16( R_EAX );
nkeynes@571
  1279
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1280
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1281
    store_reg( R_EAX, Rn );
nkeynes@417
  1282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1283
:}
nkeynes@361
  1284
MOV.W @Rm+, Rn {:  
nkeynes@361
  1285
    load_reg( R_EAX, Rm );
nkeynes@374
  1286
    check_ralign16( R_EAX );
nkeynes@571
  1287
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1288
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
  1289
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1290
    store_reg( R_EAX, Rn );
nkeynes@417
  1291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1292
:}
nkeynes@361
  1293
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1294
    load_reg( R_EAX, 0 );
nkeynes@361
  1295
    load_reg( R_ECX, Rm );
nkeynes@571
  1296
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@571
  1297
    check_ralign16( R_EAX );
nkeynes@571
  1298
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1299
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1300
    store_reg( R_EAX, Rn );
nkeynes@417
  1301
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1302
:}
nkeynes@361
  1303
MOV.W @(disp, GBR), R0 {:  
nkeynes@571
  1304
    load_spreg( R_EAX, R_GBR );
nkeynes@571
  1305
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1306
    check_ralign16( R_EAX );
nkeynes@571
  1307
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1308
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1309
    store_reg( R_EAX, 0 );
nkeynes@417
  1310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1311
:}
nkeynes@361
  1312
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1313
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1314
	SLOTILLEGAL();
nkeynes@374
  1315
    } else {
nkeynes@569
  1316
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  1317
	uint32_t target = pc + disp + 4;
nkeynes@569
  1318
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1319
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  1320
	    MOV_moff32_EAX( ptr );
nkeynes@569
  1321
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  1322
	} else {
nkeynes@571
  1323
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@571
  1324
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@571
  1325
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1326
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@569
  1327
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  1328
	}
nkeynes@374
  1329
	store_reg( R_EAX, Rn );
nkeynes@374
  1330
    }
nkeynes@361
  1331
:}
nkeynes@361
  1332
MOV.W @(disp, Rm), R0 {:  
nkeynes@571
  1333
    load_reg( R_EAX, Rm );
nkeynes@571
  1334
    ADD_imm32_r32( disp, R_EAX );
nkeynes@571
  1335
    check_ralign16( R_EAX );
nkeynes@571
  1336
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  1337
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1338
    store_reg( R_EAX, 0 );
nkeynes@417
  1339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1340
:}
nkeynes@361
  1341
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1342
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1343
	SLOTILLEGAL();
nkeynes@374
  1344
    } else {
nkeynes@569
  1345
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1346
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1347
	store_reg( R_ECX, 0 );
nkeynes@571
  1348
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1349
    }
nkeynes@361
  1350
:}
nkeynes@361
  1351
MOVCA.L R0, @Rn {:  
nkeynes@571
  1352
    load_reg( R_EAX, Rn );
nkeynes@571
  1353
    check_walign32( R_EAX );
nkeynes@571
  1354
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  1355
    load_reg( R_EDX, 0 );
nkeynes@571
  1356
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1357
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1358
:}
nkeynes@359
  1359
nkeynes@359
  1360
/* Control transfer instructions */
nkeynes@374
  1361
BF disp {:
nkeynes@374
  1362
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1363
	SLOTILLEGAL();
nkeynes@374
  1364
    } else {
nkeynes@571
  1365
	sh4vma_t target = disp + pc + 4;
nkeynes@571
  1366
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  1367
	exit_block_rel(target, pc+2 );
nkeynes@380
  1368
	JMP_TARGET(nottaken);
nkeynes@408
  1369
	return 2;
nkeynes@374
  1370
    }
nkeynes@374
  1371
:}
nkeynes@374
  1372
BF/S disp {:
nkeynes@374
  1373
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1374
	SLOTILLEGAL();
nkeynes@374
  1375
    } else {
nkeynes@571
  1376
	sh4vma_t target = disp + pc + 4;
nkeynes@408
  1377
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1378
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1379
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1380
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1381
	}
nkeynes@417
  1382
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1383
	sh4_translate_instruction(pc+2);
nkeynes@571
  1384
	exit_block_rel( target, pc+4 );
nkeynes@408
  1385
	// not taken
nkeynes@408
  1386
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1387
	sh4_translate_instruction(pc+2);
nkeynes@408
  1388
	return 4;
nkeynes@374
  1389
    }
nkeynes@374
  1390
:}
nkeynes@374
  1391
BRA disp {:  
nkeynes@374
  1392
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1393
	SLOTILLEGAL();
nkeynes@374
  1394
    } else {
nkeynes@374
  1395
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1396
	sh4_translate_instruction( pc + 2 );
nkeynes@571
  1397
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1398
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1399
	return 4;
nkeynes@374
  1400
    }
nkeynes@374
  1401
:}
nkeynes@374
  1402
BRAF Rn {:  
nkeynes@374
  1403
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1404
	SLOTILLEGAL();
nkeynes@374
  1405
    } else {
nkeynes@408
  1406
	load_reg( R_EAX, Rn );
nkeynes@408
  1407
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1408
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1409
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1410
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1411
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1412
	exit_block_pcset(pc+2);
nkeynes@409
  1413
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1414
	return 4;
nkeynes@374
  1415
    }
nkeynes@374
  1416
:}
nkeynes@374
  1417
BSR disp {:  
nkeynes@374
  1418
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1419
	SLOTILLEGAL();
nkeynes@374
  1420
    } else {
nkeynes@374
  1421
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1422
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1423
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1424
	sh4_translate_instruction( pc + 2 );
nkeynes@571
  1425
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@409
  1426
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1427
	return 4;
nkeynes@374
  1428
    }
nkeynes@374
  1429
:}
nkeynes@374
  1430
BSRF Rn {:  
nkeynes@374
  1431
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1432
	SLOTILLEGAL();
nkeynes@374
  1433
    } else {
nkeynes@408
  1434
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1435
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1436
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1437
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1438
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1439
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1440
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1441
	exit_block_pcset(pc+2);
nkeynes@409
  1442
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1443
	return 4;
nkeynes@374
  1444
    }
nkeynes@374
  1445
:}
nkeynes@374
  1446
BT disp {:
nkeynes@374
  1447
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1448
	SLOTILLEGAL();
nkeynes@374
  1449
    } else {
nkeynes@571
  1450
	sh4vma_t target = disp + pc + 4;
nkeynes@571
  1451
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@571
  1452
	exit_block_rel(target, pc+2 );
nkeynes@380
  1453
	JMP_TARGET(nottaken);
nkeynes@408
  1454
	return 2;
nkeynes@374
  1455
    }
nkeynes@374
  1456
:}
nkeynes@374
  1457
BT/S disp {:
nkeynes@374
  1458
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1459
	SLOTILLEGAL();
nkeynes@374
  1460
    } else {
nkeynes@408
  1461
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1462
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1463
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1464
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1465
	}
nkeynes@417
  1466
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1467
	sh4_translate_instruction(pc+2);
nkeynes@571
  1468
	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@408
  1469
	// not taken
nkeynes@408
  1470
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1471
	sh4_translate_instruction(pc+2);
nkeynes@408
  1472
	return 4;
nkeynes@374
  1473
    }
nkeynes@374
  1474
:}
nkeynes@374
  1475
JMP @Rn {:  
nkeynes@374
  1476
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1477
	SLOTILLEGAL();
nkeynes@374
  1478
    } else {
nkeynes@408
  1479
	load_reg( R_ECX, Rn );
nkeynes@408
  1480
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1481
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1482
	sh4_translate_instruction(pc+2);
nkeynes@408
  1483
	exit_block_pcset(pc+2);
nkeynes@409
  1484
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1485
	return 4;
nkeynes@374
  1486
    }
nkeynes@374
  1487
:}
nkeynes@374
  1488
JSR @Rn {:  
nkeynes@374
  1489
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1490
	SLOTILLEGAL();
nkeynes@374
  1491
    } else {
nkeynes@374
  1492
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1493
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1494
	load_reg( R_ECX, Rn );
nkeynes@408
  1495
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1496
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1497
	sh4_translate_instruction(pc+2);
nkeynes@408
  1498
	exit_block_pcset(pc+2);
nkeynes@409
  1499
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1500
	return 4;
nkeynes@374
  1501
    }
nkeynes@374
  1502
:}
nkeynes@374
  1503
RTE {:  
nkeynes@374
  1504
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1505
	SLOTILLEGAL();
nkeynes@374
  1506
    } else {
nkeynes@408
  1507
	check_priv();
nkeynes@408
  1508
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1509
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1510
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1511
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1512
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1513
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1514
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1515
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1516
	sh4_translate_instruction(pc+2);
nkeynes@408
  1517
	exit_block_pcset(pc+2);
nkeynes@409
  1518
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1519
	return 4;
nkeynes@374
  1520
    }
nkeynes@374
  1521
:}
nkeynes@374
  1522
RTS {:  
nkeynes@374
  1523
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1524
	SLOTILLEGAL();
nkeynes@374
  1525
    } else {
nkeynes@408
  1526
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1527
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1528
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1529
	sh4_translate_instruction(pc+2);
nkeynes@408
  1530
	exit_block_pcset(pc+2);
nkeynes@409
  1531
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1532
	return 4;
nkeynes@374
  1533
    }
nkeynes@374
  1534
:}
nkeynes@374
  1535
TRAPA #imm {:  
nkeynes@374
  1536
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1537
	SLOTILLEGAL();
nkeynes@374
  1538
    } else {
nkeynes@533
  1539
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1540
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1541
	load_imm32( R_EAX, imm );
nkeynes@527
  1542
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1543
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1544
	exit_block_pcset(pc);
nkeynes@409
  1545
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1546
	return 2;
nkeynes@374
  1547
    }
nkeynes@374
  1548
:}
nkeynes@374
  1549
UNDEF {:  
nkeynes@374
  1550
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1551
	SLOTILLEGAL();
nkeynes@374
  1552
    } else {
nkeynes@559
  1553
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1554
	return 2;
nkeynes@374
  1555
    }
nkeynes@368
  1556
:}
nkeynes@374
  1557
nkeynes@374
  1558
CLRMAC {:  
nkeynes@374
  1559
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1560
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1561
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1562
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1563
:}
nkeynes@374
  1564
CLRS {:
nkeynes@374
  1565
    CLC();
nkeynes@374
  1566
    SETC_sh4r(R_S);
nkeynes@417
  1567
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1568
:}
nkeynes@374
  1569
CLRT {:  
nkeynes@374
  1570
    CLC();
nkeynes@374
  1571
    SETC_t();
nkeynes@417
  1572
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1573
:}
nkeynes@374
  1574
SETS {:  
nkeynes@374
  1575
    STC();
nkeynes@374
  1576
    SETC_sh4r(R_S);
nkeynes@417
  1577
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1578
:}
nkeynes@374
  1579
SETT {:  
nkeynes@374
  1580
    STC();
nkeynes@374
  1581
    SETC_t();
nkeynes@417
  1582
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1583
:}
nkeynes@359
  1584
nkeynes@375
  1585
/* Floating point moves */
nkeynes@375
  1586
FMOV FRm, FRn {:  
nkeynes@375
  1587
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1588
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1589
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1590
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1591
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1592
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1593
     */
nkeynes@377
  1594
    check_fpuen();
nkeynes@375
  1595
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1596
    load_fr_bank( R_EDX );
nkeynes@375
  1597
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1598
    JNE_rel8(8, doublesize);
nkeynes@375
  1599
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1600
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1601
    if( FRm&1 ) {
nkeynes@386
  1602
	JMP_rel8(24, end);
nkeynes@380
  1603
	JMP_TARGET(doublesize);
nkeynes@375
  1604
	load_xf_bank( R_ECX ); 
nkeynes@375
  1605
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1606
	if( FRn&1 ) {
nkeynes@375
  1607
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1608
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1609
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1610
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1611
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1612
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1613
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1614
	}
nkeynes@380
  1615
	JMP_TARGET(end);
nkeynes@375
  1616
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1617
	if( FRn&1 ) {
nkeynes@386
  1618
	    JMP_rel8(24, end);
nkeynes@375
  1619
	    load_xf_bank( R_ECX );
nkeynes@375
  1620
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1621
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1622
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1623
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1624
	    JMP_TARGET(end);
nkeynes@375
  1625
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1626
	    JMP_rel8(12, end);
nkeynes@375
  1627
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1628
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1629
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1630
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1631
	    JMP_TARGET(end);
nkeynes@375
  1632
	}
nkeynes@375
  1633
    }
nkeynes@417
  1634
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1635
:}
nkeynes@416
  1636
FMOV FRm, @Rn {: 
nkeynes@559
  1637
    check_fpuen();
nkeynes@571
  1638
    load_reg( R_EAX, Rn );
nkeynes@571
  1639
    check_walign32( R_EAX );
nkeynes@571
  1640
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1641
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1642
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1643
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1644
    load_fr_bank( R_EDX );
nkeynes@571
  1645
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1646
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1647
    if( FRm&1 ) {
nkeynes@527
  1648
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1649
	JMP_TARGET(doublesize);
nkeynes@416
  1650
	load_xf_bank( R_EDX );
nkeynes@571
  1651
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1652
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1653
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1654
	JMP_TARGET(end);
nkeynes@375
  1655
    } else {
nkeynes@527
  1656
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1657
	JMP_TARGET(doublesize);
nkeynes@416
  1658
	load_fr_bank( R_EDX );
nkeynes@571
  1659
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1660
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1661
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1662
	JMP_TARGET(end);
nkeynes@375
  1663
    }
nkeynes@417
  1664
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1665
:}
nkeynes@375
  1666
FMOV @Rm, FRn {:  
nkeynes@559
  1667
    check_fpuen();
nkeynes@571
  1668
    load_reg( R_EAX, Rm );
nkeynes@571
  1669
    check_ralign32( R_EAX );
nkeynes@571
  1670
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1671
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1672
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1673
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1674
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1675
    load_fr_bank( R_EDX );
nkeynes@416
  1676
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1677
    if( FRn&1 ) {
nkeynes@527
  1678
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1679
	JMP_TARGET(doublesize);
nkeynes@571
  1680
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1681
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1682
	load_xf_bank( R_EDX );
nkeynes@571
  1683
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1684
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1685
	JMP_TARGET(end);
nkeynes@375
  1686
    } else {
nkeynes@527
  1687
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1688
	JMP_TARGET(doublesize);
nkeynes@571
  1689
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1690
	load_fr_bank( R_EDX );
nkeynes@571
  1691
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1692
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1693
	JMP_TARGET(end);
nkeynes@375
  1694
    }
nkeynes@417
  1695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1696
:}
nkeynes@377
  1697
FMOV FRm, @-Rn {:  
nkeynes@559
  1698
    check_fpuen();
nkeynes@571
  1699
    load_reg( R_EAX, Rn );
nkeynes@571
  1700
    check_walign32( R_EAX );
nkeynes@416
  1701
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1702
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@571
  1703
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@571
  1704
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  1705
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1706
    load_fr_bank( R_EDX );
nkeynes@571
  1707
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1708
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@571
  1709
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1710
    if( FRm&1 ) {
nkeynes@571
  1711
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1712
	JMP_TARGET(doublesize);
nkeynes@571
  1713
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@571
  1714
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1715
	load_xf_bank( R_EDX );
nkeynes@571
  1716
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1717
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1718
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@571
  1719
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1720
	JMP_TARGET(end);
nkeynes@377
  1721
    } else {
nkeynes@571
  1722
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1723
	JMP_TARGET(doublesize);
nkeynes@571
  1724
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@571
  1725
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1726
	load_fr_bank( R_EDX );
nkeynes@571
  1727
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1728
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1729
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@571
  1730
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1731
	JMP_TARGET(end);
nkeynes@377
  1732
    }
nkeynes@417
  1733
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1734
:}
nkeynes@416
  1735
FMOV @Rm+, FRn {:
nkeynes@559
  1736
    check_fpuen();
nkeynes@571
  1737
    load_reg( R_EAX, Rm );
nkeynes@571
  1738
    check_ralign32( R_EAX );
nkeynes@571
  1739
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1740
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1741
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@571
  1742
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1743
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  1744
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1745
    load_fr_bank( R_EDX );
nkeynes@416
  1746
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1747
    if( FRn&1 ) {
nkeynes@571
  1748
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1749
	JMP_TARGET(doublesize);
nkeynes@571
  1750
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@571
  1751
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1752
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1753
	load_xf_bank( R_EDX );
nkeynes@571
  1754
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1755
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1756
	JMP_TARGET(end);
nkeynes@377
  1757
    } else {
nkeynes@571
  1758
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@571
  1759
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@571
  1760
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1761
	load_fr_bank( R_EDX );
nkeynes@571
  1762
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1763
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1764
	JMP_TARGET(end);
nkeynes@377
  1765
    }
nkeynes@417
  1766
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1767
:}
nkeynes@377
  1768
FMOV FRm, @(R0, Rn) {:  
nkeynes@559
  1769
    check_fpuen();
nkeynes@571
  1770
    load_reg( R_EAX, Rn );
nkeynes@571
  1771
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@571
  1772
    check_walign32( R_EAX );
nkeynes@571
  1773
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1774
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1775
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1776
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1777
    load_fr_bank( R_EDX );
nkeynes@571
  1778
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@571
  1779
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1780
    if( FRm&1 ) {
nkeynes@527
  1781
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1782
	JMP_TARGET(doublesize);
nkeynes@416
  1783
	load_xf_bank( R_EDX );
nkeynes@571
  1784
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1785
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1786
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1787
	JMP_TARGET(end);
nkeynes@377
  1788
    } else {
nkeynes@527
  1789
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1790
	JMP_TARGET(doublesize);
nkeynes@416
  1791
	load_fr_bank( R_EDX );
nkeynes@571
  1792
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1793
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@571
  1794
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1795
	JMP_TARGET(end);
nkeynes@377
  1796
    }
nkeynes@417
  1797
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1798
:}
nkeynes@377
  1799
FMOV @(R0, Rm), FRn {:  
nkeynes@559
  1800
    check_fpuen();
nkeynes@571
  1801
    load_reg( R_EAX, Rm );
nkeynes@571
  1802
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@571
  1803
    check_ralign32( R_EAX );
nkeynes@571
  1804
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1805
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1806
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1807
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@571
  1808
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1809
    load_fr_bank( R_EDX );
nkeynes@416
  1810
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1811
    if( FRn&1 ) {
nkeynes@527
  1812
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1813
	JMP_TARGET(doublesize);
nkeynes@571
  1814
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1815
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1816
	load_xf_bank( R_EDX );
nkeynes@571
  1817
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1818
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1819
	JMP_TARGET(end);
nkeynes@377
  1820
    } else {
nkeynes@527
  1821
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1822
	JMP_TARGET(doublesize);
nkeynes@571
  1823
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1824
	load_fr_bank( R_EDX );
nkeynes@571
  1825
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@571
  1826
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1827
	JMP_TARGET(end);
nkeynes@377
  1828
    }
nkeynes@417
  1829
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1830
:}
nkeynes@377
  1831
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1832
    check_fpuen();
nkeynes@377
  1833
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1834
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1835
    JNE_rel8(8, end);
nkeynes@377
  1836
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1837
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1838
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1839
    JMP_TARGET(end);
nkeynes@417
  1840
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1841
:}
nkeynes@377
  1842
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1843
    check_fpuen();
nkeynes@377
  1844
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1845
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1846
    JNE_rel8(11, end);
nkeynes@377
  1847
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1848
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1849
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1850
    JMP_TARGET(end);
nkeynes@417
  1851
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1852
:}
nkeynes@377
  1853
nkeynes@377
  1854
FLOAT FPUL, FRn {:  
nkeynes@377
  1855
    check_fpuen();
nkeynes@377
  1856
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1857
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1858
    FILD_sh4r(R_FPUL);
nkeynes@377
  1859
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1860
    JNE_rel8(5, doubleprec);
nkeynes@377
  1861
    pop_fr( R_EDX, FRn );
nkeynes@380
  1862
    JMP_rel8(3, end);
nkeynes@380
  1863
    JMP_TARGET(doubleprec);
nkeynes@377
  1864
    pop_dr( R_EDX, FRn );
nkeynes@380
  1865
    JMP_TARGET(end);
nkeynes@417
  1866
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1867
:}
nkeynes@377
  1868
FTRC FRm, FPUL {:  
nkeynes@377
  1869
    check_fpuen();
nkeynes@388
  1870
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1871
    load_fr_bank( R_EDX );
nkeynes@388
  1872
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1873
    JNE_rel8(5, doubleprec);
nkeynes@388
  1874
    push_fr( R_EDX, FRm );
nkeynes@388
  1875
    JMP_rel8(3, doop);
nkeynes@388
  1876
    JMP_TARGET(doubleprec);
nkeynes@388
  1877
    push_dr( R_EDX, FRm );
nkeynes@388
  1878
    JMP_TARGET( doop );
nkeynes@388
  1879
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1880
    FILD_r32ind( R_ECX );
nkeynes@388
  1881
    FCOMIP_st(1);
nkeynes@394
  1882
    JNA_rel8( 32, sat );
nkeynes@388
  1883
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1884
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1885
    FCOMIP_st(1);                   // 2
nkeynes@394
  1886
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1887
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1888
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1889
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1890
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1891
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1892
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1893
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1894
nkeynes@388
  1895
    JMP_TARGET(sat);
nkeynes@388
  1896
    JMP_TARGET(sat2);
nkeynes@388
  1897
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1898
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1899
    FPOP_st();
nkeynes@388
  1900
    JMP_TARGET(end);
nkeynes@417
  1901
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1902
:}
nkeynes@377
  1903
FLDS FRm, FPUL {:  
nkeynes@377
  1904
    check_fpuen();
nkeynes@377
  1905
    load_fr_bank( R_ECX );
nkeynes@377
  1906
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1907
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1909
:}
nkeynes@377
  1910
FSTS FPUL, FRn {:  
nkeynes@377
  1911
    check_fpuen();
nkeynes@377
  1912
    load_fr_bank( R_ECX );
nkeynes@377
  1913
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1914
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1915
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1916
:}
nkeynes@377
  1917
FCNVDS FRm, FPUL {:  
nkeynes@377
  1918
    check_fpuen();
nkeynes@377
  1919
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1920
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1921
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1922
    load_fr_bank( R_ECX );
nkeynes@377
  1923
    push_dr( R_ECX, FRm );
nkeynes@377
  1924
    pop_fpul();
nkeynes@380
  1925
    JMP_TARGET(end);
nkeynes@417
  1926
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1927
:}
nkeynes@377
  1928
FCNVSD FPUL, FRn {:  
nkeynes@377
  1929
    check_fpuen();
nkeynes@377
  1930
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1931
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1932
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1933
    load_fr_bank( R_ECX );
nkeynes@377
  1934
    push_fpul();
nkeynes@377
  1935
    pop_dr( R_ECX, FRn );
nkeynes@380
  1936
    JMP_TARGET(end);
nkeynes@417
  1937
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1938
:}
nkeynes@375
  1939
nkeynes@359
  1940
/* Floating point instructions */
nkeynes@374
  1941
FABS FRn {:  
nkeynes@377
  1942
    check_fpuen();
nkeynes@374
  1943
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1944
    load_fr_bank( R_EDX );
nkeynes@374
  1945
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1946
    JNE_rel8(10, doubleprec);
nkeynes@374
  1947
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1948
    FABS_st0(); // 2
nkeynes@374
  1949
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1950
    JMP_rel8(8,end); // 2
nkeynes@380
  1951
    JMP_TARGET(doubleprec);
nkeynes@374
  1952
    push_dr(R_EDX, FRn);
nkeynes@374
  1953
    FABS_st0();
nkeynes@374
  1954
    pop_dr(R_EDX, FRn);
nkeynes@380
  1955
    JMP_TARGET(end);
nkeynes@417
  1956
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1957
:}
nkeynes@377
  1958
FADD FRm, FRn {:  
nkeynes@377
  1959
    check_fpuen();
nkeynes@375
  1960
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1961
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1962
    load_fr_bank( R_EDX );
nkeynes@380
  1963
    JNE_rel8(13,doubleprec);
nkeynes@377
  1964
    push_fr(R_EDX, FRm);
nkeynes@377
  1965
    push_fr(R_EDX, FRn);
nkeynes@377
  1966
    FADDP_st(1);
nkeynes@377
  1967
    pop_fr(R_EDX, FRn);
nkeynes@380
  1968
    JMP_rel8(11,end);
nkeynes@380
  1969
    JMP_TARGET(doubleprec);
nkeynes@377
  1970
    push_dr(R_EDX, FRm);
nkeynes@377
  1971
    push_dr(R_EDX, FRn);
nkeynes@377
  1972
    FADDP_st(1);
nkeynes@377
  1973
    pop_dr(R_EDX, FRn);
nkeynes@380
  1974
    JMP_TARGET(end);
nkeynes@417
  1975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1976
:}
nkeynes@377
  1977
FDIV FRm, FRn {:  
nkeynes@377
  1978
    check_fpuen();
nkeynes@375
  1979
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1980
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1981
    load_fr_bank( R_EDX );
nkeynes@380
  1982
    JNE_rel8(13, doubleprec);
nkeynes@377
  1983
    push_fr(R_EDX, FRn);
nkeynes@377
  1984
    push_fr(R_EDX, FRm);
nkeynes@377
  1985
    FDIVP_st(1);
nkeynes@377
  1986
    pop_fr(R_EDX, FRn);
nkeynes@380
  1987
    JMP_rel8(11, end);
nkeynes@380
  1988
    JMP_TARGET(doubleprec);
nkeynes@377
  1989
    push_dr(R_EDX, FRn);
nkeynes@377
  1990
    push_dr(R_EDX, FRm);
nkeynes@377
  1991
    FDIVP_st(1);
nkeynes@377
  1992
    pop_dr(R_EDX, FRn);
nkeynes@380
  1993
    JMP_TARGET(end);
nkeynes@417
  1994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1995
:}
nkeynes@375
  1996
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1997
    check_fpuen();
nkeynes@375
  1998
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1999
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2000
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2001
    JNE_rel8(18, doubleprec);
nkeynes@375
  2002
    push_fr( R_EDX, 0 );
nkeynes@375
  2003
    push_fr( R_EDX, FRm );
nkeynes@375
  2004
    FMULP_st(1);
nkeynes@375
  2005
    push_fr( R_EDX, FRn );
nkeynes@375
  2006
    FADDP_st(1);
nkeynes@375
  2007
    pop_fr( R_EDX, FRn );
nkeynes@380
  2008
    JMP_rel8(16, end);
nkeynes@380
  2009
    JMP_TARGET(doubleprec);
nkeynes@375
  2010
    push_dr( R_EDX, 0 );
nkeynes@375
  2011
    push_dr( R_EDX, FRm );
nkeynes@375
  2012
    FMULP_st(1);
nkeynes@375
  2013
    push_dr( R_EDX, FRn );
nkeynes@375
  2014
    FADDP_st(1);
nkeynes@375
  2015
    pop_dr( R_EDX, FRn );
nkeynes@380
  2016
    JMP_TARGET(end);
nkeynes@417
  2017
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2018
:}
nkeynes@375
  2019
nkeynes@377
  2020
FMUL FRm, FRn {:  
nkeynes@377
  2021
    check_fpuen();
nkeynes@377
  2022
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2023
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2024
    load_fr_bank( R_EDX );
nkeynes@380
  2025
    JNE_rel8(13, doubleprec);
nkeynes@377
  2026
    push_fr(R_EDX, FRm);
nkeynes@377
  2027
    push_fr(R_EDX, FRn);
nkeynes@377
  2028
    FMULP_st(1);
nkeynes@377
  2029
    pop_fr(R_EDX, FRn);
nkeynes@380
  2030
    JMP_rel8(11, end);
nkeynes@380
  2031
    JMP_TARGET(doubleprec);
nkeynes@377
  2032
    push_dr(R_EDX, FRm);
nkeynes@377
  2033
    push_dr(R_EDX, FRn);
nkeynes@377
  2034
    FMULP_st(1);
nkeynes@377
  2035
    pop_dr(R_EDX, FRn);
nkeynes@380
  2036
    JMP_TARGET(end);
nkeynes@417
  2037
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2038
:}
nkeynes@377
  2039
FNEG FRn {:  
nkeynes@377
  2040
    check_fpuen();
nkeynes@377
  2041
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2042
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2043
    load_fr_bank( R_EDX );
nkeynes@380
  2044
    JNE_rel8(10, doubleprec);
nkeynes@377
  2045
    push_fr(R_EDX, FRn);
nkeynes@377
  2046
    FCHS_st0();
nkeynes@377
  2047
    pop_fr(R_EDX, FRn);
nkeynes@380
  2048
    JMP_rel8(8, end);
nkeynes@380
  2049
    JMP_TARGET(doubleprec);
nkeynes@377
  2050
    push_dr(R_EDX, FRn);
nkeynes@377
  2051
    FCHS_st0();
nkeynes@377
  2052
    pop_dr(R_EDX, FRn);
nkeynes@380
  2053
    JMP_TARGET(end);
nkeynes@417
  2054
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2055
:}
nkeynes@377
  2056
FSRRA FRn {:  
nkeynes@377
  2057
    check_fpuen();
nkeynes@377
  2058
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2059
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2060
    load_fr_bank( R_EDX );
nkeynes@380
  2061
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2062
    FLD1_st0();
nkeynes@377
  2063
    push_fr(R_EDX, FRn);
nkeynes@377
  2064
    FSQRT_st0();
nkeynes@377
  2065
    FDIVP_st(1);
nkeynes@377
  2066
    pop_fr(R_EDX, FRn);
nkeynes@380
  2067
    JMP_TARGET(end);
nkeynes@417
  2068
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2069
:}
nkeynes@377
  2070
FSQRT FRn {:  
nkeynes@377
  2071
    check_fpuen();
nkeynes@377
  2072
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2073
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2074
    load_fr_bank( R_EDX );
nkeynes@380
  2075
    JNE_rel8(10, doubleprec);
nkeynes@377
  2076
    push_fr(R_EDX, FRn);
nkeynes@377
  2077
    FSQRT_st0();
nkeynes@377
  2078
    pop_fr(R_EDX, FRn);
nkeynes@380
  2079
    JMP_rel8(8, end);
nkeynes@380
  2080
    JMP_TARGET(doubleprec);
nkeynes@377
  2081
    push_dr(R_EDX, FRn);
nkeynes@377
  2082
    FSQRT_st0();
nkeynes@377
  2083
    pop_dr(R_EDX, FRn);
nkeynes@380
  2084
    JMP_TARGET(end);
nkeynes@417
  2085
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2086
:}
nkeynes@377
  2087
FSUB FRm, FRn {:  
nkeynes@377
  2088
    check_fpuen();
nkeynes@377
  2089
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2090
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2091
    load_fr_bank( R_EDX );
nkeynes@380
  2092
    JNE_rel8(13, doubleprec);
nkeynes@377
  2093
    push_fr(R_EDX, FRn);
nkeynes@377
  2094
    push_fr(R_EDX, FRm);
nkeynes@388
  2095
    FSUBP_st(1);
nkeynes@377
  2096
    pop_fr(R_EDX, FRn);
nkeynes@380
  2097
    JMP_rel8(11, end);
nkeynes@380
  2098
    JMP_TARGET(doubleprec);
nkeynes@377
  2099
    push_dr(R_EDX, FRn);
nkeynes@377
  2100
    push_dr(R_EDX, FRm);
nkeynes@388
  2101
    FSUBP_st(1);
nkeynes@377
  2102
    pop_dr(R_EDX, FRn);
nkeynes@380
  2103
    JMP_TARGET(end);
nkeynes@417
  2104
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2105
:}
nkeynes@377
  2106
nkeynes@377
  2107
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2108
    check_fpuen();
nkeynes@377
  2109
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2110
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2111
    load_fr_bank( R_EDX );
nkeynes@380
  2112
    JNE_rel8(8, doubleprec);
nkeynes@377
  2113
    push_fr(R_EDX, FRm);
nkeynes@377
  2114
    push_fr(R_EDX, FRn);
nkeynes@380
  2115
    JMP_rel8(6, end);
nkeynes@380
  2116
    JMP_TARGET(doubleprec);
nkeynes@377
  2117
    push_dr(R_EDX, FRm);
nkeynes@377
  2118
    push_dr(R_EDX, FRn);
nkeynes@382
  2119
    JMP_TARGET(end);
nkeynes@377
  2120
    FCOMIP_st(1);
nkeynes@377
  2121
    SETE_t();
nkeynes@377
  2122
    FPOP_st();
nkeynes@417
  2123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2124
:}
nkeynes@377
  2125
FCMP/GT FRm, FRn {:  
nkeynes@377
  2126
    check_fpuen();
nkeynes@377
  2127
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2128
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2129
    load_fr_bank( R_EDX );
nkeynes@380
  2130
    JNE_rel8(8, doubleprec);
nkeynes@377
  2131
    push_fr(R_EDX, FRm);
nkeynes@377
  2132
    push_fr(R_EDX, FRn);
nkeynes@380
  2133
    JMP_rel8(6, end);
nkeynes@380
  2134
    JMP_TARGET(doubleprec);
nkeynes@377
  2135
    push_dr(R_EDX, FRm);
nkeynes@377
  2136
    push_dr(R_EDX, FRn);
nkeynes@380
  2137
    JMP_TARGET(end);
nkeynes@377
  2138
    FCOMIP_st(1);
nkeynes@377
  2139
    SETA_t();
nkeynes@377
  2140
    FPOP_st();
nkeynes@417
  2141
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2142
:}
nkeynes@377
  2143
nkeynes@377
  2144
FSCA FPUL, FRn {:  
nkeynes@377
  2145
    check_fpuen();
nkeynes@388
  2146
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2147
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2148
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2149
    load_fr_bank( R_ECX );
nkeynes@388
  2150
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2151
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2152
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2153
    JMP_TARGET(doubleprec);
nkeynes@417
  2154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2155
:}
nkeynes@377
  2156
FIPR FVm, FVn {:  
nkeynes@377
  2157
    check_fpuen();
nkeynes@388
  2158
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2159
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2160
    JNE_rel8(44, doubleprec);
nkeynes@388
  2161
    
nkeynes@388
  2162
    load_fr_bank( R_ECX );
nkeynes@388
  2163
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2164
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2165
    FMULP_st(1);
nkeynes@388
  2166
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2167
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2168
    FMULP_st(1);
nkeynes@388
  2169
    FADDP_st(1);
nkeynes@388
  2170
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2171
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2172
    FMULP_st(1);
nkeynes@388
  2173
    FADDP_st(1);
nkeynes@388
  2174
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2175
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2176
    FMULP_st(1);
nkeynes@388
  2177
    FADDP_st(1);
nkeynes@388
  2178
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2179
    JMP_TARGET(doubleprec);
nkeynes@417
  2180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2181
:}
nkeynes@377
  2182
FTRV XMTRX, FVn {:  
nkeynes@377
  2183
    check_fpuen();
nkeynes@388
  2184
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2185
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2186
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2187
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2188
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2189
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2190
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2191
    JMP_TARGET(doubleprec);
nkeynes@417
  2192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2193
:}
nkeynes@377
  2194
nkeynes@377
  2195
FRCHG {:  
nkeynes@377
  2196
    check_fpuen();
nkeynes@377
  2197
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2198
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2199
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2200
    update_fr_bank( R_ECX );
nkeynes@417
  2201
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2202
:}
nkeynes@377
  2203
FSCHG {:  
nkeynes@377
  2204
    check_fpuen();
nkeynes@377
  2205
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2206
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2207
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2209
:}
nkeynes@359
  2210
nkeynes@359
  2211
/* Processor control instructions */
nkeynes@368
  2212
LDC Rm, SR {:
nkeynes@386
  2213
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2214
	SLOTILLEGAL();
nkeynes@386
  2215
    } else {
nkeynes@386
  2216
	check_priv();
nkeynes@386
  2217
	load_reg( R_EAX, Rm );
nkeynes@386
  2218
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2219
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2220
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2221
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2222
    }
nkeynes@368
  2223
:}
nkeynes@359
  2224
LDC Rm, GBR {: 
nkeynes@359
  2225
    load_reg( R_EAX, Rm );
nkeynes@359
  2226
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2227
:}
nkeynes@359
  2228
LDC Rm, VBR {:  
nkeynes@386
  2229
    check_priv();
nkeynes@359
  2230
    load_reg( R_EAX, Rm );
nkeynes@359
  2231
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2233
:}
nkeynes@359
  2234
LDC Rm, SSR {:  
nkeynes@386
  2235
    check_priv();
nkeynes@359
  2236
    load_reg( R_EAX, Rm );
nkeynes@359
  2237
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2238
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2239
:}
nkeynes@359
  2240
LDC Rm, SGR {:  
nkeynes@386
  2241
    check_priv();
nkeynes@359
  2242
    load_reg( R_EAX, Rm );
nkeynes@359
  2243
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2244
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2245
:}
nkeynes@359
  2246
LDC Rm, SPC {:  
nkeynes@386
  2247
    check_priv();
nkeynes@359
  2248
    load_reg( R_EAX, Rm );
nkeynes@359
  2249
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2250
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2251
:}
nkeynes@359
  2252
LDC Rm, DBR {:  
nkeynes@386
  2253
    check_priv();
nkeynes@359
  2254
    load_reg( R_EAX, Rm );
nkeynes@359
  2255
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2256
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2257
:}
nkeynes@374
  2258
LDC Rm, Rn_BANK {:  
nkeynes@386
  2259
    check_priv();
nkeynes@374
  2260
    load_reg( R_EAX, Rm );
nkeynes@374
  2261
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2263
:}
nkeynes@359
  2264
LDC.L @Rm+, GBR {:  
nkeynes@359
  2265
    load_reg( R_EAX, Rm );
nkeynes@395
  2266
    check_ralign32( R_EAX );
nkeynes@571
  2267
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2268
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2269
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2270
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2271
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2272
:}
nkeynes@368
  2273
LDC.L @Rm+, SR {:
nkeynes@386
  2274
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2275
	SLOTILLEGAL();
nkeynes@386
  2276
    } else {
nkeynes@559
  2277
	check_priv();
nkeynes@386
  2278
	load_reg( R_EAX, Rm );
nkeynes@395
  2279
	check_ralign32( R_EAX );
nkeynes@571
  2280
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2281
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2282
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2283
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2284
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2285
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2286
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2287
    }
nkeynes@359
  2288
:}
nkeynes@359
  2289
LDC.L @Rm+, VBR {:  
nkeynes@559
  2290
    check_priv();
nkeynes@359
  2291
    load_reg( R_EAX, Rm );
nkeynes@395
  2292
    check_ralign32( R_EAX );
nkeynes@571
  2293
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2294
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2295
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2296
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2298
:}
nkeynes@359
  2299
LDC.L @Rm+, SSR {:
nkeynes@559
  2300
    check_priv();
nkeynes@359
  2301
    load_reg( R_EAX, Rm );
nkeynes@416
  2302
    check_ralign32( R_EAX );
nkeynes@571
  2303
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2304
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2305
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2306
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2307
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
:}
nkeynes@359
  2309
LDC.L @Rm+, SGR {:  
nkeynes@559
  2310
    check_priv();
nkeynes@359
  2311
    load_reg( R_EAX, Rm );
nkeynes@395
  2312
    check_ralign32( R_EAX );
nkeynes@571
  2313
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2314
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2315
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2316
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2318
:}
nkeynes@359
  2319
LDC.L @Rm+, SPC {:  
nkeynes@559
  2320
    check_priv();
nkeynes@359
  2321
    load_reg( R_EAX, Rm );
nkeynes@395
  2322
    check_ralign32( R_EAX );
nkeynes@571
  2323
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2324
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2325
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2326
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2328
:}
nkeynes@359
  2329
LDC.L @Rm+, DBR {:  
nkeynes@559
  2330
    check_priv();
nkeynes@359
  2331
    load_reg( R_EAX, Rm );
nkeynes@395
  2332
    check_ralign32( R_EAX );
nkeynes@571
  2333
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2334
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2335
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2336
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2337
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDC.L @Rm+, Rn_BANK {:  
nkeynes@559
  2340
    check_priv();
nkeynes@374
  2341
    load_reg( R_EAX, Rm );
nkeynes@395
  2342
    check_ralign32( R_EAX );
nkeynes@571
  2343
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2344
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2345
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2346
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2348
:}
nkeynes@359
  2349
LDS Rm, FPSCR {:  
nkeynes@359
  2350
    load_reg( R_EAX, Rm );
nkeynes@359
  2351
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2352
    update_fr_bank( R_EAX );
nkeynes@417
  2353
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2354
:}
nkeynes@359
  2355
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2356
    load_reg( R_EAX, Rm );
nkeynes@395
  2357
    check_ralign32( R_EAX );
nkeynes@571
  2358
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2359
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2360
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2361
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2362
    update_fr_bank( R_EAX );
nkeynes@417
  2363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2364
:}
nkeynes@359
  2365
LDS Rm, FPUL {:  
nkeynes@359
  2366
    load_reg( R_EAX, Rm );
nkeynes@359
  2367
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2368
:}
nkeynes@359
  2369
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2370
    load_reg( R_EAX, Rm );
nkeynes@395
  2371
    check_ralign32( R_EAX );
nkeynes@571
  2372
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2373
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2374
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2375
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2377
:}
nkeynes@359
  2378
LDS Rm, MACH {: 
nkeynes@359
  2379
    load_reg( R_EAX, Rm );
nkeynes@359
  2380
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2381
:}
nkeynes@359
  2382
LDS.L @Rm+, MACH {:  
nkeynes@359
  2383
    load_reg( R_EAX, Rm );
nkeynes@395
  2384
    check_ralign32( R_EAX );
nkeynes@571
  2385
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2386
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2387
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2388
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2390
:}
nkeynes@359
  2391
LDS Rm, MACL {:  
nkeynes@359
  2392
    load_reg( R_EAX, Rm );
nkeynes@359
  2393
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2394
:}
nkeynes@359
  2395
LDS.L @Rm+, MACL {:  
nkeynes@359
  2396
    load_reg( R_EAX, Rm );
nkeynes@395
  2397
    check_ralign32( R_EAX );
nkeynes@571
  2398
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2399
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2400
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2401
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2403
:}
nkeynes@359
  2404
LDS Rm, PR {:  
nkeynes@359
  2405
    load_reg( R_EAX, Rm );
nkeynes@359
  2406
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2407
:}
nkeynes@359
  2408
LDS.L @Rm+, PR {:  
nkeynes@359
  2409
    load_reg( R_EAX, Rm );
nkeynes@395
  2410
    check_ralign32( R_EAX );
nkeynes@571
  2411
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@571
  2412
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
  2413
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2414
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2416
:}
nkeynes@550
  2417
LDTLB {:  
nkeynes@553
  2418
    call_func0( MMU_ldtlb );
nkeynes@550
  2419
:}
nkeynes@359
  2420
OCBI @Rn {:  :}
nkeynes@359
  2421
OCBP @Rn {:  :}
nkeynes@359
  2422
OCBWB @Rn {:  :}
nkeynes@374
  2423
PREF @Rn {:
nkeynes@374
  2424
    load_reg( R_EAX, Rn );
nkeynes@532
  2425
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2426
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2427
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
  2428
    JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
  2429
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
  2430
    JMP_TARGET(end);
nkeynes@417
  2431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2432
:}
nkeynes@388
  2433
SLEEP {: 
nkeynes@388
  2434
    check_priv();
nkeynes@388
  2435
    call_func0( sh4_sleep );
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2437
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2438
    return 2;
nkeynes@388
  2439
:}
nkeynes@386
  2440
STC SR, Rn {:
nkeynes@386
  2441
    check_priv();
nkeynes@386
  2442
    call_func0(sh4_read_sr);
nkeynes@386
  2443
    store_reg( R_EAX, Rn );
nkeynes@417
  2444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2445
:}
nkeynes@359
  2446
STC GBR, Rn {:  
nkeynes@359
  2447
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2448
    store_reg( R_EAX, Rn );
nkeynes@359
  2449
:}
nkeynes@359
  2450
STC VBR, Rn {:  
nkeynes@386
  2451
    check_priv();
nkeynes@359
  2452
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2453
    store_reg( R_EAX, Rn );
nkeynes@417
  2454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2455
:}
nkeynes@359
  2456
STC SSR, Rn {:  
nkeynes@386
  2457
    check_priv();
nkeynes@359
  2458
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2459
    store_reg( R_EAX, Rn );
nkeynes@417
  2460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2461
:}
nkeynes@359
  2462
STC SPC, Rn {:  
nkeynes@386
  2463
    check_priv();
nkeynes@359
  2464
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2465
    store_reg( R_EAX, Rn );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2467
:}
nkeynes@359
  2468
STC SGR, Rn {:  
nkeynes@386
  2469
    check_priv();
nkeynes@359
  2470
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2471
    store_reg( R_EAX, Rn );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2473
:}
nkeynes@359
  2474
STC DBR, Rn {:  
nkeynes@386
  2475
    check_priv();
nkeynes@359
  2476
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2477
    store_reg( R_EAX, Rn );
nkeynes@417
  2478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2479
:}
nkeynes@374
  2480
STC Rm_BANK, Rn {:
nkeynes@386
  2481
    check_priv();
nkeynes@374
  2482
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2483
    store_reg( R_EAX, Rn );
nkeynes@417
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2485
:}
nkeynes@374
  2486
STC.L SR, @-Rn {:
nkeynes@559
  2487
    check_priv();
nkeynes@571
  2488
    load_reg( R_EAX, Rn );
nkeynes@571
  2489
    check_walign32( R_EAX );
nkeynes@571
  2490
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2491
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2492
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2493
    call_func0( sh4_read_sr );
nkeynes@571
  2494
    POP_realigned_r32( R_ECX );
nkeynes@571
  2495
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2496
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2498
:}
nkeynes@359
  2499
STC.L VBR, @-Rn {:  
nkeynes@559
  2500
    check_priv();
nkeynes@571
  2501
    load_reg( R_EAX, Rn );
nkeynes@571
  2502
    check_walign32( R_EAX );
nkeynes@571
  2503
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2504
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2505
    load_spreg( R_EDX, R_VBR );
nkeynes@571
  2506
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2507
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2508
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2509
:}
nkeynes@359
  2510
STC.L SSR, @-Rn {:  
nkeynes@559
  2511
    check_priv();
nkeynes@571
  2512
    load_reg( R_EAX, Rn );
nkeynes@571
  2513
    check_walign32( R_EAX );
nkeynes@571
  2514
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2515
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2516
    load_spreg( R_EDX, R_SSR );
nkeynes@571
  2517
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2518
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2519
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2520
:}
nkeynes@416
  2521
STC.L SPC, @-Rn {:
nkeynes@559
  2522
    check_priv();
nkeynes@571
  2523
    load_reg( R_EAX, Rn );
nkeynes@571
  2524
    check_walign32( R_EAX );
nkeynes@571
  2525
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2526
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2527
    load_spreg( R_EDX, R_SPC );
nkeynes@571
  2528
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2529
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2530
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2531
:}
nkeynes@359
  2532
STC.L SGR, @-Rn {:  
nkeynes@559
  2533
    check_priv();
nkeynes@571
  2534
    load_reg( R_EAX, Rn );
nkeynes@571
  2535
    check_walign32( R_EAX );
nkeynes@571
  2536
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2537
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2538
    load_spreg( R_EDX, R_SGR );
nkeynes@571
  2539
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2540
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2541
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2542
:}
nkeynes@359
  2543
STC.L DBR, @-Rn {:  
nkeynes@559
  2544
    check_priv();
nkeynes@571
  2545
    load_reg( R_EAX, Rn );
nkeynes@571
  2546
    check_walign32( R_EAX );
nkeynes@571
  2547
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2548
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2549
    load_spreg( R_EDX, R_DBR );
nkeynes@571
  2550
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2551
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2552
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2553
:}
nkeynes@374
  2554
STC.L Rm_BANK, @-Rn {:  
nkeynes@559
  2555
    check_priv();
nkeynes@571
  2556
    load_reg( R_EAX, Rn );
nkeynes@571
  2557
    check_walign32( R_EAX );
nkeynes@571
  2558
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2559
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2560
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@571
  2561
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2562
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2563
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2564
:}
nkeynes@359
  2565
STC.L GBR, @-Rn {:  
nkeynes@571
  2566
    load_reg( R_EAX, Rn );
nkeynes@571
  2567
    check_walign32( R_EAX );
nkeynes@571
  2568
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2569
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2570
    load_spreg( R_EDX, R_GBR );
nkeynes@571
  2571
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2572
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2573
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2574
:}
nkeynes@359
  2575
STS FPSCR, Rn {:  
nkeynes@359
  2576
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2577
    store_reg( R_EAX, Rn );
nkeynes@359
  2578
:}
nkeynes@359
  2579
STS.L FPSCR, @-Rn {:  
nkeynes@571
  2580
    load_reg( R_EAX, Rn );
nkeynes@571
  2581
    check_walign32( R_EAX );
nkeynes@571
  2582
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2583
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2584
    load_spreg( R_EDX, R_FPSCR );
nkeynes@571
  2585
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2586
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2588
:}
nkeynes@359
  2589
STS FPUL, Rn {:  
nkeynes@359
  2590
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2591
    store_reg( R_EAX, Rn );
nkeynes@359
  2592
:}
nkeynes@359
  2593
STS.L FPUL, @-Rn {:  
nkeynes@571
  2594
    load_reg( R_EAX, Rn );
nkeynes@571
  2595
    check_walign32( R_EAX );
nkeynes@571
  2596
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2597
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2598
    load_spreg( R_EDX, R_FPUL );
nkeynes@571
  2599
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2600
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2602
:}
nkeynes@359
  2603
STS MACH, Rn {:  
nkeynes@359
  2604
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2605
    store_reg( R_EAX, Rn );
nkeynes@359
  2606
:}
nkeynes@359
  2607
STS.L MACH, @-Rn {:  
nkeynes@571
  2608
    load_reg( R_EAX, Rn );
nkeynes@571
  2609
    check_walign32( R_EAX );
nkeynes@571
  2610
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2611
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2612
    load_spreg( R_EDX, R_MACH );
nkeynes@571
  2613
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2614
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
:}
nkeynes@359
  2617
STS MACL, Rn {:  
nkeynes@359
  2618
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2619
    store_reg( R_EAX, Rn );
nkeynes@359
  2620
:}
nkeynes@359
  2621
STS.L MACL, @-Rn {:  
nkeynes@571
  2622
    load_reg( R_EAX, Rn );
nkeynes@571
  2623
    check_walign32( R_EAX );
nkeynes@571
  2624
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2625
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2626
    load_spreg( R_EDX, R_MACL );
nkeynes@571
  2627
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2628
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2630
:}
nkeynes@359
  2631
STS PR, Rn {:  
nkeynes@359
  2632
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2633
    store_reg( R_EAX, Rn );
nkeynes@359
  2634
:}
nkeynes@359
  2635
STS.L PR, @-Rn {:  
nkeynes@571
  2636
    load_reg( R_EAX, Rn );
nkeynes@571
  2637
    check_walign32( R_EAX );
nkeynes@571
  2638
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@571
  2639
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@571
  2640
    load_spreg( R_EDX, R_PR );
nkeynes@571
  2641
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@571
  2642
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2643
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2644
:}
nkeynes@359
  2645
nkeynes@359
  2646
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2647
%%
nkeynes@416
  2648
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2649
    return 0;
nkeynes@359
  2650
}
.