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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 232:9c8ef78376ed
prev229:f27eb26ccdd2
next235:880bff11df92
author nkeynes
date Tue Sep 26 11:09:13 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add CHECKSLOTILLEGAL() checks around a few banned delay-slot instructions
that were missing it
Change CHECKPRIV() to raise slot-illegal on a delay-slot instruction rather
than general-illegal (as per the manual)
Convert UNDEF() to do the real exception rather than halting the machine
Remove a couple of superfluous alignment checks
file annotate diff log raw
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/**
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 * $Id: sh4core.c,v 1.33 2006-09-26 11:09:13 nkeynes Exp $
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <math.h>
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#include "dream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/intc.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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#define SH4_CALLTRACE 1
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#define MAX_INT 0x7FFFFFFF
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#define MIN_INT 0x80000000
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#define MAX_INTF 2147483647.0
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#define MIN_INTF -2147483648.0
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/* CPU-generated exception code/vector pairs */
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#define EXC_POWER_RESET  0x000 /* vector special */
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#define EXC_MANUAL_RESET 0x020
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#define EXC_READ_ADDR_ERR 0x0E0
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#define EXC_WRITE_ADDR_ERR 0x100
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#define EXC_SLOT_ILLEGAL 0x1A0
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#define EXC_ILLEGAL      0x180
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#define EXV_ILLEGAL      0x100
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#define EXC_TRAP         0x160
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#define EXV_TRAP         0x100
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#define EXC_FPDISABLE    0x800
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#define EXV_FPDISABLE    0x100
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/********************** SH4 Module Definition ****************************/
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void sh4_init( void );
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void sh4_reset( void );
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uint32_t sh4_run_slice( uint32_t );
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void sh4_start( void );
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void sh4_stop( void );
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void sh4_save_state( FILE *f );
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int sh4_load_state( FILE *f );
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struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
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				       NULL, sh4_run_slice, sh4_stop,
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				       sh4_save_state, sh4_load_state };
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struct sh4_registers sh4r;
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void sh4_init(void)
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{
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    register_io_regions( mmio_list_sh4mmio );
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    mmu_init();
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    sh4_reset();
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}
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void sh4_reset(void)
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{
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    /* zero everything out, for the sake of having a consistent state. */
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    memset( &sh4r, 0, sizeof(sh4r) );
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    /* Resume running if we were halted */
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    sh4r.sh4_state = SH4_STATE_RUNNING;
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    sh4r.pc    = 0xA0000000;
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    sh4r.new_pc= 0xA0000002;
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    sh4r.vbr   = 0x00000000;
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    sh4r.fpscr = 0x00040001;
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    sh4r.sr    = 0x700000F0;
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    /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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    /* Peripheral modules */
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    INTC_reset();
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    TMU_reset();
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    SCIF_reset();
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}
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static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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static int sh4_breakpoint_count = 0;
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void sh4_set_breakpoint( uint32_t pc, int type )
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{
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    sh4_breakpoints[sh4_breakpoint_count].address = pc;
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    sh4_breakpoints[sh4_breakpoint_count].type = type;
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    sh4_breakpoint_count++;
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}
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gboolean sh4_clear_breakpoint( uint32_t pc, int type )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc && 
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	    sh4_breakpoints[i].type == type ) {
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	    while( ++i < sh4_breakpoint_count ) {
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		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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	    }
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	    sh4_breakpoint_count--;
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	    return TRUE;
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	}
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    }
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    return FALSE;
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}
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int sh4_get_breakpoint( uint32_t pc )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc )
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	    return sh4_breakpoints[i].type;
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    }
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    return 0;
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}
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uint32_t sh4_run_slice( uint32_t nanosecs ) 
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{
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    int target = sh4r.icount + nanosecs / sh4_cpu_period;
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    int start = sh4r.icount;
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    int i;
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    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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	if( sh4r.int_pending != 0 )
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	    sh4r.sh4_state = SH4_STATE_RUNNING;;
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    }
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    for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	if( !sh4_execute_instruction() )
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	    break;
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#ifdef ENABLE_DEBUG_MODE
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	for( i=0; i<sh4_breakpoint_count; i++ ) {
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	    if( sh4_breakpoints[i].address == sh4r.pc ) {
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		break;
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	    }
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	}
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	if( i != sh4_breakpoint_count ) {
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	    dreamcast_stop();
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	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )
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		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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	    break;
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	}
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#endif	
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
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    return nanosecs;
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}
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void sh4_stop(void)
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{
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}
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void sh4_save_state( FILE *f )
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{
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    fwrite( &sh4r, sizeof(sh4r), 1, f );
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    INTC_save_state( f );
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    TMU_save_state( f );
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    SCIF_save_state( f );
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}
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int sh4_load_state( FILE * f )
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{
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    fread( &sh4r, sizeof(sh4r), 1, f );
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    INTC_load_state( f );
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    TMU_load_state( f );
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    return SCIF_load_state( f );
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}
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/********************** SH4 emulation core  ****************************/
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void sh4_set_pc( int pc )
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{
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    sh4r.pc = pc;
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    sh4r.new_pc = pc+2;
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}
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#define UNDEF(ir) if( sh4r.in_delay_slot ) { RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 ); } else { RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 ); }
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#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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#if(SH4_CALLTRACE == 1)
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#define MAX_CALLSTACK 32
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static struct call_stack {
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    sh4addr_t call_addr;
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    sh4addr_t target_addr;
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    sh4addr_t stack_pointer;
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} call_stack[MAX_CALLSTACK];
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static int call_stack_depth = 0;
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int sh4_call_trace_on = 0;
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static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
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{
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    if( call_stack_depth < MAX_CALLSTACK ) {
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	call_stack[call_stack_depth].call_addr = source;
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	call_stack[call_stack_depth].target_addr = dest;
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	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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    }
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    call_stack_depth++;
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}
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static inline trace_return( sh4addr_t source, sh4addr_t dest )
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{
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    if( call_stack_depth > 0 ) {
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	call_stack_depth--;
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    }
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}
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void fprint_stack_trace( FILE *f )
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{
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    int i = call_stack_depth -1;
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    if( i >= MAX_CALLSTACK )
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	i = MAX_CALLSTACK - 1;
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    for( ; i >= 0; i-- ) {
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	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
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		 (call_stack_depth - i), call_stack[i].call_addr,
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		 call_stack[i].target_addr, call_stack[i].stack_pointer );
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    }
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}
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#define TRACE_CALL( source, dest ) trace_call(source, dest)
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#define TRACE_RETURN( source, dest ) trace_return(source, dest)
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#else
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#define TRACE_CALL( dest, rts ) 
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#define TRACE_RETURN( source, dest )
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#endif
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#define RAISE( x, v, pcadj ) do{			\
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    if( sh4r.vbr == 0 ) { \
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        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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        dreamcast_stop(); return FALSE;	\
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    } else { \
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        sh4r.spc = sh4r.pc + pcadj; \
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        sh4r.ssr = sh4_read_sr(); \
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        sh4r.sgr = sh4r.r[15]; \
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        MMIO_WRITE(MMU,EXPEVT,x); \
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        sh4r.pc = sh4r.vbr + v; \
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        sh4r.new_pc = sh4r.pc + 2; \
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        sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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	sh4r.in_delay_slot = 0; \
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    } \
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    return TRUE; } while(0)
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#define RAISE_SLOTILLEGAL() RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 )
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#define RAISE_ILLEGAL() RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 )
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#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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#define MEM_READ_WORD( addr ) sh4_read_word(addr)
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#define MEM_READ_LONG( addr ) sh4_read_long(addr)
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#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
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#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
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#define CHECK( x, c, v ) if( !x ) RAISE( c, v, 0 )
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#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { if( sh4r.in_delay_slot ) { RAISE_SLOTILLEGAL(); } else { RAISE_ILLEGAL(); } }
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#define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
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#define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
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#define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
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#define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
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#define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL, -2); }
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static void sh4_switch_banks( )
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{
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    uint32_t tmp[8];
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    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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}
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static void sh4_load_sr( uint32_t newval )
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{
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    if( (newval ^ sh4r.sr) & SR_RB )
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        sh4_switch_banks();
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    sh4r.sr = newval;
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    sh4r.t = (newval&SR_T) ? 1 : 0;
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    sh4r.s = (newval&SR_S) ? 1 : 0;
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    sh4r.m = (newval&SR_M) ? 1 : 0;
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    sh4r.q = (newval&SR_Q) ? 1 : 0;
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    intc_mask_changed();
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}
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static void sh4_write_float( uint32_t addr, int reg )
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{
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   322
    if( IS_FPU_DOUBLESIZE() ) {
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	if( reg & 1 ) {
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	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
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	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
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	} else {
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	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
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	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
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	}
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    } else {
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	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
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    }
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}
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static void sh4_read_float( uint32_t addr, int reg )
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{
nkeynes@124
   337
    if( IS_FPU_DOUBLESIZE() ) {
nkeynes@124
   338
	if( reg & 1 ) {
nkeynes@124
   339
	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
nkeynes@124
   340
	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
nkeynes@124
   341
	} else {
nkeynes@124
   342
	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@124
   343
	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
nkeynes@124
   344
	}
nkeynes@124
   345
    } else {
nkeynes@124
   346
	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
nkeynes@124
   347
    }
nkeynes@124
   348
}
nkeynes@124
   349
nkeynes@1
   350
static uint32_t sh4_read_sr( void )
nkeynes@1
   351
{
nkeynes@1
   352
    /* synchronize sh4r.sr with the various bitflags */
nkeynes@1
   353
    sh4r.sr &= SR_MQSTMASK;
nkeynes@1
   354
    if( sh4r.t ) sh4r.sr |= SR_T;
nkeynes@1
   355
    if( sh4r.s ) sh4r.sr |= SR_S;
nkeynes@1
   356
    if( sh4r.m ) sh4r.sr |= SR_M;
nkeynes@1
   357
    if( sh4r.q ) sh4r.sr |= SR_Q;
nkeynes@1
   358
    return sh4r.sr;
nkeynes@1
   359
}
nkeynes@1
   360
/* function for external use */
nkeynes@1
   361
void sh4_raise_exception( int code, int vector )
nkeynes@1
   362
{
nkeynes@229
   363
    RAISE(code, vector, 0);
nkeynes@1
   364
}
nkeynes@1
   365
nkeynes@1
   366
static void sh4_accept_interrupt( void )
nkeynes@1
   367
{
nkeynes@1
   368
    uint32_t code = intc_accept_interrupt();
nkeynes@1
   369
    sh4r.ssr = sh4_read_sr();
nkeynes@1
   370
    sh4r.spc = sh4r.pc;
nkeynes@1
   371
    sh4r.sgr = sh4r.r[15];
nkeynes@1
   372
    sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
nkeynes@1
   373
    MMIO_WRITE( MMU, INTEVT, code );
nkeynes@1
   374
    sh4r.pc = sh4r.vbr + 0x600;
nkeynes@1
   375
    sh4r.new_pc = sh4r.pc + 2;
nkeynes@92
   376
    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
nkeynes@1
   377
}
nkeynes@1
   378
nkeynes@27
   379
gboolean sh4_execute_instruction( void )
nkeynes@1
   380
{
nkeynes@84
   381
    uint32_t pc;
nkeynes@2
   382
    unsigned short ir;
nkeynes@1
   383
    uint32_t tmp;
nkeynes@1
   384
    uint64_t tmpl;
nkeynes@123
   385
    float ftmp;
nkeynes@123
   386
    double dtmp;
nkeynes@1
   387
    
nkeynes@1
   388
#define R0 sh4r.r[0]
nkeynes@84
   389
#define FR0 FR(0)
nkeynes@84
   390
#define DR0 DR(0)
nkeynes@1
   391
#define RN(ir) sh4r.r[(ir&0x0F00)>>8]
nkeynes@1
   392
#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
nkeynes@1
   393
#define RM(ir) sh4r.r[(ir&0x00F0)>>4]
nkeynes@1
   394
#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
nkeynes@1
   395
#define DISP8(ir) (ir&0x00FF)
nkeynes@1
   396
#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1
   397
#define IMM8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1
   398
#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
nkeynes@1
   399
#define DISP12(ir) SIGNEXT12(ir&0x0FFF)
nkeynes@84
   400
#define FRNn(ir) ((ir&0x0F00)>>8)
nkeynes@84
   401
#define FRMn(ir) ((ir&0x00F0)>>4)
nkeynes@84
   402
#define DRNn(ir) ((ir&0x0E00)>>9)
nkeynes@84
   403
#define DRMn(ir) ((ir&0x00E0)>>5)
nkeynes@2
   404
#define FVN(ir) ((ir&0x0C00)>>8)
nkeynes@2
   405
#define FVM(ir) ((ir&0x0300)>>6)
nkeynes@84
   406
#define FRN(ir) FR(FRNn(ir))
nkeynes@84
   407
#define FRM(ir) FR(FRMn(ir))
nkeynes@84
   408
#define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
nkeynes@84
   409
#define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
nkeynes@95
   410
#define DRN(ir) DRb(DRNn(ir), ir&0x0100)
nkeynes@95
   411
#define DRM(ir) DRb(DRMn(ir),ir&0x0010)
nkeynes@84
   412
#define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
nkeynes@84
   413
#define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
nkeynes@1
   414
#define FPULf   *((float *)&sh4r.fpul)
nkeynes@1
   415
#define FPULi    (sh4r.fpul)
nkeynes@1
   416
nkeynes@2
   417
    if( SH4_INT_PENDING() ) 
nkeynes@2
   418
        sh4_accept_interrupt();
nkeynes@1
   419
                 
nkeynes@2
   420
    pc = sh4r.pc;
nkeynes@84
   421
    if( pc > 0xFFFFFF00 ) {
nkeynes@84
   422
	/* SYSCALL Magic */
nkeynes@102
   423
	syscall_invoke( pc );
nkeynes@104
   424
	sh4r.in_delay_slot = 0;
nkeynes@84
   425
	pc = sh4r.pc = sh4r.pr;
nkeynes@84
   426
	sh4r.new_pc = sh4r.pc + 2;
nkeynes@84
   427
    }
nkeynes@208
   428
    CHECKRALIGN16(pc);
nkeynes@2
   429
    ir = MEM_READ_WORD(pc);
nkeynes@1
   430
    sh4r.icount++;
nkeynes@1
   431
    
nkeynes@1
   432
    switch( (ir&0xF000)>>12 ) {
nkeynes@1
   433
        case 0: /* 0000nnnnmmmmxxxx */
nkeynes@1
   434
            switch( ir&0x000F ) {
nkeynes@1
   435
                case 2:
nkeynes@1
   436
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   437
                        case 0: /* STC     SR, Rn */
nkeynes@1
   438
                            CHECKPRIV();
nkeynes@1
   439
                            RN(ir) = sh4_read_sr();
nkeynes@1
   440
                            break;
nkeynes@1
   441
                        case 1: /* STC     GBR, Rn */
nkeynes@1
   442
                            RN(ir) = sh4r.gbr;
nkeynes@1
   443
                            break;
nkeynes@1
   444
                        case 2: /* STC     VBR, Rn */
nkeynes@1
   445
                            CHECKPRIV();
nkeynes@1
   446
                            RN(ir) = sh4r.vbr;
nkeynes@1
   447
                            break;
nkeynes@1
   448
                        case 3: /* STC     SSR, Rn */
nkeynes@1
   449
                            CHECKPRIV();
nkeynes@1
   450
                            RN(ir) = sh4r.ssr;
nkeynes@1
   451
                            break;
nkeynes@1
   452
                        case 4: /* STC     SPC, Rn */
nkeynes@1
   453
                            CHECKPRIV();
nkeynes@1
   454
                            RN(ir) = sh4r.spc;
nkeynes@1
   455
                            break;
nkeynes@1
   456
                        case 8: case 9: case 10: case 11: case 12: case 13:
nkeynes@1
   457
                        case 14: case 15:/* STC     Rm_bank, Rn */
nkeynes@1
   458
                            CHECKPRIV();
nkeynes@1
   459
                            RN(ir) = RN_BANK(ir);
nkeynes@1
   460
                            break;
nkeynes@1
   461
                        default: UNDEF(ir);
nkeynes@1
   462
                    }
nkeynes@1
   463
                    break;
nkeynes@1
   464
                case 3:
nkeynes@1
   465
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   466
                        case 0: /* BSRF    Rn */
nkeynes@232
   467
                            CHECKSLOTILLEGAL();
nkeynes@1
   468
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   469
                            sh4r.in_delay_slot = 1;
nkeynes@1
   470
                            sh4r.pr = sh4r.pc + 4;
nkeynes@1
   471
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   472
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@157
   473
			    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
   474
                            return TRUE;
nkeynes@1
   475
                        case 2: /* BRAF    Rn */
nkeynes@232
   476
                            CHECKSLOTILLEGAL();
nkeynes@1
   477
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   478
                            sh4r.in_delay_slot = 1;
nkeynes@1
   479
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   480
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27
   481
                            return TRUE;
nkeynes@1
   482
                        case 8: /* PREF    [Rn] */
nkeynes@2
   483
                            tmp = RN(ir);
nkeynes@2
   484
                            if( (tmp & 0xFC000000) == 0xE0000000 ) {
nkeynes@2
   485
                                /* Store queue operation */
nkeynes@2
   486
                                int queue = (tmp&0x20)>>2;
nkeynes@2
   487
                                int32_t *src = &sh4r.store_queue[queue];
nkeynes@2
   488
                                uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@2
   489
                                uint32_t target = tmp&0x03FFFFE0 | hi;
nkeynes@2
   490
                                mem_copy_to_sh4( target, src, 32 );
nkeynes@2
   491
                            }
nkeynes@2
   492
                            break;
nkeynes@1
   493
                        case 9: /* OCBI    [Rn] */
nkeynes@1
   494
                        case 10:/* OCBP    [Rn] */
nkeynes@1
   495
                        case 11:/* OCBWB   [Rn] */
nkeynes@1
   496
                            /* anything? */
nkeynes@1
   497
                            break;
nkeynes@1
   498
                        case 12:/* MOVCA.L R0, [Rn] */
nkeynes@164
   499
			    tmp = RN(ir);
nkeynes@208
   500
			    CHECKWALIGN32(tmp);
nkeynes@164
   501
			    MEM_WRITE_LONG( tmp, R0 );
nkeynes@164
   502
			    break;
nkeynes@1
   503
                        default: UNDEF(ir);
nkeynes@1
   504
                    }
nkeynes@1
   505
                    break;
nkeynes@1
   506
                case 4: /* MOV.B   Rm, [R0 + Rn] */
nkeynes@1
   507
                    MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
nkeynes@1
   508
                    break;
nkeynes@1
   509
                case 5: /* MOV.W   Rm, [R0 + Rn] */
nkeynes@208
   510
		    CHECKWALIGN16( R0 + RN(ir) );
nkeynes@1
   511
                    MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
nkeynes@1
   512
                    break;
nkeynes@1
   513
                case 6: /* MOV.L   Rm, [R0 + Rn] */
nkeynes@208
   514
		    CHECKWALIGN32( R0 + RN(ir) );
nkeynes@1
   515
                    MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
nkeynes@1
   516
                    break;
nkeynes@1
   517
                case 7: /* MUL.L   Rm, Rn */
nkeynes@2
   518
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   519
                        (RM(ir) * RN(ir));
nkeynes@1
   520
                    break;
nkeynes@1
   521
                case 8: 
nkeynes@1
   522
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   523
                        case 0: /* CLRT    */
nkeynes@1
   524
                            sh4r.t = 0;
nkeynes@1
   525
                            break;
nkeynes@1
   526
                        case 1: /* SETT    */
nkeynes@1
   527
                            sh4r.t = 1;
nkeynes@1
   528
                            break;
nkeynes@1
   529
                        case 2: /* CLRMAC  */
nkeynes@1
   530
                            sh4r.mac = 0;
nkeynes@1
   531
                            break;
nkeynes@1
   532
                        case 3: /* LDTLB   */
nkeynes@1
   533
                            break;
nkeynes@1
   534
                        case 4: /* CLRS    */
nkeynes@1
   535
                            sh4r.s = 0;
nkeynes@1
   536
                            break;
nkeynes@1
   537
                        case 5: /* SETS    */
nkeynes@1
   538
                            sh4r.s = 1;
nkeynes@1
   539
                            break;
nkeynes@1
   540
                        default: UNDEF(ir);
nkeynes@1
   541
                    }
nkeynes@1
   542
                    break;
nkeynes@1
   543
                case 9: 
nkeynes@1
   544
                    if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
nkeynes@1
   545
                        RN(ir) = sh4r.t;
nkeynes@1
   546
                    else if( ir == 0x0019 ) /* DIV0U   */
nkeynes@1
   547
                        sh4r.m = sh4r.q = sh4r.t = 0;
nkeynes@1
   548
                    else if( ir == 0x0009 )
nkeynes@1
   549
                        /* NOP     */;
nkeynes@1
   550
                    else UNDEF(ir);
nkeynes@1
   551
                    break;
nkeynes@1
   552
                case 10:
nkeynes@1
   553
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@1
   554
                        case 0: /* STS     MACH, Rn */
nkeynes@1
   555
                            RN(ir) = sh4r.mac >> 32;
nkeynes@1
   556
                            break;
nkeynes@1
   557
                        case 1: /* STS     MACL, Rn */
nkeynes@1
   558
                            RN(ir) = (uint32_t)sh4r.mac;
nkeynes@1
   559
                            break;
nkeynes@1
   560
                        case 2: /* STS     PR, Rn */
nkeynes@1
   561
                            RN(ir) = sh4r.pr;
nkeynes@1
   562
                            break;
nkeynes@1
   563
                        case 3: /* STC     SGR, Rn */
nkeynes@1
   564
                            CHECKPRIV();
nkeynes@1
   565
                            RN(ir) = sh4r.sgr;
nkeynes@1
   566
                            break;
nkeynes@1
   567
                        case 5:/* STS      FPUL, Rn */
nkeynes@1
   568
                            RN(ir) = sh4r.fpul;
nkeynes@1
   569
                            break;
nkeynes@1
   570
                        case 6: /* STS     FPSCR, Rn */
nkeynes@1
   571
                            RN(ir) = sh4r.fpscr;
nkeynes@1
   572
                            break;
nkeynes@1
   573
                        case 15:/* STC     DBR, Rn */
nkeynes@1
   574
                            CHECKPRIV();
nkeynes@1
   575
                            RN(ir) = sh4r.dbr;
nkeynes@1
   576
                            break;
nkeynes@1
   577
                        default: UNDEF(ir);
nkeynes@1
   578
                    }
nkeynes@1
   579
                    break;
nkeynes@1
   580
                case 11:
nkeynes@1
   581
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   582
                        case 0: /* RTS     */
nkeynes@232
   583
                            CHECKSLOTILLEGAL();
nkeynes@1
   584
                            CHECKDEST( sh4r.pr );
nkeynes@2
   585
                            sh4r.in_delay_slot = 1;
nkeynes@1
   586
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   587
                            sh4r.new_pc = sh4r.pr;
nkeynes@157
   588
                            TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@27
   589
                            return TRUE;
nkeynes@1
   590
                        case 1: /* SLEEP   */
nkeynes@27
   591
			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@27
   592
				sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@27
   593
			    } else {
nkeynes@27
   594
				sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@27
   595
			    }
nkeynes@27
   596
			    return FALSE; /* Halt CPU */
nkeynes@1
   597
                        case 2: /* RTE     */
nkeynes@1
   598
                            CHECKPRIV();
nkeynes@1
   599
                            CHECKDEST( sh4r.spc );
nkeynes@2
   600
                            CHECKSLOTILLEGAL();
nkeynes@2
   601
                            sh4r.in_delay_slot = 1;
nkeynes@1
   602
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   603
                            sh4r.new_pc = sh4r.spc;
nkeynes@1
   604
                            sh4_load_sr( sh4r.ssr );
nkeynes@27
   605
                            return TRUE;
nkeynes@1
   606
                        default:UNDEF(ir);
nkeynes@1
   607
                    }
nkeynes@1
   608
                    break;
nkeynes@1
   609
                case 12:/* MOV.B   [R0+R%d], R%d */
nkeynes@1
   610
                    RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
nkeynes@1
   611
                    break;
nkeynes@1
   612
                case 13:/* MOV.W   [R0+R%d], R%d */
nkeynes@208
   613
		    CHECKRALIGN16( R0 + RM(ir) );
nkeynes@1
   614
                    RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
nkeynes@1
   615
                    break;
nkeynes@1
   616
                case 14:/* MOV.L   [R0+R%d], R%d */
nkeynes@208
   617
		    CHECKRALIGN32( R0 + RM(ir) );
nkeynes@1
   618
                    RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
nkeynes@1
   619
                    break;
nkeynes@1
   620
                case 15:/* MAC.L   [Rm++], [Rn++] */
nkeynes@208
   621
		    CHECKRALIGN32( RM(ir) );
nkeynes@208
   622
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   623
                    tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
nkeynes@1
   624
                                  SIGNEXT32(MEM_READ_LONG(RN(ir))) );
nkeynes@1
   625
                    if( sh4r.s ) {
nkeynes@1
   626
                        /* 48-bit Saturation. Yuch */
nkeynes@1
   627
                        tmpl += SIGNEXT48(sh4r.mac);
nkeynes@2
   628
                        if( tmpl < 0xFFFF800000000000LL )
nkeynes@2
   629
                            tmpl = 0xFFFF800000000000LL;
nkeynes@2
   630
                        else if( tmpl > 0x00007FFFFFFFFFFFLL )
nkeynes@2
   631
                            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@2
   632
                        sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
nkeynes@2
   633
                            (tmpl&0x0000FFFFFFFFFFFFLL);
nkeynes@1
   634
                    } else sh4r.mac = tmpl;
nkeynes@1
   635
                    
nkeynes@1
   636
                    RM(ir) += 4;
nkeynes@1
   637
                    RN(ir) += 4;
nkeynes@1
   638
                    
nkeynes@1
   639
                    break;
nkeynes@1
   640
                default: UNDEF(ir);
nkeynes@1
   641
            }
nkeynes@1
   642
            break;
nkeynes@1
   643
        case 1: /* 0001nnnnmmmmdddd */
nkeynes@1
   644
            /* MOV.L   Rm, [Rn + disp4*4] */
nkeynes@208
   645
	    tmp = RN(ir) + (DISP4(ir)<<2);
nkeynes@208
   646
	    CHECKWALIGN32( tmp );
nkeynes@208
   647
            MEM_WRITE_LONG( tmp, RM(ir) );
nkeynes@1
   648
            break;
nkeynes@1
   649
        case 2: /* 0010nnnnmmmmxxxx */
nkeynes@1
   650
            switch( ir&0x000F ) {
nkeynes@1
   651
                case 0: /* MOV.B   Rm, [Rn] */
nkeynes@1
   652
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   653
                    break;
nkeynes@1
   654
                case 1: /* MOV.W   Rm, [Rn] */
nkeynes@208
   655
               	    CHECKWALIGN16( RN(ir) );
nkeynes@208
   656
		    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   657
                    break;
nkeynes@1
   658
                case 2: /* MOV.L   Rm, [Rn] */
nkeynes@208
   659
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   660
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   661
                    break;
nkeynes@1
   662
                case 3: UNDEF(ir);
nkeynes@1
   663
                    break;
nkeynes@1
   664
                case 4: /* MOV.B   Rm, [--Rn] */
nkeynes@1
   665
                    RN(ir) --;
nkeynes@1
   666
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   667
                    break;
nkeynes@1
   668
                case 5: /* MOV.W   Rm, [--Rn] */
nkeynes@1
   669
                    RN(ir) -= 2;
nkeynes@208
   670
		    CHECKWALIGN16( RN(ir) );
nkeynes@1
   671
                    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   672
                    break;
nkeynes@1
   673
                case 6: /* MOV.L   Rm, [--Rn] */
nkeynes@1
   674
                    RN(ir) -= 4;
nkeynes@208
   675
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   676
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   677
                    break;
nkeynes@1
   678
                case 7: /* DIV0S   Rm, Rn */
nkeynes@1
   679
                    sh4r.q = RN(ir)>>31;
nkeynes@1
   680
                    sh4r.m = RM(ir)>>31;
nkeynes@1
   681
                    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@1
   682
                    break;
nkeynes@1
   683
                case 8: /* TST     Rm, Rn */
nkeynes@1
   684
                    sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
nkeynes@1
   685
                    break;
nkeynes@1
   686
                case 9: /* AND     Rm, Rn */
nkeynes@1
   687
                    RN(ir) &= RM(ir);
nkeynes@1
   688
                    break;
nkeynes@1
   689
                case 10:/* XOR     Rm, Rn */
nkeynes@1
   690
                    RN(ir) ^= RM(ir);
nkeynes@1
   691
                    break;
nkeynes@1
   692
                case 11:/* OR      Rm, Rn */
nkeynes@1
   693
                    RN(ir) |= RM(ir);
nkeynes@1
   694
                    break;
nkeynes@1
   695
                case 12:/* CMP/STR Rm, Rn */
nkeynes@1
   696
                    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@1
   697
                    tmp = RM(ir) ^ RN(ir);
nkeynes@1
   698
                    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@1
   699
                              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@1
   700
                    break;
nkeynes@1
   701
                case 13:/* XTRCT   Rm, Rn */
nkeynes@1
   702
                    RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
nkeynes@1
   703
                    break;
nkeynes@1
   704
                case 14:/* MULU.W  Rm, Rn */
nkeynes@2
   705
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   706
                        (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
nkeynes@1
   707
                    break;
nkeynes@1
   708
                case 15:/* MULS.W  Rm, Rn */
nkeynes@2
   709
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   710
                        (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
nkeynes@1
   711
                    break;
nkeynes@1
   712
            }
nkeynes@1
   713
            break;
nkeynes@1
   714
        case 3: /* 0011nnnnmmmmxxxx */
nkeynes@1
   715
            switch( ir&0x000F ) {
nkeynes@1
   716
                case 0: /* CMP/EQ  Rm, Rn */
nkeynes@1
   717
                    sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
nkeynes@1
   718
                    break;
nkeynes@1
   719
                case 2: /* CMP/HS  Rm, Rn */
nkeynes@1
   720
                    sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
nkeynes@1
   721
                    break;
nkeynes@1
   722
                case 3: /* CMP/GE  Rm, Rn */
nkeynes@1
   723
                    sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   724
                    break;
nkeynes@1
   725
                case 4: { /* DIV1    Rm, Rn */
nkeynes@1
   726
                    /* This is just from the sh4p manual with some
nkeynes@1
   727
                     * simplifications (someone want to check it's correct? :)
nkeynes@1
   728
                     * Why they couldn't just provide a real DIV instruction...
nkeynes@1
   729
                     * Please oh please let the translator batch these things
nkeynes@1
   730
                     * up into a single DIV... */
nkeynes@1
   731
                    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@1
   732
nkeynes@1
   733
                    dir = sh4r.q ^ sh4r.m;
nkeynes@1
   734
                    sh4r.q = (RN(ir) >> 31);
nkeynes@1
   735
                    tmp2 = RM(ir);
nkeynes@1
   736
                    RN(ir) = (RN(ir) << 1) | sh4r.t;
nkeynes@1
   737
                    tmp0 = RN(ir);
nkeynes@1
   738
                    if( dir ) {
nkeynes@1
   739
                        RN(ir) += tmp2;
nkeynes@1
   740
                        tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
nkeynes@1
   741
                    } else {
nkeynes@1
   742
                        RN(ir) -= tmp2;
nkeynes@1
   743
                        tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
nkeynes@1
   744
                    }
nkeynes@1
   745
                    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@1
   746
                    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@1
   747
                    break; }
nkeynes@1
   748
                case 5: /* DMULU.L Rm, Rn */
nkeynes@1
   749
                    sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
nkeynes@1
   750
                    break;
nkeynes@1
   751
                case 6: /* CMP/HI  Rm, Rn */
nkeynes@1
   752
                    sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
nkeynes@1
   753
                    break;
nkeynes@1
   754
                case 7: /* CMP/GT  Rm, Rn */
nkeynes@1
   755
                    sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   756
                    break;
nkeynes@1
   757
                case 8: /* SUB     Rm, Rn */
nkeynes@1
   758
                    RN(ir) -= RM(ir);
nkeynes@1
   759
                    break;
nkeynes@1
   760
                case 10:/* SUBC    Rm, Rn */
nkeynes@1
   761
                    tmp = RN(ir);
nkeynes@1
   762
                    RN(ir) = RN(ir) - RM(ir) - sh4r.t;
nkeynes@1
   763
                    sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
nkeynes@1
   764
                    break;
nkeynes@1
   765
                case 11:/* SUBV    Rm, Rn */
nkeynes@1
   766
                    UNIMP(ir);
nkeynes@1
   767
                    break;
nkeynes@1
   768
                case 12:/* ADD     Rm, Rn */
nkeynes@1
   769
                    RN(ir) += RM(ir);
nkeynes@1
   770
                    break;
nkeynes@1
   771
                case 13:/* DMULS.L Rm, Rn */
nkeynes@1
   772
                    sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
nkeynes@1
   773
                    break;
nkeynes@1
   774
                case 14:/* ADDC    Rm, Rn */
nkeynes@1
   775
                    tmp = RN(ir);
nkeynes@1
   776
                    RN(ir) += RM(ir) + sh4r.t;
nkeynes@1
   777
                    sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@1
   778
                    break;
nkeynes@1
   779
                case 15:/* ADDV    Rm, Rn */
nkeynes@227
   780
		    tmp = RN(ir) + RM(ir);
nkeynes@227
   781
		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
nkeynes@227
   782
		    RN(ir) = tmp;
nkeynes@1
   783
                    break;
nkeynes@1
   784
                default: UNDEF(ir);
nkeynes@1
   785
            }
nkeynes@1
   786
            break;
nkeynes@1
   787
        case 4: /* 0100nnnnxxxxxxxx */
nkeynes@1
   788
            switch( ir&0x00FF ) {
nkeynes@1
   789
                case 0x00: /* SHLL    Rn */
nkeynes@1
   790
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   791
                    RN(ir) <<= 1;
nkeynes@1
   792
                    break;
nkeynes@1
   793
                case 0x01: /* SHLR    Rn */
nkeynes@1
   794
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   795
                    RN(ir) >>= 1;
nkeynes@1
   796
                    break;
nkeynes@1
   797
                case 0x02: /* STS.L   MACH, [--Rn] */
nkeynes@1
   798
                    RN(ir) -= 4;
nkeynes@208
   799
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   800
                    MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
nkeynes@1
   801
                    break;
nkeynes@1
   802
                case 0x03: /* STC.L   SR, [--Rn] */
nkeynes@1
   803
                    CHECKPRIV();
nkeynes@1
   804
                    RN(ir) -= 4;
nkeynes@208
   805
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   806
                    MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
nkeynes@1
   807
                    break;
nkeynes@1
   808
                case 0x04: /* ROTL    Rn */
nkeynes@1
   809
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   810
                    RN(ir) <<= 1;
nkeynes@1
   811
                    RN(ir) |= sh4r.t;
nkeynes@1
   812
                    break;
nkeynes@1
   813
                case 0x05: /* ROTR    Rn */
nkeynes@1
   814
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   815
                    RN(ir) >>= 1;
nkeynes@1
   816
                    RN(ir) |= (sh4r.t << 31);
nkeynes@1
   817
                    break;
nkeynes@1
   818
                case 0x06: /* LDS.L   [Rn++], MACH */
nkeynes@208
   819
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   820
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   821
                        (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
nkeynes@1
   822
                    RN(ir) += 4;
nkeynes@1
   823
                    break;
nkeynes@1
   824
                case 0x07: /* LDC.L   [Rn++], SR */
nkeynes@232
   825
		    CHECKSLOTILLEGAL();
nkeynes@1
   826
                    CHECKPRIV();
nkeynes@208
   827
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   828
                    sh4_load_sr( MEM_READ_LONG(RN(ir)) );
nkeynes@1
   829
                    RN(ir) +=4;
nkeynes@1
   830
                    break;
nkeynes@1
   831
                case 0x08: /* SHLL2   Rn */
nkeynes@1
   832
                    RN(ir) <<= 2;
nkeynes@1
   833
                    break;
nkeynes@1
   834
                case 0x09: /* SHLR2   Rn */
nkeynes@1
   835
                    RN(ir) >>= 2;
nkeynes@1
   836
                    break;
nkeynes@1
   837
                case 0x0A: /* LDS     Rn, MACH */
nkeynes@1
   838
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   839
                        (((uint64_t)RN(ir))<<32);
nkeynes@1
   840
                    break;
nkeynes@1
   841
                case 0x0B: /* JSR     [Rn] */
nkeynes@1
   842
                    CHECKDEST( RN(ir) );
nkeynes@2
   843
                    CHECKSLOTILLEGAL();
nkeynes@2
   844
                    sh4r.in_delay_slot = 1;
nkeynes@1
   845
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
   846
                    sh4r.new_pc = RN(ir);
nkeynes@1
   847
                    sh4r.pr = pc + 4;
nkeynes@157
   848
		    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
   849
                    return TRUE;
nkeynes@1
   850
                case 0x0E: /* LDC     Rn, SR */
nkeynes@232
   851
		    CHECKSLOTILLEGAL();
nkeynes@1
   852
                    CHECKPRIV();
nkeynes@1
   853
                    sh4_load_sr( RN(ir) );
nkeynes@1
   854
                    break;
nkeynes@1
   855
                case 0x10: /* DT      Rn */
nkeynes@1
   856
                    RN(ir) --;
nkeynes@1
   857
                    sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
nkeynes@1
   858
                    break;
nkeynes@1
   859
                case 0x11: /* CMP/PZ  Rn */
nkeynes@1
   860
                    sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
nkeynes@1
   861
                    break;
nkeynes@1
   862
                case 0x12: /* STS.L   MACL, [--Rn] */
nkeynes@1
   863
                    RN(ir) -= 4;
nkeynes@208
   864
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   865
                    MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
nkeynes@1
   866
                    break;
nkeynes@1
   867
                case 0x13: /* STC.L   GBR, [--Rn] */
nkeynes@1
   868
                    RN(ir) -= 4;
nkeynes@208
   869
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   870
                    MEM_WRITE_LONG( RN(ir), sh4r.gbr );
nkeynes@1
   871
                    break;
nkeynes@1
   872
                case 0x15: /* CMP/PL  Rn */
nkeynes@1
   873
                    sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
nkeynes@1
   874
                    break;
nkeynes@1
   875
                case 0x16: /* LDS.L   [Rn++], MACL */
nkeynes@208
   876
		    CHECKRALIGN32( RN(ir) );
nkeynes@2
   877
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   878
                        (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
nkeynes@1
   879
                    RN(ir) += 4;
nkeynes@1
   880
                    break;
nkeynes@1
   881
                case 0x17: /* LDC.L   [Rn++], GBR */
nkeynes@208
   882
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   883
                    sh4r.gbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   884
                    RN(ir) +=4;
nkeynes@1
   885
                    break;
nkeynes@1
   886
                case 0x18: /* SHLL8   Rn */
nkeynes@1
   887
                    RN(ir) <<= 8;
nkeynes@1
   888
                    break;
nkeynes@1
   889
                case 0x19: /* SHLR8   Rn */
nkeynes@1
   890
                    RN(ir) >>= 8;
nkeynes@1
   891
                    break;
nkeynes@1
   892
                case 0x1A: /* LDS     Rn, MACL */
nkeynes@2
   893
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   894
                        (uint64_t)((uint32_t)(RN(ir)));
nkeynes@1
   895
                    break;
nkeynes@1
   896
                case 0x1B: /* TAS.B   [Rn] */
nkeynes@1
   897
                    tmp = MEM_READ_BYTE( RN(ir) );
nkeynes@1
   898
                    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@1
   899
                    MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
nkeynes@1
   900
                    break;
nkeynes@1
   901
                case 0x1E: /* LDC     Rn, GBR */
nkeynes@1
   902
                    sh4r.gbr = RN(ir);
nkeynes@1
   903
                    break;
nkeynes@1
   904
                case 0x20: /* SHAL    Rn */
nkeynes@1
   905
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   906
                    RN(ir) <<= 1;
nkeynes@1
   907
                    break;
nkeynes@1
   908
                case 0x21: /* SHAR    Rn */
nkeynes@1
   909
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   910
                    RN(ir) = ((int32_t)RN(ir)) >> 1;
nkeynes@1
   911
                    break;
nkeynes@1
   912
                case 0x22: /* STS.L   PR, [--Rn] */
nkeynes@1
   913
                    RN(ir) -= 4;
nkeynes@208
   914
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   915
                    MEM_WRITE_LONG( RN(ir), sh4r.pr );
nkeynes@1
   916
                    break;
nkeynes@1
   917
                case 0x23: /* STC.L   VBR, [--Rn] */
nkeynes@1
   918
                    CHECKPRIV();
nkeynes@1
   919
                    RN(ir) -= 4;
nkeynes@208
   920
		    CHECKWALIGN32( RN(ir) );
nkeynes@2
   921
                    MEM_WRITE_LONG( RN(ir), sh4r.vbr );
nkeynes@1
   922
                    break;
nkeynes@1
   923
                case 0x24: /* ROTCL   Rn */
nkeynes@1
   924
                    tmp = RN(ir) >> 31;
nkeynes@1
   925
                    RN(ir) <<= 1;
nkeynes@1
   926
                    RN(ir) |= sh4r.t;
nkeynes@1
   927
                    sh4r.t = tmp;
nkeynes@1
   928
                    break;
nkeynes@1
   929
                case 0x25: /* ROTCR   Rn */
nkeynes@1
   930
                    tmp = RN(ir) & 0x00000001;
nkeynes@1
   931
                    RN(ir) >>= 1;
nkeynes@1
   932
                    RN(ir) |= (sh4r.t << 31 );
nkeynes@1
   933
                    sh4r.t = tmp;
nkeynes@1
   934
                    break;
nkeynes@1
   935
                case 0x26: /* LDS.L   [Rn++], PR */
nkeynes@208
   936
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   937
                    sh4r.pr = MEM_READ_LONG( RN(ir) );
nkeynes@1
   938
                    RN(ir) += 4;
nkeynes@1
   939
                    break;
nkeynes@1
   940
                case 0x27: /* LDC.L   [Rn++], VBR */
nkeynes@1
   941
                    CHECKPRIV();
nkeynes@208
   942
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   943
                    sh4r.vbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   944
                    RN(ir) +=4;
nkeynes@1
   945
                    break;
nkeynes@1
   946
                case 0x28: /* SHLL16  Rn */
nkeynes@1
   947
                    RN(ir) <<= 16;
nkeynes@1
   948
                    break;
nkeynes@1
   949
                case 0x29: /* SHLR16  Rn */
nkeynes@1
   950
                    RN(ir) >>= 16;
nkeynes@1
   951
                    break;
nkeynes@1
   952
                case 0x2A: /* LDS     Rn, PR */
nkeynes@1
   953
                    sh4r.pr = RN(ir);
nkeynes@1
   954
                    break;
nkeynes@1
   955
                case 0x2B: /* JMP     [Rn] */
nkeynes@1
   956
                    CHECKDEST( RN(ir) );
nkeynes@2
   957
                    CHECKSLOTILLEGAL();
nkeynes@2
   958
                    sh4r.in_delay_slot = 1;
nkeynes@1
   959
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
   960
                    sh4r.new_pc = RN(ir);
nkeynes@27
   961
                    return TRUE;
nkeynes@1
   962
                case 0x2E: /* LDC     Rn, VBR */
nkeynes@1
   963
                    CHECKPRIV();
nkeynes@1
   964
                    sh4r.vbr = RN(ir);
nkeynes@1
   965
                    break;
nkeynes@1
   966
                case 0x32: /* STC.L   SGR, [--Rn] */
nkeynes@1
   967
                    CHECKPRIV();
nkeynes@1
   968
                    RN(ir) -= 4;
nkeynes@208
   969
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   970
                    MEM_WRITE_LONG( RN(ir), sh4r.sgr );
nkeynes@1
   971
                    break;
nkeynes@1
   972
                case 0x33: /* STC.L   SSR, [--Rn] */
nkeynes@1
   973
                    CHECKPRIV();
nkeynes@1
   974
                    RN(ir) -= 4;
nkeynes@208
   975
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   976
                    MEM_WRITE_LONG( RN(ir), sh4r.ssr );
nkeynes@1
   977
                    break;
nkeynes@1
   978
                case 0x37: /* LDC.L   [Rn++], SSR */
nkeynes@1
   979
                    CHECKPRIV();
nkeynes@208
   980
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   981
                    sh4r.ssr = MEM_READ_LONG(RN(ir));
nkeynes@1
   982
                    RN(ir) +=4;
nkeynes@1
   983
                    break;
nkeynes@1
   984
                case 0x3E: /* LDC     Rn, SSR */
nkeynes@1
   985
                    CHECKPRIV();
nkeynes@1
   986
                    sh4r.ssr = RN(ir);
nkeynes@1
   987
                    break;
nkeynes@1
   988
                case 0x43: /* STC.L   SPC, [--Rn] */
nkeynes@1
   989
                    CHECKPRIV();
nkeynes@1
   990
                    RN(ir) -= 4;
nkeynes@208
   991
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
   992
                    MEM_WRITE_LONG( RN(ir), sh4r.spc );
nkeynes@1
   993
                    break;
nkeynes@1
   994
                case 0x47: /* LDC.L   [Rn++], SPC */
nkeynes@1
   995
                    CHECKPRIV();
nkeynes@208
   996
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
   997
                    sh4r.spc = MEM_READ_LONG(RN(ir));
nkeynes@1
   998
                    RN(ir) +=4;
nkeynes@1
   999
                    break;
nkeynes@1
  1000
                case 0x4E: /* LDC     Rn, SPC */
nkeynes@1
  1001
                    CHECKPRIV();
nkeynes@1
  1002
                    sh4r.spc = RN(ir);
nkeynes@1
  1003
                    break;
nkeynes@1
  1004
                case 0x52: /* STS.L   FPUL, [--Rn] */
nkeynes@1
  1005
                    RN(ir) -= 4;
nkeynes@208
  1006
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1007
                    MEM_WRITE_LONG( RN(ir), sh4r.fpul );
nkeynes@1
  1008
                    break;
nkeynes@1
  1009
                case 0x56: /* LDS.L   [Rn++], FPUL */
nkeynes@208
  1010
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1011
                    sh4r.fpul = MEM_READ_LONG(RN(ir));
nkeynes@1
  1012
                    RN(ir) +=4;
nkeynes@1
  1013
                    break;
nkeynes@1
  1014
                case 0x5A: /* LDS     Rn, FPUL */
nkeynes@1
  1015
                    sh4r.fpul = RN(ir);
nkeynes@1
  1016
                    break;
nkeynes@1
  1017
                case 0x62: /* STS.L   FPSCR, [--Rn] */
nkeynes@1
  1018
                    RN(ir) -= 4;
nkeynes@208
  1019
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1020
                    MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
nkeynes@1
  1021
                    break;
nkeynes@1
  1022
                case 0x66: /* LDS.L   [Rn++], FPSCR */
nkeynes@208
  1023
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1024
                    sh4r.fpscr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1025
                    RN(ir) +=4;
nkeynes@1
  1026
                    break;
nkeynes@1
  1027
                case 0x6A: /* LDS     Rn, FPSCR */
nkeynes@1
  1028
                    sh4r.fpscr = RN(ir);
nkeynes@1
  1029
                    break;
nkeynes@1
  1030
                case 0xF2: /* STC.L   DBR, [--Rn] */
nkeynes@1
  1031
                    CHECKPRIV();
nkeynes@1
  1032
                    RN(ir) -= 4;
nkeynes@208
  1033
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1034
                    MEM_WRITE_LONG( RN(ir), sh4r.dbr );
nkeynes@1
  1035
                    break;
nkeynes@1
  1036
                case 0xF6: /* LDC.L   [Rn++], DBR */
nkeynes@1
  1037
                    CHECKPRIV();
nkeynes@208
  1038
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1039
                    sh4r.dbr = MEM_READ_LONG(RN(ir));
nkeynes@1
  1040
                    RN(ir) +=4;
nkeynes@1
  1041
                    break;
nkeynes@1
  1042
                case 0xFA: /* LDC     Rn, DBR */
nkeynes@1
  1043
                    CHECKPRIV();
nkeynes@1
  1044
                    sh4r.dbr = RN(ir);
nkeynes@1
  1045
                    break;
nkeynes@1
  1046
                case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
nkeynes@1
  1047
                case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
nkeynes@1
  1048
                    CHECKPRIV();
nkeynes@1
  1049
                    RN(ir) -= 4;
nkeynes@208
  1050
		    CHECKWALIGN32( RN(ir) );
nkeynes@1
  1051
                    MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
nkeynes@1
  1052
                    break;
nkeynes@1
  1053
                case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
nkeynes@1
  1054
                case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
nkeynes@1
  1055
                    CHECKPRIV();
nkeynes@208
  1056
		    CHECKRALIGN32( RN(ir) );
nkeynes@1
  1057
                    RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
nkeynes@1
  1058
                    RN(ir) += 4;
nkeynes@1
  1059
                    break;
nkeynes@1
  1060
                case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
nkeynes@1
  1061
                case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
nkeynes@1
  1062
                    CHECKPRIV();
nkeynes@1
  1063
                    RN_BANK(ir) = RM(ir);
nkeynes@1
  1064
                    break;
nkeynes@1
  1065
                default:
nkeynes@1
  1066
                    if( (ir&0x000F) == 0x0F ) {
nkeynes@1
  1067
                        /* MAC.W   [Rm++], [Rn++] */
nkeynes@208
  1068
			CHECKRALIGN16( RN(ir) );
nkeynes@208
  1069
			CHECKRALIGN16( RM(ir) );
nkeynes@1
  1070
                        tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
nkeynes@1
  1071
                            SIGNEXT16(MEM_READ_WORD(RN(ir)));
nkeynes@1
  1072
                        if( sh4r.s ) {
nkeynes@1
  1073
                            /* FIXME */
nkeynes@1
  1074
                            UNIMP(ir);
nkeynes@1
  1075
                        } else sh4r.mac += SIGNEXT32(tmp);
nkeynes@1
  1076
                        RM(ir) += 2;
nkeynes@1
  1077
                        RN(ir) += 2;
nkeynes@1
  1078
                    } else if( (ir&0x000F) == 0x0C ) {
nkeynes@1
  1079
                        /* SHAD    Rm, Rn */
nkeynes@1
  1080
                        tmp = RM(ir);
nkeynes@1
  1081
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@9
  1082
                        else if( (tmp & 0x1F) == 0 )  
nkeynes@9
  1083
			  RN(ir) = ((int32_t)RN(ir)) >> 31;
nkeynes@9
  1084
                        else 
nkeynes@9
  1085
			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
nkeynes@1
  1086
                    } else if( (ir&0x000F) == 0x0D ) {
nkeynes@1
  1087
                        /* SHLD    Rm, Rn */
nkeynes@1
  1088
                        tmp = RM(ir);
nkeynes@1
  1089
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@1
  1090
                        else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
nkeynes@1
  1091
                        else RN(ir) >>= (((~tmp) & 0x1F)+1);
nkeynes@1
  1092
                    } else UNDEF(ir);
nkeynes@1
  1093
            }
nkeynes@1
  1094
            break;
nkeynes@1
  1095
        case 5: /* 0101nnnnmmmmdddd */
nkeynes@1
  1096
            /* MOV.L   [Rm + disp4*4], Rn */
nkeynes@208
  1097
	    tmp = RM(ir) + (DISP4(ir)<<2);
nkeynes@208
  1098
	    CHECKRALIGN32( tmp );
nkeynes@208
  1099
            RN(ir) = MEM_READ_LONG( tmp );
nkeynes@1
  1100
            break;
nkeynes@1
  1101
        case 6: /* 0110xxxxxxxxxxxx */
nkeynes@1
  1102
            switch( ir&0x000f ) {
nkeynes@1
  1103
                case 0: /* MOV.B   [Rm], Rn */
nkeynes@1
  1104
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
  1105
                    break;
nkeynes@1
  1106
                case 1: /* MOV.W   [Rm], Rn */
nkeynes@208
  1107
		    CHECKRALIGN16( RM(ir) );
nkeynes@1
  1108
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
  1109
                    break;
nkeynes@1
  1110
                case 2: /* MOV.L   [Rm], Rn */
nkeynes@208
  1111
		    CHECKRALIGN32( RM(ir) );
nkeynes@1
  1112
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
  1113
                    break;
nkeynes@1
  1114
                case 3: /* MOV     Rm, Rn */
nkeynes@1
  1115
                    RN(ir) = RM(ir);
nkeynes@1
  1116
                    break;
nkeynes@1
  1117
                case 4: /* MOV.B   [Rm++], Rn */
nkeynes@1
  1118
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
  1119
                    RM(ir) ++;
nkeynes@1
  1120
                    break;
nkeynes@1
  1121
                case 5: /* MOV.W   [Rm++], Rn */
nkeynes@208
  1122
		    CHECKRALIGN16( RM(ir) );
nkeynes@1
  1123
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
  1124
                    RM(ir) += 2;
nkeynes@1
  1125
                    break;
nkeynes@1
  1126
                case 6: /* MOV.L   [Rm++], Rn */
nkeynes@208
  1127
		    CHECKRALIGN32( RM(ir) );
nkeynes@1
  1128
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
  1129
                    RM(ir) += 4;
nkeynes@1
  1130
                    break;
nkeynes@1
  1131
                case 7: /* NOT     Rm, Rn */
nkeynes@1
  1132
                    RN(ir) = ~RM(ir);
nkeynes@1
  1133
                    break;
nkeynes@1
  1134
                case 8: /* SWAP.B  Rm, Rn */
nkeynes@1
  1135
                    RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
nkeynes@1
  1136
                        ((RM(ir)&0x000000FF)<<8);
nkeynes@1
  1137
                    break;
nkeynes@1
  1138
                case 9: /* SWAP.W  Rm, Rn */
nkeynes@1
  1139
                    RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
nkeynes@1
  1140
                    break;
nkeynes@1
  1141
                case 10:/* NEGC    Rm, Rn */
nkeynes@1
  1142
                    tmp = 0 - RM(ir);
nkeynes@1
  1143
                    RN(ir) = tmp - sh4r.t;
nkeynes@1
  1144
                    sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
nkeynes@1
  1145
                    break;
nkeynes@1
  1146
                case 11:/* NEG     Rm, Rn */
nkeynes@1
  1147
                    RN(ir) = 0 - RM(ir);
nkeynes@1
  1148
                    break;
nkeynes@1
  1149
                case 12:/* EXTU.B  Rm, Rn */
nkeynes@1
  1150
                    RN(ir) = RM(ir)&0x000000FF;
nkeynes@1
  1151
                    break;
nkeynes@1
  1152
                case 13:/* EXTU.W  Rm, Rn */
nkeynes@1
  1153
                    RN(ir) = RM(ir)&0x0000FFFF;
nkeynes@1
  1154
                    break;
nkeynes@1
  1155
                case 14:/* EXTS.B  Rm, Rn */
nkeynes@1
  1156
                    RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
nkeynes@1
  1157
                    break;
nkeynes@1
  1158
                case 15:/* EXTS.W  Rm, Rn */
nkeynes@1
  1159
                    RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
nkeynes@1
  1160
                    break;
nkeynes@1
  1161
            }
nkeynes@1
  1162
            break;
nkeynes@1
  1163
        case 7: /* 0111nnnniiiiiiii */
nkeynes@1
  1164
            /* ADD    imm8, Rn */
nkeynes@1
  1165
            RN(ir) += IMM8(ir);
nkeynes@1
  1166
            break;
nkeynes@1
  1167
        case 8: /* 1000xxxxxxxxxxxx */
nkeynes@1
  1168
            switch( (ir&0x0F00) >> 8 ) {
nkeynes@1
  1169
                case 0: /* MOV.B   R0, [Rm + disp4] */
nkeynes@1
  1170
                    MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
nkeynes@1
  1171
                    break;
nkeynes@1
  1172
                case 1: /* MOV.W   R0, [Rm + disp4*2] */
nkeynes@208
  1173
		    tmp = RM(ir) + (DISP4(ir)<<1);
nkeynes@208
  1174
		    CHECKWALIGN16( tmp );
nkeynes@208
  1175
                    MEM_WRITE_WORD( tmp, R0 );
nkeynes@1
  1176
                    break;
nkeynes@1
  1177
                case 4: /* MOV.B   [Rm + disp4], R0 */
nkeynes@1
  1178
                    R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
nkeynes@1
  1179
                    break;
nkeynes@1
  1180
                case 5: /* MOV.W   [Rm + disp4*2], R0 */
nkeynes@208
  1181
		    tmp = RM(ir) + (DISP4(ir)<<1);
nkeynes@208
  1182
		    CHECKRALIGN16( tmp );
nkeynes@208
  1183
                    R0 = MEM_READ_WORD( tmp );
nkeynes@1
  1184
                    break;
nkeynes@1
  1185
                case 8: /* CMP/EQ  imm, R0 */
nkeynes@1
  1186
                    sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
nkeynes@1
  1187
                    break;
nkeynes@1
  1188
                case 9: /* BT      disp8 */
nkeynes@2
  1189
                    CHECKSLOTILLEGAL()
nkeynes@1
  1190
                    if( sh4r.t ) {
nkeynes@1
  1191
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1192
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1193
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1194
                        return TRUE;
nkeynes@1
  1195
                    }
nkeynes@1
  1196
                    break;
nkeynes@1
  1197
                case 11:/* BF      disp8 */
nkeynes@2
  1198
                    CHECKSLOTILLEGAL()
nkeynes@1
  1199
                    if( !sh4r.t ) {
nkeynes@1
  1200
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1201
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1202
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1203
                        return TRUE;
nkeynes@1
  1204
                    }
nkeynes@1
  1205
                    break;
nkeynes@1
  1206
                case 13:/* BT/S    disp8 */
nkeynes@2
  1207
                    CHECKSLOTILLEGAL()
nkeynes@1
  1208
                    if( sh4r.t ) {
nkeynes@1
  1209
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1210
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1211
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1212
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@2
  1213
                        sh4r.in_delay_slot = 1;
nkeynes@27
  1214
                        return TRUE;
nkeynes@1
  1215
                    }
nkeynes@1
  1216
                    break;
nkeynes@1
  1217
                case 15:/* BF/S    disp8 */
nkeynes@2
  1218
                    CHECKSLOTILLEGAL()
nkeynes@1
  1219
                    if( !sh4r.t ) {
nkeynes@1
  1220
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1221
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1222
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1223
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@27
  1224
                        return TRUE;
nkeynes@1
  1225
                    }
nkeynes@1
  1226
                    break;
nkeynes@1
  1227
                default: UNDEF(ir);
nkeynes@1
  1228
            }
nkeynes@1
  1229
            break;
nkeynes@1
  1230
        case 9: /* 1001xxxxxxxxxxxx */
nkeynes@1
  1231
            /* MOV.W   [disp8*2 + pc + 4], Rn */
nkeynes@232
  1232
	    CHECKSLOTILLEGAL();
nkeynes@208
  1233
	    tmp = pc + 4 + (DISP8(ir)<<1);
nkeynes@208
  1234
            RN(ir) = MEM_READ_WORD( tmp );
nkeynes@1
  1235
            break;
nkeynes@1
  1236
        case 10:/* 1010dddddddddddd */
nkeynes@1
  1237
            /* BRA     disp12 */
nkeynes@232
  1238
            CHECKSLOTILLEGAL()
nkeynes@2
  1239
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2
  1240
            sh4r.in_delay_slot = 1;
nkeynes@1
  1241
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1242
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27
  1243
            return TRUE;
nkeynes@1
  1244
        case 11:/* 1011dddddddddddd */
nkeynes@1
  1245
            /* BSR     disp12 */
nkeynes@1
  1246
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2
  1247
            CHECKSLOTILLEGAL()
nkeynes@2
  1248
            sh4r.in_delay_slot = 1;
nkeynes@1
  1249
            sh4r.pr = pc + 4;
nkeynes@1
  1250
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1251
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@157
  1252
	    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@27
  1253
            return TRUE;
nkeynes@1
  1254
        case 12:/* 1100xxxxdddddddd */
nkeynes@1
  1255
        switch( (ir&0x0F00)>>8 ) {
nkeynes@1
  1256
                case 0: /* MOV.B  R0, [GBR + disp8] */
nkeynes@1
  1257
                    MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
nkeynes@1
  1258
                    break;
nkeynes@1
  1259
                case 1: /* MOV.W  R0, [GBR + disp8*2] */
nkeynes@208
  1260
		    tmp = sh4r.gbr + (DISP8(ir)<<1);
nkeynes@208
  1261
		    CHECKWALIGN16( tmp );
nkeynes@208
  1262
                    MEM_WRITE_WORD( tmp, R0 );
nkeynes@1
  1263
                    break;
nkeynes@1
  1264
                case  2: /*MOV.L   R0, [GBR + disp8*4] */
nkeynes@208
  1265
		    tmp = sh4r.gbr + (DISP8(ir)<<2);
nkeynes@208
  1266
		    CHECKWALIGN32( tmp );
nkeynes@208
  1267
                    MEM_WRITE_LONG( tmp, R0 );
nkeynes@1
  1268
                    break;
nkeynes@1
  1269
                case 3: /* TRAPA   imm8 */
nkeynes@2
  1270
                    CHECKSLOTILLEGAL()
nkeynes@2
  1271
                    sh4r.in_delay_slot = 1;
nkeynes@116
  1272
                    MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
nkeynes@229
  1273
                    RAISE( EXC_TRAP, EXV_TRAP, 2 );
nkeynes@1
  1274
                    break;
nkeynes@1
  1275
                case 4: /* MOV.B   [GBR + disp8], R0 */
nkeynes@1
  1276
                    R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
nkeynes@1
  1277
                    break;
nkeynes@1
  1278
                case 5: /* MOV.W   [GBR + disp8*2], R0 */
nkeynes@208
  1279
		    tmp = sh4r.gbr + (DISP8(ir)<<1);
nkeynes@208
  1280
		    CHECKRALIGN16( tmp );
nkeynes@208
  1281
                    R0 = MEM_READ_WORD( tmp );
nkeynes@1
  1282
                    break;
nkeynes@1
  1283
                case 6: /* MOV.L   [GBR + disp8*4], R0 */
nkeynes@208
  1284
		    tmp = sh4r.gbr + (DISP8(ir)<<2);
nkeynes@208
  1285
		    CHECKRALIGN32( tmp );
nkeynes@208
  1286
                    R0 = MEM_READ_LONG( tmp );
nkeynes@1
  1287
                    break;
nkeynes@1
  1288
                case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
nkeynes@232
  1289
		    CHECKSLOTILLEGAL();
nkeynes@1
  1290
                    R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@1
  1291
                    break;
nkeynes@1
  1292
                case 8: /* TST     imm8, R0 */
nkeynes@1
  1293
                    sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
nkeynes@1
  1294
                    break;
nkeynes@1
  1295
                case 9: /* AND     imm8, R0 */
nkeynes@1
  1296
                    R0 &= UIMM8(ir);
nkeynes@1
  1297
                    break;
nkeynes@1
  1298
                case 10:/* XOR     imm8, R0 */
nkeynes@1
  1299
                    R0 ^= UIMM8(ir);
nkeynes@1
  1300
                    break;
nkeynes@1
  1301
                case 11:/* OR      imm8, R0 */
nkeynes@1
  1302
                    R0 |= UIMM8(ir);
nkeynes@1
  1303
                    break;
nkeynes@208
  1304
                case 12:/* TST.B   imm8, [R0+GBR] */		    
nkeynes@1
  1305
                    sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
nkeynes@1
  1306
                    break;
nkeynes@1
  1307
                case 13:/* AND.B   imm8, [R0+GBR] */
nkeynes@1
  1308
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1309
                                    UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1310
                    break;
nkeynes@1
  1311
                case 14:/* XOR.B   imm8, [R0+GBR] */
nkeynes@1
  1312
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1313
                                    UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1314
                    break;
nkeynes@1
  1315
                case 15:/* OR.B    imm8, [R0+GBR] */
nkeynes@1
  1316
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1317
                                    UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1318
                    break;
nkeynes@1
  1319
            }
nkeynes@1
  1320
            break;
nkeynes@1
  1321
        case 13:/* 1101nnnndddddddd */
nkeynes@1
  1322
            /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
nkeynes@232
  1323
	    CHECKSLOTILLEGAL();
nkeynes@208
  1324
	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@208
  1325
            RN(ir) = MEM_READ_LONG( tmp );
nkeynes@1
  1326
            break;
nkeynes@1
  1327
        case 14:/* 1110nnnniiiiiiii */
nkeynes@1
  1328
            /* MOV     imm8, Rn */
nkeynes@1
  1329
            RN(ir) = IMM8(ir);
nkeynes@1
  1330
            break;
nkeynes@1
  1331
        case 15:/* 1111xxxxxxxxxxxx */
nkeynes@1
  1332
            CHECKFPUEN();
nkeynes@84
  1333
	    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@84
  1334
		switch( ir&0x000F ) {
nkeynes@84
  1335
                case 0: /* FADD    FRm, FRn */
nkeynes@84
  1336
                    DRN(ir) += DRM(ir);
nkeynes@84
  1337
                    break;
nkeynes@84
  1338
                case 1: /* FSUB    FRm, FRn */
nkeynes@84
  1339
                    DRN(ir) -= DRM(ir);
nkeynes@84
  1340
                    break;
nkeynes@84
  1341
                case 2: /* FMUL    FRm, FRn */
nkeynes@84
  1342
                    DRN(ir) = DRN(ir) * DRM(ir);
nkeynes@84
  1343
                    break;
nkeynes@84
  1344
                case 3: /* FDIV    FRm, FRn */
nkeynes@84
  1345
                    DRN(ir) = DRN(ir) / DRM(ir);
nkeynes@84
  1346
                    break;
nkeynes@84
  1347
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@84
  1348
                    sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
nkeynes@84
  1349
                    break;
nkeynes@84
  1350
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@84
  1351
                    sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
nkeynes@84
  1352
                    break;
nkeynes@84
  1353
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@84
  1354
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@84
  1355
                    break;
nkeynes@84
  1356
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@84
  1357
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@84
  1358
                    break;
nkeynes@84
  1359
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@84
  1360
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1361
                    break;
nkeynes@84
  1362
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@84
  1363
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1364
                    RM(ir) += FP_WIDTH;
nkeynes@84
  1365
                    break;
nkeynes@84
  1366
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@84
  1367
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1368
                    break;
nkeynes@84
  1369
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@84
  1370
                    RN(ir) -= FP_WIDTH;
nkeynes@84
  1371
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1372
                    break;
nkeynes@84
  1373
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1374
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1375
			DRN(ir) = DRM(ir);
nkeynes@84
  1376
		    else
nkeynes@84
  1377
			FRN(ir) = FRM(ir);
nkeynes@84
  1378
                    break;
nkeynes@84
  1379
                case 13:
nkeynes@84
  1380
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1381
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1382
			FRN(ir) = FPULf;
nkeynes@84
  1383
			break;
nkeynes@84
  1384
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1385
			FPULf = FRN(ir);
nkeynes@84
  1386
			break;
nkeynes@84
  1387
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1388
			DRN(ir) = (float)FPULi;
nkeynes@84
  1389
			break;
nkeynes@84
  1390
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@123
  1391
			dtmp = DRN(ir);
nkeynes@123
  1392
			if( dtmp >= MAX_INTF )
nkeynes@123
  1393
			    FPULi = MAX_INT;
nkeynes@123
  1394
			else if( dtmp <= MIN_INTF )
nkeynes@123
  1395
			    FPULi = MIN_INT;
nkeynes@123
  1396
			else 
nkeynes@123
  1397
			    FPULi = (int32_t)dtmp;
nkeynes@84
  1398
			break;
nkeynes@84
  1399
		    case 4: /* FNEG    FRn */
nkeynes@84
  1400
			DRN(ir) = -DRN(ir);
nkeynes@84
  1401
			break;
nkeynes@84
  1402
		    case 5: /* FABS    FRn */
nkeynes@84
  1403
			DRN(ir) = fabs(DRN(ir));
nkeynes@84
  1404
			break;
nkeynes@84
  1405
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1406
			DRN(ir) = sqrt(DRN(ir));
nkeynes@84
  1407
			break;
nkeynes@84
  1408
		    case 7: /* FSRRA FRn */
nkeynes@181
  1409
			/* NO-OP when PR=1 */
nkeynes@84
  1410
			break;
nkeynes@84
  1411
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1412
			DRN(ir) = 0.0;
nkeynes@84
  1413
			break;
nkeynes@84
  1414
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1415
			DRN(ir) = 1.0;
nkeynes@84
  1416
			break;
nkeynes@84
  1417
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@181
  1418
			if( ! IS_FPU_DOUBLESIZE() )
nkeynes@181
  1419
			    DRN(ir) = (double)FPULf;
nkeynes@84
  1420
			break;
nkeynes@84
  1421
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@181
  1422
			if( ! IS_FPU_DOUBLESIZE() )
nkeynes@181
  1423
			    FPULf = (float)DRN(ir);
nkeynes@84
  1424
			break;
nkeynes@84
  1425
		    case 14:/* FIPR    FVm, FVn */
nkeynes@181
  1426
			/* NO-OP when PR=1 */
nkeynes@84
  1427
			break;
nkeynes@84
  1428
		    case 15:
nkeynes@84
  1429
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@181
  1430
			    /* NO-OP when PR=1 */
nkeynes@84
  1431
			    break;
nkeynes@84
  1432
			}
nkeynes@181
  1433
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
nkeynes@181
  1434
			    /* NO-OP when PR=1 */
nkeynes@84
  1435
			    break;
nkeynes@84
  1436
			}
nkeynes@84
  1437
			else if( ir == 0xFBFD ) {
nkeynes@84
  1438
			    /* FRCHG   */
nkeynes@84
  1439
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1440
			    break;
nkeynes@84
  1441
			}
nkeynes@84
  1442
			else if( ir == 0xF3FD ) {
nkeynes@84
  1443
			    /* FSCHG   */
nkeynes@84
  1444
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1445
			    break;
nkeynes@84
  1446
			}
nkeynes@84
  1447
		    default: UNDEF(ir);
nkeynes@84
  1448
                    }
nkeynes@84
  1449
                    break;
nkeynes@84
  1450
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@84
  1451
                    DRN(ir) += DRM(ir)*DR0;
nkeynes@84
  1452
                    break;
nkeynes@84
  1453
                default: UNDEF(ir);
nkeynes@84
  1454
		}
nkeynes@122
  1455
	    } else { /* Single precision */
nkeynes@84
  1456
		switch( ir&0x000F ) {
nkeynes@1
  1457
                case 0: /* FADD    FRm, FRn */
nkeynes@1
  1458
                    FRN(ir) += FRM(ir);
nkeynes@1
  1459
                    break;
nkeynes@1
  1460
                case 1: /* FSUB    FRm, FRn */
nkeynes@1
  1461
                    FRN(ir) -= FRM(ir);
nkeynes@1
  1462
                    break;
nkeynes@1
  1463
                case 2: /* FMUL    FRm, FRn */
nkeynes@1
  1464
                    FRN(ir) = FRN(ir) * FRM(ir);
nkeynes@1
  1465
                    break;
nkeynes@1
  1466
                case 3: /* FDIV    FRm, FRn */
nkeynes@1
  1467
                    FRN(ir) = FRN(ir) / FRM(ir);
nkeynes@1
  1468
                    break;
nkeynes@1
  1469
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@1
  1470
                    sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
nkeynes@1
  1471
                    break;
nkeynes@1
  1472
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@1
  1473
                    sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
nkeynes@1
  1474
                    break;
nkeynes@1
  1475
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@1
  1476
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@1
  1477
                    break;
nkeynes@1
  1478
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@1
  1479
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@1
  1480
                    break;
nkeynes@1
  1481
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@1
  1482
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1483
                    break;
nkeynes@1
  1484
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@1
  1485
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1486
                    RM(ir) += FP_WIDTH;
nkeynes@1
  1487
                    break;
nkeynes@1
  1488
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@1
  1489
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1490
                    break;
nkeynes@1
  1491
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@1
  1492
                    RN(ir) -= FP_WIDTH;
nkeynes@1
  1493
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1494
                    break;
nkeynes@1
  1495
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1496
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1497
			DRN(ir) = DRM(ir);
nkeynes@84
  1498
		    else
nkeynes@84
  1499
			FRN(ir) = FRM(ir);
nkeynes@1
  1500
                    break;
nkeynes@1
  1501
                case 13:
nkeynes@1
  1502
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1503
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1504
			FRN(ir) = FPULf;
nkeynes@84
  1505
			break;
nkeynes@84
  1506
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1507
			FPULf = FRN(ir);
nkeynes@84
  1508
			break;
nkeynes@84
  1509
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1510
			FRN(ir) = (float)FPULi;
nkeynes@84
  1511
			break;
nkeynes@84
  1512
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@123
  1513
			ftmp = FRN(ir);
nkeynes@123
  1514
			if( ftmp >= MAX_INTF )
nkeynes@123
  1515
			    FPULi = MAX_INT;
nkeynes@123
  1516
			else if( ftmp <= MIN_INTF )
nkeynes@123
  1517
			    FPULi = MIN_INT;
nkeynes@123
  1518
			else
nkeynes@123
  1519
			    FPULi = (int32_t)ftmp;
nkeynes@84
  1520
			break;
nkeynes@84
  1521
		    case 4: /* FNEG    FRn */
nkeynes@84
  1522
			FRN(ir) = -FRN(ir);
nkeynes@84
  1523
			break;
nkeynes@84
  1524
		    case 5: /* FABS    FRn */
nkeynes@84
  1525
			FRN(ir) = fabsf(FRN(ir));
nkeynes@84
  1526
			break;
nkeynes@84
  1527
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1528
			FRN(ir) = sqrtf(FRN(ir));
nkeynes@84
  1529
			break;
nkeynes@84
  1530
		    case 7: /* FSRRA FRn */
nkeynes@84
  1531
			FRN(ir) = 1.0/sqrtf(FRN(ir));
nkeynes@84
  1532
			break;
nkeynes@84
  1533
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1534
			FRN(ir) = 0.0;
nkeynes@84
  1535
			break;
nkeynes@84
  1536
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1537
			FRN(ir) = 1.0;
nkeynes@84
  1538
			break;
nkeynes@84
  1539
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@84
  1540
			break;
nkeynes@84
  1541
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@84
  1542
			break;
nkeynes@84
  1543
		    case 14:/* FIPR    FVm, FVn */
nkeynes@2
  1544
                            /* FIXME: This is not going to be entirely accurate
nkeynes@2
  1545
                             * as the SH4 instruction is less precise. Also
nkeynes@2
  1546
                             * need to check for 0s and infinities.
nkeynes@2
  1547
                             */
nkeynes@2
  1548
                        {
nkeynes@2
  1549
                            int tmp2 = FVN(ir);
nkeynes@2
  1550
                            tmp = FVM(ir);
nkeynes@84
  1551
                            FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@84
  1552
                                FR(tmp+1)*FR(tmp2+1) +
nkeynes@84
  1553
                                FR(tmp+2)*FR(tmp2+2) +
nkeynes@84
  1554
                                FR(tmp+3)*FR(tmp2+3);
nkeynes@1
  1555
                            break;
nkeynes@2
  1556
                        }
nkeynes@84
  1557
		    case 15:
nkeynes@84
  1558
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@84
  1559
			    tmp = FVN(ir);
nkeynes@84
  1560
			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
nkeynes@84
  1561
			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
nkeynes@84
  1562
				XF(8)*fv[2] + XF(12)*fv[3];
nkeynes@84
  1563
			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
nkeynes@84
  1564
				XF(9)*fv[2] + XF(13)*fv[3];
nkeynes@84
  1565
			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
nkeynes@84
  1566
				XF(10)*fv[2] + XF(14)*fv[3];
nkeynes@84
  1567
			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
nkeynes@84
  1568
				XF(11)*fv[2] + XF(15)*fv[3];
nkeynes@84
  1569
			    break;
nkeynes@84
  1570
			}
nkeynes@84
  1571
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
nkeynes@84
  1572
			    float angle = (((float)(short)(FPULi>>16)) +
nkeynes@122
  1573
					   (((float)(FPULi&0xFFFF))/65536.0)) *
nkeynes@84
  1574
				2 * M_PI;
nkeynes@84
  1575
			    int reg = FRNn(ir);
nkeynes@84
  1576
			    FR(reg) = sinf(angle);
nkeynes@84
  1577
			    FR(reg+1) = cosf(angle);
nkeynes@84
  1578
			    break;
nkeynes@84
  1579
			}
nkeynes@84
  1580
			else if( ir == 0xFBFD ) {
nkeynes@84
  1581
			    /* FRCHG   */
nkeynes@84
  1582
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1583
			    break;
nkeynes@84
  1584
			}
nkeynes@84
  1585
			else if( ir == 0xF3FD ) {
nkeynes@84
  1586
			    /* FSCHG   */
nkeynes@84
  1587
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1588
			    break;
nkeynes@84
  1589
			}
nkeynes@84
  1590
		    default: UNDEF(ir);
nkeynes@1
  1591
                    }
nkeynes@1
  1592
                    break;
nkeynes@1
  1593
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@1
  1594
                    FRN(ir) += FRM(ir)*FR0;
nkeynes@1
  1595
                    break;
nkeynes@1
  1596
                default: UNDEF(ir);
nkeynes@84
  1597
		}
nkeynes@84
  1598
	    }
nkeynes@84
  1599
	    break;
nkeynes@1
  1600
    }
nkeynes@1
  1601
    sh4r.pc = sh4r.new_pc;
nkeynes@1
  1602
    sh4r.new_pc += 2;
nkeynes@2
  1603
    sh4r.in_delay_slot = 0;
nkeynes@1
  1604
}
.