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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 19:9da7a8e38f9d
prev16:f383e7640da4
next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 07:38:12 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Implement 95% of the SCIF serial interface
Implement basic load_bin_file function to try to load demos directly
Update TMU to run all 3 timers, start on general timing
file annotate diff log raw
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#include "dream.h"
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#include "video.h"
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#include "mem.h"
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#include "asic.h"
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#include "modules.h"
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#include "pvr2.h"
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#define MMIO_IMPL
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#include "pvr2.h"
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char *video_base;
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void pvr2_init( void );
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, NULL,
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					NULL, NULL };
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void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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}
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uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
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int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
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char *frame_start; /* current video start address (in real memory) */
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/*
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_next_frame( void )
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{
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    if( bChanged ) {
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        int dispsize = MMIO_READ( PVR2, DISPSIZE );
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        int dispmode = MMIO_READ( PVR2, DISPMODE );
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        int vidcfg = MMIO_READ( PVR2, VIDCFG );
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        vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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        vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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        vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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        vid_col = (dispmode & DISPMODE_COL);
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        frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
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        interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
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        bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
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        vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
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        vid_hres = vid_ppl;
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        vid_vres = vid_lpf;
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        if( interlaced ) vid_vres <<= 1;
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        switch( vid_col ) {
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            case MODE_RGB15:
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            case MODE_RGB16: vid_hres <<= 1; break;
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            case MODE_RGB24: vid_hres *= 3; break;
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            case MODE_RGB32: vid_hres <<= 2; break;
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        }
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        vid_hres >>= 2;
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        video_update_size( vid_hres, vid_vres, vid_col );
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        bChanged = 0;
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    }
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    if( bEnabled ) {
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        /* Assume bit depths match for now... */
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        memcpy( video_data, frame_start, vid_size );
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    } else {
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        memset( video_data, 0, vid_size );
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    }
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    video_update_frame();
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    asic_event( EVENT_SCANLINE1 );
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    asic_event( EVENT_SCANLINE2 );
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    asic_event( EVENT_RETRACE );
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}
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        /* I don't want to hear about these */
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        return;
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    }
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    INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
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          MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
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    switch(reg) {
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        case DISPSIZE: bChanged = 1;
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        case DISPMODE: bChanged = 1;
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        case DISPADDR1: bChanged = 1;
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        case DISPADDR2: bChanged = 1;
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        case VIDCFG: bChanged = 1;
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            break;
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    }
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    MMIO_WRITE( PVR2, reg, val );
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}
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MMIO_REGION_READ_FN( PVR2, reg )
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{
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    switch( reg ) {
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        case BEAMPOS:
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            return sh4r.icount&0x20 ? 0x2000 : 1;
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        default:
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            return MMIO_READ( PVR2, reg );
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    }
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}
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void pvr2_set_base_address( uint32_t base ) 
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{
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    mmio_region_PVR2_write( DISPADDR1, base );
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}
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