filename | src/pvr2/pvr2.c |
changeset | 19:9da7a8e38f9d |
prev | 16:f383e7640da4 |
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author | nkeynes |
date | Thu Dec 22 07:38:12 2005 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Implement 95% of the SCIF serial interface Implement basic load_bin_file function to try to load demos directly Update TMU to run all 3 timers, start on general timing |
file | annotate | diff | log | raw |
nkeynes@1 | 1 | #include "dream.h" |
nkeynes@1 | 2 | #include "video.h" |
nkeynes@1 | 3 | #include "mem.h" |
nkeynes@1 | 4 | #include "asic.h" |
nkeynes@15 | 5 | #include "modules.h" |
nkeynes@1 | 6 | #include "pvr2.h" |
nkeynes@1 | 7 | #define MMIO_IMPL |
nkeynes@1 | 8 | #include "pvr2.h" |
nkeynes@1 | 9 | |
nkeynes@1 | 10 | char *video_base; |
nkeynes@1 | 11 | |
nkeynes@15 | 12 | void pvr2_init( void ); |
nkeynes@15 | 13 | |
nkeynes@15 | 14 | struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, NULL, |
nkeynes@15 | 15 | NULL, NULL }; |
nkeynes@15 | 16 | |
nkeynes@1 | 17 | void pvr2_init( void ) |
nkeynes@1 | 18 | { |
nkeynes@1 | 19 | register_io_region( &mmio_region_PVR2 ); |
nkeynes@1 | 20 | video_base = mem_get_region_by_name( MEM_REGION_VIDEO ); |
nkeynes@1 | 21 | } |
nkeynes@1 | 22 | |
nkeynes@1 | 23 | uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col; |
nkeynes@1 | 24 | int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0; |
nkeynes@1 | 25 | char *frame_start; /* current video start address (in real memory) */ |
nkeynes@1 | 26 | |
nkeynes@1 | 27 | /* |
nkeynes@1 | 28 | * Display the next frame, copying the current contents of video ram to |
nkeynes@1 | 29 | * the window. If the video configuration has changed, first recompute the |
nkeynes@1 | 30 | * new frame size/depth. |
nkeynes@1 | 31 | */ |
nkeynes@1 | 32 | void pvr2_next_frame( void ) |
nkeynes@1 | 33 | { |
nkeynes@1 | 34 | if( bChanged ) { |
nkeynes@1 | 35 | int dispsize = MMIO_READ( PVR2, DISPSIZE ); |
nkeynes@1 | 36 | int dispmode = MMIO_READ( PVR2, DISPMODE ); |
nkeynes@1 | 37 | int vidcfg = MMIO_READ( PVR2, VIDCFG ); |
nkeynes@1 | 38 | vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1; |
nkeynes@1 | 39 | vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1; |
nkeynes@1 | 40 | vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1; |
nkeynes@1 | 41 | vid_col = (dispmode & DISPMODE_COL); |
nkeynes@1 | 42 | frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 ); |
nkeynes@1 | 43 | interlaced = (vidcfg & VIDCFG_I ? 1 : 0); |
nkeynes@1 | 44 | bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0; |
nkeynes@1 | 45 | vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2); |
nkeynes@1 | 46 | vid_hres = vid_ppl; |
nkeynes@1 | 47 | vid_vres = vid_lpf; |
nkeynes@1 | 48 | if( interlaced ) vid_vres <<= 1; |
nkeynes@1 | 49 | switch( vid_col ) { |
nkeynes@1 | 50 | case MODE_RGB15: |
nkeynes@1 | 51 | case MODE_RGB16: vid_hres <<= 1; break; |
nkeynes@1 | 52 | case MODE_RGB24: vid_hres *= 3; break; |
nkeynes@1 | 53 | case MODE_RGB32: vid_hres <<= 2; break; |
nkeynes@1 | 54 | } |
nkeynes@1 | 55 | vid_hres >>= 2; |
nkeynes@1 | 56 | video_update_size( vid_hres, vid_vres, vid_col ); |
nkeynes@1 | 57 | bChanged = 0; |
nkeynes@1 | 58 | } |
nkeynes@1 | 59 | if( bEnabled ) { |
nkeynes@1 | 60 | /* Assume bit depths match for now... */ |
nkeynes@1 | 61 | memcpy( video_data, frame_start, vid_size ); |
nkeynes@1 | 62 | } else { |
nkeynes@1 | 63 | memset( video_data, 0, vid_size ); |
nkeynes@1 | 64 | } |
nkeynes@1 | 65 | video_update_frame(); |
nkeynes@1 | 66 | asic_event( EVENT_SCANLINE1 ); |
nkeynes@1 | 67 | asic_event( EVENT_SCANLINE2 ); |
nkeynes@1 | 68 | asic_event( EVENT_RETRACE ); |
nkeynes@1 | 69 | } |
nkeynes@1 | 70 | |
nkeynes@1 | 71 | void mmio_region_PVR2_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 72 | { |
nkeynes@1 | 73 | if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */ |
nkeynes@1 | 74 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@1 | 75 | /* I don't want to hear about these */ |
nkeynes@1 | 76 | return; |
nkeynes@1 | 77 | } |
nkeynes@1 | 78 | |
nkeynes@1 | 79 | INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, |
nkeynes@1 | 80 | MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) ); |
nkeynes@1 | 81 | |
nkeynes@1 | 82 | switch(reg) { |
nkeynes@1 | 83 | case DISPSIZE: bChanged = 1; |
nkeynes@1 | 84 | case DISPMODE: bChanged = 1; |
nkeynes@1 | 85 | case DISPADDR1: bChanged = 1; |
nkeynes@1 | 86 | case DISPADDR2: bChanged = 1; |
nkeynes@1 | 87 | case VIDCFG: bChanged = 1; |
nkeynes@1 | 88 | break; |
nkeynes@1 | 89 | |
nkeynes@1 | 90 | } |
nkeynes@1 | 91 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@1 | 92 | } |
nkeynes@1 | 93 | |
nkeynes@1 | 94 | MMIO_REGION_READ_FN( PVR2, reg ) |
nkeynes@1 | 95 | { |
nkeynes@1 | 96 | switch( reg ) { |
nkeynes@1 | 97 | case BEAMPOS: |
nkeynes@2 | 98 | return sh4r.icount&0x20 ? 0x2000 : 1; |
nkeynes@1 | 99 | default: |
nkeynes@1 | 100 | return MMIO_READ( PVR2, reg ); |
nkeynes@1 | 101 | } |
nkeynes@1 | 102 | } |
nkeynes@19 | 103 | |
nkeynes@19 | 104 | void pvr2_set_base_address( uint32_t base ) |
nkeynes@19 | 105 | { |
nkeynes@19 | 106 | mmio_region_PVR2_write( DISPADDR1, base ); |
nkeynes@19 | 107 | } |
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