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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 908:a00debcf2600
prev905:4c17ebd9ef5e
next911:2f6ba75b84d1
author nkeynes
date Thu Oct 30 05:50:21 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix x86-64 build (typos et al)
Remove Push/pop ebx - don't really need it and saves adding more target-specific asm
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
nkeynes@586
   310
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   311
nkeynes@590
   312
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   313
nkeynes@539
   314
/****** Import appropriate calling conventions ******/
nkeynes@675
   315
#if SIZEOF_VOID_P == 8
nkeynes@539
   316
#include "sh4/ia64abi.h"
nkeynes@675
   317
#else /* 32-bit system */
nkeynes@539
   318
#ifdef APPLE_BUILD
nkeynes@539
   319
#include "sh4/ia32mac.h"
nkeynes@539
   320
#else
nkeynes@539
   321
#include "sh4/ia32abi.h"
nkeynes@539
   322
#endif
nkeynes@539
   323
#endif
nkeynes@539
   324
nkeynes@901
   325
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   326
{
nkeynes@901
   327
	enter_block();
nkeynes@901
   328
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   329
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   330
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   331
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   332
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   333
    sh4_x86.block_start_pc = pc;
nkeynes@901
   334
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   336
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   337
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   338
}
nkeynes@901
   339
nkeynes@901
   340
nkeynes@593
   341
uint32_t sh4_translate_end_block_size()
nkeynes@593
   342
{
nkeynes@596
   343
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   344
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   345
    } else {
nkeynes@901
   346
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   347
    }
nkeynes@593
   348
}
nkeynes@593
   349
nkeynes@593
   350
nkeynes@590
   351
/**
nkeynes@590
   352
 * Embed a breakpoint into the generated code
nkeynes@590
   353
 */
nkeynes@586
   354
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   355
{
nkeynes@591
   356
    load_imm32( R_EAX, pc );
nkeynes@591
   357
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   359
}
nkeynes@590
   360
nkeynes@601
   361
nkeynes@601
   362
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   363
nkeynes@590
   364
/**
nkeynes@590
   365
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   366
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   367
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   368
 *
nkeynes@601
   369
 * Performs:
nkeynes@601
   370
 *   Set PC = endpc
nkeynes@601
   371
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   372
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   373
 *   Call sh4_execute_instruction
nkeynes@601
   374
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   375
 */
nkeynes@601
   376
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   377
{
nkeynes@590
   378
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   379
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   380
    
nkeynes@601
   381
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   382
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   383
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   384
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   385
nkeynes@590
   386
    call_func0( sh4_execute_instruction );    
nkeynes@601
   387
    load_spreg( R_EAX, R_PC );
nkeynes@590
   388
    if( sh4_x86.tlb_on ) {
nkeynes@590
   389
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   390
    } else {
nkeynes@590
   391
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   392
    }
nkeynes@601
   393
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   394
    POP_r32(R_EBP);
nkeynes@590
   395
    RET();
nkeynes@590
   396
} 
nkeynes@539
   397
nkeynes@359
   398
/**
nkeynes@359
   399
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   400
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   401
 * 
nkeynes@586
   402
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   403
 *
nkeynes@359
   404
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   405
 * (eg a branch or 
nkeynes@359
   406
 */
nkeynes@590
   407
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   408
{
nkeynes@388
   409
    uint32_t ir;
nkeynes@586
   410
    /* Read instruction from icache */
nkeynes@586
   411
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   412
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   413
    
nkeynes@586
   414
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   415
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   416
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   417
	 * almost certainly in a delay slot.
nkeynes@586
   418
	 *
nkeynes@586
   419
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   420
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   421
	 * small repairs to cope with the different environment).
nkeynes@586
   422
	 */
nkeynes@586
   423
nkeynes@586
   424
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   425
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   426
    }
nkeynes@359
   427
%%
nkeynes@359
   428
/* ALU operations */
nkeynes@359
   429
ADD Rm, Rn {:
nkeynes@671
   430
    COUNT_INST(I_ADD);
nkeynes@359
   431
    load_reg( R_EAX, Rm );
nkeynes@359
   432
    load_reg( R_ECX, Rn );
nkeynes@359
   433
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   434
    store_reg( R_ECX, Rn );
nkeynes@417
   435
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   436
:}
nkeynes@359
   437
ADD #imm, Rn {:  
nkeynes@671
   438
    COUNT_INST(I_ADDI);
nkeynes@359
   439
    load_reg( R_EAX, Rn );
nkeynes@359
   440
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   441
    store_reg( R_EAX, Rn );
nkeynes@417
   442
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   443
:}
nkeynes@359
   444
ADDC Rm, Rn {:
nkeynes@671
   445
    COUNT_INST(I_ADDC);
nkeynes@417
   446
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   447
	LDC_t();
nkeynes@417
   448
    }
nkeynes@359
   449
    load_reg( R_EAX, Rm );
nkeynes@359
   450
    load_reg( R_ECX, Rn );
nkeynes@359
   451
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   452
    store_reg( R_ECX, Rn );
nkeynes@359
   453
    SETC_t();
nkeynes@417
   454
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   455
:}
nkeynes@359
   456
ADDV Rm, Rn {:
nkeynes@671
   457
    COUNT_INST(I_ADDV);
nkeynes@359
   458
    load_reg( R_EAX, Rm );
nkeynes@359
   459
    load_reg( R_ECX, Rn );
nkeynes@359
   460
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   461
    store_reg( R_ECX, Rn );
nkeynes@359
   462
    SETO_t();
nkeynes@417
   463
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   464
:}
nkeynes@359
   465
AND Rm, Rn {:
nkeynes@671
   466
    COUNT_INST(I_AND);
nkeynes@359
   467
    load_reg( R_EAX, Rm );
nkeynes@359
   468
    load_reg( R_ECX, Rn );
nkeynes@359
   469
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   470
    store_reg( R_ECX, Rn );
nkeynes@417
   471
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   472
:}
nkeynes@359
   473
AND #imm, R0 {:  
nkeynes@671
   474
    COUNT_INST(I_ANDI);
nkeynes@359
   475
    load_reg( R_EAX, 0 );
nkeynes@359
   476
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   477
    store_reg( R_EAX, 0 );
nkeynes@417
   478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   479
:}
nkeynes@359
   480
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   481
    COUNT_INST(I_ANDB);
nkeynes@359
   482
    load_reg( R_EAX, 0 );
nkeynes@359
   483
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   484
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   485
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   486
    PUSH_realigned_r32(R_EAX);
nkeynes@905
   487
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
   488
    POP_realigned_r32(R_EAX);
nkeynes@905
   489
    AND_imm32_r32(imm, R_EDX );
nkeynes@905
   490
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   491
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   492
:}
nkeynes@359
   493
CMP/EQ Rm, Rn {:  
nkeynes@671
   494
    COUNT_INST(I_CMPEQ);
nkeynes@359
   495
    load_reg( R_EAX, Rm );
nkeynes@359
   496
    load_reg( R_ECX, Rn );
nkeynes@359
   497
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   498
    SETE_t();
nkeynes@417
   499
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   500
:}
nkeynes@359
   501
CMP/EQ #imm, R0 {:  
nkeynes@671
   502
    COUNT_INST(I_CMPEQI);
nkeynes@359
   503
    load_reg( R_EAX, 0 );
nkeynes@359
   504
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   505
    SETE_t();
nkeynes@417
   506
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   507
:}
nkeynes@359
   508
CMP/GE Rm, Rn {:  
nkeynes@671
   509
    COUNT_INST(I_CMPGE);
nkeynes@359
   510
    load_reg( R_EAX, Rm );
nkeynes@359
   511
    load_reg( R_ECX, Rn );
nkeynes@359
   512
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   513
    SETGE_t();
nkeynes@417
   514
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   515
:}
nkeynes@359
   516
CMP/GT Rm, Rn {: 
nkeynes@671
   517
    COUNT_INST(I_CMPGT);
nkeynes@359
   518
    load_reg( R_EAX, Rm );
nkeynes@359
   519
    load_reg( R_ECX, Rn );
nkeynes@359
   520
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   521
    SETG_t();
nkeynes@417
   522
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   523
:}
nkeynes@359
   524
CMP/HI Rm, Rn {:  
nkeynes@671
   525
    COUNT_INST(I_CMPHI);
nkeynes@359
   526
    load_reg( R_EAX, Rm );
nkeynes@359
   527
    load_reg( R_ECX, Rn );
nkeynes@359
   528
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   529
    SETA_t();
nkeynes@417
   530
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   531
:}
nkeynes@359
   532
CMP/HS Rm, Rn {: 
nkeynes@671
   533
    COUNT_INST(I_CMPHS);
nkeynes@359
   534
    load_reg( R_EAX, Rm );
nkeynes@359
   535
    load_reg( R_ECX, Rn );
nkeynes@359
   536
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   537
    SETAE_t();
nkeynes@417
   538
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   539
 :}
nkeynes@359
   540
CMP/PL Rn {: 
nkeynes@671
   541
    COUNT_INST(I_CMPPL);
nkeynes@359
   542
    load_reg( R_EAX, Rn );
nkeynes@359
   543
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   544
    SETG_t();
nkeynes@417
   545
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   546
:}
nkeynes@359
   547
CMP/PZ Rn {:  
nkeynes@671
   548
    COUNT_INST(I_CMPPZ);
nkeynes@359
   549
    load_reg( R_EAX, Rn );
nkeynes@359
   550
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   551
    SETGE_t();
nkeynes@417
   552
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   553
:}
nkeynes@361
   554
CMP/STR Rm, Rn {:  
nkeynes@671
   555
    COUNT_INST(I_CMPSTR);
nkeynes@368
   556
    load_reg( R_EAX, Rm );
nkeynes@368
   557
    load_reg( R_ECX, Rn );
nkeynes@368
   558
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   559
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   560
    JE_rel8(target1);
nkeynes@669
   561
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   562
    JE_rel8(target2);
nkeynes@669
   563
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   564
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   565
    JE_rel8(target3);
nkeynes@669
   566
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   567
    JMP_TARGET(target1);
nkeynes@380
   568
    JMP_TARGET(target2);
nkeynes@380
   569
    JMP_TARGET(target3);
nkeynes@368
   570
    SETE_t();
nkeynes@417
   571
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   572
:}
nkeynes@361
   573
DIV0S Rm, Rn {:
nkeynes@671
   574
    COUNT_INST(I_DIV0S);
nkeynes@361
   575
    load_reg( R_EAX, Rm );
nkeynes@386
   576
    load_reg( R_ECX, Rn );
nkeynes@361
   577
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   578
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   579
    store_spreg( R_EAX, R_M );
nkeynes@361
   580
    store_spreg( R_ECX, R_Q );
nkeynes@361
   581
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   582
    SETNE_t();
nkeynes@417
   583
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   584
:}
nkeynes@361
   585
DIV0U {:  
nkeynes@671
   586
    COUNT_INST(I_DIV0U);
nkeynes@361
   587
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   588
    store_spreg( R_EAX, R_Q );
nkeynes@361
   589
    store_spreg( R_EAX, R_M );
nkeynes@361
   590
    store_spreg( R_EAX, R_T );
nkeynes@417
   591
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   592
:}
nkeynes@386
   593
DIV1 Rm, Rn {:
nkeynes@671
   594
    COUNT_INST(I_DIV1);
nkeynes@386
   595
    load_spreg( R_ECX, R_M );
nkeynes@386
   596
    load_reg( R_EAX, Rn );
nkeynes@417
   597
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   598
	LDC_t();
nkeynes@417
   599
    }
nkeynes@386
   600
    RCL1_r32( R_EAX );
nkeynes@386
   601
    SETC_r8( R_DL ); // Q'
nkeynes@386
   602
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   603
    JE_rel8(mqequal);
nkeynes@386
   604
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   605
    JMP_rel8(end);
nkeynes@380
   606
    JMP_TARGET(mqequal);
nkeynes@386
   607
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   608
    JMP_TARGET(end);
nkeynes@386
   609
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   610
    SETC_r8(R_AL); // tmp1
nkeynes@386
   611
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   612
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   613
    store_spreg( R_ECX, R_Q );
nkeynes@386
   614
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   615
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   616
    store_spreg( R_EAX, R_T );
nkeynes@417
   617
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   618
:}
nkeynes@361
   619
DMULS.L Rm, Rn {:  
nkeynes@671
   620
    COUNT_INST(I_DMULS);
nkeynes@361
   621
    load_reg( R_EAX, Rm );
nkeynes@361
   622
    load_reg( R_ECX, Rn );
nkeynes@361
   623
    IMUL_r32(R_ECX);
nkeynes@361
   624
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   625
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   627
:}
nkeynes@361
   628
DMULU.L Rm, Rn {:  
nkeynes@671
   629
    COUNT_INST(I_DMULU);
nkeynes@361
   630
    load_reg( R_EAX, Rm );
nkeynes@361
   631
    load_reg( R_ECX, Rn );
nkeynes@361
   632
    MUL_r32(R_ECX);
nkeynes@361
   633
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   634
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   635
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   636
:}
nkeynes@359
   637
DT Rn {:  
nkeynes@671
   638
    COUNT_INST(I_DT);
nkeynes@359
   639
    load_reg( R_EAX, Rn );
nkeynes@382
   640
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   641
    store_reg( R_EAX, Rn );
nkeynes@359
   642
    SETE_t();
nkeynes@417
   643
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   644
:}
nkeynes@359
   645
EXTS.B Rm, Rn {:  
nkeynes@671
   646
    COUNT_INST(I_EXTSB);
nkeynes@359
   647
    load_reg( R_EAX, Rm );
nkeynes@359
   648
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   649
    store_reg( R_EAX, Rn );
nkeynes@359
   650
:}
nkeynes@361
   651
EXTS.W Rm, Rn {:  
nkeynes@671
   652
    COUNT_INST(I_EXTSW);
nkeynes@361
   653
    load_reg( R_EAX, Rm );
nkeynes@361
   654
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   655
    store_reg( R_EAX, Rn );
nkeynes@361
   656
:}
nkeynes@361
   657
EXTU.B Rm, Rn {:  
nkeynes@671
   658
    COUNT_INST(I_EXTUB);
nkeynes@361
   659
    load_reg( R_EAX, Rm );
nkeynes@361
   660
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   661
    store_reg( R_EAX, Rn );
nkeynes@361
   662
:}
nkeynes@361
   663
EXTU.W Rm, Rn {:  
nkeynes@671
   664
    COUNT_INST(I_EXTUW);
nkeynes@361
   665
    load_reg( R_EAX, Rm );
nkeynes@361
   666
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   667
    store_reg( R_EAX, Rn );
nkeynes@361
   668
:}
nkeynes@586
   669
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   670
    COUNT_INST(I_MACL);
nkeynes@586
   671
    if( Rm == Rn ) {
nkeynes@586
   672
	load_reg( R_EAX, Rm );
nkeynes@586
   673
	check_ralign32( R_EAX );
nkeynes@586
   674
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   675
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   676
	load_reg( R_EAX, Rn );
nkeynes@586
   677
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   678
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   679
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   680
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   681
	// adding a page-boundary check to skip the second translation
nkeynes@586
   682
    } else {
nkeynes@586
   683
	load_reg( R_EAX, Rm );
nkeynes@586
   684
	check_ralign32( R_EAX );
nkeynes@586
   685
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   686
	load_reg( R_ECX, Rn );
nkeynes@596
   687
	check_ralign32( R_ECX );
nkeynes@586
   688
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   689
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   690
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   691
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   692
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   693
    }
nkeynes@586
   694
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   695
    POP_r32( R_ECX );
nkeynes@586
   696
    PUSH_r32( R_EAX );
nkeynes@386
   697
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   698
    POP_realigned_r32( R_ECX );
nkeynes@586
   699
nkeynes@386
   700
    IMUL_r32( R_ECX );
nkeynes@386
   701
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   702
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   703
nkeynes@386
   704
    load_spreg( R_ECX, R_S );
nkeynes@386
   705
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   706
    JE_rel8( nosat );
nkeynes@386
   707
    call_func0( signsat48 );
nkeynes@386
   708
    JMP_TARGET( nosat );
nkeynes@417
   709
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   710
:}
nkeynes@386
   711
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   712
    COUNT_INST(I_MACW);
nkeynes@586
   713
    if( Rm == Rn ) {
nkeynes@586
   714
	load_reg( R_EAX, Rm );
nkeynes@586
   715
	check_ralign16( R_EAX );
nkeynes@586
   716
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   717
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   718
	load_reg( R_EAX, Rn );
nkeynes@586
   719
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   720
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   721
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   722
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   723
	// adding a page-boundary check to skip the second translation
nkeynes@586
   724
    } else {
nkeynes@586
   725
	load_reg( R_EAX, Rm );
nkeynes@586
   726
	check_ralign16( R_EAX );
nkeynes@586
   727
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   728
	load_reg( R_ECX, Rn );
nkeynes@596
   729
	check_ralign16( R_ECX );
nkeynes@586
   730
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   731
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   732
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   733
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   734
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   735
    }
nkeynes@586
   736
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   737
    POP_r32( R_ECX );
nkeynes@586
   738
    PUSH_r32( R_EAX );
nkeynes@386
   739
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   740
    POP_realigned_r32( R_ECX );
nkeynes@386
   741
    IMUL_r32( R_ECX );
nkeynes@386
   742
nkeynes@386
   743
    load_spreg( R_ECX, R_S );
nkeynes@386
   744
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   745
    JE_rel8( nosat );
nkeynes@386
   746
nkeynes@386
   747
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   748
    JNO_rel8( end );            // 2
nkeynes@386
   749
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   750
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   751
    JS_rel8( positive );        // 2
nkeynes@386
   752
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   753
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   754
    JMP_rel8(end2);           // 2
nkeynes@386
   755
nkeynes@386
   756
    JMP_TARGET(positive);
nkeynes@386
   757
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   758
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   759
    JMP_rel8(end3);            // 2
nkeynes@386
   760
nkeynes@386
   761
    JMP_TARGET(nosat);
nkeynes@386
   762
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   763
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   764
    JMP_TARGET(end);
nkeynes@386
   765
    JMP_TARGET(end2);
nkeynes@386
   766
    JMP_TARGET(end3);
nkeynes@417
   767
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   768
:}
nkeynes@359
   769
MOVT Rn {:  
nkeynes@671
   770
    COUNT_INST(I_MOVT);
nkeynes@359
   771
    load_spreg( R_EAX, R_T );
nkeynes@359
   772
    store_reg( R_EAX, Rn );
nkeynes@359
   773
:}
nkeynes@361
   774
MUL.L Rm, Rn {:  
nkeynes@671
   775
    COUNT_INST(I_MULL);
nkeynes@361
   776
    load_reg( R_EAX, Rm );
nkeynes@361
   777
    load_reg( R_ECX, Rn );
nkeynes@361
   778
    MUL_r32( R_ECX );
nkeynes@361
   779
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   780
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   781
:}
nkeynes@374
   782
MULS.W Rm, Rn {:
nkeynes@671
   783
    COUNT_INST(I_MULSW);
nkeynes@374
   784
    load_reg16s( R_EAX, Rm );
nkeynes@374
   785
    load_reg16s( R_ECX, Rn );
nkeynes@374
   786
    MUL_r32( R_ECX );
nkeynes@374
   787
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   788
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   789
:}
nkeynes@374
   790
MULU.W Rm, Rn {:  
nkeynes@671
   791
    COUNT_INST(I_MULUW);
nkeynes@374
   792
    load_reg16u( R_EAX, Rm );
nkeynes@374
   793
    load_reg16u( R_ECX, Rn );
nkeynes@374
   794
    MUL_r32( R_ECX );
nkeynes@374
   795
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   796
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   797
:}
nkeynes@359
   798
NEG Rm, Rn {:
nkeynes@671
   799
    COUNT_INST(I_NEG);
nkeynes@359
   800
    load_reg( R_EAX, Rm );
nkeynes@359
   801
    NEG_r32( R_EAX );
nkeynes@359
   802
    store_reg( R_EAX, Rn );
nkeynes@417
   803
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   804
:}
nkeynes@359
   805
NEGC Rm, Rn {:  
nkeynes@671
   806
    COUNT_INST(I_NEGC);
nkeynes@359
   807
    load_reg( R_EAX, Rm );
nkeynes@359
   808
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   809
    LDC_t();
nkeynes@359
   810
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   811
    store_reg( R_ECX, Rn );
nkeynes@359
   812
    SETC_t();
nkeynes@417
   813
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   814
:}
nkeynes@359
   815
NOT Rm, Rn {:  
nkeynes@671
   816
    COUNT_INST(I_NOT);
nkeynes@359
   817
    load_reg( R_EAX, Rm );
nkeynes@359
   818
    NOT_r32( R_EAX );
nkeynes@359
   819
    store_reg( R_EAX, Rn );
nkeynes@417
   820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   821
:}
nkeynes@359
   822
OR Rm, Rn {:  
nkeynes@671
   823
    COUNT_INST(I_OR);
nkeynes@359
   824
    load_reg( R_EAX, Rm );
nkeynes@359
   825
    load_reg( R_ECX, Rn );
nkeynes@359
   826
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   827
    store_reg( R_ECX, Rn );
nkeynes@417
   828
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   829
:}
nkeynes@359
   830
OR #imm, R0 {:
nkeynes@671
   831
    COUNT_INST(I_ORI);
nkeynes@359
   832
    load_reg( R_EAX, 0 );
nkeynes@359
   833
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   834
    store_reg( R_EAX, 0 );
nkeynes@417
   835
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   836
:}
nkeynes@374
   837
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   838
    COUNT_INST(I_ORB);
nkeynes@374
   839
    load_reg( R_EAX, 0 );
nkeynes@374
   840
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   841
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   842
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   843
    PUSH_realigned_r32(R_EAX);
nkeynes@905
   844
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
   845
    POP_realigned_r32(R_EAX);
nkeynes@905
   846
    OR_imm32_r32(imm, R_EDX );
nkeynes@905
   847
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   848
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   849
:}
nkeynes@359
   850
ROTCL Rn {:
nkeynes@671
   851
    COUNT_INST(I_ROTCL);
nkeynes@359
   852
    load_reg( R_EAX, Rn );
nkeynes@417
   853
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   854
	LDC_t();
nkeynes@417
   855
    }
nkeynes@359
   856
    RCL1_r32( R_EAX );
nkeynes@359
   857
    store_reg( R_EAX, Rn );
nkeynes@359
   858
    SETC_t();
nkeynes@417
   859
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   860
:}
nkeynes@359
   861
ROTCR Rn {:  
nkeynes@671
   862
    COUNT_INST(I_ROTCR);
nkeynes@359
   863
    load_reg( R_EAX, Rn );
nkeynes@417
   864
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   865
	LDC_t();
nkeynes@417
   866
    }
nkeynes@359
   867
    RCR1_r32( R_EAX );
nkeynes@359
   868
    store_reg( R_EAX, Rn );
nkeynes@359
   869
    SETC_t();
nkeynes@417
   870
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   871
:}
nkeynes@359
   872
ROTL Rn {:  
nkeynes@671
   873
    COUNT_INST(I_ROTL);
nkeynes@359
   874
    load_reg( R_EAX, Rn );
nkeynes@359
   875
    ROL1_r32( R_EAX );
nkeynes@359
   876
    store_reg( R_EAX, Rn );
nkeynes@359
   877
    SETC_t();
nkeynes@417
   878
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   879
:}
nkeynes@359
   880
ROTR Rn {:  
nkeynes@671
   881
    COUNT_INST(I_ROTR);
nkeynes@359
   882
    load_reg( R_EAX, Rn );
nkeynes@359
   883
    ROR1_r32( R_EAX );
nkeynes@359
   884
    store_reg( R_EAX, Rn );
nkeynes@359
   885
    SETC_t();
nkeynes@417
   886
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   887
:}
nkeynes@359
   888
SHAD Rm, Rn {:
nkeynes@671
   889
    COUNT_INST(I_SHAD);
nkeynes@359
   890
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   891
    load_reg( R_EAX, Rn );
nkeynes@361
   892
    load_reg( R_ECX, Rm );
nkeynes@361
   893
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   894
    JGE_rel8(doshl);
nkeynes@361
   895
                    
nkeynes@361
   896
    NEG_r32( R_ECX );      // 2
nkeynes@361
   897
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   898
    JE_rel8(emptysar);     // 2
nkeynes@361
   899
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   900
    JMP_rel8(end);          // 2
nkeynes@386
   901
nkeynes@386
   902
    JMP_TARGET(emptysar);
nkeynes@386
   903
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   904
    JMP_rel8(end2);
nkeynes@382
   905
nkeynes@380
   906
    JMP_TARGET(doshl);
nkeynes@361
   907
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   908
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   909
    JMP_TARGET(end);
nkeynes@386
   910
    JMP_TARGET(end2);
nkeynes@361
   911
    store_reg( R_EAX, Rn );
nkeynes@417
   912
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   913
:}
nkeynes@359
   914
SHLD Rm, Rn {:  
nkeynes@671
   915
    COUNT_INST(I_SHLD);
nkeynes@368
   916
    load_reg( R_EAX, Rn );
nkeynes@368
   917
    load_reg( R_ECX, Rm );
nkeynes@382
   918
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   919
    JGE_rel8(doshl);
nkeynes@368
   920
nkeynes@382
   921
    NEG_r32( R_ECX );      // 2
nkeynes@382
   922
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   923
    JE_rel8(emptyshr );
nkeynes@382
   924
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   925
    JMP_rel8(end);          // 2
nkeynes@386
   926
nkeynes@386
   927
    JMP_TARGET(emptyshr);
nkeynes@386
   928
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   929
    JMP_rel8(end2);
nkeynes@382
   930
nkeynes@382
   931
    JMP_TARGET(doshl);
nkeynes@382
   932
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   933
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   934
    JMP_TARGET(end);
nkeynes@386
   935
    JMP_TARGET(end2);
nkeynes@368
   936
    store_reg( R_EAX, Rn );
nkeynes@417
   937
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   938
:}
nkeynes@359
   939
SHAL Rn {: 
nkeynes@671
   940
    COUNT_INST(I_SHAL);
nkeynes@359
   941
    load_reg( R_EAX, Rn );
nkeynes@359
   942
    SHL1_r32( R_EAX );
nkeynes@397
   943
    SETC_t();
nkeynes@359
   944
    store_reg( R_EAX, Rn );
nkeynes@417
   945
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   946
:}
nkeynes@359
   947
SHAR Rn {:  
nkeynes@671
   948
    COUNT_INST(I_SHAR);
nkeynes@359
   949
    load_reg( R_EAX, Rn );
nkeynes@359
   950
    SAR1_r32( R_EAX );
nkeynes@397
   951
    SETC_t();
nkeynes@359
   952
    store_reg( R_EAX, Rn );
nkeynes@417
   953
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   954
:}
nkeynes@359
   955
SHLL Rn {:  
nkeynes@671
   956
    COUNT_INST(I_SHLL);
nkeynes@359
   957
    load_reg( R_EAX, Rn );
nkeynes@359
   958
    SHL1_r32( R_EAX );
nkeynes@397
   959
    SETC_t();
nkeynes@359
   960
    store_reg( R_EAX, Rn );
nkeynes@417
   961
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   962
:}
nkeynes@359
   963
SHLL2 Rn {:
nkeynes@671
   964
    COUNT_INST(I_SHLL);
nkeynes@359
   965
    load_reg( R_EAX, Rn );
nkeynes@359
   966
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   967
    store_reg( R_EAX, Rn );
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   969
:}
nkeynes@359
   970
SHLL8 Rn {:  
nkeynes@671
   971
    COUNT_INST(I_SHLL);
nkeynes@359
   972
    load_reg( R_EAX, Rn );
nkeynes@359
   973
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   974
    store_reg( R_EAX, Rn );
nkeynes@417
   975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   976
:}
nkeynes@359
   977
SHLL16 Rn {:  
nkeynes@671
   978
    COUNT_INST(I_SHLL);
nkeynes@359
   979
    load_reg( R_EAX, Rn );
nkeynes@359
   980
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   981
    store_reg( R_EAX, Rn );
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   983
:}
nkeynes@359
   984
SHLR Rn {:  
nkeynes@671
   985
    COUNT_INST(I_SHLR);
nkeynes@359
   986
    load_reg( R_EAX, Rn );
nkeynes@359
   987
    SHR1_r32( R_EAX );
nkeynes@397
   988
    SETC_t();
nkeynes@359
   989
    store_reg( R_EAX, Rn );
nkeynes@417
   990
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   991
:}
nkeynes@359
   992
SHLR2 Rn {:  
nkeynes@671
   993
    COUNT_INST(I_SHLR);
nkeynes@359
   994
    load_reg( R_EAX, Rn );
nkeynes@359
   995
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   996
    store_reg( R_EAX, Rn );
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   998
:}
nkeynes@359
   999
SHLR8 Rn {:  
nkeynes@671
  1000
    COUNT_INST(I_SHLR);
nkeynes@359
  1001
    load_reg( R_EAX, Rn );
nkeynes@359
  1002
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1003
    store_reg( R_EAX, Rn );
nkeynes@417
  1004
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1005
:}
nkeynes@359
  1006
SHLR16 Rn {:  
nkeynes@671
  1007
    COUNT_INST(I_SHLR);
nkeynes@359
  1008
    load_reg( R_EAX, Rn );
nkeynes@359
  1009
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1010
    store_reg( R_EAX, Rn );
nkeynes@417
  1011
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1012
:}
nkeynes@359
  1013
SUB Rm, Rn {:  
nkeynes@671
  1014
    COUNT_INST(I_SUB);
nkeynes@359
  1015
    load_reg( R_EAX, Rm );
nkeynes@359
  1016
    load_reg( R_ECX, Rn );
nkeynes@359
  1017
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1018
    store_reg( R_ECX, Rn );
nkeynes@417
  1019
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1020
:}
nkeynes@359
  1021
SUBC Rm, Rn {:  
nkeynes@671
  1022
    COUNT_INST(I_SUBC);
nkeynes@359
  1023
    load_reg( R_EAX, Rm );
nkeynes@359
  1024
    load_reg( R_ECX, Rn );
nkeynes@417
  1025
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1026
	LDC_t();
nkeynes@417
  1027
    }
nkeynes@359
  1028
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1029
    store_reg( R_ECX, Rn );
nkeynes@394
  1030
    SETC_t();
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1032
:}
nkeynes@359
  1033
SUBV Rm, Rn {:  
nkeynes@671
  1034
    COUNT_INST(I_SUBV);
nkeynes@359
  1035
    load_reg( R_EAX, Rm );
nkeynes@359
  1036
    load_reg( R_ECX, Rn );
nkeynes@359
  1037
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1038
    store_reg( R_ECX, Rn );
nkeynes@359
  1039
    SETO_t();
nkeynes@417
  1040
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1041
:}
nkeynes@359
  1042
SWAP.B Rm, Rn {:  
nkeynes@671
  1043
    COUNT_INST(I_SWAPB);
nkeynes@359
  1044
    load_reg( R_EAX, Rm );
nkeynes@601
  1045
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1046
    store_reg( R_EAX, Rn );
nkeynes@359
  1047
:}
nkeynes@359
  1048
SWAP.W Rm, Rn {:  
nkeynes@671
  1049
    COUNT_INST(I_SWAPB);
nkeynes@359
  1050
    load_reg( R_EAX, Rm );
nkeynes@359
  1051
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1052
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1053
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1054
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1055
    store_reg( R_ECX, Rn );
nkeynes@417
  1056
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1057
:}
nkeynes@361
  1058
TAS.B @Rn {:  
nkeynes@671
  1059
    COUNT_INST(I_TASB);
nkeynes@586
  1060
    load_reg( R_EAX, Rn );
nkeynes@586
  1061
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1062
    PUSH_realigned_r32( R_EAX );
nkeynes@905
  1063
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1064
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1065
    SETE_t();
nkeynes@905
  1066
    OR_imm8_r8( 0x80, R_DL );
nkeynes@905
  1067
    POP_realigned_r32( R_EAX );
nkeynes@905
  1068
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1069
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1070
:}
nkeynes@361
  1071
TST Rm, Rn {:  
nkeynes@671
  1072
    COUNT_INST(I_TST);
nkeynes@361
  1073
    load_reg( R_EAX, Rm );
nkeynes@361
  1074
    load_reg( R_ECX, Rn );
nkeynes@361
  1075
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1076
    SETE_t();
nkeynes@417
  1077
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1078
:}
nkeynes@368
  1079
TST #imm, R0 {:  
nkeynes@671
  1080
    COUNT_INST(I_TSTI);
nkeynes@368
  1081
    load_reg( R_EAX, 0 );
nkeynes@368
  1082
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1083
    SETE_t();
nkeynes@417
  1084
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1085
:}
nkeynes@368
  1086
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1087
    COUNT_INST(I_TSTB);
nkeynes@368
  1088
    load_reg( R_EAX, 0);
nkeynes@368
  1089
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1090
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1091
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1092
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1093
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1094
    SETE_t();
nkeynes@417
  1095
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1096
:}
nkeynes@359
  1097
XOR Rm, Rn {:  
nkeynes@671
  1098
    COUNT_INST(I_XOR);
nkeynes@359
  1099
    load_reg( R_EAX, Rm );
nkeynes@359
  1100
    load_reg( R_ECX, Rn );
nkeynes@359
  1101
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1102
    store_reg( R_ECX, Rn );
nkeynes@417
  1103
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1104
:}
nkeynes@359
  1105
XOR #imm, R0 {:  
nkeynes@671
  1106
    COUNT_INST(I_XORI);
nkeynes@359
  1107
    load_reg( R_EAX, 0 );
nkeynes@359
  1108
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1109
    store_reg( R_EAX, 0 );
nkeynes@417
  1110
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1111
:}
nkeynes@359
  1112
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1113
    COUNT_INST(I_XORB);
nkeynes@359
  1114
    load_reg( R_EAX, 0 );
nkeynes@359
  1115
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1116
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1117
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1118
    PUSH_realigned_r32(R_EAX);
nkeynes@905
  1119
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@905
  1120
    POP_realigned_r32(R_EAX);
nkeynes@905
  1121
    XOR_imm32_r32( imm, R_EDX );
nkeynes@905
  1122
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1124
:}
nkeynes@361
  1125
XTRCT Rm, Rn {:
nkeynes@671
  1126
    COUNT_INST(I_XTRCT);
nkeynes@361
  1127
    load_reg( R_EAX, Rm );
nkeynes@394
  1128
    load_reg( R_ECX, Rn );
nkeynes@394
  1129
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1130
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1131
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1132
    store_reg( R_ECX, Rn );
nkeynes@417
  1133
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1134
:}
nkeynes@359
  1135
nkeynes@359
  1136
/* Data move instructions */
nkeynes@359
  1137
MOV Rm, Rn {:  
nkeynes@671
  1138
    COUNT_INST(I_MOV);
nkeynes@359
  1139
    load_reg( R_EAX, Rm );
nkeynes@359
  1140
    store_reg( R_EAX, Rn );
nkeynes@359
  1141
:}
nkeynes@359
  1142
MOV #imm, Rn {:  
nkeynes@671
  1143
    COUNT_INST(I_MOVI);
nkeynes@359
  1144
    load_imm32( R_EAX, imm );
nkeynes@359
  1145
    store_reg( R_EAX, Rn );
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B Rm, @Rn {:  
nkeynes@671
  1148
    COUNT_INST(I_MOVB);
nkeynes@586
  1149
    load_reg( R_EAX, Rn );
nkeynes@586
  1150
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1151
    load_reg( R_EDX, Rm );
nkeynes@586
  1152
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1154
:}
nkeynes@359
  1155
MOV.B Rm, @-Rn {:  
nkeynes@671
  1156
    COUNT_INST(I_MOVB);
nkeynes@586
  1157
    load_reg( R_EAX, Rn );
nkeynes@586
  1158
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1159
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1160
    load_reg( R_EDX, Rm );
nkeynes@586
  1161
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1162
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1164
:}
nkeynes@359
  1165
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1166
    COUNT_INST(I_MOVB);
nkeynes@359
  1167
    load_reg( R_EAX, 0 );
nkeynes@359
  1168
    load_reg( R_ECX, Rn );
nkeynes@586
  1169
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1170
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1171
    load_reg( R_EDX, Rm );
nkeynes@586
  1172
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1174
:}
nkeynes@359
  1175
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1176
    COUNT_INST(I_MOVB);
nkeynes@586
  1177
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1178
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1179
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1180
    load_reg( R_EDX, 0 );
nkeynes@586
  1181
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1182
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1183
:}
nkeynes@359
  1184
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1185
    COUNT_INST(I_MOVB);
nkeynes@586
  1186
    load_reg( R_EAX, Rn );
nkeynes@586
  1187
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1188
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1189
    load_reg( R_EDX, 0 );
nkeynes@586
  1190
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1192
:}
nkeynes@359
  1193
MOV.B @Rm, Rn {:  
nkeynes@671
  1194
    COUNT_INST(I_MOVB);
nkeynes@586
  1195
    load_reg( R_EAX, Rm );
nkeynes@586
  1196
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1197
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1198
    store_reg( R_EAX, Rn );
nkeynes@417
  1199
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1200
:}
nkeynes@359
  1201
MOV.B @Rm+, Rn {:  
nkeynes@671
  1202
    COUNT_INST(I_MOVB);
nkeynes@586
  1203
    load_reg( R_EAX, Rm );
nkeynes@586
  1204
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1205
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1206
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1207
    store_reg( R_EAX, Rn );
nkeynes@417
  1208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1209
:}
nkeynes@359
  1210
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1211
    COUNT_INST(I_MOVB);
nkeynes@359
  1212
    load_reg( R_EAX, 0 );
nkeynes@359
  1213
    load_reg( R_ECX, Rm );
nkeynes@586
  1214
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1215
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1216
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1217
    store_reg( R_EAX, Rn );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1219
:}
nkeynes@359
  1220
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1221
    COUNT_INST(I_MOVB);
nkeynes@586
  1222
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1223
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1224
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1225
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1226
    store_reg( R_EAX, 0 );
nkeynes@417
  1227
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1228
:}
nkeynes@359
  1229
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1230
    COUNT_INST(I_MOVB);
nkeynes@586
  1231
    load_reg( R_EAX, Rm );
nkeynes@586
  1232
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1233
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1234
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1235
    store_reg( R_EAX, 0 );
nkeynes@417
  1236
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1237
:}
nkeynes@374
  1238
MOV.L Rm, @Rn {:
nkeynes@671
  1239
    COUNT_INST(I_MOVL);
nkeynes@586
  1240
    load_reg( R_EAX, Rn );
nkeynes@586
  1241
    check_walign32(R_EAX);
nkeynes@586
  1242
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1243
    load_reg( R_EDX, Rm );
nkeynes@586
  1244
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1246
:}
nkeynes@361
  1247
MOV.L Rm, @-Rn {:  
nkeynes@671
  1248
    COUNT_INST(I_MOVL);
nkeynes@586
  1249
    load_reg( R_EAX, Rn );
nkeynes@586
  1250
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1251
    check_walign32( R_EAX );
nkeynes@586
  1252
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1253
    load_reg( R_EDX, Rm );
nkeynes@586
  1254
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1255
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1256
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1257
:}
nkeynes@361
  1258
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1259
    COUNT_INST(I_MOVL);
nkeynes@361
  1260
    load_reg( R_EAX, 0 );
nkeynes@361
  1261
    load_reg( R_ECX, Rn );
nkeynes@586
  1262
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1263
    check_walign32( R_EAX );
nkeynes@586
  1264
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1265
    load_reg( R_EDX, Rm );
nkeynes@586
  1266
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1267
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1268
:}
nkeynes@361
  1269
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1270
    COUNT_INST(I_MOVL);
nkeynes@586
  1271
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1272
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1273
    check_walign32( R_EAX );
nkeynes@586
  1274
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1275
    load_reg( R_EDX, 0 );
nkeynes@586
  1276
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1277
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1278
:}
nkeynes@361
  1279
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1280
    COUNT_INST(I_MOVL);
nkeynes@586
  1281
    load_reg( R_EAX, Rn );
nkeynes@586
  1282
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1283
    check_walign32( R_EAX );
nkeynes@586
  1284
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1285
    load_reg( R_EDX, Rm );
nkeynes@586
  1286
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1288
:}
nkeynes@361
  1289
MOV.L @Rm, Rn {:  
nkeynes@671
  1290
    COUNT_INST(I_MOVL);
nkeynes@586
  1291
    load_reg( R_EAX, Rm );
nkeynes@586
  1292
    check_ralign32( R_EAX );
nkeynes@586
  1293
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1294
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1295
    store_reg( R_EAX, Rn );
nkeynes@417
  1296
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1297
:}
nkeynes@361
  1298
MOV.L @Rm+, Rn {:  
nkeynes@671
  1299
    COUNT_INST(I_MOVL);
nkeynes@361
  1300
    load_reg( R_EAX, Rm );
nkeynes@382
  1301
    check_ralign32( R_EAX );
nkeynes@586
  1302
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1303
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1304
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1305
    store_reg( R_EAX, Rn );
nkeynes@417
  1306
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1307
:}
nkeynes@361
  1308
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1309
    COUNT_INST(I_MOVL);
nkeynes@361
  1310
    load_reg( R_EAX, 0 );
nkeynes@361
  1311
    load_reg( R_ECX, Rm );
nkeynes@586
  1312
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1313
    check_ralign32( R_EAX );
nkeynes@586
  1314
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1315
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1316
    store_reg( R_EAX, Rn );
nkeynes@417
  1317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1318
:}
nkeynes@361
  1319
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1320
    COUNT_INST(I_MOVL);
nkeynes@586
  1321
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1322
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1323
    check_ralign32( R_EAX );
nkeynes@586
  1324
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1325
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1326
    store_reg( R_EAX, 0 );
nkeynes@417
  1327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1328
:}
nkeynes@361
  1329
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1330
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1331
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1332
	SLOTILLEGAL();
nkeynes@374
  1333
    } else {
nkeynes@388
  1334
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1335
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1336
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1337
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1338
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1339
nkeynes@586
  1340
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1341
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1342
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1343
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1344
	    // behaviour though.
nkeynes@586
  1345
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1346
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1347
	} else {
nkeynes@586
  1348
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1349
	    // different virtual address than the translation was done with,
nkeynes@586
  1350
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1351
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1352
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1353
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1354
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1355
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1356
	}
nkeynes@382
  1357
	store_reg( R_EAX, Rn );
nkeynes@374
  1358
    }
nkeynes@361
  1359
:}
nkeynes@361
  1360
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1361
    COUNT_INST(I_MOVL);
nkeynes@586
  1362
    load_reg( R_EAX, Rm );
nkeynes@586
  1363
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1364
    check_ralign32( R_EAX );
nkeynes@586
  1365
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1366
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1367
    store_reg( R_EAX, Rn );
nkeynes@417
  1368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1369
:}
nkeynes@361
  1370
MOV.W Rm, @Rn {:  
nkeynes@671
  1371
    COUNT_INST(I_MOVW);
nkeynes@586
  1372
    load_reg( R_EAX, Rn );
nkeynes@586
  1373
    check_walign16( R_EAX );
nkeynes@586
  1374
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1375
    load_reg( R_EDX, Rm );
nkeynes@586
  1376
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1377
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1378
:}
nkeynes@361
  1379
MOV.W Rm, @-Rn {:  
nkeynes@671
  1380
    COUNT_INST(I_MOVW);
nkeynes@586
  1381
    load_reg( R_EAX, Rn );
nkeynes@586
  1382
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1383
    check_walign16( R_EAX );
nkeynes@586
  1384
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1385
    load_reg( R_EDX, Rm );
nkeynes@586
  1386
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1387
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1388
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1389
:}
nkeynes@361
  1390
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1391
    COUNT_INST(I_MOVW);
nkeynes@361
  1392
    load_reg( R_EAX, 0 );
nkeynes@361
  1393
    load_reg( R_ECX, Rn );
nkeynes@586
  1394
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1395
    check_walign16( R_EAX );
nkeynes@586
  1396
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1397
    load_reg( R_EDX, Rm );
nkeynes@586
  1398
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1399
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1400
:}
nkeynes@361
  1401
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1402
    COUNT_INST(I_MOVW);
nkeynes@586
  1403
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1404
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1405
    check_walign16( R_EAX );
nkeynes@586
  1406
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1407
    load_reg( R_EDX, 0 );
nkeynes@586
  1408
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1409
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1410
:}
nkeynes@361
  1411
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1412
    COUNT_INST(I_MOVW);
nkeynes@586
  1413
    load_reg( R_EAX, Rn );
nkeynes@586
  1414
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1415
    check_walign16( R_EAX );
nkeynes@586
  1416
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1417
    load_reg( R_EDX, 0 );
nkeynes@586
  1418
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1419
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1420
:}
nkeynes@361
  1421
MOV.W @Rm, Rn {:  
nkeynes@671
  1422
    COUNT_INST(I_MOVW);
nkeynes@586
  1423
    load_reg( R_EAX, Rm );
nkeynes@586
  1424
    check_ralign16( R_EAX );
nkeynes@586
  1425
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1426
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1427
    store_reg( R_EAX, Rn );
nkeynes@417
  1428
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1429
:}
nkeynes@361
  1430
MOV.W @Rm+, Rn {:  
nkeynes@671
  1431
    COUNT_INST(I_MOVW);
nkeynes@361
  1432
    load_reg( R_EAX, Rm );
nkeynes@374
  1433
    check_ralign16( R_EAX );
nkeynes@586
  1434
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1435
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1436
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1437
    store_reg( R_EAX, Rn );
nkeynes@417
  1438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1439
:}
nkeynes@361
  1440
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1441
    COUNT_INST(I_MOVW);
nkeynes@361
  1442
    load_reg( R_EAX, 0 );
nkeynes@361
  1443
    load_reg( R_ECX, Rm );
nkeynes@586
  1444
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1445
    check_ralign16( R_EAX );
nkeynes@586
  1446
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1447
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1448
    store_reg( R_EAX, Rn );
nkeynes@417
  1449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1450
:}
nkeynes@361
  1451
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1452
    COUNT_INST(I_MOVW);
nkeynes@586
  1453
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1454
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1455
    check_ralign16( R_EAX );
nkeynes@586
  1456
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1457
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1458
    store_reg( R_EAX, 0 );
nkeynes@417
  1459
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1460
:}
nkeynes@361
  1461
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1462
    COUNT_INST(I_MOVW);
nkeynes@374
  1463
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1464
	SLOTILLEGAL();
nkeynes@374
  1465
    } else {
nkeynes@586
  1466
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1467
	uint32_t target = pc + disp + 4;
nkeynes@586
  1468
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1469
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1470
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1471
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1472
	} else {
nkeynes@586
  1473
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1474
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1475
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1476
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1477
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1478
	}
nkeynes@374
  1479
	store_reg( R_EAX, Rn );
nkeynes@374
  1480
    }
nkeynes@361
  1481
:}
nkeynes@361
  1482
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1483
    COUNT_INST(I_MOVW);
nkeynes@586
  1484
    load_reg( R_EAX, Rm );
nkeynes@586
  1485
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1486
    check_ralign16( R_EAX );
nkeynes@586
  1487
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1488
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1489
    store_reg( R_EAX, 0 );
nkeynes@417
  1490
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1491
:}
nkeynes@361
  1492
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1493
    COUNT_INST(I_MOVA);
nkeynes@374
  1494
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1495
	SLOTILLEGAL();
nkeynes@374
  1496
    } else {
nkeynes@586
  1497
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1498
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1499
	store_reg( R_ECX, 0 );
nkeynes@586
  1500
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1501
    }
nkeynes@361
  1502
:}
nkeynes@361
  1503
MOVCA.L R0, @Rn {:  
nkeynes@671
  1504
    COUNT_INST(I_MOVCA);
nkeynes@586
  1505
    load_reg( R_EAX, Rn );
nkeynes@586
  1506
    check_walign32( R_EAX );
nkeynes@586
  1507
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1508
    load_reg( R_EDX, 0 );
nkeynes@586
  1509
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1510
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1511
:}
nkeynes@359
  1512
nkeynes@359
  1513
/* Control transfer instructions */
nkeynes@374
  1514
BF disp {:
nkeynes@671
  1515
    COUNT_INST(I_BF);
nkeynes@374
  1516
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1517
	SLOTILLEGAL();
nkeynes@374
  1518
    } else {
nkeynes@586
  1519
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1520
	JT_rel8( nottaken );
nkeynes@586
  1521
	exit_block_rel(target, pc+2 );
nkeynes@380
  1522
	JMP_TARGET(nottaken);
nkeynes@408
  1523
	return 2;
nkeynes@374
  1524
    }
nkeynes@374
  1525
:}
nkeynes@374
  1526
BF/S disp {:
nkeynes@671
  1527
    COUNT_INST(I_BFS);
nkeynes@374
  1528
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1529
	SLOTILLEGAL();
nkeynes@374
  1530
    } else {
nkeynes@590
  1531
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1532
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1533
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1534
	    JT_rel8(nottaken);
nkeynes@601
  1535
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1536
	    JMP_TARGET(nottaken);
nkeynes@601
  1537
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1538
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1539
	    exit_block_emu(pc+2);
nkeynes@601
  1540
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1541
	    return 2;
nkeynes@601
  1542
	} else {
nkeynes@601
  1543
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1544
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1545
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1546
	    }
nkeynes@601
  1547
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1548
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1549
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1550
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1551
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1552
	    
nkeynes@601
  1553
	    // not taken
nkeynes@601
  1554
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1555
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1556
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1557
	    return 4;
nkeynes@417
  1558
	}
nkeynes@374
  1559
    }
nkeynes@374
  1560
:}
nkeynes@374
  1561
BRA disp {:  
nkeynes@671
  1562
    COUNT_INST(I_BRA);
nkeynes@374
  1563
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1564
	SLOTILLEGAL();
nkeynes@374
  1565
    } else {
nkeynes@590
  1566
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1567
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1568
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1569
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1570
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1571
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1572
	    exit_block_emu(pc+2);
nkeynes@601
  1573
	    return 2;
nkeynes@601
  1574
	} else {
nkeynes@601
  1575
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1576
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1577
	    return 4;
nkeynes@601
  1578
	}
nkeynes@374
  1579
    }
nkeynes@374
  1580
:}
nkeynes@374
  1581
BRAF Rn {:  
nkeynes@671
  1582
    COUNT_INST(I_BRAF);
nkeynes@374
  1583
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1584
	SLOTILLEGAL();
nkeynes@374
  1585
    } else {
nkeynes@590
  1586
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1587
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1588
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1589
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1590
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1591
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1592
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1593
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1594
	    exit_block_emu(pc+2);
nkeynes@601
  1595
	    return 2;
nkeynes@601
  1596
	} else {
nkeynes@601
  1597
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1598
	    exit_block_newpcset(pc+2);
nkeynes@601
  1599
	    return 4;
nkeynes@601
  1600
	}
nkeynes@374
  1601
    }
nkeynes@374
  1602
:}
nkeynes@374
  1603
BSR disp {:  
nkeynes@671
  1604
    COUNT_INST(I_BSR);
nkeynes@374
  1605
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1606
	SLOTILLEGAL();
nkeynes@374
  1607
    } else {
nkeynes@590
  1608
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1609
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1610
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1611
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1612
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1613
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1614
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1615
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1616
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1617
	    exit_block_emu(pc+2);
nkeynes@601
  1618
	    return 2;
nkeynes@601
  1619
	} else {
nkeynes@601
  1620
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1621
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1622
	    return 4;
nkeynes@601
  1623
	}
nkeynes@374
  1624
    }
nkeynes@374
  1625
:}
nkeynes@374
  1626
BSRF Rn {:  
nkeynes@671
  1627
    COUNT_INST(I_BSRF);
nkeynes@374
  1628
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1629
	SLOTILLEGAL();
nkeynes@374
  1630
    } else {
nkeynes@590
  1631
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1632
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1633
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1634
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1635
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1636
nkeynes@601
  1637
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1638
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1639
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1640
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1641
	    exit_block_emu(pc+2);
nkeynes@601
  1642
	    return 2;
nkeynes@601
  1643
	} else {
nkeynes@601
  1644
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1645
	    exit_block_newpcset(pc+2);
nkeynes@601
  1646
	    return 4;
nkeynes@601
  1647
	}
nkeynes@374
  1648
    }
nkeynes@374
  1649
:}
nkeynes@374
  1650
BT disp {:
nkeynes@671
  1651
    COUNT_INST(I_BT);
nkeynes@374
  1652
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1653
	SLOTILLEGAL();
nkeynes@374
  1654
    } else {
nkeynes@586
  1655
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1656
	JF_rel8( nottaken );
nkeynes@586
  1657
	exit_block_rel(target, pc+2 );
nkeynes@380
  1658
	JMP_TARGET(nottaken);
nkeynes@408
  1659
	return 2;
nkeynes@374
  1660
    }
nkeynes@374
  1661
:}
nkeynes@374
  1662
BT/S disp {:
nkeynes@671
  1663
    COUNT_INST(I_BTS);
nkeynes@374
  1664
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1665
	SLOTILLEGAL();
nkeynes@374
  1666
    } else {
nkeynes@590
  1667
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1668
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1669
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1670
	    JF_rel8(nottaken);
nkeynes@601
  1671
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1672
	    JMP_TARGET(nottaken);
nkeynes@601
  1673
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1674
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1675
	    exit_block_emu(pc+2);
nkeynes@601
  1676
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1677
	    return 2;
nkeynes@601
  1678
	} else {
nkeynes@601
  1679
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1680
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1681
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1682
	    }
nkeynes@601
  1683
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1684
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1685
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1686
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1687
	    // not taken
nkeynes@601
  1688
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1689
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1690
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1691
	    return 4;
nkeynes@417
  1692
	}
nkeynes@374
  1693
    }
nkeynes@374
  1694
:}
nkeynes@374
  1695
JMP @Rn {:  
nkeynes@671
  1696
    COUNT_INST(I_JMP);
nkeynes@374
  1697
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1698
	SLOTILLEGAL();
nkeynes@374
  1699
    } else {
nkeynes@408
  1700
	load_reg( R_ECX, Rn );
nkeynes@590
  1701
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1702
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1703
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1704
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1705
	    exit_block_emu(pc+2);
nkeynes@601
  1706
	    return 2;
nkeynes@601
  1707
	} else {
nkeynes@601
  1708
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1709
	    exit_block_newpcset(pc+2);
nkeynes@601
  1710
	    return 4;
nkeynes@601
  1711
	}
nkeynes@374
  1712
    }
nkeynes@374
  1713
:}
nkeynes@374
  1714
JSR @Rn {:  
nkeynes@671
  1715
    COUNT_INST(I_JSR);
nkeynes@374
  1716
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1717
	SLOTILLEGAL();
nkeynes@374
  1718
    } else {
nkeynes@590
  1719
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1720
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1721
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1722
	load_reg( R_ECX, Rn );
nkeynes@590
  1723
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1724
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1725
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1726
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1727
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1728
	    exit_block_emu(pc+2);
nkeynes@601
  1729
	    return 2;
nkeynes@601
  1730
	} else {
nkeynes@601
  1731
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1732
	    exit_block_newpcset(pc+2);
nkeynes@601
  1733
	    return 4;
nkeynes@601
  1734
	}
nkeynes@374
  1735
    }
nkeynes@374
  1736
:}
nkeynes@374
  1737
RTE {:  
nkeynes@671
  1738
    COUNT_INST(I_RTE);
nkeynes@374
  1739
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1740
	SLOTILLEGAL();
nkeynes@374
  1741
    } else {
nkeynes@408
  1742
	check_priv();
nkeynes@408
  1743
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1744
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1745
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1746
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1747
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1748
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1749
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1750
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1751
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1752
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1753
	    exit_block_emu(pc+2);
nkeynes@601
  1754
	    return 2;
nkeynes@601
  1755
	} else {
nkeynes@601
  1756
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1757
	    exit_block_newpcset(pc+2);
nkeynes@601
  1758
	    return 4;
nkeynes@601
  1759
	}
nkeynes@374
  1760
    }
nkeynes@374
  1761
:}
nkeynes@374
  1762
RTS {:  
nkeynes@671
  1763
    COUNT_INST(I_RTS);
nkeynes@374
  1764
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1765
	SLOTILLEGAL();
nkeynes@374
  1766
    } else {
nkeynes@408
  1767
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1768
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1769
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1770
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1771
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1772
	    exit_block_emu(pc+2);
nkeynes@601
  1773
	    return 2;
nkeynes@601
  1774
	} else {
nkeynes@601
  1775
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1776
	    exit_block_newpcset(pc+2);
nkeynes@601
  1777
	    return 4;
nkeynes@601
  1778
	}
nkeynes@374
  1779
    }
nkeynes@374
  1780
:}
nkeynes@374
  1781
TRAPA #imm {:  
nkeynes@671
  1782
    COUNT_INST(I_TRAPA);
nkeynes@374
  1783
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1784
	SLOTILLEGAL();
nkeynes@374
  1785
    } else {
nkeynes@590
  1786
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1787
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1788
	load_imm32( R_EAX, imm );
nkeynes@527
  1789
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1790
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1791
	exit_block_pcset(pc);
nkeynes@409
  1792
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1793
	return 2;
nkeynes@374
  1794
    }
nkeynes@374
  1795
:}
nkeynes@374
  1796
UNDEF {:  
nkeynes@671
  1797
    COUNT_INST(I_UNDEF);
nkeynes@374
  1798
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1799
	SLOTILLEGAL();
nkeynes@374
  1800
    } else {
nkeynes@586
  1801
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1802
	return 2;
nkeynes@374
  1803
    }
nkeynes@368
  1804
:}
nkeynes@374
  1805
nkeynes@374
  1806
CLRMAC {:  
nkeynes@671
  1807
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1808
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1809
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1810
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1811
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1812
:}
nkeynes@374
  1813
CLRS {:
nkeynes@671
  1814
    COUNT_INST(I_CLRS);
nkeynes@374
  1815
    CLC();
nkeynes@374
  1816
    SETC_sh4r(R_S);
nkeynes@872
  1817
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1818
:}
nkeynes@374
  1819
CLRT {:  
nkeynes@671
  1820
    COUNT_INST(I_CLRT);
nkeynes@374
  1821
    CLC();
nkeynes@374
  1822
    SETC_t();
nkeynes@417
  1823
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1824
:}
nkeynes@374
  1825
SETS {:  
nkeynes@671
  1826
    COUNT_INST(I_SETS);
nkeynes@374
  1827
    STC();
nkeynes@374
  1828
    SETC_sh4r(R_S);
nkeynes@872
  1829
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1830
:}
nkeynes@374
  1831
SETT {:  
nkeynes@671
  1832
    COUNT_INST(I_SETT);
nkeynes@374
  1833
    STC();
nkeynes@374
  1834
    SETC_t();
nkeynes@417
  1835
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1836
:}
nkeynes@359
  1837
nkeynes@375
  1838
/* Floating point moves */
nkeynes@375
  1839
FMOV FRm, FRn {:  
nkeynes@671
  1840
    COUNT_INST(I_FMOV1);
nkeynes@377
  1841
    check_fpuen();
nkeynes@901
  1842
    if( sh4_x86.double_size ) {
nkeynes@901
  1843
        load_dr0( R_EAX, FRm );
nkeynes@901
  1844
        load_dr1( R_ECX, FRm );
nkeynes@901
  1845
        store_dr0( R_EAX, FRn );
nkeynes@901
  1846
        store_dr1( R_ECX, FRn );
nkeynes@901
  1847
    } else {
nkeynes@901
  1848
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1849
        store_fr( R_EAX, FRn );
nkeynes@901
  1850
    }
nkeynes@375
  1851
:}
nkeynes@416
  1852
FMOV FRm, @Rn {: 
nkeynes@671
  1853
    COUNT_INST(I_FMOV2);
nkeynes@586
  1854
    check_fpuen();
nkeynes@586
  1855
    load_reg( R_EAX, Rn );
nkeynes@901
  1856
    if( sh4_x86.double_size ) {
nkeynes@901
  1857
        check_walign64( R_EAX );
nkeynes@901
  1858
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1859
        load_dr0( R_EDX, FRm );
nkeynes@905
  1860
        load_dr1( R_ECX, FRm );
nkeynes@905
  1861
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1862
    } else {
nkeynes@901
  1863
        check_walign32( R_EAX );
nkeynes@901
  1864
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1865
        load_fr( R_EDX, FRm );
nkeynes@905
  1866
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1867
    }
nkeynes@417
  1868
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1869
:}
nkeynes@375
  1870
FMOV @Rm, FRn {:  
nkeynes@671
  1871
    COUNT_INST(I_FMOV5);
nkeynes@586
  1872
    check_fpuen();
nkeynes@586
  1873
    load_reg( R_EAX, Rm );
nkeynes@901
  1874
    if( sh4_x86.double_size ) {
nkeynes@901
  1875
        check_ralign64( R_EAX );
nkeynes@901
  1876
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@905
  1877
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1878
        store_dr0( R_EDX, FRn );
nkeynes@901
  1879
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1880
    } else {
nkeynes@901
  1881
        check_ralign32( R_EAX );
nkeynes@901
  1882
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1883
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1884
        store_fr( R_EAX, FRn );
nkeynes@901
  1885
    }
nkeynes@417
  1886
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1887
:}
nkeynes@377
  1888
FMOV FRm, @-Rn {:  
nkeynes@671
  1889
    COUNT_INST(I_FMOV3);
nkeynes@586
  1890
    check_fpuen();
nkeynes@586
  1891
    load_reg( R_EAX, Rn );
nkeynes@901
  1892
    if( sh4_x86.double_size ) {
nkeynes@901
  1893
        check_walign64( R_EAX );
nkeynes@901
  1894
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1895
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1896
        load_dr0( R_EDX, FRm );
nkeynes@905
  1897
        load_dr1( R_ECX, FRm );
nkeynes@901
  1898
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@905
  1899
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1900
    } else {
nkeynes@901
  1901
        check_walign32( R_EAX );
nkeynes@901
  1902
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1903
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1904
        load_fr( R_EDX, FRm );
nkeynes@901
  1905
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@905
  1906
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1907
    }
nkeynes@417
  1908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1909
:}
nkeynes@416
  1910
FMOV @Rm+, FRn {:
nkeynes@671
  1911
    COUNT_INST(I_FMOV6);
nkeynes@586
  1912
    check_fpuen();
nkeynes@586
  1913
    load_reg( R_EAX, Rm );
nkeynes@901
  1914
    if( sh4_x86.double_size ) {
nkeynes@901
  1915
        check_ralign64( R_EAX );
nkeynes@901
  1916
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1917
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@905
  1918
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1919
        store_dr0( R_EDX, FRn );
nkeynes@901
  1920
        store_dr1( R_EAX, FRn );
nkeynes@901
  1921
    } else {
nkeynes@901
  1922
        check_ralign32( R_EAX );
nkeynes@901
  1923
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1924
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1925
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1926
        store_fr( R_EAX, FRn );
nkeynes@901
  1927
    }
nkeynes@417
  1928
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1929
:}
nkeynes@377
  1930
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1931
    COUNT_INST(I_FMOV4);
nkeynes@586
  1932
    check_fpuen();
nkeynes@586
  1933
    load_reg( R_EAX, Rn );
nkeynes@586
  1934
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1935
    if( sh4_x86.double_size ) {
nkeynes@901
  1936
        check_walign64( R_EAX );
nkeynes@901
  1937
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1938
        load_dr0( R_EDX, FRm );
nkeynes@905
  1939
        load_dr1( R_ECX, FRm );
nkeynes@905
  1940
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1941
    } else {
nkeynes@901
  1942
        check_walign32( R_EAX );
nkeynes@901
  1943
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1944
        load_fr( R_EDX, FRm );
nkeynes@905
  1945
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1946
    }
nkeynes@417
  1947
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1948
:}
nkeynes@377
  1949
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1950
    COUNT_INST(I_FMOV7);
nkeynes@586
  1951
    check_fpuen();
nkeynes@586
  1952
    load_reg( R_EAX, Rm );
nkeynes@586
  1953
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1954
    if( sh4_x86.double_size ) {
nkeynes@901
  1955
        check_ralign64( R_EAX );
nkeynes@901
  1956
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1957
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1958
        store_dr0( R_ECX, FRn );
nkeynes@901
  1959
        store_dr1( R_EAX, FRn );
nkeynes@901
  1960
    } else {
nkeynes@901
  1961
        check_ralign32( R_EAX );
nkeynes@901
  1962
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1963
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1964
        store_fr( R_EAX, FRn );
nkeynes@901
  1965
    }
nkeynes@417
  1966
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1967
:}
nkeynes@377
  1968
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1969
    COUNT_INST(I_FLDI0);
nkeynes@377
  1970
    check_fpuen();
nkeynes@901
  1971
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1972
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1973
        store_fr( R_EAX, FRn );
nkeynes@901
  1974
    }
nkeynes@417
  1975
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1976
:}
nkeynes@377
  1977
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1978
    COUNT_INST(I_FLDI1);
nkeynes@377
  1979
    check_fpuen();
nkeynes@901
  1980
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1981
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1982
        store_fr( R_EAX, FRn );
nkeynes@901
  1983
    }
nkeynes@377
  1984
:}
nkeynes@377
  1985
nkeynes@377
  1986
FLOAT FPUL, FRn {:  
nkeynes@671
  1987
    COUNT_INST(I_FLOAT);
nkeynes@377
  1988
    check_fpuen();
nkeynes@377
  1989
    FILD_sh4r(R_FPUL);
nkeynes@901
  1990
    if( sh4_x86.double_prec ) {
nkeynes@901
  1991
        pop_dr( FRn );
nkeynes@901
  1992
    } else {
nkeynes@901
  1993
        pop_fr( FRn );
nkeynes@901
  1994
    }
nkeynes@377
  1995
:}
nkeynes@377
  1996
FTRC FRm, FPUL {:  
nkeynes@671
  1997
    COUNT_INST(I_FTRC);
nkeynes@377
  1998
    check_fpuen();
nkeynes@901
  1999
    if( sh4_x86.double_prec ) {
nkeynes@901
  2000
        push_dr( FRm );
nkeynes@901
  2001
    } else {
nkeynes@901
  2002
        push_fr( FRm );
nkeynes@901
  2003
    }
nkeynes@789
  2004
    load_ptr( R_ECX, &max_int );
nkeynes@388
  2005
    FILD_r32ind( R_ECX );
nkeynes@388
  2006
    FCOMIP_st(1);
nkeynes@669
  2007
    JNA_rel8( sat );
nkeynes@789
  2008
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2009
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2010
    FCOMIP_st(1);                   // 2
nkeynes@669
  2011
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2012
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2013
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2014
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2015
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2016
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2017
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2018
    JMP_rel8(end);             // 2
nkeynes@388
  2019
nkeynes@388
  2020
    JMP_TARGET(sat);
nkeynes@388
  2021
    JMP_TARGET(sat2);
nkeynes@388
  2022
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2023
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2024
    FPOP_st();
nkeynes@388
  2025
    JMP_TARGET(end);
nkeynes@417
  2026
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2027
:}
nkeynes@377
  2028
FLDS FRm, FPUL {:  
nkeynes@671
  2029
    COUNT_INST(I_FLDS);
nkeynes@377
  2030
    check_fpuen();
nkeynes@669
  2031
    load_fr( R_EAX, FRm );
nkeynes@377
  2032
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2033
:}
nkeynes@377
  2034
FSTS FPUL, FRn {:  
nkeynes@671
  2035
    COUNT_INST(I_FSTS);
nkeynes@377
  2036
    check_fpuen();
nkeynes@377
  2037
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2038
    store_fr( R_EAX, FRn );
nkeynes@377
  2039
:}
nkeynes@377
  2040
FCNVDS FRm, FPUL {:  
nkeynes@671
  2041
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2042
    check_fpuen();
nkeynes@901
  2043
    if( sh4_x86.double_prec ) {
nkeynes@901
  2044
        push_dr( FRm );
nkeynes@901
  2045
        pop_fpul();
nkeynes@901
  2046
    }
nkeynes@377
  2047
:}
nkeynes@377
  2048
FCNVSD FPUL, FRn {:  
nkeynes@671
  2049
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2050
    check_fpuen();
nkeynes@901
  2051
    if( sh4_x86.double_prec ) {
nkeynes@901
  2052
        push_fpul();
nkeynes@901
  2053
        pop_dr( FRn );
nkeynes@901
  2054
    }
nkeynes@377
  2055
:}
nkeynes@375
  2056
nkeynes@359
  2057
/* Floating point instructions */
nkeynes@374
  2058
FABS FRn {:  
nkeynes@671
  2059
    COUNT_INST(I_FABS);
nkeynes@377
  2060
    check_fpuen();
nkeynes@901
  2061
    if( sh4_x86.double_prec ) {
nkeynes@901
  2062
        push_dr(FRn);
nkeynes@901
  2063
        FABS_st0();
nkeynes@901
  2064
        pop_dr(FRn);
nkeynes@901
  2065
    } else {
nkeynes@901
  2066
        push_fr(FRn);
nkeynes@901
  2067
        FABS_st0();
nkeynes@901
  2068
        pop_fr(FRn);
nkeynes@901
  2069
    }
nkeynes@374
  2070
:}
nkeynes@377
  2071
FADD FRm, FRn {:  
nkeynes@671
  2072
    COUNT_INST(I_FADD);
nkeynes@377
  2073
    check_fpuen();
nkeynes@901
  2074
    if( sh4_x86.double_prec ) {
nkeynes@901
  2075
        push_dr(FRm);
nkeynes@901
  2076
        push_dr(FRn);
nkeynes@901
  2077
        FADDP_st(1);
nkeynes@901
  2078
        pop_dr(FRn);
nkeynes@901
  2079
    } else {
nkeynes@901
  2080
        push_fr(FRm);
nkeynes@901
  2081
        push_fr(FRn);
nkeynes@901
  2082
        FADDP_st(1);
nkeynes@901
  2083
        pop_fr(FRn);
nkeynes@901
  2084
    }
nkeynes@375
  2085
:}
nkeynes@377
  2086
FDIV FRm, FRn {:  
nkeynes@671
  2087
    COUNT_INST(I_FDIV);
nkeynes@377
  2088
    check_fpuen();
nkeynes@901
  2089
    if( sh4_x86.double_prec ) {
nkeynes@901
  2090
        push_dr(FRn);
nkeynes@901
  2091
        push_dr(FRm);
nkeynes@901
  2092
        FDIVP_st(1);
nkeynes@901
  2093
        pop_dr(FRn);
nkeynes@901
  2094
    } else {
nkeynes@901
  2095
        push_fr(FRn);
nkeynes@901
  2096
        push_fr(FRm);
nkeynes@901
  2097
        FDIVP_st(1);
nkeynes@901
  2098
        pop_fr(FRn);
nkeynes@901
  2099
    }
nkeynes@375
  2100
:}
nkeynes@375
  2101
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2102
    COUNT_INST(I_FMAC);
nkeynes@377
  2103
    check_fpuen();
nkeynes@901
  2104
    if( sh4_x86.double_prec ) {
nkeynes@901
  2105
        push_dr( 0 );
nkeynes@901
  2106
        push_dr( FRm );
nkeynes@901
  2107
        FMULP_st(1);
nkeynes@901
  2108
        push_dr( FRn );
nkeynes@901
  2109
        FADDP_st(1);
nkeynes@901
  2110
        pop_dr( FRn );
nkeynes@901
  2111
    } else {
nkeynes@901
  2112
        push_fr( 0 );
nkeynes@901
  2113
        push_fr( FRm );
nkeynes@901
  2114
        FMULP_st(1);
nkeynes@901
  2115
        push_fr( FRn );
nkeynes@901
  2116
        FADDP_st(1);
nkeynes@901
  2117
        pop_fr( FRn );
nkeynes@901
  2118
    }
nkeynes@375
  2119
:}
nkeynes@375
  2120
nkeynes@377
  2121
FMUL FRm, FRn {:  
nkeynes@671
  2122
    COUNT_INST(I_FMUL);
nkeynes@377
  2123
    check_fpuen();
nkeynes@901
  2124
    if( sh4_x86.double_prec ) {
nkeynes@901
  2125
        push_dr(FRm);
nkeynes@901
  2126
        push_dr(FRn);
nkeynes@901
  2127
        FMULP_st(1);
nkeynes@901
  2128
        pop_dr(FRn);
nkeynes@901
  2129
    } else {
nkeynes@901
  2130
        push_fr(FRm);
nkeynes@901
  2131
        push_fr(FRn);
nkeynes@901
  2132
        FMULP_st(1);
nkeynes@901
  2133
        pop_fr(FRn);
nkeynes@901
  2134
    }
nkeynes@377
  2135
:}
nkeynes@377
  2136
FNEG FRn {:  
nkeynes@671
  2137
    COUNT_INST(I_FNEG);
nkeynes@377
  2138
    check_fpuen();
nkeynes@901
  2139
    if( sh4_x86.double_prec ) {
nkeynes@901
  2140
        push_dr(FRn);
nkeynes@901
  2141
        FCHS_st0();
nkeynes@901
  2142
        pop_dr(FRn);
nkeynes@901
  2143
    } else {
nkeynes@901
  2144
        push_fr(FRn);
nkeynes@901
  2145
        FCHS_st0();
nkeynes@901
  2146
        pop_fr(FRn);
nkeynes@901
  2147
    }
nkeynes@377
  2148
:}
nkeynes@377
  2149
FSRRA FRn {:  
nkeynes@671
  2150
    COUNT_INST(I_FSRRA);
nkeynes@377
  2151
    check_fpuen();
nkeynes@901
  2152
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2153
        FLD1_st0();
nkeynes@901
  2154
        push_fr(FRn);
nkeynes@901
  2155
        FSQRT_st0();
nkeynes@901
  2156
        FDIVP_st(1);
nkeynes@901
  2157
        pop_fr(FRn);
nkeynes@901
  2158
    }
nkeynes@377
  2159
:}
nkeynes@377
  2160
FSQRT FRn {:  
nkeynes@671
  2161
    COUNT_INST(I_FSQRT);
nkeynes@377
  2162
    check_fpuen();
nkeynes@901
  2163
    if( sh4_x86.double_prec ) {
nkeynes@901
  2164
        push_dr(FRn);
nkeynes@901
  2165
        FSQRT_st0();
nkeynes@901
  2166
        pop_dr(FRn);
nkeynes@901
  2167
    } else {
nkeynes@901
  2168
        push_fr(FRn);
nkeynes@901
  2169
        FSQRT_st0();
nkeynes@901
  2170
        pop_fr(FRn);
nkeynes@901
  2171
    }
nkeynes@377
  2172
:}
nkeynes@377
  2173
FSUB FRm, FRn {:  
nkeynes@671
  2174
    COUNT_INST(I_FSUB);
nkeynes@377
  2175
    check_fpuen();
nkeynes@901
  2176
    if( sh4_x86.double_prec ) {
nkeynes@901
  2177
        push_dr(FRn);
nkeynes@901
  2178
        push_dr(FRm);
nkeynes@901
  2179
        FSUBP_st(1);
nkeynes@901
  2180
        pop_dr(FRn);
nkeynes@901
  2181
    } else {
nkeynes@901
  2182
        push_fr(FRn);
nkeynes@901
  2183
        push_fr(FRm);
nkeynes@901
  2184
        FSUBP_st(1);
nkeynes@901
  2185
        pop_fr(FRn);
nkeynes@901
  2186
    }
nkeynes@377
  2187
:}
nkeynes@377
  2188
nkeynes@377
  2189
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2190
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2191
    check_fpuen();
nkeynes@901
  2192
    if( sh4_x86.double_prec ) {
nkeynes@901
  2193
        push_dr(FRm);
nkeynes@901
  2194
        push_dr(FRn);
nkeynes@901
  2195
    } else {
nkeynes@901
  2196
        push_fr(FRm);
nkeynes@901
  2197
        push_fr(FRn);
nkeynes@901
  2198
    }
nkeynes@377
  2199
    FCOMIP_st(1);
nkeynes@377
  2200
    SETE_t();
nkeynes@377
  2201
    FPOP_st();
nkeynes@901
  2202
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2203
:}
nkeynes@377
  2204
FCMP/GT FRm, FRn {:  
nkeynes@671
  2205
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2206
    check_fpuen();
nkeynes@901
  2207
    if( sh4_x86.double_prec ) {
nkeynes@901
  2208
        push_dr(FRm);
nkeynes@901
  2209
        push_dr(FRn);
nkeynes@901
  2210
    } else {
nkeynes@901
  2211
        push_fr(FRm);
nkeynes@901
  2212
        push_fr(FRn);
nkeynes@901
  2213
    }
nkeynes@377
  2214
    FCOMIP_st(1);
nkeynes@377
  2215
    SETA_t();
nkeynes@377
  2216
    FPOP_st();
nkeynes@901
  2217
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2218
:}
nkeynes@377
  2219
nkeynes@377
  2220
FSCA FPUL, FRn {:  
nkeynes@671
  2221
    COUNT_INST(I_FSCA);
nkeynes@377
  2222
    check_fpuen();
nkeynes@901
  2223
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2224
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2225
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2226
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2227
    }
nkeynes@417
  2228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2229
:}
nkeynes@377
  2230
FIPR FVm, FVn {:  
nkeynes@671
  2231
    COUNT_INST(I_FIPR);
nkeynes@377
  2232
    check_fpuen();
nkeynes@901
  2233
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2234
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2235
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2236
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2237
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2238
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2239
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2240
        } else {
nkeynes@904
  2241
            push_fr( FVm<<2 );
nkeynes@903
  2242
            push_fr( FVn<<2 );
nkeynes@903
  2243
            FMULP_st(1);
nkeynes@903
  2244
            push_fr( (FVm<<2)+1);
nkeynes@903
  2245
            push_fr( (FVn<<2)+1);
nkeynes@903
  2246
            FMULP_st(1);
nkeynes@903
  2247
            FADDP_st(1);
nkeynes@903
  2248
            push_fr( (FVm<<2)+2);
nkeynes@903
  2249
            push_fr( (FVn<<2)+2);
nkeynes@903
  2250
            FMULP_st(1);
nkeynes@903
  2251
            FADDP_st(1);
nkeynes@903
  2252
            push_fr( (FVm<<2)+3);
nkeynes@903
  2253
            push_fr( (FVn<<2)+3);
nkeynes@903
  2254
            FMULP_st(1);
nkeynes@903
  2255
            FADDP_st(1);
nkeynes@903
  2256
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2257
        }
nkeynes@901
  2258
    }
nkeynes@377
  2259
:}
nkeynes@377
  2260
FTRV XMTRX, FVn {:  
nkeynes@671
  2261
    COUNT_INST(I_FTRV);
nkeynes@377
  2262
    check_fpuen();
nkeynes@901
  2263
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2264
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2265
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2266
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2267
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2268
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2269
nkeynes@903
  2270
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2271
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2272
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2273
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2274
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2275
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2276
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2277
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2278
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2279
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2280
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2281
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2282
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2283
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2284
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2285
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2286
        } else {
nkeynes@903
  2287
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2288
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2289
        }
nkeynes@901
  2290
    }
nkeynes@417
  2291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2292
:}
nkeynes@377
  2293
nkeynes@377
  2294
FRCHG {:  
nkeynes@671
  2295
    COUNT_INST(I_FRCHG);
nkeynes@377
  2296
    check_fpuen();
nkeynes@377
  2297
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2298
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2299
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2300
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2301
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2302
:}
nkeynes@377
  2303
FSCHG {:  
nkeynes@671
  2304
    COUNT_INST(I_FSCHG);
nkeynes@377
  2305
    check_fpuen();
nkeynes@377
  2306
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2307
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2308
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2309
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2310
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2311
:}
nkeynes@359
  2312
nkeynes@359
  2313
/* Processor control instructions */
nkeynes@368
  2314
LDC Rm, SR {:
nkeynes@671
  2315
    COUNT_INST(I_LDCSR);
nkeynes@386
  2316
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2317
	SLOTILLEGAL();
nkeynes@386
  2318
    } else {
nkeynes@386
  2319
	check_priv();
nkeynes@386
  2320
	load_reg( R_EAX, Rm );
nkeynes@386
  2321
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2322
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2323
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2324
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2325
    }
nkeynes@368
  2326
:}
nkeynes@359
  2327
LDC Rm, GBR {: 
nkeynes@671
  2328
    COUNT_INST(I_LDC);
nkeynes@359
  2329
    load_reg( R_EAX, Rm );
nkeynes@359
  2330
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2331
:}
nkeynes@359
  2332
LDC Rm, VBR {:  
nkeynes@671
  2333
    COUNT_INST(I_LDC);
nkeynes@386
  2334
    check_priv();
nkeynes@359
  2335
    load_reg( R_EAX, Rm );
nkeynes@359
  2336
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2337
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDC Rm, SSR {:  
nkeynes@671
  2340
    COUNT_INST(I_LDC);
nkeynes@386
  2341
    check_priv();
nkeynes@359
  2342
    load_reg( R_EAX, Rm );
nkeynes@359
  2343
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2344
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2345
:}
nkeynes@359
  2346
LDC Rm, SGR {:  
nkeynes@671
  2347
    COUNT_INST(I_LDC);
nkeynes@386
  2348
    check_priv();
nkeynes@359
  2349
    load_reg( R_EAX, Rm );
nkeynes@359
  2350
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2351
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2352
:}
nkeynes@359
  2353
LDC Rm, SPC {:  
nkeynes@671
  2354
    COUNT_INST(I_LDC);
nkeynes@386
  2355
    check_priv();
nkeynes@359
  2356
    load_reg( R_EAX, Rm );
nkeynes@359
  2357
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2359
:}
nkeynes@359
  2360
LDC Rm, DBR {:  
nkeynes@671
  2361
    COUNT_INST(I_LDC);
nkeynes@386
  2362
    check_priv();
nkeynes@359
  2363
    load_reg( R_EAX, Rm );
nkeynes@359
  2364
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2365
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2366
:}
nkeynes@374
  2367
LDC Rm, Rn_BANK {:  
nkeynes@671
  2368
    COUNT_INST(I_LDC);
nkeynes@386
  2369
    check_priv();
nkeynes@374
  2370
    load_reg( R_EAX, Rm );
nkeynes@374
  2371
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2373
:}
nkeynes@359
  2374
LDC.L @Rm+, GBR {:  
nkeynes@671
  2375
    COUNT_INST(I_LDCM);
nkeynes@359
  2376
    load_reg( R_EAX, Rm );
nkeynes@395
  2377
    check_ralign32( R_EAX );
nkeynes@586
  2378
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2379
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2380
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2381
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2382
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2383
:}
nkeynes@368
  2384
LDC.L @Rm+, SR {:
nkeynes@671
  2385
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2386
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2387
	SLOTILLEGAL();
nkeynes@386
  2388
    } else {
nkeynes@586
  2389
	check_priv();
nkeynes@386
  2390
	load_reg( R_EAX, Rm );
nkeynes@395
  2391
	check_ralign32( R_EAX );
nkeynes@586
  2392
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2393
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2394
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2395
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2396
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2397
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2398
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2399
    }
nkeynes@359
  2400
:}
nkeynes@359
  2401
LDC.L @Rm+, VBR {:  
nkeynes@671
  2402
    COUNT_INST(I_LDCM);
nkeynes@586
  2403
    check_priv();
nkeynes@359
  2404
    load_reg( R_EAX, Rm );
nkeynes@395
  2405
    check_ralign32( R_EAX );
nkeynes@586
  2406
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2407
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2408
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2409
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2411
:}
nkeynes@359
  2412
LDC.L @Rm+, SSR {:
nkeynes@671
  2413
    COUNT_INST(I_LDCM);
nkeynes@586
  2414
    check_priv();
nkeynes@359
  2415
    load_reg( R_EAX, Rm );
nkeynes@416
  2416
    check_ralign32( R_EAX );
nkeynes@586
  2417
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2418
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2419
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2420
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2421
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2422
:}
nkeynes@359
  2423
LDC.L @Rm+, SGR {:  
nkeynes@671
  2424
    COUNT_INST(I_LDCM);
nkeynes@586
  2425
    check_priv();
nkeynes@359
  2426
    load_reg( R_EAX, Rm );
nkeynes@395
  2427
    check_ralign32( R_EAX );
nkeynes@586
  2428
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2429
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2430
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2431
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2433
:}
nkeynes@359
  2434
LDC.L @Rm+, SPC {:  
nkeynes@671
  2435
    COUNT_INST(I_LDCM);
nkeynes@586
  2436
    check_priv();
nkeynes@359
  2437
    load_reg( R_EAX, Rm );
nkeynes@395
  2438
    check_ralign32( R_EAX );
nkeynes@586
  2439
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2440
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2441
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2442
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2443
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2444
:}
nkeynes@359
  2445
LDC.L @Rm+, DBR {:  
nkeynes@671
  2446
    COUNT_INST(I_LDCM);
nkeynes@586
  2447
    check_priv();
nkeynes@359
  2448
    load_reg( R_EAX, Rm );
nkeynes@395
  2449
    check_ralign32( R_EAX );
nkeynes@586
  2450
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2451
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2452
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2453
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2455
:}
nkeynes@359
  2456
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2457
    COUNT_INST(I_LDCM);
nkeynes@586
  2458
    check_priv();
nkeynes@374
  2459
    load_reg( R_EAX, Rm );
nkeynes@395
  2460
    check_ralign32( R_EAX );
nkeynes@586
  2461
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2462
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2463
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2464
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2465
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2466
:}
nkeynes@626
  2467
LDS Rm, FPSCR {:
nkeynes@673
  2468
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2469
    check_fpuen();
nkeynes@359
  2470
    load_reg( R_EAX, Rm );
nkeynes@669
  2471
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2473
    return 2;
nkeynes@359
  2474
:}
nkeynes@359
  2475
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2476
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2477
    check_fpuen();
nkeynes@359
  2478
    load_reg( R_EAX, Rm );
nkeynes@395
  2479
    check_ralign32( R_EAX );
nkeynes@586
  2480
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2481
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2482
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2483
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2485
    return 2;
nkeynes@359
  2486
:}
nkeynes@359
  2487
LDS Rm, FPUL {:  
nkeynes@671
  2488
    COUNT_INST(I_LDS);
nkeynes@626
  2489
    check_fpuen();
nkeynes@359
  2490
    load_reg( R_EAX, Rm );
nkeynes@359
  2491
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2492
:}
nkeynes@359
  2493
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2494
    COUNT_INST(I_LDSM);
nkeynes@626
  2495
    check_fpuen();
nkeynes@359
  2496
    load_reg( R_EAX, Rm );
nkeynes@395
  2497
    check_ralign32( R_EAX );
nkeynes@586
  2498
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2499
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2500
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2501
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2502
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2503
:}
nkeynes@359
  2504
LDS Rm, MACH {: 
nkeynes@671
  2505
    COUNT_INST(I_LDS);
nkeynes@359
  2506
    load_reg( R_EAX, Rm );
nkeynes@359
  2507
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2508
:}
nkeynes@359
  2509
LDS.L @Rm+, MACH {:  
nkeynes@671
  2510
    COUNT_INST(I_LDSM);
nkeynes@359
  2511
    load_reg( R_EAX, Rm );
nkeynes@395
  2512
    check_ralign32( R_EAX );
nkeynes@586
  2513
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2514
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2515
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2516
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2518
:}
nkeynes@359
  2519
LDS Rm, MACL {:  
nkeynes@671
  2520
    COUNT_INST(I_LDS);
nkeynes@359
  2521
    load_reg( R_EAX, Rm );
nkeynes@359
  2522
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2523
:}
nkeynes@359
  2524
LDS.L @Rm+, MACL {:  
nkeynes@671
  2525
    COUNT_INST(I_LDSM);
nkeynes@359
  2526
    load_reg( R_EAX, Rm );
nkeynes@395
  2527
    check_ralign32( R_EAX );
nkeynes@586
  2528
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2529
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2530
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2531
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2532
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2533
:}
nkeynes@359
  2534
LDS Rm, PR {:  
nkeynes@671
  2535
    COUNT_INST(I_LDS);
nkeynes@359
  2536
    load_reg( R_EAX, Rm );
nkeynes@359
  2537
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2538
:}
nkeynes@359
  2539
LDS.L @Rm+, PR {:  
nkeynes@671
  2540
    COUNT_INST(I_LDSM);
nkeynes@359
  2541
    load_reg( R_EAX, Rm );
nkeynes@395
  2542
    check_ralign32( R_EAX );
nkeynes@586
  2543
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2544
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2545
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2546
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2547
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2548
:}
nkeynes@550
  2549
LDTLB {:  
nkeynes@671
  2550
    COUNT_INST(I_LDTLB);
nkeynes@553
  2551
    call_func0( MMU_ldtlb );
nkeynes@875
  2552
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2553
:}
nkeynes@671
  2554
OCBI @Rn {:
nkeynes@671
  2555
    COUNT_INST(I_OCBI);
nkeynes@671
  2556
:}
nkeynes@671
  2557
OCBP @Rn {:
nkeynes@671
  2558
    COUNT_INST(I_OCBP);
nkeynes@671
  2559
:}
nkeynes@671
  2560
OCBWB @Rn {:
nkeynes@671
  2561
    COUNT_INST(I_OCBWB);
nkeynes@671
  2562
:}
nkeynes@374
  2563
PREF @Rn {:
nkeynes@671
  2564
    COUNT_INST(I_PREF);
nkeynes@374
  2565
    load_reg( R_EAX, Rn );
nkeynes@532
  2566
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2567
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2568
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2569
    JNE_rel8(end);
nkeynes@905
  2570
    call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@586
  2571
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2572
    JE_exc(-1);
nkeynes@380
  2573
    JMP_TARGET(end);
nkeynes@417
  2574
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2575
:}
nkeynes@388
  2576
SLEEP {: 
nkeynes@671
  2577
    COUNT_INST(I_SLEEP);
nkeynes@388
  2578
    check_priv();
nkeynes@388
  2579
    call_func0( sh4_sleep );
nkeynes@417
  2580
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2581
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2582
    return 2;
nkeynes@388
  2583
:}
nkeynes@386
  2584
STC SR, Rn {:
nkeynes@671
  2585
    COUNT_INST(I_STCSR);
nkeynes@386
  2586
    check_priv();
nkeynes@386
  2587
    call_func0(sh4_read_sr);
nkeynes@386
  2588
    store_reg( R_EAX, Rn );
nkeynes@417
  2589
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2590
:}
nkeynes@359
  2591
STC GBR, Rn {:  
nkeynes@671
  2592
    COUNT_INST(I_STC);
nkeynes@359
  2593
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2594
    store_reg( R_EAX, Rn );
nkeynes@359
  2595
:}
nkeynes@359
  2596
STC VBR, Rn {:  
nkeynes@671
  2597
    COUNT_INST(I_STC);
nkeynes@386
  2598
    check_priv();
nkeynes@359
  2599
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2600
    store_reg( R_EAX, Rn );
nkeynes@417
  2601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2602
:}
nkeynes@359
  2603
STC SSR, Rn {:  
nkeynes@671
  2604
    COUNT_INST(I_STC);
nkeynes@386
  2605
    check_priv();
nkeynes@359
  2606
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2607
    store_reg( R_EAX, Rn );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2609
:}
nkeynes@359
  2610
STC SPC, Rn {:  
nkeynes@671
  2611
    COUNT_INST(I_STC);
nkeynes@386
  2612
    check_priv();
nkeynes@359
  2613
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2614
    store_reg( R_EAX, Rn );
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
:}
nkeynes@359
  2617
STC SGR, Rn {:  
nkeynes@671
  2618
    COUNT_INST(I_STC);
nkeynes@386
  2619
    check_priv();
nkeynes@359
  2620
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2621
    store_reg( R_EAX, Rn );
nkeynes@417
  2622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2623
:}
nkeynes@359
  2624
STC DBR, Rn {:  
nkeynes@671
  2625
    COUNT_INST(I_STC);
nkeynes@386
  2626
    check_priv();
nkeynes@359
  2627
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2628
    store_reg( R_EAX, Rn );
nkeynes@417
  2629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2630
:}
nkeynes@374
  2631
STC Rm_BANK, Rn {:
nkeynes@671
  2632
    COUNT_INST(I_STC);
nkeynes@386
  2633
    check_priv();
nkeynes@374
  2634
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2635
    store_reg( R_EAX, Rn );
nkeynes@417
  2636
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2637
:}
nkeynes@374
  2638
STC.L SR, @-Rn {:
nkeynes@671
  2639
    COUNT_INST(I_STCSRM);
nkeynes@586
  2640
    check_priv();
nkeynes@586
  2641
    load_reg( R_EAX, Rn );
nkeynes@586
  2642
    check_walign32( R_EAX );
nkeynes@586
  2643
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2644
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2645
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2646
    call_func0( sh4_read_sr );
nkeynes@586
  2647
    POP_realigned_r32( R_ECX );
nkeynes@586
  2648
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2649
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2650
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2651
:}
nkeynes@359
  2652
STC.L VBR, @-Rn {:  
nkeynes@671
  2653
    COUNT_INST(I_STCM);
nkeynes@586
  2654
    check_priv();
nkeynes@586
  2655
    load_reg( R_EAX, Rn );
nkeynes@586
  2656
    check_walign32( R_EAX );
nkeynes@586
  2657
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2658
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2659
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2660
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2661
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2662
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2663
:}
nkeynes@359
  2664
STC.L SSR, @-Rn {:  
nkeynes@671
  2665
    COUNT_INST(I_STCM);
nkeynes@586
  2666
    check_priv();
nkeynes@586
  2667
    load_reg( R_EAX, Rn );
nkeynes@586
  2668
    check_walign32( R_EAX );
nkeynes@586
  2669
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2670
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2671
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2672
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2673
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2674
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2675
:}
nkeynes@416
  2676
STC.L SPC, @-Rn {:
nkeynes@671
  2677
    COUNT_INST(I_STCM);
nkeynes@586
  2678
    check_priv();
nkeynes@586
  2679
    load_reg( R_EAX, Rn );
nkeynes@586
  2680
    check_walign32( R_EAX );
nkeynes@586
  2681
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2682
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2683
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2684
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2685
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2686
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2687
:}
nkeynes@359
  2688
STC.L SGR, @-Rn {:  
nkeynes@671
  2689
    COUNT_INST(I_STCM);
nkeynes@586
  2690
    check_priv();
nkeynes@586
  2691
    load_reg( R_EAX, Rn );
nkeynes@586
  2692
    check_walign32( R_EAX );
nkeynes@586
  2693
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2694
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2695
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2696
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2697
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2698
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2699
:}
nkeynes@359
  2700
STC.L DBR, @-Rn {:  
nkeynes@671
  2701
    COUNT_INST(I_STCM);
nkeynes@586
  2702
    check_priv();
nkeynes@586
  2703
    load_reg( R_EAX, Rn );
nkeynes@586
  2704
    check_walign32( R_EAX );
nkeynes@586
  2705
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2706
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2707
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2708
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2709
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2710
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2711
:}
nkeynes@374
  2712
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2713
    COUNT_INST(I_STCM);
nkeynes@586
  2714
    check_priv();
nkeynes@586
  2715
    load_reg( R_EAX, Rn );
nkeynes@586
  2716
    check_walign32( R_EAX );
nkeynes@586
  2717
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2718
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2719
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2720
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2721
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2722
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2723
:}
nkeynes@359
  2724
STC.L GBR, @-Rn {:  
nkeynes@671
  2725
    COUNT_INST(I_STCM);
nkeynes@586
  2726
    load_reg( R_EAX, Rn );
nkeynes@586
  2727
    check_walign32( R_EAX );
nkeynes@586
  2728
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2729
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2730
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2731
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2732
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2733
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2734
:}
nkeynes@359
  2735
STS FPSCR, Rn {:  
nkeynes@673
  2736
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2737
    check_fpuen();
nkeynes@359
  2738
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2739
    store_reg( R_EAX, Rn );
nkeynes@359