lxdream.org :: lxdream/src/sh4/sh4x86.c r626:a010e30a30e9 (annotated)

tree revision 626:a010e30a30e9

filename	src/sh4/sh4x86.c
changeset	626:a010e30a30e9
prev	604:1024c3a9cb88
next	669:ab344e42bca9
author	nkeynes
date	Fri Feb 08 00:06:56 2008 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes the linux 2.4.0-test8 kernel boot (this wasn't exactly very well documented in the original manual)

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nkeynes@359	1	/**
nkeynes@586	2	* $Id$
nkeynes@359	3	*
nkeynes@359	4	* SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359	5	* outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359	6	* to test the optimizing versions against.
nkeynes@359	7	*
nkeynes@359	8	* Copyright (c) 2007 Nathan Keynes.
nkeynes@359	9	*
nkeynes@359	10	* This program is free software; you can redistribute it and/or modify
nkeynes@359	11	* it under the terms of the GNU General Public License as published by
nkeynes@359	12	* the Free Software Foundation; either version 2 of the License, or
nkeynes@359	13	* (at your option) any later version.
nkeynes@359	14	*
nkeynes@359	15	* This program is distributed in the hope that it will be useful,
nkeynes@359	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
nkeynes@359	18	* GNU General Public License for more details.
nkeynes@359	19	*/
nkeynes@359	20
nkeynes@368	21	#include <assert.h>
nkeynes@388	22	#include <math.h>
nkeynes@368	23
nkeynes@380	24	#ifndef NDEBUG
nkeynes@380	25	#define DEBUG_JUMPS 1
nkeynes@380	26	#endif
nkeynes@380	27
nkeynes@417	28	#include "sh4/xltcache.h"
nkeynes@368	29	#include "sh4/sh4core.h"
nkeynes@368	30	#include "sh4/sh4trans.h"
nkeynes@388	31	#include "sh4/sh4mmio.h"
nkeynes@368	32	#include "sh4/x86op.h"
nkeynes@368	33	#include "clock.h"
nkeynes@368	34
nkeynes@368	35	#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368	36
nkeynes@586	37	struct backpatch_record {
nkeynes@604	38	uint32_t fixup_offset;
nkeynes@586	39	uint32_t fixup_icount;
nkeynes@596	40	int32_t exc_code;
nkeynes@586	41	};
nkeynes@586	42
nkeynes@586	43	#define MAX_RECOVERY_SIZE 2048
nkeynes@586	44
nkeynes@590	45	#define DELAY_NONE 0
nkeynes@590	46	#define DELAY_PC 1
nkeynes@590	47	#define DELAY_PC_PR 2
nkeynes@590	48
nkeynes@368	49	/**
nkeynes@368	50	* Struct to manage internal translation state. This state is not saved -
nkeynes@368	51	* it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368	52	* sh4_translate_end_block()
nkeynes@368	53	*/
nkeynes@368	54	struct sh4_x86_state {
nkeynes@590	55	int in_delay_slot;
nkeynes@368	56	gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368	57	gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409	58	gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@408	59	uint32_t block_start_pc;
nkeynes@547	60	uint32_t stack_posn; /* Trace stack height for alignment purposes */
nkeynes@417	61	int tstate;
nkeynes@368	62
nkeynes@586	63	/* mode flags */
nkeynes@586	64	gboolean tlb_on; /* True if tlb translation is active */
nkeynes@586	65
nkeynes@368	66	/* Allocated memory for the (block-wide) back-patch list */
nkeynes@586	67	struct backpatch_record *backpatch_list;
nkeynes@368	68	uint32_t backpatch_posn;
nkeynes@368	69	uint32_t backpatch_size;
nkeynes@368	70	};
nkeynes@368	71
nkeynes@417	72	#define TSTATE_NONE -1
nkeynes@417	73	#define TSTATE_O 0
nkeynes@417	74	#define TSTATE_C 2
nkeynes@417	75	#define TSTATE_E 4
nkeynes@417	76	#define TSTATE_NE 5
nkeynes@417	77	#define TSTATE_G 0xF
nkeynes@417	78	#define TSTATE_GE 0xD
nkeynes@417	79	#define TSTATE_A 7
nkeynes@417	80	#define TSTATE_AE 3
nkeynes@417	81
nkeynes@417	82	/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@417	83	#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417	84	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417	85	OP(0x70+sh4_x86.tstate); OP(rel8); \
nkeynes@417	86	MARK_JMP(rel8,label)
nkeynes@417	87	/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@417	88	#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417	89	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@417	90	OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
nkeynes@417	91	MARK_JMP(rel8, label)
nkeynes@417	92
nkeynes@368	93	static struct sh4_x86_state sh4_x86;
nkeynes@368	94
nkeynes@388	95	static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388	96	static uint32_t min_int = 0x80000000;
nkeynes@394	97	static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394	98	static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386	99
nkeynes@368	100	void sh4_x86_init()
nkeynes@368	101	{
nkeynes@368	102	sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@586	103	sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@368	104	}
nkeynes@368	105
nkeynes@368	106
nkeynes@586	107	static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368	108	{
nkeynes@368	109	if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368	110	sh4_x86.backpatch_size <<= 1;
nkeynes@586	111	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
nkeynes@586	112	sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368	113	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368	114	}
nkeynes@586	115	if( sh4_x86.in_delay_slot ) {
nkeynes@586	116	fixup_pc -= 2;
nkeynes@586	117	}
nkeynes@604	118	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =
nkeynes@604	119	((uint8_t )fixup_addr) - ((uint8_t )xlat_current_block->code);
nkeynes@586	120	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@586	121	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@586	122	sh4_x86.backpatch_posn++;
nkeynes@368	123	}
nkeynes@368	124
nkeynes@359	125	/**
nkeynes@359	126	* Emit an instruction to load an SH4 reg into a real register
nkeynes@359	127	*/
nkeynes@359	128	static inline void load_reg( int x86reg, int sh4reg )
nkeynes@359	129	{
nkeynes@359	130	/* mov [bp+n], reg */
nkeynes@361	131	OP(0x8B);
nkeynes@361	132	OP(0x45 + (x86reg<<3));
nkeynes@359	133	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	134	}
nkeynes@359	135
nkeynes@374	136	static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368	137	{
nkeynes@374	138	OP(0x0F);
nkeynes@374	139	OP(0xBF);
nkeynes@374	140	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368	141	}
nkeynes@368	142
nkeynes@374	143	static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368	144	{
nkeynes@374	145	OP(0x0F);
nkeynes@374	146	OP(0xB7);
nkeynes@374	147	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374	148
nkeynes@368	149	}
nkeynes@368	150
nkeynes@380	151	#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380	152	#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359	153	/**
nkeynes@359	154	* Emit an instruction to load an immediate value into a register
nkeynes@359	155	*/
nkeynes@359	156	static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359	157	/* mov #value, reg */
nkeynes@359	158	OP(0xB8 + x86reg);
nkeynes@359	159	OP32(value);
nkeynes@359	160	}
nkeynes@359	161
nkeynes@359	162	/**
nkeynes@527	163	* Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527	164	*/
nkeynes@527	165	static inline void load_imm64( int x86reg, uint32_t value ) {
nkeynes@527	166	/* mov #value, reg */
nkeynes@527	167	REXW();
nkeynes@527	168	OP(0xB8 + x86reg);
nkeynes@527	169	OP64(value);
nkeynes@527	170	}
nkeynes@527	171
nkeynes@527	172
nkeynes@527	173	/**
nkeynes@359	174	* Emit an instruction to store an SH4 reg (RN)
nkeynes@359	175	*/
nkeynes@359	176	void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359	177	/* mov reg, [bp+n] */
nkeynes@361	178	OP(0x89);
nkeynes@361	179	OP(0x45 + (x86reg<<3));
nkeynes@359	180	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	181	}
nkeynes@374	182
nkeynes@374	183	#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374	184
nkeynes@375	185	/**
nkeynes@375	186	* Load an FR register (single-precision floating point) into an integer x86
nkeynes@375	187	* register (eg for register-to-register moves)
nkeynes@375	188	*/
nkeynes@375	189	void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375	190	{
nkeynes@375	191	OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375	192	}
nkeynes@375	193
nkeynes@375	194	/**
nkeynes@375	195	* Store an FR register (single-precision floating point) into an integer x86
nkeynes@375	196	* register (eg for register-to-register moves)
nkeynes@375	197	*/
nkeynes@375	198	void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375	199	{
nkeynes@375	200	OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375	201	}
nkeynes@375	202
nkeynes@375	203
nkeynes@375	204	/**
nkeynes@375	205	* Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375	206	* bankreg must have been previously loaded with FPSCR.
nkeynes@388	207	* NB: 12 bytes
nkeynes@375	208	*/
nkeynes@374	209	static inline void load_xf_bank( int bankreg )
nkeynes@374	210	{
nkeynes@386	211	NOT_r32( bankreg );
nkeynes@374	212	SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374	213	AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
nkeynes@374	214	OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374	215	}
nkeynes@374	216
nkeynes@375	217	/**
nkeynes@386	218	* Update the fr_bank pointer based on the current fpscr value.
nkeynes@386	219	*/
nkeynes@386	220	static inline void update_fr_bank( int fpscrreg )
nkeynes@386	221	{
nkeynes@386	222	SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386	223	AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
nkeynes@386	224	OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386	225	store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386	226	}
nkeynes@386	227	/**
nkeynes@377	228	* Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377	229	*/
nkeynes@377	230	static inline void push_fpul( )
nkeynes@377	231	{
nkeynes@377	232	OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377	233	}
nkeynes@377	234
nkeynes@377	235	/**
nkeynes@377	236	* Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377	237	*/
nkeynes@377	238	static inline void pop_fpul( )
nkeynes@377	239	{
nkeynes@377	240	OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377	241	}
nkeynes@377	242
nkeynes@377	243	/**
nkeynes@375	244	* Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375	245	* with the location of the current fp bank.
nkeynes@375	246	*/
nkeynes@374	247	static inline void push_fr( int bankreg, int frm )
nkeynes@374	248	{
nkeynes@374	249	OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
nkeynes@374	250	}
nkeynes@374	251
nkeynes@375	252	/**
nkeynes@375	253	* Pop a 32-bit float from the FPU stack and store it back into the fp bank,
nkeynes@375	254	* with bankreg previously loaded with the location of the current fp bank.
nkeynes@375	255	*/
nkeynes@374	256	static inline void pop_fr( int bankreg, int frm )
nkeynes@374	257	{
nkeynes@374	258	OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374	259	}
nkeynes@374	260
nkeynes@375	261	/**
nkeynes@375	262	* Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375	263	* with the location of the current fp bank.
nkeynes@375	264	*/
nkeynes@374	265	static inline void push_dr( int bankreg, int frm )
nkeynes@374	266	{
nkeynes@377	267	OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374	268	}
nkeynes@374	269
nkeynes@374	270	static inline void pop_dr( int bankreg, int frm )
nkeynes@374	271	{
nkeynes@377	272	OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374	273	}
nkeynes@374	274
nkeynes@368	275	/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416	276
nkeynes@416	277	#define check_priv( ) \
nkeynes@416	278	if( !sh4_x86.priv_checked ) { \
nkeynes@416	279	sh4_x86.priv_checked = TRUE;\
nkeynes@416	280	load_spreg( R_EAX, R_SR );\
nkeynes@416	281	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416	282	if( sh4_x86.in_delay_slot ) {\
nkeynes@586	283	JE_exc( EXC_SLOT_ILLEGAL );\
nkeynes@416	284	} else {\
nkeynes@586	285	JE_exc( EXC_ILLEGAL );\
nkeynes@416	286	}\
nkeynes@416	287	}\
nkeynes@416	288
nkeynes@416	289	#define check_fpuen( ) \
nkeynes@416	290	if( !sh4_x86.fpuen_checked ) {\
nkeynes@416	291	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416	292	load_spreg( R_EAX, R_SR );\
nkeynes@416	293	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416	294	if( sh4_x86.in_delay_slot ) {\
nkeynes@586	295	JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416	296	} else {\
nkeynes@586	297	JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416	298	}\
nkeynes@416	299	}
nkeynes@416	300
nkeynes@586	301	#define check_ralign16( x86reg ) \
nkeynes@586	302	TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586	303	JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416	304
nkeynes@586	305	#define check_walign16( x86reg ) \
nkeynes@586	306	TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586	307	JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368	308
nkeynes@586	309	#define check_ralign32( x86reg ) \
nkeynes@586	310	TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586	311	JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368	312
nkeynes@586	313	#define check_walign32( x86reg ) \
nkeynes@586	314	TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586	315	JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368	316
nkeynes@361	317	#define UNDEF()
nkeynes@361	318	#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361	319	#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	320	#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	321	#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	322	#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361	323	#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361	324	#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361	325
nkeynes@586	326	/**
nkeynes@586	327	* Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned
nkeynes@586	328	* on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586	329	*/
nkeynes@586	330	#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@596	331
nkeynes@596	332	#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
nkeynes@586	333	/**
nkeynes@586	334	* Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned
nkeynes@586	335	* on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586	336	*/
nkeynes@586	337	#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368	338
nkeynes@586	339	#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586	340	#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586	341	#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586	342
nkeynes@590	343	#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388	344
nkeynes@539	345	/**** Import appropriate calling conventions ****/
nkeynes@539	346	#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539	347	#include "sh4/ia64abi.h"
nkeynes@539	348	#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539	349	#ifdef APPLE_BUILD
nkeynes@539	350	#include "sh4/ia32mac.h"
nkeynes@539	351	#else
nkeynes@539	352	#include "sh4/ia32abi.h"
nkeynes@539	353	#endif
nkeynes@539	354	#endif
nkeynes@539	355
nkeynes@593	356	uint32_t sh4_translate_end_block_size()
nkeynes@593	357	{
nkeynes@596	358	if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596	359	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596	360	} else {
nkeynes@596	361	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596	362	}
nkeynes@593	363	}
nkeynes@593	364
nkeynes@593	365
nkeynes@590	366	/**
nkeynes@590	367	* Embed a breakpoint into the generated code
nkeynes@590	368	*/
nkeynes@586	369	void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586	370	{
nkeynes@591	371	load_imm32( R_EAX, pc );
nkeynes@591	372	call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586	373	}
nkeynes@590	374
nkeynes@601	375
nkeynes@601	376	#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601	377
nkeynes@590	378	/**
nkeynes@590	379	* Embed a call to sh4_execute_instruction for situations that we
nkeynes@601	380	* can't translate (just page-crossing delay slots at the moment).
nkeynes@601	381	* Caller is responsible for setting new_pc before calling this function.
nkeynes@601	382	*
nkeynes@601	383	* Performs:
nkeynes@601	384	* Set PC = endpc
nkeynes@601	385	* Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601	386	* Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601	387	* Call sh4_execute_instruction
nkeynes@601	388	* Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590	389	*/
nkeynes@601	390	void exit_block_emu( sh4vma_t endpc )
nkeynes@590	391	{
nkeynes@590	392	load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5
nkeynes@590	393	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586	394
nkeynes@601	395	load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590	396	ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
nkeynes@590	397	load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590	398	store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590	399
nkeynes@590	400	call_func0( sh4_execute_instruction );
nkeynes@601	401	load_spreg( R_EAX, R_PC );
nkeynes@590	402	if( sh4_x86.tlb_on ) {
nkeynes@590	403	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590	404	} else {
nkeynes@590	405	call_func1(xlat_get_code,R_EAX);
nkeynes@590	406	}
nkeynes@601	407	AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590	408	POP_r32(R_EBP);
nkeynes@590	409	RET();
nkeynes@590	410	}
nkeynes@539	411
nkeynes@359	412	/**
nkeynes@359	413	* Translate a single instruction. Delayed branches are handled specially
nkeynes@359	414	* by translating both branch and delayed instruction as a single unit (as
nkeynes@359	415	*
nkeynes@586	416	* The instruction MUST be in the icache (assert check)
nkeynes@359	417	*
nkeynes@359	418	* @return true if the instruction marks the end of a basic block
nkeynes@359	419	* (eg a branch or
nkeynes@359	420	*/
nkeynes@590	421	uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359	422	{
nkeynes@388	423	uint32_t ir;
nkeynes@586	424	/* Read instruction from icache */
nkeynes@586	425	assert( IS_IN_ICACHE(pc) );
nkeynes@586	426	ir = (uint16_t )GET_ICACHE_PTR(pc);
nkeynes@586	427
nkeynes@586	428	/* PC is not in the current icache - this usually means we're running
nkeynes@586	429	* with MMU on, and we've gone past the end of the page. And since
nkeynes@586	430	* sh4_translate_block is pretty careful about this, it means we're
nkeynes@586	431	* almost certainly in a delay slot.
nkeynes@586	432	*
nkeynes@586	433	* Since we can't assume the page is present (and we can't fault it in
nkeynes@586	434	* at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586	435	* small repairs to cope with the different environment).
nkeynes@586	436	*/
nkeynes@586	437
nkeynes@586	438	if( !sh4_x86.in_delay_slot ) {
nkeynes@596	439	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388	440	}
nkeynes@359	441	switch( (ir&0xF000) >> 12 ) {
nkeynes@359	442	case 0x0:
nkeynes@359	443	switch( ir&0xF ) {
nkeynes@359	444	case 0x2:
nkeynes@359	445	switch( (ir&0x80) >> 7 ) {
nkeynes@359	446	case 0x0:
nkeynes@359	447	switch( (ir&0x70) >> 4 ) {
nkeynes@359	448	case 0x0:
nkeynes@359	449	{ /* STC SR, Rn */
nkeynes@359	450	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	451	check_priv();
nkeynes@374	452	call_func0(sh4_read_sr);
nkeynes@368	453	store_reg( R_EAX, Rn );
nkeynes@417	454	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	455	}
nkeynes@359	456	break;
nkeynes@359	457	case 0x1:
nkeynes@359	458	{ /* STC GBR, Rn */
nkeynes@359	459	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	460	load_spreg( R_EAX, R_GBR );
nkeynes@359	461	store_reg( R_EAX, Rn );
nkeynes@359	462	}
nkeynes@359	463	break;
nkeynes@359	464	case 0x2:
nkeynes@359	465	{ /* STC VBR, Rn */
nkeynes@359	466	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	467	check_priv();
nkeynes@359	468	load_spreg( R_EAX, R_VBR );
nkeynes@359	469	store_reg( R_EAX, Rn );
nkeynes@417	470	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	471	}
nkeynes@359	472	break;
nkeynes@359	473	case 0x3:
nkeynes@359	474	{ /* STC SSR, Rn */
nkeynes@359	475	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	476	check_priv();
nkeynes@359	477	load_spreg( R_EAX, R_SSR );
nkeynes@359	478	store_reg( R_EAX, Rn );
nkeynes@417	479	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	480	}
nkeynes@359	481	break;
nkeynes@359	482	case 0x4:
nkeynes@359	483	{ /* STC SPC, Rn */
nkeynes@359	484	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	485	check_priv();
nkeynes@359	486	load_spreg( R_EAX, R_SPC );
nkeynes@359	487	store_reg( R_EAX, Rn );
nkeynes@417	488	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	489	}
nkeynes@359	490	break;
nkeynes@359	491	default:
nkeynes@359	492	UNDEF();
nkeynes@359	493	break;
nkeynes@359	494	}
nkeynes@359	495	break;
nkeynes@359	496	case 0x1:
nkeynes@359	497	{ /* STC Rm_BANK, Rn */
nkeynes@359	498	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
nkeynes@386	499	check_priv();
nkeynes@374	500	load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374	501	store_reg( R_EAX, Rn );
nkeynes@417	502	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	503	}
nkeynes@359	504	break;
nkeynes@359	505	}
nkeynes@359	506	break;
nkeynes@359	507	case 0x3:
nkeynes@359	508	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	509	case 0x0:
nkeynes@359	510	{ /* BSRF Rn */
nkeynes@359	511	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	512	if( sh4_x86.in_delay_slot ) {
nkeynes@374	513	SLOTILLEGAL();
nkeynes@374	514	} else {
nkeynes@590	515	load_spreg( R_EAX, R_PC );
nkeynes@590	516	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590	517	store_spreg( R_EAX, R_PR );
nkeynes@590	518	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590	519	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590	520
nkeynes@601	521	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417	522	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	523	sh4_x86.branch_taken = TRUE;
nkeynes@601	524	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	525	exit_block_emu(pc+2);
nkeynes@601	526	return 2;
nkeynes@601	527	} else {
nkeynes@601	528	sh4_translate_instruction( pc + 2 );
nkeynes@601	529	exit_block_newpcset(pc+2);
nkeynes@601	530	return 4;
nkeynes@601	531	}
nkeynes@374	532	}
nkeynes@359	533	}
nkeynes@359	534	break;
nkeynes@359	535	case 0x2:
nkeynes@359	536	{ /* BRAF Rn */
nkeynes@359	537	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	538	if( sh4_x86.in_delay_slot ) {
nkeynes@374	539	SLOTILLEGAL();
nkeynes@374	540	} else {
nkeynes@590	541	load_spreg( R_EAX, R_PC );
nkeynes@590	542	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590	543	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590	544	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590	545	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417	546	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	547	sh4_x86.branch_taken = TRUE;
nkeynes@601	548	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	549	exit_block_emu(pc+2);
nkeynes@601	550	return 2;
nkeynes@601	551	} else {
nkeynes@601	552	sh4_translate_instruction( pc + 2 );
nkeynes@601	553	exit_block_newpcset(pc+2);
nkeynes@601	554	return 4;
nkeynes@601	555	}
nkeynes@374	556	}
nkeynes@359	557	}
nkeynes@359	558	break;
nkeynes@359	559	case 0x8:
nkeynes@359	560	{ /* PREF @Rn */
nkeynes@359	561	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	562	load_reg( R_EAX, Rn );
nkeynes@532	563	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374	564	AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374	565	CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586	566	JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532	567	call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586	568	TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586	569	JE_exc(-1);
nkeynes@380	570	JMP_TARGET(end);
nkeynes@417	571	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	572	}
nkeynes@359	573	break;
nkeynes@359	574	case 0x9:
nkeynes@359	575	{ /* OCBI @Rn */
nkeynes@359	576	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	577	}
nkeynes@359	578	break;
nkeynes@359	579	case 0xA:
nkeynes@359	580	{ /* OCBP @Rn */
nkeynes@359	581	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	582	}
nkeynes@359	583	break;
nkeynes@359	584	case 0xB:
nkeynes@359	585	{ /* OCBWB @Rn */
nkeynes@359	586	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	587	}
nkeynes@359	588	break;
nkeynes@359	589	case 0xC:
nkeynes@359	590	{ /* MOVCA.L R0, @Rn */
nkeynes@359	591	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	592	load_reg( R_EAX, Rn );
nkeynes@586	593	check_walign32( R_EAX );
nkeynes@586	594	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	595	load_reg( R_EDX, 0 );
nkeynes@586	596	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	597	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	598	}
nkeynes@359	599	break;
nkeynes@359	600	default:
nkeynes@359	601	UNDEF();
nkeynes@359	602	break;
nkeynes@359	603	}
nkeynes@359	604	break;
nkeynes@359	605	case 0x4:
nkeynes@359	606	{ /* MOV.B Rm, @(R0, Rn) */
nkeynes@359	607	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	608	load_reg( R_EAX, 0 );
nkeynes@359	609	load_reg( R_ECX, Rn );
nkeynes@586	610	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	611	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	612	load_reg( R_EDX, Rm );
nkeynes@586	613	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	614	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	615	}
nkeynes@359	616	break;
nkeynes@359	617	case 0x5:
nkeynes@359	618	{ /* MOV.W Rm, @(R0, Rn) */
nkeynes@359	619	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	620	load_reg( R_EAX, 0 );
nkeynes@361	621	load_reg( R_ECX, Rn );
nkeynes@586	622	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	623	check_walign16( R_EAX );
nkeynes@586	624	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	625	load_reg( R_EDX, Rm );
nkeynes@586	626	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	627	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	628	}
nkeynes@359	629	break;
nkeynes@359	630	case 0x6:
nkeynes@359	631	{ /* MOV.L Rm, @(R0, Rn) */
nkeynes@359	632	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	633	load_reg( R_EAX, 0 );
nkeynes@361	634	load_reg( R_ECX, Rn );
nkeynes@586	635	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	636	check_walign32( R_EAX );
nkeynes@586	637	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	638	load_reg( R_EDX, Rm );
nkeynes@586	639	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	640	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	641	}
nkeynes@359	642	break;
nkeynes@359	643	case 0x7:
nkeynes@359	644	{ /* MUL.L Rm, Rn */
nkeynes@359	645	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	646	load_reg( R_EAX, Rm );
nkeynes@361	647	load_reg( R_ECX, Rn );
nkeynes@361	648	MUL_r32( R_ECX );
nkeynes@361	649	store_spreg( R_EAX, R_MACL );
nkeynes@417	650	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	651	}
nkeynes@359	652	break;
nkeynes@359	653	case 0x8:
nkeynes@359	654	switch( (ir&0xFF0) >> 4 ) {
nkeynes@359	655	case 0x0:
nkeynes@359	656	{ /* CLRT */
nkeynes@374	657	CLC();
nkeynes@374	658	SETC_t();
nkeynes@417	659	sh4_x86.tstate = TSTATE_C;
nkeynes@359	660	}
nkeynes@359	661	break;
nkeynes@359	662	case 0x1:
nkeynes@359	663	{ /* SETT */
nkeynes@374	664	STC();
nkeynes@374	665	SETC_t();
nkeynes@417	666	sh4_x86.tstate = TSTATE_C;
nkeynes@359	667	}
nkeynes@359	668	break;
nkeynes@359	669	case 0x2:
nkeynes@359	670	{ /* CLRMAC */
nkeynes@374	671	XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374	672	store_spreg( R_EAX, R_MACL );
nkeynes@374	673	store_spreg( R_EAX, R_MACH );
nkeynes@417	674	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	675	}
nkeynes@359	676	break;
nkeynes@359	677	case 0x3:
nkeynes@359	678	{ /* LDTLB */
nkeynes@553	679	call_func0( MMU_ldtlb );
nkeynes@359	680	}
nkeynes@359	681	break;
nkeynes@359	682	case 0x4:
nkeynes@359	683	{ /* CLRS */
nkeynes@374	684	CLC();
nkeynes@374	685	SETC_sh4r(R_S);
nkeynes@417	686	sh4_x86.tstate = TSTATE_C;
nkeynes@359	687	}
nkeynes@359	688	break;
nkeynes@359	689	case 0x5:
nkeynes@359	690	{ /* SETS */
nkeynes@374	691	STC();
nkeynes@374	692	SETC_sh4r(R_S);
nkeynes@417	693	sh4_x86.tstate = TSTATE_C;
nkeynes@359	694	}
nkeynes@359	695	break;
nkeynes@359	696	default:
nkeynes@359	697	UNDEF();
nkeynes@359	698	break;
nkeynes@359	699	}
nkeynes@359	700	break;
nkeynes@359	701	case 0x9:
nkeynes@359	702	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	703	case 0x0:
nkeynes@359	704	{ /* NOP */
nkeynes@359	705	/* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359	706	}
nkeynes@359	707	break;
nkeynes@359	708	case 0x1:
nkeynes@359	709	{ /* DIV0U */
nkeynes@361	710	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361	711	store_spreg( R_EAX, R_Q );
nkeynes@361	712	store_spreg( R_EAX, R_M );
nkeynes@361	713	store_spreg( R_EAX, R_T );
nkeynes@417	714	sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359	715	}
nkeynes@359	716	break;
nkeynes@359	717	case 0x2:
nkeynes@359	718	{ /* MOVT Rn */
nkeynes@359	719	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	720	load_spreg( R_EAX, R_T );
nkeynes@359	721	store_reg( R_EAX, Rn );
nkeynes@359	722	}
nkeynes@359	723	break;
nkeynes@359	724	default:
nkeynes@359	725	UNDEF();
nkeynes@359	726	break;
nkeynes@359	727	}
nkeynes@359	728	break;
nkeynes@359	729	case 0xA:
nkeynes@359	730	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	731	case 0x0:
nkeynes@359	732	{ /* STS MACH, Rn */
nkeynes@359	733	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	734	load_spreg( R_EAX, R_MACH );
nkeynes@359	735	store_reg( R_EAX, Rn );
nkeynes@359	736	}
nkeynes@359	737	break;
nkeynes@359	738	case 0x1:
nkeynes@359	739	{ /* STS MACL, Rn */
nkeynes@359	740	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	741	load_spreg( R_EAX, R_MACL );
nkeynes@359	742	store_reg( R_EAX, Rn );
nkeynes@359	743	}
nkeynes@359	744	break;
nkeynes@359	745	case 0x2:
nkeynes@359	746	{ /* STS PR, Rn */
nkeynes@359	747	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	748	load_spreg( R_EAX, R_PR );
nkeynes@359	749	store_reg( R_EAX, Rn );
nkeynes@359	750	}
nkeynes@359	751	break;
nkeynes@359	752	case 0x3:
nkeynes@359	753	{ /* STC SGR, Rn */
nkeynes@359	754	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	755	check_priv();
nkeynes@359	756	load_spreg( R_EAX, R_SGR );
nkeynes@359	757	store_reg( R_EAX, Rn );
nkeynes@417	758	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	759	}
nkeynes@359	760	break;
nkeynes@359	761	case 0x5:
nkeynes@359	762	{ /* STS FPUL, Rn */
nkeynes@359	763	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@626	764	check_fpuen();
nkeynes@359	765	load_spreg( R_EAX, R_FPUL );
nkeynes@359	766	store_reg( R_EAX, Rn );
nkeynes@359	767	}
nkeynes@359	768	break;
nkeynes@359	769	case 0x6:
nkeynes@359	770	{ /* STS FPSCR, Rn */
nkeynes@359	771	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@626	772	check_fpuen();
nkeynes@359	773	load_spreg( R_EAX, R_FPSCR );
nkeynes@359	774	store_reg( R_EAX, Rn );
nkeynes@359	775	}
nkeynes@359	776	break;
nkeynes@359	777	case 0xF:
nkeynes@359	778	{ /* STC DBR, Rn */
nkeynes@359	779	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	780	check_priv();
nkeynes@359	781	load_spreg( R_EAX, R_DBR );
nkeynes@359	782	store_reg( R_EAX, Rn );
nkeynes@417	783	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	784	}
nkeynes@359	785	break;
nkeynes@359	786	default:
nkeynes@359	787	UNDEF();
nkeynes@359	788	break;
nkeynes@359	789	}
nkeynes@359	790	break;
nkeynes@359	791	case 0xB:
nkeynes@359	792	switch( (ir&0xFF0) >> 4 ) {
nkeynes@359	793	case 0x0:
nkeynes@359	794	{ /* RTS */
nkeynes@374	795	if( sh4_x86.in_delay_slot ) {
nkeynes@374	796	SLOTILLEGAL();
nkeynes@374	797	} else {
nkeynes@408	798	load_spreg( R_ECX, R_PR );
nkeynes@590	799	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590	800	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	801	sh4_x86.branch_taken = TRUE;
nkeynes@601	802	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	803	exit_block_emu(pc+2);
nkeynes@601	804	return 2;
nkeynes@601	805	} else {
nkeynes@601	806	sh4_translate_instruction(pc+2);
nkeynes@601	807	exit_block_newpcset(pc+2);
nkeynes@601	808	return 4;
nkeynes@601	809	}
nkeynes@374	810	}
nkeynes@359	811	}
nkeynes@359	812	break;
nkeynes@359	813	case 0x1:
nkeynes@359	814	{ /* SLEEP */
nkeynes@388	815	check_priv();
nkeynes@388	816	call_func0( sh4_sleep );
nkeynes@417	817	sh4_x86.tstate = TSTATE_NONE;
nkeynes@590	818	sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408	819	return 2;
nkeynes@359	820	}
nkeynes@359	821	break;
nkeynes@359	822	case 0x2:
nkeynes@359	823	{ /* RTE */
nkeynes@374	824	if( sh4_x86.in_delay_slot ) {
nkeynes@374	825	SLOTILLEGAL();
nkeynes@374	826	} else {
nkeynes@408	827	check_priv();
nkeynes@408	828	load_spreg( R_ECX, R_SPC );
nkeynes@590	829	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374	830	load_spreg( R_EAX, R_SSR );
nkeynes@374	831	call_func1( sh4_write_sr, R_EAX );
nkeynes@590	832	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377	833	sh4_x86.priv_checked = FALSE;
nkeynes@377	834	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	835	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	836	sh4_x86.branch_taken = TRUE;
nkeynes@601	837	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	838	exit_block_emu(pc+2);
nkeynes@601	839	return 2;
nkeynes@601	840	} else {
nkeynes@601	841	sh4_translate_instruction(pc+2);
nkeynes@601	842	exit_block_newpcset(pc+2);
nkeynes@601	843	return 4;
nkeynes@601	844	}
nkeynes@374	845	}
nkeynes@359	846	}
nkeynes@359	847	break;
nkeynes@359	848	default:
nkeynes@359	849	UNDEF();
nkeynes@359	850	break;
nkeynes@359	851	}
nkeynes@359	852	break;
nkeynes@359	853	case 0xC:
nkeynes@359	854	{ /* MOV.B @(R0, Rm), Rn */
nkeynes@359	855	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	856	load_reg( R_EAX, 0 );
nkeynes@359	857	load_reg( R_ECX, Rm );
nkeynes@586	858	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	859	MMU_TRANSLATE_READ( R_EAX )
nkeynes@586	860	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	861	store_reg( R_EAX, Rn );
nkeynes@417	862	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	863	}
nkeynes@359	864	break;
nkeynes@359	865	case 0xD:
nkeynes@359	866	{ /* MOV.W @(R0, Rm), Rn */
nkeynes@359	867	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	868	load_reg( R_EAX, 0 );
nkeynes@361	869	load_reg( R_ECX, Rm );
nkeynes@586	870	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	871	check_ralign16( R_EAX );
nkeynes@586	872	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	873	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	874	store_reg( R_EAX, Rn );
nkeynes@417	875	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	876	}
nkeynes@359	877	break;
nkeynes@359	878	case 0xE:
nkeynes@359	879	{ /* MOV.L @(R0, Rm), Rn */
nkeynes@359	880	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	881	load_reg( R_EAX, 0 );
nkeynes@361	882	load_reg( R_ECX, Rm );
nkeynes@586	883	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	884	check_ralign32( R_EAX );
nkeynes@586	885	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	886	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	887	store_reg( R_EAX, Rn );
nkeynes@417	888	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	889	}
nkeynes@359	890	break;
nkeynes@359	891	case 0xF:
nkeynes@359	892	{ /* MAC.L @Rm+, @Rn+ */
nkeynes@359	893	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	894	if( Rm == Rn ) {
nkeynes@586	895	load_reg( R_EAX, Rm );
nkeynes@586	896	check_ralign32( R_EAX );
nkeynes@586	897	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	898	PUSH_realigned_r32( R_EAX );
nkeynes@586	899	load_reg( R_EAX, Rn );
nkeynes@586	900	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596	901	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586	902	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586	903	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586	904	// adding a page-boundary check to skip the second translation
nkeynes@586	905	} else {
nkeynes@586	906	load_reg( R_EAX, Rm );
nkeynes@586	907	check_ralign32( R_EAX );
nkeynes@586	908	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596	909	load_reg( R_ECX, Rn );
nkeynes@596	910	check_ralign32( R_ECX );
nkeynes@586	911	PUSH_realigned_r32( R_EAX );
nkeynes@596	912	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596	913	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586	914	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586	915	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	916	}
nkeynes@586	917	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	918	POP_r32( R_ECX );
nkeynes@586	919	PUSH_r32( R_EAX );
nkeynes@386	920	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547	921	POP_realigned_r32( R_ECX );
nkeynes@586	922
nkeynes@386	923	IMUL_r32( R_ECX );
nkeynes@386	924	ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386	925	ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386	926
nkeynes@386	927	load_spreg( R_ECX, R_S );
nkeynes@386	928	TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527	929	JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386	930	call_func0( signsat48 );
nkeynes@386	931	JMP_TARGET( nosat );
nkeynes@417	932	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	933	}
nkeynes@359	934	break;
nkeynes@359	935	default:
nkeynes@359	936	UNDEF();
nkeynes@359	937	break;
nkeynes@359	938	}
nkeynes@359	939	break;
nkeynes@359	940	case 0x1:
nkeynes@359	941	{ /* MOV.L Rm, @(disp, Rn) */
nkeynes@359	942	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
nkeynes@586	943	load_reg( R_EAX, Rn );
nkeynes@586	944	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	945	check_walign32( R_EAX );
nkeynes@586	946	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	947	load_reg( R_EDX, Rm );
nkeynes@586	948	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	949	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	950	}
nkeynes@359	951	break;
nkeynes@359	952	case 0x2:
nkeynes@359	953	switch( ir&0xF ) {
nkeynes@359	954	case 0x0:
nkeynes@359	955	{ /* MOV.B Rm, @Rn */
nkeynes@359	956	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	957	load_reg( R_EAX, Rn );
nkeynes@586	958	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	959	load_reg( R_EDX, Rm );
nkeynes@586	960	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	961	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	962	}
nkeynes@359	963	break;
nkeynes@359	964	case 0x1:
nkeynes@359	965	{ /* MOV.W Rm, @Rn */
nkeynes@359	966	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	967	load_reg( R_EAX, Rn );
nkeynes@586	968	check_walign16( R_EAX );
nkeynes@586	969	MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586	970	load_reg( R_EDX, Rm );
nkeynes@586	971	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	972	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	973	}
nkeynes@359	974	break;
nkeynes@359	975	case 0x2:
nkeynes@359	976	{ /* MOV.L Rm, @Rn */
nkeynes@359	977	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	978	load_reg( R_EAX, Rn );
nkeynes@586	979	check_walign32(R_EAX);
nkeynes@586	980	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	981	load_reg( R_EDX, Rm );
nkeynes@586	982	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	983	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	984	}
nkeynes@359	985	break;
nkeynes@359	986	case 0x4:
nkeynes@359	987	{ /* MOV.B Rm, @-Rn */
nkeynes@359	988	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	989	load_reg( R_EAX, Rn );
nkeynes@586	990	ADD_imm8s_r32( -1, R_EAX );
nkeynes@586	991	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	992	load_reg( R_EDX, Rm );
nkeynes@586	993	ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586	994	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	995	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	996	}
nkeynes@359	997	break;
nkeynes@359	998	case 0x5:
nkeynes@359	999	{ /* MOV.W Rm, @-Rn */
nkeynes@359	1000	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	1001	load_reg( R_EAX, Rn );
nkeynes@586	1002	ADD_imm8s_r32( -2, R_EAX );
nkeynes@586	1003	check_walign16( R_EAX );
nkeynes@586	1004	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1005	load_reg( R_EDX, Rm );
nkeynes@586	1006	ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586	1007	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	1008	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1009	}
nkeynes@359	1010	break;
nkeynes@359	1011	case 0x6:
nkeynes@359	1012	{ /* MOV.L Rm, @-Rn */
nkeynes@359	1013	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	1014	load_reg( R_EAX, Rn );
nkeynes@586	1015	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1016	check_walign32( R_EAX );
nkeynes@586	1017	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1018	load_reg( R_EDX, Rm );
nkeynes@586	1019	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1020	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1021	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1022	}
nkeynes@359	1023	break;
nkeynes@359	1024	case 0x7:
nkeynes@359	1025	{ /* DIV0S Rm, Rn */
nkeynes@359	1026	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1027	load_reg( R_EAX, Rm );
nkeynes@386	1028	load_reg( R_ECX, Rn );
nkeynes@361	1029	SHR_imm8_r32( 31, R_EAX );
nkeynes@361	1030	SHR_imm8_r32( 31, R_ECX );
nkeynes@361	1031	store_spreg( R_EAX, R_M );
nkeynes@361	1032	store_spreg( R_ECX, R_Q );
nkeynes@361	1033	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386	1034	SETNE_t();
nkeynes@417	1035	sh4_x86.tstate = TSTATE_NE;
nkeynes@359	1036	}
nkeynes@359	1037	break;
nkeynes@359	1038	case 0x8:
nkeynes@359	1039	{ /* TST Rm, Rn */
nkeynes@359	1040	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1041	load_reg( R_EAX, Rm );
nkeynes@361	1042	load_reg( R_ECX, Rn );
nkeynes@361	1043	TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361	1044	SETE_t();
nkeynes@417	1045	sh4_x86.tstate = TSTATE_E;
nkeynes@359	1046	}
nkeynes@359	1047	break;
nkeynes@359	1048	case 0x9:
nkeynes@359	1049	{ /* AND Rm, Rn */
nkeynes@359	1050	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1051	load_reg( R_EAX, Rm );
nkeynes@359	1052	load_reg( R_ECX, Rn );
nkeynes@359	1053	AND_r32_r32( R_EAX, R_ECX );
nkeynes@359	1054	store_reg( R_ECX, Rn );
nkeynes@417	1055	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1056	}
nkeynes@359	1057	break;
nkeynes@359	1058	case 0xA:
nkeynes@359	1059	{ /* XOR Rm, Rn */
nkeynes@359	1060	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1061	load_reg( R_EAX, Rm );
nkeynes@359	1062	load_reg( R_ECX, Rn );
nkeynes@359	1063	XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1064	store_reg( R_ECX, Rn );
nkeynes@417	1065	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1066	}
nkeynes@359	1067	break;
nkeynes@359	1068	case 0xB:
nkeynes@359	1069	{ /* OR Rm, Rn */
nkeynes@359	1070	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1071	load_reg( R_EAX, Rm );
nkeynes@359	1072	load_reg( R_ECX, Rn );
nkeynes@359	1073	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1074	store_reg( R_ECX, Rn );
nkeynes@417	1075	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1076	}
nkeynes@359	1077	break;
nkeynes@359	1078	case 0xC:
nkeynes@359	1079	{ /* CMP/STR Rm, Rn */
nkeynes@359	1080	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@368	1081	load_reg( R_EAX, Rm );
nkeynes@368	1082	load_reg( R_ECX, Rn );
nkeynes@368	1083	XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368	1084	TEST_r8_r8( R_AL, R_AL );
nkeynes@380	1085	JE_rel8(13, target1);
nkeynes@368	1086	TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380	1087	JE_rel8(9, target2);
nkeynes@368	1088	SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368	1089	TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380	1090	JE_rel8(2, target3);
nkeynes@368	1091	TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380	1092	JMP_TARGET(target1);
nkeynes@380	1093	JMP_TARGET(target2);
nkeynes@380	1094	JMP_TARGET(target3);
nkeynes@368	1095	SETE_t();
nkeynes@417	1096	sh4_x86.tstate = TSTATE_E;
nkeynes@359	1097	}
nkeynes@359	1098	break;
nkeynes@359	1099	case 0xD:
nkeynes@359	1100	{ /* XTRCT Rm, Rn */
nkeynes@359	1101	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1102	load_reg( R_EAX, Rm );
nkeynes@394	1103	load_reg( R_ECX, Rn );
nkeynes@394	1104	SHL_imm8_r32( 16, R_EAX );
nkeynes@394	1105	SHR_imm8_r32( 16, R_ECX );
nkeynes@361	1106	OR_r32_r32( R_EAX, R_ECX );
nkeynes@361	1107	store_reg( R_ECX, Rn );
nkeynes@417	1108	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1109	}
nkeynes@359	1110	break;
nkeynes@359	1111	case 0xE:
nkeynes@359	1112	{ /* MULU.W Rm, Rn */
nkeynes@359	1113	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@374	1114	load_reg16u( R_EAX, Rm );
nkeynes@374	1115	load_reg16u( R_ECX, Rn );
nkeynes@374	1116	MUL_r32( R_ECX );
nkeynes@374	1117	store_spreg( R_EAX, R_MACL );
nkeynes@417	1118	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1119	}
nkeynes@359	1120	break;
nkeynes@359	1121	case 0xF:
nkeynes@359	1122	{ /* MULS.W Rm, Rn */
nkeynes@359	1123	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@374	1124	load_reg16s( R_EAX, Rm );
nkeynes@374	1125	load_reg16s( R_ECX, Rn );
nkeynes@374	1126	MUL_r32( R_ECX );
nkeynes@374	1127	store_spreg( R_EAX, R_MACL );
nkeynes@417	1128	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1129	}
nkeynes@359	1130	break;
nkeynes@359	1131	default:
nkeynes@359	1132	UNDEF();
nkeynes@359	1133	break;
nkeynes@359	1134	}
nkeynes@359	1135	break;
nkeynes@359	1136	case 0x3:
nkeynes@359	1137	switch( ir&0xF ) {
nkeynes@359	1138	case 0x0:
nkeynes@359	1139	{ /* CMP/EQ Rm, Rn */
nkeynes@359	1140	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1141	load_reg( R_EAX, Rm );
nkeynes@359	1142	load_reg( R_ECX, Rn );
nkeynes@359	1143	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1144	SETE_t();
nkeynes@417	1145	sh4_x86.tstate = TSTATE_E;
nkeynes@359	1146	}
nkeynes@359	1147	break;
nkeynes@359	1148	case 0x2:
nkeynes@359	1149	{ /* CMP/HS Rm, Rn */
nkeynes@359	1150	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1151	load_reg( R_EAX, Rm );
nkeynes@359	1152	load_reg( R_ECX, Rn );
nkeynes@359	1153	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1154	SETAE_t();
nkeynes@417	1155	sh4_x86.tstate = TSTATE_AE;
nkeynes@359	1156	}
nkeynes@359	1157	break;
nkeynes@359	1158	case 0x3:
nkeynes@359	1159	{ /* CMP/GE Rm, Rn */
nkeynes@359	1160	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1161	load_reg( R_EAX, Rm );
nkeynes@359	1162	load_reg( R_ECX, Rn );
nkeynes@359	1163	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1164	SETGE_t();
nkeynes@417	1165	sh4_x86.tstate = TSTATE_GE;
nkeynes@359	1166	}
nkeynes@359	1167	break;
nkeynes@359	1168	case 0x4:
nkeynes@359	1169	{ /* DIV1 Rm, Rn */
nkeynes@359	1170	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@386	1171	load_spreg( R_ECX, R_M );
nkeynes@386	1172	load_reg( R_EAX, Rn );
nkeynes@417	1173	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	1174	LDC_t();
nkeynes@417	1175	}
nkeynes@386	1176	RCL1_r32( R_EAX );
nkeynes@386	1177	SETC_r8( R_DL ); // Q'
nkeynes@386	1178	CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386	1179	JE_rel8(5, mqequal);
nkeynes@386	1180	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386	1181	JMP_rel8(3, end);
nkeynes@380	1182	JMP_TARGET(mqequal);
nkeynes@386	1183	SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386	1184	JMP_TARGET(end);
nkeynes@386	1185	store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386	1186	SETC_r8(R_AL); // tmp1
nkeynes@386	1187	XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386	1188	XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386	1189	store_spreg( R_ECX, R_Q );
nkeynes@386	1190	XOR_imm8s_r32( 1, R_AL ); // T = !Q'
nkeynes@386	1191	MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386	1192	store_spreg( R_EAX, R_T );
nkeynes@417	1193	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1194	}
nkeynes@359	1195	break;
nkeynes@359	1196	case 0x5:
nkeynes@359	1197	{ /* DMULU.L Rm, Rn */
nkeynes@359	1198	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1199	load_reg( R_EAX, Rm );
nkeynes@361	1200	load_reg( R_ECX, Rn );
nkeynes@361	1201	MUL_r32(R_ECX);
nkeynes@361	1202	store_spreg( R_EDX, R_MACH );
nkeynes@417	1203	store_spreg( R_EAX, R_MACL );
nkeynes@417	1204	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1205	}
nkeynes@359	1206	break;
nkeynes@359	1207	case 0x6:
nkeynes@359	1208	{ /* CMP/HI Rm, Rn */
nkeynes@359	1209	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1210	load_reg( R_EAX, Rm );
nkeynes@359	1211	load_reg( R_ECX, Rn );
nkeynes@359	1212	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1213	SETA_t();
nkeynes@417	1214	sh4_x86.tstate = TSTATE_A;
nkeynes@359	1215	}
nkeynes@359	1216	break;
nkeynes@359	1217	case 0x7:
nkeynes@359	1218	{ /* CMP/GT Rm, Rn */
nkeynes@359	1219	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1220	load_reg( R_EAX, Rm );
nkeynes@359	1221	load_reg( R_ECX, Rn );
nkeynes@359	1222	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1223	SETG_t();
nkeynes@417	1224	sh4_x86.tstate = TSTATE_G;
nkeynes@359	1225	}
nkeynes@359	1226	break;
nkeynes@359	1227	case 0x8:
nkeynes@359	1228	{ /* SUB Rm, Rn */
nkeynes@359	1229	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1230	load_reg( R_EAX, Rm );
nkeynes@359	1231	load_reg( R_ECX, Rn );
nkeynes@359	1232	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1233	store_reg( R_ECX, Rn );
nkeynes@417	1234	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1235	}
nkeynes@359	1236	break;
nkeynes@359	1237	case 0xA:
nkeynes@359	1238	{ /* SUBC Rm, Rn */
nkeynes@359	1239	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1240	load_reg( R_EAX, Rm );
nkeynes@359	1241	load_reg( R_ECX, Rn );
nkeynes@417	1242	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	1243	LDC_t();
nkeynes@417	1244	}
nkeynes@359	1245	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1246	store_reg( R_ECX, Rn );
nkeynes@394	1247	SETC_t();
nkeynes@417	1248	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1249	}
nkeynes@359	1250	break;
nkeynes@359	1251	case 0xB:
nkeynes@359	1252	{ /* SUBV Rm, Rn */
nkeynes@359	1253	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1254	load_reg( R_EAX, Rm );
nkeynes@359	1255	load_reg( R_ECX, Rn );
nkeynes@359	1256	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1257	store_reg( R_ECX, Rn );
nkeynes@359	1258	SETO_t();
nkeynes@417	1259	sh4_x86.tstate = TSTATE_O;
nkeynes@359	1260	}
nkeynes@359	1261	break;
nkeynes@359	1262	case 0xC:
nkeynes@359	1263	{ /* ADD Rm, Rn */
nkeynes@359	1264	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1265	load_reg( R_EAX, Rm );
nkeynes@359	1266	load_reg( R_ECX, Rn );
nkeynes@359	1267	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	1268	store_reg( R_ECX, Rn );
nkeynes@417	1269	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1270	}
nkeynes@359	1271	break;
nkeynes@359	1272	case 0xD:
nkeynes@359	1273	{ /* DMULS.L Rm, Rn */
nkeynes@359	1274	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1275	load_reg( R_EAX, Rm );
nkeynes@361	1276	load_reg( R_ECX, Rn );
nkeynes@361	1277	IMUL_r32(R_ECX);
nkeynes@361	1278	store_spreg( R_EDX, R_MACH );
nkeynes@361	1279	store_spreg( R_EAX, R_MACL );
nkeynes@417	1280	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1281	}
nkeynes@359	1282	break;
nkeynes@359	1283	case 0xE:
nkeynes@359	1284	{ /* ADDC Rm, Rn */
nkeynes@359	1285	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@417	1286	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	1287	LDC_t();
nkeynes@417	1288	}
nkeynes@359	1289	load_reg( R_EAX, Rm );
nkeynes@359	1290	load_reg( R_ECX, Rn );
nkeynes@359	1291	ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359	1292	store_reg( R_ECX, Rn );
nkeynes@359	1293	SETC_t();
nkeynes@417	1294	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1295	}
nkeynes@359	1296	break;
nkeynes@359	1297	case 0xF:
nkeynes@359	1298	{ /* ADDV Rm, Rn */
nkeynes@359	1299	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1300	load_reg( R_EAX, Rm );
nkeynes@359	1301	load_reg( R_ECX, Rn );
nkeynes@359	1302	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	1303	store_reg( R_ECX, Rn );
nkeynes@359	1304	SETO_t();
nkeynes@417	1305	sh4_x86.tstate = TSTATE_O;
nkeynes@359	1306	}
nkeynes@359	1307	break;
nkeynes@359	1308	default:
nkeynes@359	1309	UNDEF();
nkeynes@359	1310	break;
nkeynes@359	1311	}
nkeynes@359	1312	break;
nkeynes@359	1313	case 0x4:
nkeynes@359	1314	switch( ir&0xF ) {
nkeynes@359	1315	case 0x0:
nkeynes@359	1316	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1317	case 0x0:
nkeynes@359	1318	{ /* SHLL Rn */
nkeynes@359	1319	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1320	load_reg( R_EAX, Rn );
nkeynes@359	1321	SHL1_r32( R_EAX );
nkeynes@397	1322	SETC_t();
nkeynes@359	1323	store_reg( R_EAX, Rn );
nkeynes@417	1324	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1325	}
nkeynes@359	1326	break;
nkeynes@359	1327	case 0x1:
nkeynes@359	1328	{ /* DT Rn */
nkeynes@359	1329	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1330	load_reg( R_EAX, Rn );
nkeynes@386	1331	ADD_imm8s_r32( -1, R_EAX );
nkeynes@359	1332	store_reg( R_EAX, Rn );
nkeynes@359	1333	SETE_t();
nkeynes@417	1334	sh4_x86.tstate = TSTATE_E;
nkeynes@359	1335	}
nkeynes@359	1336	break;
nkeynes@359	1337	case 0x2:
nkeynes@359	1338	{ /* SHAL Rn */
nkeynes@359	1339	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1340	load_reg( R_EAX, Rn );
nkeynes@359	1341	SHL1_r32( R_EAX );
nkeynes@397	1342	SETC_t();
nkeynes@359	1343	store_reg( R_EAX, Rn );
nkeynes@417	1344	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1345	}
nkeynes@359	1346	break;
nkeynes@359	1347	default:
nkeynes@359	1348	UNDEF();
nkeynes@359	1349	break;
nkeynes@359	1350	}
nkeynes@359	1351	break;
nkeynes@359	1352	case 0x1:
nkeynes@359	1353	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1354	case 0x0:
nkeynes@359	1355	{ /* SHLR Rn */
nkeynes@359	1356	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1357	load_reg( R_EAX, Rn );
nkeynes@359	1358	SHR1_r32( R_EAX );
nkeynes@397	1359	SETC_t();
nkeynes@359	1360	store_reg( R_EAX, Rn );
nkeynes@417	1361	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1362	}
nkeynes@359	1363	break;
nkeynes@359	1364	case 0x1:
nkeynes@359	1365	{ /* CMP/PZ Rn */
nkeynes@359	1366	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1367	load_reg( R_EAX, Rn );
nkeynes@359	1368	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	1369	SETGE_t();
nkeynes@417	1370	sh4_x86.tstate = TSTATE_GE;
nkeynes@359	1371	}
nkeynes@359	1372	break;
nkeynes@359	1373	case 0x2:
nkeynes@359	1374	{ /* SHAR Rn */
nkeynes@359	1375	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1376	load_reg( R_EAX, Rn );
nkeynes@359	1377	SAR1_r32( R_EAX );
nkeynes@397	1378	SETC_t();
nkeynes@359	1379	store_reg( R_EAX, Rn );
nkeynes@417	1380	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1381	}
nkeynes@359	1382	break;
nkeynes@359	1383	default:
nkeynes@359	1384	UNDEF();
nkeynes@359	1385	break;
nkeynes@359	1386	}
nkeynes@359	1387	break;
nkeynes@359	1388	case 0x2:
nkeynes@359	1389	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1390	case 0x0:
nkeynes@359	1391	{ /* STS.L MACH, @-Rn */
nkeynes@359	1392	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1393	load_reg( R_EAX, Rn );
nkeynes@586	1394	check_walign32( R_EAX );
nkeynes@586	1395	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1396	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1397	load_spreg( R_EDX, R_MACH );
nkeynes@586	1398	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1399	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1400	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1401	}
nkeynes@359	1402	break;
nkeynes@359	1403	case 0x1:
nkeynes@359	1404	{ /* STS.L MACL, @-Rn */
nkeynes@359	1405	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1406	load_reg( R_EAX, Rn );
nkeynes@586	1407	check_walign32( R_EAX );
nkeynes@586	1408	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1409	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1410	load_spreg( R_EDX, R_MACL );
nkeynes@586	1411	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1412	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1413	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1414	}
nkeynes@359	1415	break;
nkeynes@359	1416	case 0x2:
nkeynes@359	1417	{ /* STS.L PR, @-Rn */
nkeynes@359	1418	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1419	load_reg( R_EAX, Rn );
nkeynes@586	1420	check_walign32( R_EAX );
nkeynes@586	1421	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1422	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1423	load_spreg( R_EDX, R_PR );
nkeynes@586	1424	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1425	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1426	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1427	}
nkeynes@359	1428	break;
nkeynes@359	1429	case 0x3:
nkeynes@359	1430	{ /* STC.L SGR, @-Rn */
nkeynes@359	1431	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1432	check_priv();
nkeynes@586	1433	load_reg( R_EAX, Rn );
nkeynes@586	1434	check_walign32( R_EAX );
nkeynes@586	1435	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1436	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1437	load_spreg( R_EDX, R_SGR );
nkeynes@586	1438	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1439	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1440	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1441	}
nkeynes@359	1442	break;
nkeynes@359	1443	case 0x5:
nkeynes@359	1444	{ /* STS.L FPUL, @-Rn */
nkeynes@359	1445	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@626	1446	check_fpuen();
nkeynes@586	1447	load_reg( R_EAX, Rn );
nkeynes@586	1448	check_walign32( R_EAX );
nkeynes@586	1449	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1450	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1451	load_spreg( R_EDX, R_FPUL );
nkeynes@586	1452	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1453	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1454	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1455	}
nkeynes@359	1456	break;
nkeynes@359	1457	case 0x6:
nkeynes@359	1458	{ /* STS.L FPSCR, @-Rn */
nkeynes@359	1459	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@626	1460	check_fpuen();
nkeynes@586	1461	load_reg( R_EAX, Rn );
nkeynes@586	1462	check_walign32( R_EAX );
nkeynes@586	1463	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1464	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1465	load_spreg( R_EDX, R_FPSCR );
nkeynes@586	1466	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1467	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1468	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1469	}
nkeynes@359	1470	break;
nkeynes@359	1471	case 0xF:
nkeynes@359	1472	{ /* STC.L DBR, @-Rn */
nkeynes@359	1473	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1474	check_priv();
nkeynes@586	1475	load_reg( R_EAX, Rn );
nkeynes@586	1476	check_walign32( R_EAX );
nkeynes@586	1477	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1478	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1479	load_spreg( R_EDX, R_DBR );
nkeynes@586	1480	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1481	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1482	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1483	}
nkeynes@359	1484	break;
nkeynes@359	1485	default:
nkeynes@359	1486	UNDEF();
nkeynes@359	1487	break;
nkeynes@359	1488	}
nkeynes@359	1489	break;
nkeynes@359	1490	case 0x3:
nkeynes@359	1491	switch( (ir&0x80) >> 7 ) {
nkeynes@359	1492	case 0x0:
nkeynes@359	1493	switch( (ir&0x70) >> 4 ) {
nkeynes@359	1494	case 0x0:
nkeynes@359	1495	{ /* STC.L SR, @-Rn */
nkeynes@359	1496	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1497	check_priv();
nkeynes@586	1498	load_reg( R_EAX, Rn );
nkeynes@586	1499	check_walign32( R_EAX );
nkeynes@586	1500	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1501	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1502	PUSH_realigned_r32( R_EAX );
nkeynes@395	1503	call_func0( sh4_read_sr );
nkeynes@586	1504	POP_realigned_r32( R_ECX );
nkeynes@586	1505	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374	1506	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417	1507	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1508	}
nkeynes@359	1509	break;
nkeynes@359	1510	case 0x1:
nkeynes@359	1511	{ /* STC.L GBR, @-Rn */
nkeynes@359	1512	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1513	load_reg( R_EAX, Rn );
nkeynes@586	1514	check_walign32( R_EAX );
nkeynes@586	1515	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1516	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1517	load_spreg( R_EDX, R_GBR );
nkeynes@586	1518	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1519	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1520	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1521	}
nkeynes@359	1522	break;
nkeynes@359	1523	case 0x2:
nkeynes@359	1524	{ /* STC.L VBR, @-Rn */
nkeynes@359	1525	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1526	check_priv();
nkeynes@586	1527	load_reg( R_EAX, Rn );
nkeynes@586	1528	check_walign32( R_EAX );
nkeynes@586	1529	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1530	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1531	load_spreg( R_EDX, R_VBR );
nkeynes@586	1532	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1533	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1534	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1535	}
nkeynes@359	1536	break;
nkeynes@359	1537	case 0x3:
nkeynes@359	1538	{ /* STC.L SSR, @-Rn */
nkeynes@359	1539	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1540	check_priv();
nkeynes@586	1541	load_reg( R_EAX, Rn );
nkeynes@586	1542	check_walign32( R_EAX );
nkeynes@586	1543	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1544	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1545	load_spreg( R_EDX, R_SSR );
nkeynes@586	1546	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1547	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1548	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1549	}
nkeynes@359	1550	break;
nkeynes@359	1551	case 0x4:
nkeynes@359	1552	{ /* STC.L SPC, @-Rn */
nkeynes@359	1553	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	1554	check_priv();
nkeynes@586	1555	load_reg( R_EAX, Rn );
nkeynes@586	1556	check_walign32( R_EAX );
nkeynes@586	1557	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1558	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1559	load_spreg( R_EDX, R_SPC );
nkeynes@586	1560	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1561	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1562	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1563	}
nkeynes@359	1564	break;
nkeynes@359	1565	default:
nkeynes@359	1566	UNDEF();
nkeynes@359	1567	break;
nkeynes@359	1568	}
nkeynes@359	1569	break;
nkeynes@359	1570	case 0x1:
nkeynes@359	1571	{ /* STC.L Rm_BANK, @-Rn */
nkeynes@359	1572	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
nkeynes@586	1573	check_priv();
nkeynes@586	1574	load_reg( R_EAX, Rn );
nkeynes@586	1575	check_walign32( R_EAX );
nkeynes@586	1576	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1577	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	1578	load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586	1579	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586	1580	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1581	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1582	}
nkeynes@359	1583	break;
nkeynes@359	1584	}
nkeynes@359	1585	break;
nkeynes@359	1586	case 0x4:
nkeynes@359	1587	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1588	case 0x0:
nkeynes@359	1589	{ /* ROTL Rn */
nkeynes@359	1590	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1591	load_reg( R_EAX, Rn );
nkeynes@359	1592	ROL1_r32( R_EAX );
nkeynes@359	1593	store_reg( R_EAX, Rn );
nkeynes@359	1594	SETC_t();
nkeynes@417	1595	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1596	}
nkeynes@359	1597	break;
nkeynes@359	1598	case 0x2:
nkeynes@359	1599	{ /* ROTCL Rn */
nkeynes@359	1600	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1601	load_reg( R_EAX, Rn );
nkeynes@417	1602	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	1603	LDC_t();
nkeynes@417	1604	}
nkeynes@359	1605	RCL1_r32( R_EAX );
nkeynes@359	1606	store_reg( R_EAX, Rn );
nkeynes@359	1607	SETC_t();
nkeynes@417	1608	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1609	}
nkeynes@359	1610	break;
nkeynes@359	1611	default:
nkeynes@359	1612	UNDEF();
nkeynes@359	1613	break;
nkeynes@359	1614	}
nkeynes@359	1615	break;
nkeynes@359	1616	case 0x5:
nkeynes@359	1617	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1618	case 0x0:
nkeynes@359	1619	{ /* ROTR Rn */
nkeynes@359	1620	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1621	load_reg( R_EAX, Rn );
nkeynes@359	1622	ROR1_r32( R_EAX );
nkeynes@359	1623	store_reg( R_EAX, Rn );
nkeynes@359	1624	SETC_t();
nkeynes@417	1625	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1626	}
nkeynes@359	1627	break;
nkeynes@359	1628	case 0x1:
nkeynes@359	1629	{ /* CMP/PL Rn */
nkeynes@359	1630	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1631	load_reg( R_EAX, Rn );
nkeynes@359	1632	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	1633	SETG_t();
nkeynes@417	1634	sh4_x86.tstate = TSTATE_G;
nkeynes@359	1635	}
nkeynes@359	1636	break;
nkeynes@359	1637	case 0x2:
nkeynes@359	1638	{ /* ROTCR Rn */
nkeynes@359	1639	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1640	load_reg( R_EAX, Rn );
nkeynes@417	1641	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	1642	LDC_t();
nkeynes@417	1643	}
nkeynes@359	1644	RCR1_r32( R_EAX );
nkeynes@359	1645	store_reg( R_EAX, Rn );
nkeynes@359	1646	SETC_t();
nkeynes@417	1647	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1648	}
nkeynes@359	1649	break;
nkeynes@359	1650	default:
nkeynes@359	1651	UNDEF();
nkeynes@359	1652	break;
nkeynes@359	1653	}
nkeynes@359	1654	break;
nkeynes@359	1655	case 0x6:
nkeynes@359	1656	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1657	case 0x0:
nkeynes@359	1658	{ /* LDS.L @Rm+, MACH */
nkeynes@359	1659	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1660	load_reg( R_EAX, Rm );
nkeynes@395	1661	check_ralign32( R_EAX );
nkeynes@586	1662	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1663	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1664	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1665	store_spreg( R_EAX, R_MACH );
nkeynes@417	1666	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1667	}
nkeynes@359	1668	break;
nkeynes@359	1669	case 0x1:
nkeynes@359	1670	{ /* LDS.L @Rm+, MACL */
nkeynes@359	1671	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1672	load_reg( R_EAX, Rm );
nkeynes@395	1673	check_ralign32( R_EAX );
nkeynes@586	1674	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1675	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1676	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1677	store_spreg( R_EAX, R_MACL );
nkeynes@417	1678	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1679	}
nkeynes@359	1680	break;
nkeynes@359	1681	case 0x2:
nkeynes@359	1682	{ /* LDS.L @Rm+, PR */
nkeynes@359	1683	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1684	load_reg( R_EAX, Rm );
nkeynes@395	1685	check_ralign32( R_EAX );
nkeynes@586	1686	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1687	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1688	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1689	store_spreg( R_EAX, R_PR );
nkeynes@417	1690	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1691	}
nkeynes@359	1692	break;
nkeynes@359	1693	case 0x3:
nkeynes@359	1694	{ /* LDC.L @Rm+, SGR */
nkeynes@359	1695	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@586	1696	check_priv();
nkeynes@359	1697	load_reg( R_EAX, Rm );
nkeynes@395	1698	check_ralign32( R_EAX );
nkeynes@586	1699	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1700	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1701	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1702	store_spreg( R_EAX, R_SGR );
nkeynes@417	1703	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1704	}
nkeynes@359	1705	break;
nkeynes@359	1706	case 0x5:
nkeynes@359	1707	{ /* LDS.L @Rm+, FPUL */
nkeynes@359	1708	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@626	1709	check_fpuen();
nkeynes@359	1710	load_reg( R_EAX, Rm );
nkeynes@395	1711	check_ralign32( R_EAX );
nkeynes@586	1712	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1713	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1714	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1715	store_spreg( R_EAX, R_FPUL );
nkeynes@417	1716	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1717	}
nkeynes@359	1718	break;
nkeynes@359	1719	case 0x6:
nkeynes@359	1720	{ /* LDS.L @Rm+, FPSCR */
nkeynes@359	1721	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@626	1722	check_fpuen();
nkeynes@359	1723	load_reg( R_EAX, Rm );
nkeynes@395	1724	check_ralign32( R_EAX );
nkeynes@586	1725	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1726	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1727	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1728	store_spreg( R_EAX, R_FPSCR );
nkeynes@386	1729	update_fr_bank( R_EAX );
nkeynes@417	1730	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1731	}
nkeynes@359	1732	break;
nkeynes@359	1733	case 0xF:
nkeynes@359	1734	{ /* LDC.L @Rm+, DBR */
nkeynes@359	1735	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@586	1736	check_priv();
nkeynes@359	1737	load_reg( R_EAX, Rm );
nkeynes@395	1738	check_ralign32( R_EAX );
nkeynes@586	1739	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1740	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1741	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1742	store_spreg( R_EAX, R_DBR );
nkeynes@417	1743	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1744	}
nkeynes@359	1745	break;
nkeynes@359	1746	default:
nkeynes@359	1747	UNDEF();
nkeynes@359	1748	break;
nkeynes@359	1749	}
nkeynes@359	1750	break;
nkeynes@359	1751	case 0x7:
nkeynes@359	1752	switch( (ir&0x80) >> 7 ) {
nkeynes@359	1753	case 0x0:
nkeynes@359	1754	switch( (ir&0x70) >> 4 ) {
nkeynes@359	1755	case 0x0:
nkeynes@359	1756	{ /* LDC.L @Rm+, SR */
nkeynes@359	1757	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1758	if( sh4_x86.in_delay_slot ) {
nkeynes@386	1759	SLOTILLEGAL();
nkeynes@386	1760	} else {
nkeynes@586	1761	check_priv();
nkeynes@386	1762	load_reg( R_EAX, Rm );
nkeynes@395	1763	check_ralign32( R_EAX );
nkeynes@586	1764	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1765	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1766	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386	1767	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	1768	sh4_x86.priv_checked = FALSE;
nkeynes@386	1769	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	1770	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386	1771	}
nkeynes@359	1772	}
nkeynes@359	1773	break;
nkeynes@359	1774	case 0x1:
nkeynes@359	1775	{ /* LDC.L @Rm+, GBR */
nkeynes@359	1776	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1777	load_reg( R_EAX, Rm );
nkeynes@395	1778	check_ralign32( R_EAX );
nkeynes@586	1779	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1780	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1781	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1782	store_spreg( R_EAX, R_GBR );
nkeynes@417	1783	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1784	}
nkeynes@359	1785	break;
nkeynes@359	1786	case 0x2:
nkeynes@359	1787	{ /* LDC.L @Rm+, VBR */
nkeynes@359	1788	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@586	1789	check_priv();
nkeynes@359	1790	load_reg( R_EAX, Rm );
nkeynes@395	1791	check_ralign32( R_EAX );
nkeynes@586	1792	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1793	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1794	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1795	store_spreg( R_EAX, R_VBR );
nkeynes@417	1796	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1797	}
nkeynes@359	1798	break;
nkeynes@359	1799	case 0x3:
nkeynes@359	1800	{ /* LDC.L @Rm+, SSR */
nkeynes@359	1801	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@586	1802	check_priv();
nkeynes@359	1803	load_reg( R_EAX, Rm );
nkeynes@416	1804	check_ralign32( R_EAX );
nkeynes@586	1805	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1806	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1807	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1808	store_spreg( R_EAX, R_SSR );
nkeynes@417	1809	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1810	}
nkeynes@359	1811	break;
nkeynes@359	1812	case 0x4:
nkeynes@359	1813	{ /* LDC.L @Rm+, SPC */
nkeynes@359	1814	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@586	1815	check_priv();
nkeynes@359	1816	load_reg( R_EAX, Rm );
nkeynes@395	1817	check_ralign32( R_EAX );
nkeynes@586	1818	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1819	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1820	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359	1821	store_spreg( R_EAX, R_SPC );
nkeynes@417	1822	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1823	}
nkeynes@359	1824	break;
nkeynes@359	1825	default:
nkeynes@359	1826	UNDEF();
nkeynes@359	1827	break;
nkeynes@359	1828	}
nkeynes@359	1829	break;
nkeynes@359	1830	case 0x1:
nkeynes@359	1831	{ /* LDC.L @Rm+, Rn_BANK */
nkeynes@359	1832	uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
nkeynes@586	1833	check_priv();
nkeynes@374	1834	load_reg( R_EAX, Rm );
nkeynes@395	1835	check_ralign32( R_EAX );
nkeynes@586	1836	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	1837	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	1838	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374	1839	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417	1840	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1841	}
nkeynes@359	1842	break;
nkeynes@359	1843	}
nkeynes@359	1844	break;
nkeynes@359	1845	case 0x8:
nkeynes@359	1846	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1847	case 0x0:
nkeynes@359	1848	{ /* SHLL2 Rn */
nkeynes@359	1849	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1850	load_reg( R_EAX, Rn );
nkeynes@359	1851	SHL_imm8_r32( 2, R_EAX );
nkeynes@359	1852	store_reg( R_EAX, Rn );
nkeynes@417	1853	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1854	}
nkeynes@359	1855	break;
nkeynes@359	1856	case 0x1:
nkeynes@359	1857	{ /* SHLL8 Rn */
nkeynes@359	1858	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1859	load_reg( R_EAX, Rn );
nkeynes@359	1860	SHL_imm8_r32( 8, R_EAX );
nkeynes@359	1861	store_reg( R_EAX, Rn );
nkeynes@417	1862	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1863	}
nkeynes@359	1864	break;
nkeynes@359	1865	case 0x2:
nkeynes@359	1866	{ /* SHLL16 Rn */
nkeynes@359	1867	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1868	load_reg( R_EAX, Rn );
nkeynes@359	1869	SHL_imm8_r32( 16, R_EAX );
nkeynes@359	1870	store_reg( R_EAX, Rn );
nkeynes@417	1871	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1872	}
nkeynes@359	1873	break;
nkeynes@359	1874	default:
nkeynes@359	1875	UNDEF();
nkeynes@359	1876	break;
nkeynes@359	1877	}
nkeynes@359	1878	break;
nkeynes@359	1879	case 0x9:
nkeynes@359	1880	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1881	case 0x0:
nkeynes@359	1882	{ /* SHLR2 Rn */
nkeynes@359	1883	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1884	load_reg( R_EAX, Rn );
nkeynes@359	1885	SHR_imm8_r32( 2, R_EAX );
nkeynes@359	1886	store_reg( R_EAX, Rn );
nkeynes@417	1887	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1888	}
nkeynes@359	1889	break;
nkeynes@359	1890	case 0x1:
nkeynes@359	1891	{ /* SHLR8 Rn */
nkeynes@359	1892	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1893	load_reg( R_EAX, Rn );
nkeynes@359	1894	SHR_imm8_r32( 8, R_EAX );
nkeynes@359	1895	store_reg( R_EAX, Rn );
nkeynes@417	1896	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1897	}
nkeynes@359	1898	break;
nkeynes@359	1899	case 0x2:
nkeynes@359	1900	{ /* SHLR16 Rn */
nkeynes@359	1901	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1902	load_reg( R_EAX, Rn );
nkeynes@359	1903	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	1904	store_reg( R_EAX, Rn );
nkeynes@417	1905	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1906	}
nkeynes@359	1907	break;
nkeynes@359	1908	default:
nkeynes@359	1909	UNDEF();
nkeynes@359	1910	break;
nkeynes@359	1911	}
nkeynes@359	1912	break;
nkeynes@359	1913	case 0xA:
nkeynes@359	1914	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1915	case 0x0:
nkeynes@359	1916	{ /* LDS Rm, MACH */
nkeynes@359	1917	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1918	load_reg( R_EAX, Rm );
nkeynes@359	1919	store_spreg( R_EAX, R_MACH );
nkeynes@359	1920	}
nkeynes@359	1921	break;
nkeynes@359	1922	case 0x1:
nkeynes@359	1923	{ /* LDS Rm, MACL */
nkeynes@359	1924	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1925	load_reg( R_EAX, Rm );
nkeynes@359	1926	store_spreg( R_EAX, R_MACL );
nkeynes@359	1927	}
nkeynes@359	1928	break;
nkeynes@359	1929	case 0x2:
nkeynes@359	1930	{ /* LDS Rm, PR */
nkeynes@359	1931	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1932	load_reg( R_EAX, Rm );
nkeynes@359	1933	store_spreg( R_EAX, R_PR );
nkeynes@359	1934	}
nkeynes@359	1935	break;
nkeynes@359	1936	case 0x3:
nkeynes@359	1937	{ /* LDC Rm, SGR */
nkeynes@359	1938	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1939	check_priv();
nkeynes@359	1940	load_reg( R_EAX, Rm );
nkeynes@359	1941	store_spreg( R_EAX, R_SGR );
nkeynes@417	1942	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1943	}
nkeynes@359	1944	break;
nkeynes@359	1945	case 0x5:
nkeynes@359	1946	{ /* LDS Rm, FPUL */
nkeynes@359	1947	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@626	1948	check_fpuen();
nkeynes@359	1949	load_reg( R_EAX, Rm );
nkeynes@359	1950	store_spreg( R_EAX, R_FPUL );
nkeynes@359	1951	}
nkeynes@359	1952	break;
nkeynes@359	1953	case 0x6:
nkeynes@359	1954	{ /* LDS Rm, FPSCR */
nkeynes@359	1955	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@626	1956	check_fpuen();
nkeynes@359	1957	load_reg( R_EAX, Rm );
nkeynes@359	1958	store_spreg( R_EAX, R_FPSCR );
nkeynes@386	1959	update_fr_bank( R_EAX );
nkeynes@417	1960	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1961	}
nkeynes@359	1962	break;
nkeynes@359	1963	case 0xF:
nkeynes@359	1964	{ /* LDC Rm, DBR */
nkeynes@359	1965	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1966	check_priv();
nkeynes@359	1967	load_reg( R_EAX, Rm );
nkeynes@359	1968	store_spreg( R_EAX, R_DBR );
nkeynes@417	1969	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1970	}
nkeynes@359	1971	break;
nkeynes@359	1972	default:
nkeynes@359	1973	UNDEF();
nkeynes@359	1974	break;
nkeynes@359	1975	}
nkeynes@359	1976	break;
nkeynes@359	1977	case 0xB:
nkeynes@359	1978	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1979	case 0x0:
nkeynes@359	1980	{ /* JSR @Rn */
nkeynes@359	1981	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	1982	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1983	SLOTILLEGAL();
nkeynes@374	1984	} else {
nkeynes@590	1985	load_spreg( R_EAX, R_PC );
nkeynes@590	1986	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374	1987	store_spreg( R_EAX, R_PR );
nkeynes@408	1988	load_reg( R_ECX, Rn );
nkeynes@590	1989	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601	1990	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1991	sh4_x86.branch_taken = TRUE;
nkeynes@601	1992	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601	1993	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1994	exit_block_emu(pc+2);
nkeynes@601	1995	return 2;
nkeynes@601	1996	} else {
nkeynes@601	1997	sh4_translate_instruction(pc+2);
nkeynes@601	1998	exit_block_newpcset(pc+2);
nkeynes@601	1999	return 4;
nkeynes@601	2000	}
nkeynes@374	2001	}
nkeynes@359	2002	}
nkeynes@359	2003	break;
nkeynes@359	2004	case 0x1:
nkeynes@359	2005	{ /* TAS.B @Rn */
nkeynes@359	2006	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@586	2007	load_reg( R_EAX, Rn );
nkeynes@586	2008	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2009	PUSH_realigned_r32( R_EAX );
nkeynes@586	2010	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361	2011	TEST_r8_r8( R_AL, R_AL );
nkeynes@361	2012	SETE_t();
nkeynes@361	2013	OR_imm8_r8( 0x80, R_AL );
nkeynes@586	2014	POP_realigned_r32( R_ECX );
nkeynes@361	2015	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417	2016	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2017	}
nkeynes@359	2018	break;
nkeynes@359	2019	case 0x2:
nkeynes@359	2020	{ /* JMP @Rn */
nkeynes@359	2021	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	2022	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2023	SLOTILLEGAL();
nkeynes@374	2024	} else {
nkeynes@408	2025	load_reg( R_ECX, Rn );
nkeynes@590	2026	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590	2027	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	2028	sh4_x86.branch_taken = TRUE;
nkeynes@601	2029	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	2030	exit_block_emu(pc+2);
nkeynes@601	2031	return 2;
nkeynes@601	2032	} else {
nkeynes@601	2033	sh4_translate_instruction(pc+2);
nkeynes@601	2034	exit_block_newpcset(pc+2);
nkeynes@601	2035	return 4;
nkeynes@601	2036	}
nkeynes@374	2037	}
nkeynes@359	2038	}
nkeynes@359	2039	break;
nkeynes@359	2040	default:
nkeynes@359	2041	UNDEF();
nkeynes@359	2042	break;
nkeynes@359	2043	}
nkeynes@359	2044	break;
nkeynes@359	2045	case 0xC:
nkeynes@359	2046	{ /* SHAD Rm, Rn */
nkeynes@359	2047	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2048	/* Annoyingly enough, not directly convertible */
nkeynes@361	2049	load_reg( R_EAX, Rn );
nkeynes@361	2050	load_reg( R_ECX, Rm );
nkeynes@361	2051	CMP_imm32_r32( 0, R_ECX );
nkeynes@386	2052	JGE_rel8(16, doshl);
nkeynes@361	2053
nkeynes@361	2054	NEG_r32( R_ECX ); // 2
nkeynes@361	2055	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	2056	JE_rel8( 4, emptysar); // 2
nkeynes@361	2057	SAR_r32_CL( R_EAX ); // 2
nkeynes@386	2058	JMP_rel8(10, end); // 2
nkeynes@386	2059
nkeynes@386	2060	JMP_TARGET(emptysar);
nkeynes@386	2061	SAR_imm8_r32(31, R_EAX ); // 3
nkeynes@386	2062	JMP_rel8(5, end2);
nkeynes@386	2063
nkeynes@380	2064	JMP_TARGET(doshl);
nkeynes@361	2065	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361	2066	SHL_r32_CL( R_EAX ); // 2
nkeynes@380	2067	JMP_TARGET(end);
nkeynes@386	2068	JMP_TARGET(end2);
nkeynes@361	2069	store_reg( R_EAX, Rn );
nkeynes@417	2070	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2071	}
nkeynes@359	2072	break;
nkeynes@359	2073	case 0xD:
nkeynes@359	2074	{ /* SHLD Rm, Rn */
nkeynes@359	2075	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@368	2076	load_reg( R_EAX, Rn );
nkeynes@368	2077	load_reg( R_ECX, Rm );
nkeynes@386	2078	CMP_imm32_r32( 0, R_ECX );
nkeynes@386	2079	JGE_rel8(15, doshl);
nkeynes@368	2080
nkeynes@386	2081	NEG_r32( R_ECX ); // 2
nkeynes@386	2082	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	2083	JE_rel8( 4, emptyshr );
nkeynes@386	2084	SHR_r32_CL( R_EAX ); // 2
nkeynes@386	2085	JMP_rel8(9, end); // 2
nkeynes@386	2086
nkeynes@386	2087	JMP_TARGET(emptyshr);
nkeynes@386	2088	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386	2089	JMP_rel8(5, end2);
nkeynes@386	2090
nkeynes@386	2091	JMP_TARGET(doshl);
nkeynes@386	2092	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	2093	SHL_r32_CL( R_EAX ); // 2
nkeynes@386	2094	JMP_TARGET(end);
nkeynes@386	2095	JMP_TARGET(end2);
nkeynes@368	2096	store_reg( R_EAX, Rn );
nkeynes@417	2097	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2098	}
nkeynes@359	2099	break;
nkeynes@359	2100	case 0xE:
nkeynes@359	2101	switch( (ir&0x80) >> 7 ) {
nkeynes@359	2102	case 0x0:
nkeynes@359	2103	switch( (ir&0x70) >> 4 ) {
nkeynes@359	2104	case 0x0:
nkeynes@359	2105	{ /* LDC Rm, SR */
nkeynes@359	2106	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	2107	if( sh4_x86.in_delay_slot ) {
nkeynes@386	2108	SLOTILLEGAL();
nkeynes@386	2109	} else {
nkeynes@386	2110	check_priv();
nkeynes@386	2111	load_reg( R_EAX, Rm );
nkeynes@386	2112	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	2113	sh4_x86.priv_checked = FALSE;
nkeynes@386	2114	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	2115	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386	2116	}
nkeynes@359	2117	}
nkeynes@359	2118	break;
nkeynes@359	2119	case 0x1:
nkeynes@359	2120	{ /* LDC Rm, GBR */
nkeynes@359	2121	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	2122	load_reg( R_EAX, Rm );
nkeynes@359	2123	store_spreg( R_EAX, R_GBR );
nkeynes@359	2124	}
nkeynes@359	2125	break;
nkeynes@359	2126	case 0x2:
nkeynes@359	2127	{ /* LDC Rm, VBR */
nkeynes@359	2128	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	2129	check_priv();
nkeynes@359	2130	load_reg( R_EAX, Rm );
nkeynes@359	2131	store_spreg( R_EAX, R_VBR );
nkeynes@417	2132	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2133	}
nkeynes@359	2134	break;
nkeynes@359	2135	case 0x3:
nkeynes@359	2136	{ /* LDC Rm, SSR */
nkeynes@359	2137	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	2138	check_priv();
nkeynes@359	2139	load_reg( R_EAX, Rm );
nkeynes@359	2140	store_spreg( R_EAX, R_SSR );
nkeynes@417	2141	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2142	}
nkeynes@359	2143	break;
nkeynes@359	2144	case 0x4:
nkeynes@359	2145	{ /* LDC Rm, SPC */
nkeynes@359	2146	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	2147	check_priv();
nkeynes@359	2148	load_reg( R_EAX, Rm );
nkeynes@359	2149	store_spreg( R_EAX, R_SPC );
nkeynes@417	2150	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2151	}
nkeynes@359	2152	break;
nkeynes@359	2153	default:
nkeynes@359	2154	UNDEF();
nkeynes@359	2155	break;
nkeynes@359	2156	}
nkeynes@359	2157	break;
nkeynes@359	2158	case 0x1:
nkeynes@359	2159	{ /* LDC Rm, Rn_BANK */
nkeynes@359	2160	uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
nkeynes@386	2161	check_priv();
nkeynes@374	2162	load_reg( R_EAX, Rm );
nkeynes@374	2163	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417	2164	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2165	}
nkeynes@359	2166	break;
nkeynes@359	2167	}
nkeynes@359	2168	break;
nkeynes@359	2169	case 0xF:
nkeynes@359	2170	{ /* MAC.W @Rm+, @Rn+ */
nkeynes@359	2171	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	2172	if( Rm == Rn ) {
nkeynes@586	2173	load_reg( R_EAX, Rm );
nkeynes@586	2174	check_ralign16( R_EAX );
nkeynes@586	2175	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2176	PUSH_realigned_r32( R_EAX );
nkeynes@586	2177	load_reg( R_EAX, Rn );
nkeynes@586	2178	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596	2179	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586	2180	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586	2181	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586	2182	// adding a page-boundary check to skip the second translation
nkeynes@586	2183	} else {
nkeynes@586	2184	load_reg( R_EAX, Rm );
nkeynes@586	2185	check_ralign16( R_EAX );
nkeynes@586	2186	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596	2187	load_reg( R_ECX, Rn );
nkeynes@596	2188	check_ralign16( R_ECX );
nkeynes@586	2189	PUSH_realigned_r32( R_EAX );
nkeynes@596	2190	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596	2191	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586	2192	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586	2193	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586	2194	}
nkeynes@586	2195	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586	2196	POP_r32( R_ECX );
nkeynes@586	2197	PUSH_r32( R_EAX );
nkeynes@386	2198	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547	2199	POP_realigned_r32( R_ECX );
nkeynes@386	2200	IMUL_r32( R_ECX );
nkeynes@386	2201
nkeynes@386	2202	load_spreg( R_ECX, R_S );
nkeynes@386	2203	TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386	2204	JE_rel8( 47, nosat );
nkeynes@386	2205
nkeynes@386	2206	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@386	2207	JNO_rel8( 51, end ); // 2
nkeynes@386	2208	load_imm32( R_EDX, 1 ); // 5
nkeynes@386	2209	store_spreg( R_EDX, R_MACH ); // 6
nkeynes@386	2210	JS_rel8( 13, positive ); // 2
nkeynes@386	2211	load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386	2212	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@386	2213	JMP_rel8( 25, end2 ); // 2
nkeynes@386	2214
nkeynes@386	2215	JMP_TARGET(positive);
nkeynes@386	2216	load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386	2217	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@386	2218	JMP_rel8( 12, end3); // 2
nkeynes@386	2219
nkeynes@386	2220	JMP_TARGET(nosat);
nkeynes@386	2221	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@386	2222	ADC_r32_sh4r( R_EDX, R_MACH ); // 6
nkeynes@386	2223	JMP_TARGET(end);
nkeynes@386	2224	JMP_TARGET(end2);
nkeynes@386	2225	JMP_TARGET(end3);
nkeynes@417	2226	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2227	}
nkeynes@359	2228	break;
nkeynes@359	2229	}
nkeynes@359	2230	break;
nkeynes@359	2231	case 0x5:
nkeynes@359	2232	{ /* MOV.L @(disp, Rm), Rn */
nkeynes@359	2233	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
nkeynes@586	2234	load_reg( R_EAX, Rm );
nkeynes@586	2235	ADD_imm8s_r32( disp, R_EAX );
nkeynes@586	2236	check_ralign32( R_EAX );
nkeynes@586	2237	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2238	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	2239	store_reg( R_EAX, Rn );
nkeynes@417	2240	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2241	}
nkeynes@359	2242	break;
nkeynes@359	2243	case 0x6:
nkeynes@359	2244	switch( ir&0xF ) {
nkeynes@359	2245	case 0x0:
nkeynes@359	2246	{ /* MOV.B @Rm, Rn */
nkeynes@359	2247	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	2248	load_reg( R_EAX, Rm );
nkeynes@586	2249	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2250	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386	2251	store_reg( R_EAX, Rn );
nkeynes@417	2252	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2253	}
nkeynes@359	2254	break;
nkeynes@359	2255	case 0x1:
nkeynes@359	2256	{ /* MOV.W @Rm, Rn */
nkeynes@359	2257	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	2258	load_reg( R_EAX, Rm );
nkeynes@586	2259	check_ralign16( R_EAX );
nkeynes@586	2260	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2261	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	2262	store_reg( R_EAX, Rn );
nkeynes@417	2263	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2264	}
nkeynes@359	2265	break;
nkeynes@359	2266	case 0x2:
nkeynes@359	2267	{ /* MOV.L @Rm, Rn */
nkeynes@359	2268	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	2269	load_reg( R_EAX, Rm );
nkeynes@586	2270	check_ralign32( R_EAX );
nkeynes@586	2271	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2272	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	2273	store_reg( R_EAX, Rn );
nkeynes@417	2274	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2275	}
nkeynes@359	2276	break;
nkeynes@359	2277	case 0x3:
nkeynes@359	2278	{ /* MOV Rm, Rn */
nkeynes@359	2279	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2280	load_reg( R_EAX, Rm );
nkeynes@359	2281	store_reg( R_EAX, Rn );
nkeynes@359	2282	}
nkeynes@359	2283	break;
nkeynes@359	2284	case 0x4:
nkeynes@359	2285	{ /* MOV.B @Rm+, Rn */
nkeynes@359	2286	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	2287	load_reg( R_EAX, Rm );
nkeynes@586	2288	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2289	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586	2290	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	2291	store_reg( R_EAX, Rn );
nkeynes@417	2292	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2293	}
nkeynes@359	2294	break;
nkeynes@359	2295	case 0x5:
nkeynes@359	2296	{ /* MOV.W @Rm+, Rn */
nkeynes@359	2297	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2298	load_reg( R_EAX, Rm );
nkeynes@374	2299	check_ralign16( R_EAX );
nkeynes@586	2300	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2301	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586	2302	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	2303	store_reg( R_EAX, Rn );
nkeynes@417	2304	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2305	}
nkeynes@359	2306	break;
nkeynes@359	2307	case 0x6:
nkeynes@359	2308	{ /* MOV.L @Rm+, Rn */
nkeynes@359	2309	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2310	load_reg( R_EAX, Rm );
nkeynes@386	2311	check_ralign32( R_EAX );
nkeynes@586	2312	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2313	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	2314	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	2315	store_reg( R_EAX, Rn );
nkeynes@417	2316	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2317	}
nkeynes@359	2318	break;
nkeynes@359	2319	case 0x7:
nkeynes@359	2320	{ /* NOT Rm, Rn */
nkeynes@359	2321	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2322	load_reg( R_EAX, Rm );
nkeynes@359	2323	NOT_r32( R_EAX );
nkeynes@359	2324	store_reg( R_EAX, Rn );
nkeynes@417	2325	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2326	}
nkeynes@359	2327	break;
nkeynes@359	2328	case 0x8:
nkeynes@359	2329	{ /* SWAP.B Rm, Rn */
nkeynes@359	2330	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2331	load_reg( R_EAX, Rm );
nkeynes@601	2332	XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359	2333	store_reg( R_EAX, Rn );
nkeynes@359	2334	}
nkeynes@359	2335	break;
nkeynes@359	2336	case 0x9:
nkeynes@359	2337	{ /* SWAP.W Rm, Rn */
nkeynes@359	2338	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2339	load_reg( R_EAX, Rm );
nkeynes@359	2340	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	2341	SHL_imm8_r32( 16, R_ECX );
nkeynes@359	2342	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	2343	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	2344	store_reg( R_ECX, Rn );
nkeynes@417	2345	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2346	}
nkeynes@359	2347	break;
nkeynes@359	2348	case 0xA:
nkeynes@359	2349	{ /* NEGC Rm, Rn */
nkeynes@359	2350	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2351	load_reg( R_EAX, Rm );
nkeynes@359	2352	XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359	2353	LDC_t();
nkeynes@359	2354	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	2355	store_reg( R_ECX, Rn );
nkeynes@359	2356	SETC_t();
nkeynes@417	2357	sh4_x86.tstate = TSTATE_C;
nkeynes@359	2358	}
nkeynes@359	2359	break;
nkeynes@359	2360	case 0xB:
nkeynes@359	2361	{ /* NEG Rm, Rn */
nkeynes@359	2362	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2363	load_reg( R_EAX, Rm );
nkeynes@359	2364	NEG_r32( R_EAX );
nkeynes@359	2365	store_reg( R_EAX, Rn );
nkeynes@417	2366	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2367	}
nkeynes@359	2368	break;
nkeynes@359	2369	case 0xC:
nkeynes@359	2370	{ /* EXTU.B Rm, Rn */
nkeynes@359	2371	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2372	load_reg( R_EAX, Rm );
nkeynes@361	2373	MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361	2374	store_reg( R_EAX, Rn );
nkeynes@359	2375	}
nkeynes@359	2376	break;
nkeynes@359	2377	case 0xD:
nkeynes@359	2378	{ /* EXTU.W Rm, Rn */
nkeynes@359	2379	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2380	load_reg( R_EAX, Rm );
nkeynes@361	2381	MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361	2382	store_reg( R_EAX, Rn );
nkeynes@359	2383	}
nkeynes@359	2384	break;
nkeynes@359	2385	case 0xE:
nkeynes@359	2386	{ /* EXTS.B Rm, Rn */
nkeynes@359	2387	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2388	load_reg( R_EAX, Rm );
nkeynes@359	2389	MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359	2390	store_reg( R_EAX, Rn );
nkeynes@359	2391	}
nkeynes@359	2392	break;
nkeynes@359	2393	case 0xF:
nkeynes@359	2394	{ /* EXTS.W Rm, Rn */
nkeynes@359	2395	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2396	load_reg( R_EAX, Rm );
nkeynes@361	2397	MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361	2398	store_reg( R_EAX, Rn );
nkeynes@359	2399	}
nkeynes@359	2400	break;
nkeynes@359	2401	}
nkeynes@359	2402	break;
nkeynes@359	2403	case 0x7:
nkeynes@359	2404	{ /* ADD #imm, Rn */
nkeynes@359	2405	uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2406	load_reg( R_EAX, Rn );
nkeynes@359	2407	ADD_imm8s_r32( imm, R_EAX );
nkeynes@359	2408	store_reg( R_EAX, Rn );
nkeynes@417	2409	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2410	}
nkeynes@359	2411	break;
nkeynes@359	2412	case 0x8:
nkeynes@359	2413	switch( (ir&0xF00) >> 8 ) {
nkeynes@359	2414	case 0x0:
nkeynes@359	2415	{ /* MOV.B R0, @(disp, Rn) */
nkeynes@359	2416	uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
nkeynes@586	2417	load_reg( R_EAX, Rn );
nkeynes@586	2418	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2419	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2420	load_reg( R_EDX, 0 );
nkeynes@586	2421	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	2422	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2423	}
nkeynes@359	2424	break;
nkeynes@359	2425	case 0x1:
nkeynes@359	2426	{ /* MOV.W R0, @(disp, Rn) */
nkeynes@359	2427	uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
nkeynes@586	2428	load_reg( R_EAX, Rn );
nkeynes@586	2429	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2430	check_walign16( R_EAX );
nkeynes@586	2431	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2432	load_reg( R_EDX, 0 );
nkeynes@586	2433	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	2434	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2435	}
nkeynes@359	2436	break;
nkeynes@359	2437	case 0x4:
nkeynes@359	2438	{ /* MOV.B @(disp, Rm), R0 */
nkeynes@359	2439	uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
nkeynes@586	2440	load_reg( R_EAX, Rm );
nkeynes@586	2441	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2442	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2443	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	2444	store_reg( R_EAX, 0 );
nkeynes@417	2445	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2446	}
nkeynes@359	2447	break;
nkeynes@359	2448	case 0x5:
nkeynes@359	2449	{ /* MOV.W @(disp, Rm), R0 */
nkeynes@359	2450	uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
nkeynes@586	2451	load_reg( R_EAX, Rm );
nkeynes@586	2452	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2453	check_ralign16( R_EAX );
nkeynes@586	2454	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2455	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	2456	store_reg( R_EAX, 0 );
nkeynes@417	2457	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2458	}
nkeynes@359	2459	break;
nkeynes@359	2460	case 0x8:
nkeynes@359	2461	{ /* CMP/EQ #imm, R0 */
nkeynes@359	2462	int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2463	load_reg( R_EAX, 0 );
nkeynes@359	2464	CMP_imm8s_r32(imm, R_EAX);
nkeynes@359	2465	SETE_t();
nkeynes@417	2466	sh4_x86.tstate = TSTATE_E;
nkeynes@359	2467	}
nkeynes@359	2468	break;
nkeynes@359	2469	case 0x9:
nkeynes@359	2470	{ /* BT disp */
nkeynes@359	2471	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2472	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2473	SLOTILLEGAL();
nkeynes@374	2474	} else {
nkeynes@586	2475	sh4vma_t target = disp + pc + 4;
nkeynes@586	2476	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586	2477	exit_block_rel(target, pc+2 );
nkeynes@380	2478	JMP_TARGET(nottaken);
nkeynes@408	2479	return 2;
nkeynes@374	2480	}
nkeynes@359	2481	}
nkeynes@359	2482	break;
nkeynes@359	2483	case 0xB:
nkeynes@359	2484	{ /* BF disp */
nkeynes@359	2485	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2486	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2487	SLOTILLEGAL();
nkeynes@374	2488	} else {
nkeynes@586	2489	sh4vma_t target = disp + pc + 4;
nkeynes@586	2490	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586	2491	exit_block_rel(target, pc+2 );
nkeynes@380	2492	JMP_TARGET(nottaken);
nkeynes@408	2493	return 2;
nkeynes@374	2494	}
nkeynes@359	2495	}
nkeynes@359	2496	break;
nkeynes@359	2497	case 0xD:
nkeynes@359	2498	{ /* BT/S disp */
nkeynes@359	2499	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2500	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2501	SLOTILLEGAL();
nkeynes@374	2502	} else {
nkeynes@590	2503	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601	2504	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	2505	load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601	2506	JF_rel8(6,nottaken);
nkeynes@601	2507	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	2508	JMP_TARGET(nottaken);
nkeynes@601	2509	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601	2510	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	2511	exit_block_emu(pc+2);
nkeynes@601	2512	sh4_x86.branch_taken = TRUE;
nkeynes@601	2513	return 2;
nkeynes@601	2514	} else {
nkeynes@601	2515	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601	2516	CMP_imm8s_sh4r( 1, R_T );
nkeynes@601	2517	sh4_x86.tstate = TSTATE_E;
nkeynes@601	2518	}
nkeynes@601	2519	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t patch = (uint32_t )xlat_output; OP32(0); // JF rel32
nkeynes@601	2520	sh4_translate_instruction(pc+2);
nkeynes@601	2521	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	2522	// not taken
nkeynes@601	2523	patch = (xlat_output - ((uint8_t )patch)) - 4;
nkeynes@601	2524	sh4_translate_instruction(pc+2);
nkeynes@601	2525	return 4;
nkeynes@417	2526	}
nkeynes@374	2527	}
nkeynes@359	2528	}
nkeynes@359	2529	break;
nkeynes@359	2530	case 0xF:
nkeynes@359	2531	{ /* BF/S disp */
nkeynes@359	2532	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2533	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2534	SLOTILLEGAL();
nkeynes@374	2535	} else {
nkeynes@590	2536	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601	2537	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	2538	load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601	2539	JT_rel8(6,nottaken);
nkeynes@601	2540	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	2541	JMP_TARGET(nottaken);
nkeynes@601	2542	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601	2543	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	2544	exit_block_emu(pc+2);
nkeynes@601	2545	sh4_x86.branch_taken = TRUE;
nkeynes@601	2546	return 2;
nkeynes@601	2547	} else {
nkeynes@601	2548	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601	2549	CMP_imm8s_sh4r( 1, R_T );
nkeynes@601	2550	sh4_x86.tstate = TSTATE_E;
nkeynes@601	2551	}
nkeynes@601	2552	sh4vma_t target = disp + pc + 4;
nkeynes@601	2553	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t patch = (uint32_t )xlat_output; OP32(0); // JT rel32
nkeynes@601	2554	sh4_translate_instruction(pc+2);
nkeynes@601	2555	exit_block_rel( target, pc+4 );
nkeynes@601	2556
nkeynes@601	2557	// not taken
nkeynes@601	2558	patch = (xlat_output - ((uint8_t )patch)) - 4;
nkeynes@601	2559	sh4_translate_instruction(pc+2);
nkeynes@601	2560	return 4;
nkeynes@417	2561	}
nkeynes@374	2562	}
nkeynes@359	2563	}
nkeynes@359	2564	break;
nkeynes@359	2565	default:
nkeynes@359	2566	UNDEF();
nkeynes@359	2567	break;
nkeynes@359	2568	}
nkeynes@359	2569	break;
nkeynes@359	2570	case 0x9:
nkeynes@359	2571	{ /* MOV.W @(disp, PC), Rn */
nkeynes@359	2572	uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
nkeynes@374	2573	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2574	SLOTILLEGAL();
nkeynes@374	2575	} else {
nkeynes@586	2576	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586	2577	uint32_t target = pc + disp + 4;
nkeynes@586	2578	if( IS_IN_ICACHE(target) ) {
nkeynes@586	2579	sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586	2580	MOV_moff32_EAX( ptr );
nkeynes@586	2581	MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586	2582	} else {
nkeynes@586	2583	load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586	2584	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586	2585	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2586	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586	2587	sh4_x86.tstate = TSTATE_NONE;
nkeynes@586	2588	}
nkeynes@374	2589	store_reg( R_EAX, Rn );
nkeynes@374	2590	}
nkeynes@359	2591	}
nkeynes@359	2592	break;
nkeynes@359	2593	case 0xA:
nkeynes@359	2594	{ /* BRA disp */
nkeynes@359	2595	int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
nkeynes@374	2596	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2597	SLOTILLEGAL();
nkeynes@374	2598	} else {
nkeynes@590	2599	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	2600	sh4_x86.branch_taken = TRUE;
nkeynes@601	2601	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	2602	load_spreg( R_EAX, R_PC );
nkeynes@601	2603	ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601	2604	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	2605	exit_block_emu(pc+2);
nkeynes@601	2606	return 2;
nkeynes@601	2607	} else {
nkeynes@601	2608	sh4_translate_instruction( pc + 2 );
nkeynes@601	2609	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	2610	return 4;
nkeynes@601	2611	}
nkeynes@374	2612	}
nkeynes@359	2613	}
nkeynes@359	2614	break;
nkeynes@359	2615	case 0xB:
nkeynes@359	2616	{ /* BSR disp */
nkeynes@359	2617	int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
nkeynes@374	2618	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2619	SLOTILLEGAL();
nkeynes@374	2620	} else {
nkeynes@590	2621	load_spreg( R_EAX, R_PC );
nkeynes@590	2622	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374	2623	store_spreg( R_EAX, R_PR );
nkeynes@590	2624	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	2625	sh4_x86.branch_taken = TRUE;
nkeynes@601	2626	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601	2627	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	2628	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	2629	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	2630	exit_block_emu(pc+2);
nkeynes@601	2631	return 2;
nkeynes@601	2632	} else {
nkeynes@601	2633	sh4_translate_instruction( pc + 2 );
nkeynes@601	2634	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	2635	return 4;
nkeynes@601	2636	}
nkeynes@374	2637	}
nkeynes@359	2638	}
nkeynes@359	2639	break;
nkeynes@359	2640	case 0xC:
nkeynes@359	2641	switch( (ir&0xF00) >> 8 ) {
nkeynes@359	2642	case 0x0:
nkeynes@359	2643	{ /* MOV.B R0, @(disp, GBR) */
nkeynes@359	2644	uint32_t disp = (ir&0xFF);
nkeynes@586	2645	load_spreg( R_EAX, R_GBR );
nkeynes@586	2646	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2647	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2648	load_reg( R_EDX, 0 );
nkeynes@586	2649	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	2650	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2651	}
nkeynes@359	2652	break;
nkeynes@359	2653	case 0x1:
nkeynes@359	2654	{ /* MOV.W R0, @(disp, GBR) */
nkeynes@359	2655	uint32_t disp = (ir&0xFF)<<1;
nkeynes@586	2656	load_spreg( R_EAX, R_GBR );
nkeynes@586	2657	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2658	check_walign16( R_EAX );
nkeynes@586	2659	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2660	load_reg( R_EDX, 0 );
nkeynes@586	2661	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	2662	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2663	}
nkeynes@359	2664	break;
nkeynes@359	2665	case 0x2:
nkeynes@359	2666	{ /* MOV.L R0, @(disp, GBR) */
nkeynes@359	2667	uint32_t disp = (ir&0xFF)<<2;
nkeynes@586	2668	load_spreg( R_EAX, R_GBR );
nkeynes@586	2669	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2670	check_walign32( R_EAX );
nkeynes@586	2671	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2672	load_reg( R_EDX, 0 );
nkeynes@586	2673	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	2674	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2675	}
nkeynes@359	2676	break;
nkeynes@359	2677	case 0x3:
nkeynes@359	2678	{ /* TRAPA #imm */
nkeynes@359	2679	uint32_t imm = (ir&0xFF);
nkeynes@374	2680	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2681	SLOTILLEGAL();
nkeynes@374	2682	} else {
nkeynes@590	2683	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5
nkeynes@590	2684	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527	2685	load_imm32( R_EAX, imm );
nkeynes@527	2686	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417	2687	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408	2688	exit_block_pcset(pc);
nkeynes@409	2689	sh4_x86.branch_taken = TRUE;
nkeynes@408	2690	return 2;
nkeynes@374	2691	}
nkeynes@359	2692	}
nkeynes@359	2693	break;
nkeynes@359	2694	case 0x4:
nkeynes@359	2695	{ /* MOV.B @(disp, GBR), R0 */
nkeynes@359	2696	uint32_t disp = (ir&0xFF);
nkeynes@586	2697	load_spreg( R_EAX, R_GBR );
nkeynes@586	2698	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2699	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2700	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	2701	store_reg( R_EAX, 0 );
nkeynes@417	2702	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2703	}
nkeynes@359	2704	break;
nkeynes@359	2705	case 0x5:
nkeynes@359	2706	{ /* MOV.W @(disp, GBR), R0 */
nkeynes@359	2707	uint32_t disp = (ir&0xFF)<<1;
nkeynes@586	2708	load_spreg( R_EAX, R_GBR );
nkeynes@586	2709	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2710	check_ralign16( R_EAX );
nkeynes@586	2711	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2712	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	2713	store_reg( R_EAX, 0 );
nkeynes@417	2714	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2715	}
nkeynes@359	2716	break;
nkeynes@359	2717	case 0x6:
nkeynes@359	2718	{ /* MOV.L @(disp, GBR), R0 */
nkeynes@359	2719	uint32_t disp = (ir&0xFF)<<2;
nkeynes@586	2720	load_spreg( R_EAX, R_GBR );
nkeynes@586	2721	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	2722	check_ralign32( R_EAX );
nkeynes@586	2723	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2724	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	2725	store_reg( R_EAX, 0 );
nkeynes@417	2726	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2727	}
nkeynes@359	2728	break;
nkeynes@359	2729	case 0x7:
nkeynes@359	2730	{ /* MOVA @(disp, PC), R0 */
nkeynes@359	2731	uint32_t disp = (ir&0xFF)<<2;
nkeynes@374	2732	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2733	SLOTILLEGAL();
nkeynes@374	2734	} else {
nkeynes@586	2735	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586	2736	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374	2737	store_reg( R_ECX, 0 );
nkeynes@586	2738	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	2739	}
nkeynes@359	2740	}
nkeynes@359	2741	break;
nkeynes@359	2742	case 0x8:
nkeynes@359	2743	{ /* TST #imm, R0 */
nkeynes@359	2744	uint32_t imm = (ir&0xFF);
nkeynes@368	2745	load_reg( R_EAX, 0 );
nkeynes@368	2746	TEST_imm32_r32( imm, R_EAX );
nkeynes@368	2747	SETE_t();
nkeynes@417	2748	sh4_x86.tstate = TSTATE_E;
nkeynes@359	2749	}
nkeynes@359	2750	break;
nkeynes@359	2751	case 0x9:
nkeynes@359	2752	{ /* AND #imm, R0 */
nkeynes@359	2753	uint32_t imm = (ir&0xFF);
nkeynes@359	2754	load_reg( R_EAX, 0 );
nkeynes@359	2755	AND_imm32_r32(imm, R_EAX);
nkeynes@359	2756	store_reg( R_EAX, 0 );
nkeynes@417	2757	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2758	}
nkeynes@359	2759	break;
nkeynes@359	2760	case 0xA:
nkeynes@359	2761	{ /* XOR #imm, R0 */
nkeynes@359	2762	uint32_t imm = (ir&0xFF);
nkeynes@359	2763	load_reg( R_EAX, 0 );
nkeynes@359	2764	XOR_imm32_r32( imm, R_EAX );
nkeynes@359	2765	store_reg( R_EAX, 0 );
nkeynes@417	2766	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2767	}
nkeynes@359	2768	break;
nkeynes@359	2769	case 0xB:
nkeynes@359	2770	{ /* OR #imm, R0 */
nkeynes@359	2771	uint32_t imm = (ir&0xFF);
nkeynes@359	2772	load_reg( R_EAX, 0 );
nkeynes@359	2773	OR_imm32_r32(imm, R_EAX);
nkeynes@359	2774	store_reg( R_EAX, 0 );
nkeynes@417	2775	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2776	}
nkeynes@359	2777	break;
nkeynes@359	2778	case 0xC:
nkeynes@359	2779	{ /* TST.B #imm, @(R0, GBR) */
nkeynes@359	2780	uint32_t imm = (ir&0xFF);
nkeynes@368	2781	load_reg( R_EAX, 0);
nkeynes@368	2782	load_reg( R_ECX, R_GBR);
nkeynes@586	2783	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	2784	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2785	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394	2786	TEST_imm8_r8( imm, R_AL );
nkeynes@368	2787	SETE_t();
nkeynes@417	2788	sh4_x86.tstate = TSTATE_E;
nkeynes@359	2789	}
nkeynes@359	2790	break;
nkeynes@359	2791	case 0xD:
nkeynes@359	2792	{ /* AND.B #imm, @(R0, GBR) */
nkeynes@359	2793	uint32_t imm = (ir&0xFF);
nkeynes@359	2794	load_reg( R_EAX, 0 );
nkeynes@359	2795	load_spreg( R_ECX, R_GBR );
nkeynes@586	2796	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	2797	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2798	PUSH_realigned_r32(R_EAX);
nkeynes@586	2799	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547	2800	POP_realigned_r32(R_ECX);
nkeynes@386	2801	AND_imm32_r32(imm, R_EAX );
nkeynes@359	2802	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417	2803	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2804	}
nkeynes@359	2805	break;
nkeynes@359	2806	case 0xE:
nkeynes@359	2807	{ /* XOR.B #imm, @(R0, GBR) */
nkeynes@359	2808	uint32_t imm = (ir&0xFF);
nkeynes@359	2809	load_reg( R_EAX, 0 );
nkeynes@359	2810	load_spreg( R_ECX, R_GBR );
nkeynes@586	2811	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	2812	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2813	PUSH_realigned_r32(R_EAX);
nkeynes@586	2814	MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547	2815	POP_realigned_r32(R_ECX);
nkeynes@359	2816	XOR_imm32_r32( imm, R_EAX );
nkeynes@359	2817	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417	2818	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2819	}
nkeynes@359	2820	break;
nkeynes@359	2821	case 0xF:
nkeynes@359	2822	{ /* OR.B #imm, @(R0, GBR) */
nkeynes@359	2823	uint32_t imm = (ir&0xFF);
nkeynes@374	2824	load_reg( R_EAX, 0 );
nkeynes@374	2825	load_spreg( R_ECX, R_GBR );
nkeynes@586	2826	ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586	2827	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586	2828	PUSH_realigned_r32(R_EAX);
nkeynes@586	2829	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547	2830	POP_realigned_r32(R_ECX);
nkeynes@386	2831	OR_imm32_r32(imm, R_EAX );
nkeynes@374	2832	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417	2833	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2834	}
nkeynes@359	2835	break;
nkeynes@359	2836	}
nkeynes@359	2837	break;
nkeynes@359	2838	case 0xD:
nkeynes@359	2839	{ /* MOV.L @(disp, PC), Rn */
nkeynes@359	2840	uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
nkeynes@374	2841	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2842	SLOTILLEGAL();
nkeynes@374	2843	} else {
nkeynes@388	2844	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586	2845	if( IS_IN_ICACHE(target) ) {
nkeynes@586	2846	// If the target address is in the same page as the code, it's
nkeynes@586	2847	// pretty safe to just ref it directly and circumvent the whole
nkeynes@586	2848	// memory subsystem. (this is a big performance win)
nkeynes@586	2849
nkeynes@586	2850	// FIXME: There's a corner-case that's not handled here when
nkeynes@586	2851	// the current code-page is in the ITLB but not in the UTLB.
nkeynes@586	2852	// (should generate a TLB miss although need to test SH4
nkeynes@586	2853	// behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586	2854	// behaviour though.
nkeynes@586	2855	sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527	2856	MOV_moff32_EAX( ptr );
nkeynes@388	2857	} else {
nkeynes@586	2858	// Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586	2859	// different virtual address than the translation was done with,
nkeynes@586	2860	// but we can safely assume that the low bits are the same.
nkeynes@586	2861	load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586	2862	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586	2863	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586	2864	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2865	sh4_x86.tstate = TSTATE_NONE;
nkeynes@388	2866	}
nkeynes@386	2867	store_reg( R_EAX, Rn );
nkeynes@374	2868	}
nkeynes@359	2869	}
nkeynes@359	2870	break;
nkeynes@359	2871	case 0xE:
nkeynes@359	2872	{ /* MOV #imm, Rn */
nkeynes@359	2873	uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2874	load_imm32( R_EAX, imm );
nkeynes@359	2875	store_reg( R_EAX, Rn );
nkeynes@359	2876	}
nkeynes@359	2877	break;
nkeynes@359	2878	case 0xF:
nkeynes@359	2879	switch( ir&0xF ) {
nkeynes@359	2880	case 0x0:
nkeynes@359	2881	{ /* FADD FRm, FRn */
nkeynes@359	2882	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2883	check_fpuen();
nkeynes@377	2884	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2885	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2886	load_fr_bank( R_EDX );
nkeynes@380	2887	JNE_rel8(13,doubleprec);
nkeynes@377	2888	push_fr(R_EDX, FRm);
nkeynes@377	2889	push_fr(R_EDX, FRn);
nkeynes@377	2890	FADDP_st(1);
nkeynes@377	2891	pop_fr(R_EDX, FRn);
nkeynes@380	2892	JMP_rel8(11,end);
nkeynes@380	2893	JMP_TARGET(doubleprec);
nkeynes@377	2894	push_dr(R_EDX, FRm);
nkeynes@377	2895	push_dr(R_EDX, FRn);
nkeynes@377	2896	FADDP_st(1);
nkeynes@377	2897	pop_dr(R_EDX, FRn);
nkeynes@380	2898	JMP_TARGET(end);
nkeynes@417	2899	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2900	}
nkeynes@359	2901	break;
nkeynes@359	2902	case 0x1:
nkeynes@359	2903	{ /* FSUB FRm, FRn */
nkeynes@359	2904	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2905	check_fpuen();
nkeynes@377	2906	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2907	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2908	load_fr_bank( R_EDX );
nkeynes@380	2909	JNE_rel8(13, doubleprec);
nkeynes@377	2910	push_fr(R_EDX, FRn);
nkeynes@377	2911	push_fr(R_EDX, FRm);
nkeynes@388	2912	FSUBP_st(1);
nkeynes@377	2913	pop_fr(R_EDX, FRn);
nkeynes@380	2914	JMP_rel8(11, end);
nkeynes@380	2915	JMP_TARGET(doubleprec);
nkeynes@377	2916	push_dr(R_EDX, FRn);
nkeynes@377	2917	push_dr(R_EDX, FRm);
nkeynes@388	2918	FSUBP_st(1);
nkeynes@377	2919	pop_dr(R_EDX, FRn);
nkeynes@380	2920	JMP_TARGET(end);
nkeynes@417	2921	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2922	}
nkeynes@359	2923	break;
nkeynes@359	2924	case 0x2:
nkeynes@359	2925	{ /* FMUL FRm, FRn */
nkeynes@359	2926	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2927	check_fpuen();
nkeynes@377	2928	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2929	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2930	load_fr_bank( R_EDX );
nkeynes@380	2931	JNE_rel8(13, doubleprec);
nkeynes@377	2932	push_fr(R_EDX, FRm);
nkeynes@377	2933	push_fr(R_EDX, FRn);
nkeynes@377	2934	FMULP_st(1);
nkeynes@377	2935	pop_fr(R_EDX, FRn);
nkeynes@380	2936	JMP_rel8(11, end);
nkeynes@380	2937	JMP_TARGET(doubleprec);
nkeynes@377	2938	push_dr(R_EDX, FRm);
nkeynes@377	2939	push_dr(R_EDX, FRn);
nkeynes@377	2940	FMULP_st(1);
nkeynes@377	2941	pop_dr(R_EDX, FRn);
nkeynes@380	2942	JMP_TARGET(end);
nkeynes@417	2943	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2944	}
nkeynes@359	2945	break;
nkeynes@359	2946	case 0x3:
nkeynes@359	2947	{ /* FDIV FRm, FRn */
nkeynes@359	2948	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2949	check_fpuen();
nkeynes@377	2950	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2951	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2952	load_fr_bank( R_EDX );
nkeynes@380	2953	JNE_rel8(13, doubleprec);
nkeynes@377	2954	push_fr(R_EDX, FRn);
nkeynes@377	2955	push_fr(R_EDX, FRm);
nkeynes@377	2956	FDIVP_st(1);
nkeynes@377	2957	pop_fr(R_EDX, FRn);
nkeynes@380	2958	JMP_rel8(11, end);
nkeynes@380	2959	JMP_TARGET(doubleprec);
nkeynes@377	2960	push_dr(R_EDX, FRn);
nkeynes@377	2961	push_dr(R_EDX, FRm);
nkeynes@377	2962	FDIVP_st(1);
nkeynes@377	2963	pop_dr(R_EDX, FRn);
nkeynes@380	2964	JMP_TARGET(end);
nkeynes@417	2965	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2966	}
nkeynes@359	2967	break;
nkeynes@359	2968	case 0x4:
nkeynes@359	2969	{ /* FCMP/EQ FRm, FRn */
nkeynes@359	2970	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2971	check_fpuen();
nkeynes@377	2972	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2973	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2974	load_fr_bank( R_EDX );
nkeynes@380	2975	JNE_rel8(8, doubleprec);
nkeynes@377	2976	push_fr(R_EDX, FRm);
nkeynes@377	2977	push_fr(R_EDX, FRn);
nkeynes@380	2978	JMP_rel8(6, end);
nkeynes@380	2979	JMP_TARGET(doubleprec);
nkeynes@377	2980	push_dr(R_EDX, FRm);
nkeynes@377	2981	push_dr(R_EDX, FRn);
nkeynes@386	2982	JMP_TARGET(end);
nkeynes@377	2983	FCOMIP_st(1);
nkeynes@377	2984	SETE_t();
nkeynes@377	2985	FPOP_st();
nkeynes@417	2986	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2987	}
nkeynes@359	2988	break;
nkeynes@359	2989	case 0x5:
nkeynes@359	2990	{ /* FCMP/GT FRm, FRn */
nkeynes@359	2991	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2992	check_fpuen();
nkeynes@377	2993	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2994	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2995	load_fr_bank( R_EDX );
nkeynes@380	2996	JNE_rel8(8, doubleprec);
nkeynes@377	2997	push_fr(R_EDX, FRm);
nkeynes@377	2998	push_fr(R_EDX, FRn);
nkeynes@380	2999	JMP_rel8(6, end);
nkeynes@380	3000	JMP_TARGET(doubleprec);
nkeynes@377	3001	push_dr(R_EDX, FRm);
nkeynes@377	3002	push_dr(R_EDX, FRn);
nkeynes@380	3003	JMP_TARGET(end);
nkeynes@377	3004	FCOMIP_st(1);
nkeynes@377	3005	SETA_t();
nkeynes@377	3006	FPOP_st();
nkeynes@417	3007	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3008	}
nkeynes@359	3009	break;
nkeynes@359	3010	case 0x6:
nkeynes@359	3011	{ /* FMOV @(R0, Rm), FRn */
nkeynes@359	3012	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	3013	check_fpuen();
nkeynes@586	3014	load_reg( R_EAX, Rm );
nkeynes@586	3015	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586	3016	check_ralign32( R_EAX );
nkeynes@586	3017	MMU_TRANSLATE_READ( R_EAX );
nkeynes@416	3018	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3019	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3020	JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586	3021	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416	3022	load_fr_bank( R_EDX );
nkeynes@416	3023	store_fr( R_EDX, R_EAX, FRn );
nkeynes@375	3024	if( FRn&1 ) {
nkeynes@527	3025	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380	3026	JMP_TARGET(doublesize);
nkeynes@586	3027	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3028	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416	3029	load_xf_bank( R_EDX );
nkeynes@586	3030	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3031	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3032	JMP_TARGET(end);
nkeynes@375	3033	} else {
nkeynes@527	3034	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380	3035	JMP_TARGET(doublesize);
nkeynes@586	3036	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3037	load_fr_bank( R_EDX );
nkeynes@586	3038	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3039	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3040	JMP_TARGET(end);
nkeynes@377	3041	}
nkeynes@417	3042	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	3043	}
nkeynes@377	3044	break;
nkeynes@377	3045	case 0x7:
nkeynes@377	3046	{ /* FMOV FRm, @(R0, Rn) */
nkeynes@377	3047	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@586	3048	check_fpuen();
nkeynes@586	3049	load_reg( R_EAX, Rn );
nkeynes@586	3050	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586	3051	check_walign32( R_EAX );
nkeynes@586	3052	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416	3053	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3054	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3055	JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416	3056	load_fr_bank( R_EDX );
nkeynes@586	3057	load_fr( R_EDX, R_ECX, FRm );
nkeynes@586	3058	MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377	3059	if( FRm&1 ) {
nkeynes@527	3060	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380	3061	JMP_TARGET(doublesize);
nkeynes@416	3062	load_xf_bank( R_EDX );
nkeynes@586	3063	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3064	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3065	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3066	JMP_TARGET(end);
nkeynes@377	3067	} else {
nkeynes@527	3068	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380	3069	JMP_TARGET(doublesize);
nkeynes@416	3070	load_fr_bank( R_EDX );
nkeynes@586	3071	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3072	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3073	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3074	JMP_TARGET(end);
nkeynes@377	3075	}
nkeynes@417	3076	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	3077	}
nkeynes@377	3078	break;
nkeynes@377	3079	case 0x8:
nkeynes@377	3080	{ /* FMOV @Rm, FRn */
nkeynes@377	3081	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	3082	check_fpuen();
nkeynes@586	3083	load_reg( R_EAX, Rm );
nkeynes@586	3084	check_ralign32( R_EAX );
nkeynes@586	3085	MMU_TRANSLATE_READ( R_EAX );
nkeynes@416	3086	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3087	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3088	JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586	3089	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416	3090	load_fr_bank( R_EDX );
nkeynes@416	3091	store_fr( R_EDX, R_EAX, FRn );
nkeynes@377	3092	if( FRn&1 ) {
nkeynes@527	3093	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380	3094	JMP_TARGET(doublesize);
nkeynes@586	3095	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3096	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416	3097	load_xf_bank( R_EDX );
nkeynes@586	3098	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3099	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3100	JMP_TARGET(end);
nkeynes@377	3101	} else {
nkeynes@527	3102	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380	3103	JMP_TARGET(doublesize);
nkeynes@586	3104	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3105	load_fr_bank( R_EDX );
nkeynes@586	3106	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3107	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3108	JMP_TARGET(end);
nkeynes@375	3109	}
nkeynes@417	3110	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3111	}
nkeynes@359	3112	break;
nkeynes@359	3113	case 0x9:
nkeynes@359	3114	{ /* FMOV @Rm+, FRn */
nkeynes@359	3115	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@586	3116	check_fpuen();
nkeynes@586	3117	load_reg( R_EAX, Rm );
nkeynes@586	3118	check_ralign32( R_EAX );
nkeynes@586	3119	MMU_TRANSLATE_READ( R_EAX );
nkeynes@416	3120	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3121	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3122	JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@586	3123	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	3124	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416	3125	load_fr_bank( R_EDX );
nkeynes@416	3126	store_fr( R_EDX, R_EAX, FRn );
nkeynes@377	3127	if( FRn&1 ) {
nkeynes@586	3128	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380	3129	JMP_TARGET(doublesize);
nkeynes@586	3130	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586	3131	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3132	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416	3133	load_xf_bank( R_EDX );
nkeynes@586	3134	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3135	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3136	JMP_TARGET(end);
nkeynes@377	3137	} else {
nkeynes@586	3138	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@586	3139	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586	3140	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416	3141	load_fr_bank( R_EDX );
nkeynes@586	3142	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586	3143	store_fr( R_EDX, R_EAX, FRn\|0x01 );
nkeynes@380	3144	JMP_TARGET(end);
nkeynes@377	3145	}
nkeynes@417	3146	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3147	}
nkeynes@359	3148	break;
nkeynes@359	3149	case 0xA:
nkeynes@359	3150	{ /* FMOV FRm, @Rn */
nkeynes@359	3151	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@586	3152	check_fpuen();
nkeynes@586	3153	load_reg( R_EAX, Rn );
nkeynes@586	3154	check_walign32( R_EAX );
nkeynes@586	3155	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416	3156	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3157	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3158	JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416	3159	load_fr_bank( R_EDX );
nkeynes@586	3160	load_fr( R_EDX, R_ECX, FRm );
nkeynes@586	3161	MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375	3162	if( FRm&1 ) {
nkeynes@527	3163	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380	3164	JMP_TARGET(doublesize);
nkeynes@416	3165	load_xf_bank( R_EDX );
nkeynes@586	3166	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3167	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3168	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3169	JMP_TARGET(end);
nkeynes@375	3170	} else {
nkeynes@527	3171	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380	3172	JMP_TARGET(doublesize);
nkeynes@416	3173	load_fr_bank( R_EDX );
nkeynes@586	3174	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3175	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3176	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3177	JMP_TARGET(end);
nkeynes@375	3178	}
nkeynes@417	3179	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3180	}
nkeynes@359	3181	break;
nkeynes@359	3182	case 0xB:
nkeynes@359	3183	{ /* FMOV FRm, @-Rn */
nkeynes@359	3184	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@586	3185	check_fpuen();
nkeynes@586	3186	load_reg( R_EAX, Rn );
nkeynes@586	3187	check_walign32( R_EAX );
nkeynes@416	3188	load_spreg( R_EDX, R_FPSCR );
nkeynes@416	3189	TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586	3190	JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@586	3191	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	3192	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416	3193	load_fr_bank( R_EDX );
nkeynes@586	3194	load_fr( R_EDX, R_ECX, FRm );
nkeynes@586	3195	ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@586	3196	MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377	3197	if( FRm&1 ) {
nkeynes@586	3198	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380	3199	JMP_TARGET(doublesize);
nkeynes@586	3200	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586	3201	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416	3202	load_xf_bank( R_EDX );
nkeynes@586	3203	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3204	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3205	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586	3206	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3207	JMP_TARGET(end);
nkeynes@377	3208	} else {
nkeynes@586	3209	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380	3210	JMP_TARGET(doublesize);
nkeynes@586	3211	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586	3212	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416	3213	load_fr_bank( R_EDX );
nkeynes@586	3214	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416	3215	load_fr( R_EDX, R_EDX, FRm\|0x01 );
nkeynes@586	3216	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586	3217	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380	3218	JMP_TARGET(end);
nkeynes@377	3219	}
nkeynes@417	3220	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3221	}
nkeynes@359	3222	break;
nkeynes@359	3223	case 0xC:
nkeynes@359	3224	{ /* FMOV FRm, FRn */
nkeynes@359	3225	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@375	3226	/* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375	3227	* 1. 32-bit fr-to-fr (PR=0)
nkeynes@375	3228	* 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375	3229	* 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375	3230	* 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375	3231	* 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375	3232	*/
nkeynes@377	3233	check_fpuen();
nkeynes@375	3234	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3235	load_fr_bank( R_EDX );
nkeynes@375	3236	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	3237	JNE_rel8(8, doublesize);
nkeynes@375	3238	load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375	3239	store_fr( R_EDX, R_EAX, FRn );
nkeynes@375	3240	if( FRm&1 ) {
nkeynes@386	3241	JMP_rel8(24, end);
nkeynes@380	3242	JMP_TARGET(doublesize);
nkeynes@375	3243	load_xf_bank( R_ECX );
nkeynes@375	3244	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375	3245	if( FRn&1 ) {
nkeynes@375	3246	load_fr( R_ECX, R_EDX, FRm );
nkeynes@375	3247	store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375	3248	store_fr( R_ECX, R_EDX, FRn );
nkeynes@375	3249	} else /* FRn&1 == 0 */ {
nkeynes@375	3250	load_fr( R_ECX, R_ECX, FRm );
nkeynes@388	3251	store_fr( R_EDX, R_EAX, FRn );
nkeynes@388	3252	store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375	3253	}
nkeynes@380	3254	JMP_TARGET(end);
nkeynes@375	3255	} else /* FRm&1 == 0 */ {
nkeynes@375	3256	if( FRn&1 ) {
nkeynes@386	3257	JMP_rel8(24, end);
nkeynes@375	3258	load_xf_bank( R_ECX );
nkeynes@375	3259	load_fr( R_EDX, R_EAX, FRm );
nkeynes@375	3260	load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375	3261	store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375	3262	store_fr( R_ECX, R_EDX, FRn );
nkeynes@380	3263	JMP_TARGET(end);
nkeynes@375	3264	} else /* FRn&1 == 0 */ {
nkeynes@380	3265	JMP_rel8(12, end);
nkeynes@375	3266	load_fr( R_EDX, R_EAX, FRm );
nkeynes@375	3267	load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375	3268	store_fr( R_EDX, R_EAX, FRn );
nkeynes@375	3269	store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380	3270	JMP_TARGET(end);
nkeynes@375	3271	}
nkeynes@375	3272	}
nkeynes@417	3273	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3274	}
nkeynes@359	3275	break;
nkeynes@359	3276	case 0xD:
nkeynes@359	3277	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	3278	case 0x0:
nkeynes@359	3279	{ /* FSTS FPUL, FRn */
nkeynes@359	3280	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3281	check_fpuen();
nkeynes@377	3282	load_fr_bank( R_ECX );
nkeynes@377	3283	load_spreg( R_EAX, R_FPUL );
nkeynes@377	3284	store_fr( R_ECX, R_EAX, FRn );
nkeynes@417	3285	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3286	}
nkeynes@359	3287	break;
nkeynes@359	3288	case 0x1:
nkeynes@359	3289	{ /* FLDS FRm, FPUL */
nkeynes@359	3290	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	3291	check_fpuen();
nkeynes@377	3292	load_fr_bank( R_ECX );
nkeynes@377	3293	load_fr( R_ECX, R_EAX, FRm );
nkeynes@377	3294	store_spreg( R_EAX, R_FPUL );
nkeynes@417	3295	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3296	}
nkeynes@359	3297	break;
nkeynes@359	3298	case 0x2:
nkeynes@359	3299	{ /* FLOAT FPUL, FRn */
nkeynes@359	3300	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3301	check_fpuen();
nkeynes@377	3302	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3303	load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377	3304	FILD_sh4r(R_FPUL);
nkeynes@377	3305	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3306	JNE_rel8(5, doubleprec);
nkeynes@377	3307	pop_fr( R_EDX, FRn );
nkeynes@380	3308	JMP_rel8(3, end);
nkeynes@380	3309	JMP_TARGET(doubleprec);
nkeynes@377	3310	pop_dr( R_EDX, FRn );
nkeynes@380	3311	JMP_TARGET(end);
nkeynes@417	3312	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3313	}
nkeynes@359	3314	break;
nkeynes@359	3315	case 0x3:
nkeynes@359	3316	{ /* FTRC FRm, FPUL */
nkeynes@359	3317	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	3318	check_fpuen();
nkeynes@388	3319	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3320	load_fr_bank( R_EDX );
nkeynes@388	3321	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	3322	JNE_rel8(5, doubleprec);
nkeynes@388	3323	push_fr( R_EDX, FRm );
nkeynes@388	3324	JMP_rel8(3, doop);
nkeynes@388	3325	JMP_TARGET(doubleprec);
nkeynes@388	3326	push_dr( R_EDX, FRm );
nkeynes@388	3327	JMP_TARGET( doop );
nkeynes@388	3328	load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388	3329	FILD_r32ind( R_ECX );
nkeynes@388	3330	FCOMIP_st(1);
nkeynes@394	3331	JNA_rel8( 32, sat );
nkeynes@388	3332	load_imm32( R_ECX, (uint32_t)&min_int ); // 5
nkeynes@388	3333	FILD_r32ind( R_ECX ); // 2
nkeynes@388	3334	FCOMIP_st(1); // 2
nkeynes@394	3335	JAE_rel8( 21, sat2 ); // 2
nkeynes@394	3336	load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394	3337	FNSTCW_r32ind( R_EAX );
nkeynes@394	3338	load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394	3339	FLDCW_r32ind( R_EDX );
nkeynes@388	3340	FISTP_sh4r(R_FPUL); // 3
nkeynes@394	3341	FLDCW_r32ind( R_EAX );
nkeynes@388	3342	JMP_rel8( 9, end ); // 2
nkeynes@388	3343
nkeynes@388	3344	JMP_TARGET(sat);
nkeynes@388	3345	JMP_TARGET(sat2);
nkeynes@388	3346	MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388	3347	store_spreg( R_ECX, R_FPUL );
nkeynes@388	3348	FPOP_st();
nkeynes@388	3349	JMP_TARGET(end);
nkeynes@417	3350	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3351	}
nkeynes@359	3352	break;
nkeynes@359	3353	case 0x4:
nkeynes@359	3354	{ /* FNEG FRn */
nkeynes@359	3355	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3356	check_fpuen();
nkeynes@377	3357	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3358	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3359	load_fr_bank( R_EDX );
nkeynes@380	3360	JNE_rel8(10, doubleprec);
nkeynes@377	3361	push_fr(R_EDX, FRn);
nkeynes@377	3362	FCHS_st0();
nkeynes@377	3363	pop_fr(R_EDX, FRn);
nkeynes@380	3364	JMP_rel8(8, end);
nkeynes@380	3365	JMP_TARGET(doubleprec);
nkeynes@377	3366	push_dr(R_EDX, FRn);
nkeynes@377	3367	FCHS_st0();
nkeynes@377	3368	pop_dr(R_EDX, FRn);
nkeynes@380	3369	JMP_TARGET(end);
nkeynes@417	3370	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3371	}
nkeynes@359	3372	break;
nkeynes@359	3373	case 0x5:
nkeynes@359	3374	{ /* FABS FRn */
nkeynes@359	3375	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3376	check_fpuen();
nkeynes@374	3377	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3378	load_fr_bank( R_EDX );
nkeynes@374	3379	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3380	JNE_rel8(10, doubleprec);
nkeynes@374	3381	push_fr(R_EDX, FRn); // 3
nkeynes@374	3382	FABS_st0(); // 2
nkeynes@374	3383	pop_fr( R_EDX, FRn); //3
nkeynes@380	3384	JMP_rel8(8,end); // 2
nkeynes@380	3385	JMP_TARGET(doubleprec);
nkeynes@374	3386	push_dr(R_EDX, FRn);
nkeynes@374	3387	FABS_st0();
nkeynes@374	3388	pop_dr(R_EDX, FRn);
nkeynes@380	3389	JMP_TARGET(end);
nkeynes@417	3390	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3391	}
nkeynes@359	3392	break;
nkeynes@359	3393	case 0x6:
nkeynes@359	3394	{ /* FSQRT FRn */
nkeynes@359	3395	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3396	check_fpuen();
nkeynes@377	3397	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3398	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3399	load_fr_bank( R_EDX );
nkeynes@380	3400	JNE_rel8(10, doubleprec);
nkeynes@377	3401	push_fr(R_EDX, FRn);
nkeynes@377	3402	FSQRT_st0();
nkeynes@377	3403	pop_fr(R_EDX, FRn);
nkeynes@380	3404	JMP_rel8(8, end);
nkeynes@380	3405	JMP_TARGET(doubleprec);
nkeynes@377	3406	push_dr(R_EDX, FRn);
nkeynes@377	3407	FSQRT_st0();
nkeynes@377	3408	pop_dr(R_EDX, FRn);
nkeynes@380	3409	JMP_TARGET(end);
nkeynes@417	3410	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3411	}
nkeynes@359	3412	break;
nkeynes@359	3413	case 0x7:
nkeynes@359	3414	{ /* FSRRA FRn */
nkeynes@359	3415	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3416	check_fpuen();
nkeynes@377	3417	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3418	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3419	load_fr_bank( R_EDX );
nkeynes@380	3420	JNE_rel8(12, end); // PR=0 only
nkeynes@377	3421	FLD1_st0();
nkeynes@377	3422	push_fr(R_EDX, FRn);
nkeynes@377	3423	FSQRT_st0();
nkeynes@377	3424	FDIVP_st(1);
nkeynes@377	3425	pop_fr(R_EDX, FRn);
nkeynes@380	3426	JMP_TARGET(end);
nkeynes@417	3427	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3428	}
nkeynes@359	3429	break;
nkeynes@359	3430	case 0x8:
nkeynes@359	3431	{ /* FLDI0 FRn */
nkeynes@359	3432	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3433	/* IFF PR=0 */
nkeynes@377	3434	check_fpuen();
nkeynes@377	3435	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3436	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3437	JNE_rel8(8, end);
nkeynes@377	3438	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377	3439	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377	3440	store_fr( R_ECX, R_EAX, FRn );
nkeynes@380	3441	JMP_TARGET(end);
nkeynes@417	3442	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3443	}
nkeynes@359	3444	break;
nkeynes@359	3445	case 0x9:
nkeynes@359	3446	{ /* FLDI1 FRn */
nkeynes@359	3447	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3448	/* IFF PR=0 */
nkeynes@377	3449	check_fpuen();
nkeynes@377	3450	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3451	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3452	JNE_rel8(11, end);
nkeynes@377	3453	load_imm32(R_EAX, 0x3F800000);
nkeynes@377	3454	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377	3455	store_fr( R_ECX, R_EAX, FRn );
nkeynes@380	3456	JMP_TARGET(end);
nkeynes@417	3457	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3458	}
nkeynes@359	3459	break;
nkeynes@359	3460	case 0xA:
nkeynes@359	3461	{ /* FCNVSD FPUL, FRn */
nkeynes@359	3462	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3463	check_fpuen();
nkeynes@377	3464	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3465	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3466	JE_rel8(9, end); // only when PR=1
nkeynes@377	3467	load_fr_bank( R_ECX );
nkeynes@377	3468	push_fpul();
nkeynes@377	3469	pop_dr( R_ECX, FRn );
nkeynes@380	3470	JMP_TARGET(end);
nkeynes@417	3471	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3472	}
nkeynes@359	3473	break;
nkeynes@359	3474	case 0xB:
nkeynes@359	3475	{ /* FCNVDS FRm, FPUL */
nkeynes@359	3476	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	3477	check_fpuen();
nkeynes@377	3478	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3479	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3480	JE_rel8(9, end); // only when PR=1
nkeynes@377	3481	load_fr_bank( R_ECX );
nkeynes@377	3482	push_dr( R_ECX, FRm );
nkeynes@377	3483	pop_fpul();
nkeynes@380	3484	JMP_TARGET(end);
nkeynes@417	3485	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3486	}
nkeynes@359	3487	break;
nkeynes@359	3488	case 0xE:
nkeynes@359	3489	{ /* FIPR FVm, FVn */
nkeynes@359	3490	uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
nkeynes@377	3491	check_fpuen();
nkeynes@388	3492	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3493	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	3494	JNE_rel8(44, doubleprec);
nkeynes@388	3495
nkeynes@388	3496	load_fr_bank( R_ECX );
nkeynes@388	3497	push_fr( R_ECX, FVm<<2 );
nkeynes@388	3498	push_fr( R_ECX, FVn<<2 );
nkeynes@388	3499	FMULP_st(1);
nkeynes@388	3500	push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388	3501	push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388	3502	FMULP_st(1);
nkeynes@388	3503	FADDP_st(1);
nkeynes@388	3504	push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388	3505	push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388	3506	FMULP_st(1);
nkeynes@388	3507	FADDP_st(1);
nkeynes@388	3508	push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388	3509	push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388	3510	FMULP_st(1);
nkeynes@388	3511	FADDP_st(1);
nkeynes@388	3512	pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388	3513	JMP_TARGET(doubleprec);
nkeynes@417	3514	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3515	}
nkeynes@359	3516	break;
nkeynes@359	3517	case 0xF:
nkeynes@359	3518	switch( (ir&0x100) >> 8 ) {
nkeynes@359	3519	case 0x0:
nkeynes@359	3520	{ /* FSCA FPUL, FRn */
nkeynes@359	3521	uint32_t FRn = ((ir>>9)&0x7)<<1;
nkeynes@377	3522	check_fpuen();
nkeynes@388	3523	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3524	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527	3525	JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388	3526	load_fr_bank( R_ECX );
nkeynes@388	3527	ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388	3528	load_spreg( R_EDX, R_FPUL );
nkeynes@388	3529	call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388	3530	JMP_TARGET(doubleprec);
nkeynes@417	3531	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3532	}
nkeynes@359	3533	break;
nkeynes@359	3534	case 0x1:
nkeynes@359	3535	switch( (ir&0x200) >> 9 ) {
nkeynes@359	3536	case 0x0:
nkeynes@359	3537	{ /* FTRV XMTRX, FVn */
nkeynes@359	3538	uint32_t FVn = ((ir>>10)&0x3);
nkeynes@377	3539	check_fpuen();
nkeynes@388	3540	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3541	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527	3542	JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388	3543	load_fr_bank( R_EDX ); // 3
nkeynes@388	3544	ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
nkeynes@388	3545	load_xf_bank( R_ECX ); // 12
nkeynes@388	3546	call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
nkeynes@388	3547	JMP_TARGET(doubleprec);
nkeynes@417	3548	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3549	}
nkeynes@359	3550	break;
nkeynes@359	3551	case 0x1:
nkeynes@359	3552	switch( (ir&0xC00) >> 10 ) {
nkeynes@359	3553	case 0x0:
nkeynes@359	3554	{ /* FSCHG */
nkeynes@377	3555	check_fpuen();
nkeynes@377	3556	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3557	XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377	3558	store_spreg( R_ECX, R_FPSCR );
nkeynes@417	3559	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3560	}
nkeynes@359	3561	break;
nkeynes@359	3562	case 0x2:
nkeynes@359	3563	{ /* FRCHG */
nkeynes@377	3564	check_fpuen();
nkeynes@377	3565	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3566	XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377	3567	store_spreg( R_ECX, R_FPSCR );
nkeynes@386	3568	update_fr_bank( R_ECX );
nkeynes@417	3569	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3570	}
nkeynes@359	3571	break;
nkeynes@359	3572	case 0x3:
nkeynes@359	3573	{ /* UNDEF */
nkeynes@374	3574	if( sh4_x86.in_delay_slot ) {
nkeynes@386	3575	SLOTILLEGAL();
nkeynes@374	3576	} else {
nkeynes@586	3577	JMP_exc(EXC_ILLEGAL);
nkeynes@408	3578	return 2;
nkeynes@374	3579	}
nkeynes@359	3580	}
nkeynes@359	3581	break;
nkeynes@359	3582	default:
nkeynes@359	3583	UNDEF();
nkeynes@359	3584	break;
nkeynes@359	3585	}
nkeynes@359	3586	break;
nkeynes@359	3587	}
nkeynes@359	3588	break;
nkeynes@359	3589	}
nkeynes@359	3590	break;
nkeynes@359	3591	default:
nkeynes@359	3592	UNDEF();
nkeynes@359	3593	break;
nkeynes@359	3594	}
nkeynes@359	3595	break;
nkeynes@359	3596	case 0xE:
nkeynes@359	3597	{ /* FMAC FR0, FRm, FRn */
nkeynes@359	3598	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	3599	check_fpuen();
nkeynes@377	3600	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3601	load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@377	3602	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3603	JNE_rel8(18, doubleprec);
nkeynes@377	3604	push_fr( R_EDX, 0 );
nkeynes@377	3605	push_fr( R_EDX, FRm );
nkeynes@377	3606	FMULP_st(1);
nkeynes@377	3607	push_fr( R_EDX, FRn );
nkeynes@377	3608	FADDP_st(1);
nkeynes@377	3609	pop_fr( R_EDX, FRn );
nkeynes@380	3610	JMP_rel8(16, end);
nkeynes@380	3611	JMP_TARGET(doubleprec);
nkeynes@377	3612	push_dr( R_EDX, 0 );
nkeynes@377	3613	push_dr( R_EDX, FRm );
nkeynes@377	3614	FMULP_st(1);
nkeynes@377	3615	push_dr( R_EDX, FRn );
nkeynes@377	3616	FADDP_st(1);
nkeynes@377	3617	pop_dr( R_EDX, FRn );
nkeynes@380	3618	JMP_TARGET(end);
nkeynes@417	3619	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	3620	}
nkeynes@359	3621	break;
nkeynes@359	3622	default:
nkeynes@359	3623	UNDEF();
nkeynes@359	3624	break;
nkeynes@359	3625	}
nkeynes@359	3626	break;
nkeynes@359	3627	}
nkeynes@359	3628
nkeynes@590	3629	sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359	3630	return 0;
nkeynes@359	3631	}