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lxdream.org :: lxdream/src/aica/armcore.c
lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.c
changeset 736:a02d1475ccfd
prev642:c7383f21f122
next811:7ff871670e58
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * ARM7TDMI CPU emulation core.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE aica_module
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#include "dream.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "aica/armcore.h"
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#include "aica/aica.h"
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#define STM_R15_OFFSET 12
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struct arm_registers armr;
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void arm_set_mode( int mode );
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uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
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        { MODE_UND, 0x00000004 },
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        { MODE_SVC, 0x00000008 },
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        { MODE_ABT, 0x0000000C },
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        { MODE_ABT, 0x00000010 },
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        { MODE_IRQ, 0x00000018 },
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        { MODE_FIQ, 0x0000001C } };
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#define EXC_RESET 0
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#define EXC_UNDEFINED 1
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#define EXC_SOFTWARE 2
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#define EXC_PREFETCH_ABORT 3
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#define EXC_DATA_ABORT 4
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#define EXC_IRQ 5
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#define EXC_FAST_IRQ 6
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    47
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uint32_t arm_cpu_freq = ARM_BASE_RATE;
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uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
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#define CYCLES_PER_SAMPLE ((ARM_BASE_RATE * 1000000) / AICA_SAMPLE_RATE)
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static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
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static int arm_breakpoint_count = 0;
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void arm_set_breakpoint( uint32_t pc, breakpoint_type_t type )
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{
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    arm_breakpoints[arm_breakpoint_count].address = pc;
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    arm_breakpoints[arm_breakpoint_count].type = type;
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    arm_breakpoint_count++;
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}
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gboolean arm_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
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{
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    int i;
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    for( i=0; i<arm_breakpoint_count; i++ ) {
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        if( arm_breakpoints[i].address == pc && 
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                arm_breakpoints[i].type == type ) {
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            while( ++i < arm_breakpoint_count ) {
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                arm_breakpoints[i-1].address = arm_breakpoints[i].address;
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                arm_breakpoints[i-1].type = arm_breakpoints[i].type;
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            }
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            arm_breakpoint_count--;
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            return TRUE;
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        }
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    }
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    return FALSE;
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}
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int arm_get_breakpoint( uint32_t pc )
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{
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    int i;
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    for( i=0; i<arm_breakpoint_count; i++ ) {
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        if( arm_breakpoints[i].address == pc )
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            return arm_breakpoints[i].type;
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    }
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    return 0;
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}
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uint32_t arm_run_slice( uint32_t num_samples )
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{
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    int i,j,k;
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    if( !armr.running )
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        return num_samples;
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    for( i=0; i<num_samples; i++ ) {
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        for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
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            armr.icount++;
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            if( !arm_execute_instruction() )
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                return i;
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#ifdef ENABLE_DEBUG_MODE
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            for( k=0; k<arm_breakpoint_count; k++ ) {
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                if( arm_breakpoints[k].address == armr.r[15] ) {
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                    dreamcast_stop();
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                    if( arm_breakpoints[k].type == BREAK_ONESHOT )
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                        arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
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                    return i;
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                }
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            }
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#endif	
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        }
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        k = MMIO_READ( AICA2, AICA_TCR );
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        uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
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        val++;
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        if( val == 0 ) {
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            aica_event( AICA_EVENT_TIMER );
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            // MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );
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        }
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        MMIO_WRITE( AICA2, AICA_TIMER, val );
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        if( !dreamcast_is_running() )
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            break;
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    }
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    return i;
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}
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void arm_save_state( FILE *f )
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{
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    fwrite( &armr, sizeof(armr), 1, f );
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}
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int arm_load_state( FILE *f )
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{
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    fread( &armr, sizeof(armr), 1, f );
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    return 0;
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}
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/* Exceptions */
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void arm_reset( void )
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{
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    /* Wipe all processor state */
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    memset( &armr, 0, sizeof(armr) );
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    armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
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    armr.r[15] = 0x00000000;
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    armr.running = TRUE;
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}
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#define SET_CPSR_CONTROL   0x00010000
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#define SET_CPSR_EXTENSION 0x00020000
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#define SET_CPSR_STATUS    0x00040000
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#define SET_CPSR_FLAGS     0x00080000
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uint32_t arm_get_cpsr( void )
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{
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    /* write back all flags to the cpsr */
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    armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;
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    if( armr.n ) armr.cpsr |= CPSR_N;
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    if( armr.z ) armr.cpsr |= CPSR_Z;
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    if( armr.c ) armr.cpsr |= CPSR_C;
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    if( armr.v ) armr.cpsr |= CPSR_V;
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    if( armr.t ) armr.cpsr |= CPSR_T;  
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    return armr.cpsr;
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}
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/**
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 * Return a pointer to the specified register in the user bank,
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 * regardless of the active bank
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 */
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static uint32_t *arm_user_reg( int reg )
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{
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    if( IS_EXCEPTION_MODE() ) {
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        if( reg == 13 || reg == 14 )
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            return &armr.user_r[reg-8];
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        if( IS_FIQ_MODE() ) {
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            if( reg >= 8 || reg <= 12 )
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                return &armr.user_r[reg-8];
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        }
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    }
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    return &armr.r[reg];
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}
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#define USER_R(n) *arm_user_reg(n)
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/**
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 * Set the CPSR to the specified value.
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 *
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 * @param value values to set in CPSR
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 * @param fields set of mask values to define which sections of the 
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 *   CPSR to set (one of the SET_CPSR_* values above)
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 */
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void arm_set_cpsr( uint32_t value, uint32_t fields )
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{
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    if( IS_PRIVILEGED_MODE() ) {
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        if( fields & SET_CPSR_CONTROL ) {
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            int mode = value & CPSR_MODE;
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            arm_set_mode( mode );
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            armr.t = ( value & CPSR_T ); /* Technically illegal to change */
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            armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
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        }
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        /* Middle 16 bits not currently defined */
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    }
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    if( fields & SET_CPSR_FLAGS ) {
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        /* Break flags directly out of given value - don't bother writing
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         * back to CPSR 
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         */
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        armr.n = ( value & CPSR_N );
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        armr.z = ( value & CPSR_Z );
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        armr.c = ( value & CPSR_C );
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        armr.v = ( value & CPSR_V );
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    }
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}
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void arm_set_spsr( uint32_t value, uint32_t fields )
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{
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    /* Only defined if we actually have an SPSR register */
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    if( IS_EXCEPTION_MODE() ) {
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        if( fields & SET_CPSR_CONTROL ) {
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            armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
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        }
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        /* Middle 16 bits not currently defined */
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        if( fields & SET_CPSR_FLAGS ) {
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            armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
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        }
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    }
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}
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/**
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 * Raise an ARM exception (other than reset, which uses arm_reset().
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 * @param exception one of the EXC_* exception codes defined above.
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 */
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void arm_raise_exception( int exception )
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{
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    int mode = arm_exceptions[exception][0];
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    uint32_t spsr = arm_get_cpsr();
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    arm_set_mode( mode );
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    armr.spsr = spsr;
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    armr.r[14] = armr.r[15] + 4;
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    armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I; 
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    if( mode == MODE_FIQ )
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        armr.cpsr |= CPSR_F;
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    armr.r[15] = arm_exceptions[exception][1];
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}
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void arm_restore_cpsr( void )
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{
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    int spsr = armr.spsr;
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    int mode = spsr & CPSR_MODE;
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    arm_set_mode( mode );
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    armr.cpsr = spsr;
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    armr.n = ( spsr & CPSR_N );
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    armr.z = ( spsr & CPSR_Z );
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    armr.c = ( spsr & CPSR_C );
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    armr.v = ( spsr & CPSR_V );
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    armr.t = ( spsr & CPSR_T );
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}
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/**
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 * Change the current executing ARM mode to the requested mode.
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 * Saves any required registers to banks and restores those for the
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 * correct mode. (Note does not actually update CPSR at the moment).
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 */
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void arm_set_mode( int targetMode )
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{
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    int currentMode = armr.cpsr & CPSR_MODE;
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   274
    if( currentMode == targetMode )
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        return;
nkeynes@35
   276
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   277
    switch( currentMode ) {
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    case MODE_USER:
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   279
    case MODE_SYS:
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        armr.user_r[5] = armr.r[13];
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        armr.user_r[6] = armr.r[14];
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        break;
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   283
    case MODE_SVC:
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        armr.svc_r[0] = armr.r[13];
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   285
        armr.svc_r[1] = armr.r[14];
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   286
        armr.svc_r[2] = armr.spsr;
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   287
        break;
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   288
    case MODE_ABT:
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   289
        armr.abt_r[0] = armr.r[13];
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   290
        armr.abt_r[1] = armr.r[14];
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   291
        armr.abt_r[2] = armr.spsr;
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   292
        break;
nkeynes@35
   293
    case MODE_UND:
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   294
        armr.und_r[0] = armr.r[13];
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   295
        armr.und_r[1] = armr.r[14];
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   296
        armr.und_r[2] = armr.spsr;
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   297
        break;
nkeynes@35
   298
    case MODE_IRQ:
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   299
        armr.irq_r[0] = armr.r[13];
nkeynes@736
   300
        armr.irq_r[1] = armr.r[14];
nkeynes@736
   301
        armr.irq_r[2] = armr.spsr;
nkeynes@736
   302
        break;
nkeynes@35
   303
    case MODE_FIQ:
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   304
        armr.fiq_r[0] = armr.r[8];
nkeynes@736
   305
        armr.fiq_r[1] = armr.r[9];
nkeynes@736
   306
        armr.fiq_r[2] = armr.r[10];
nkeynes@736
   307
        armr.fiq_r[3] = armr.r[11];
nkeynes@736
   308
        armr.fiq_r[4] = armr.r[12];
nkeynes@736
   309
        armr.fiq_r[5] = armr.r[13];
nkeynes@736
   310
        armr.fiq_r[6] = armr.r[14];
nkeynes@736
   311
        armr.fiq_r[7] = armr.spsr;
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   312
        armr.r[8] = armr.user_r[0];
nkeynes@736
   313
        armr.r[9] = armr.user_r[1];
nkeynes@736
   314
        armr.r[10] = armr.user_r[2];
nkeynes@736
   315
        armr.r[11] = armr.user_r[3];
nkeynes@736
   316
        armr.r[12] = armr.user_r[4];
nkeynes@736
   317
        break;
nkeynes@35
   318
    }
nkeynes@736
   319
nkeynes@35
   320
    switch( targetMode ) {
nkeynes@35
   321
    case MODE_USER:
nkeynes@35
   322
    case MODE_SYS:
nkeynes@736
   323
        armr.r[13] = armr.user_r[5];
nkeynes@736
   324
        armr.r[14] = armr.user_r[6];
nkeynes@736
   325
        break;
nkeynes@35
   326
    case MODE_SVC:
nkeynes@736
   327
        armr.r[13] = armr.svc_r[0];
nkeynes@736
   328
        armr.r[14] = armr.svc_r[1];
nkeynes@736
   329
        armr.spsr = armr.svc_r[2];
nkeynes@736
   330
        break;
nkeynes@35
   331
    case MODE_ABT:
nkeynes@736
   332
        armr.r[13] = armr.abt_r[0];
nkeynes@736
   333
        armr.r[14] = armr.abt_r[1];
nkeynes@736
   334
        armr.spsr = armr.abt_r[2];
nkeynes@736
   335
        break;
nkeynes@35
   336
    case MODE_UND:
nkeynes@736
   337
        armr.r[13] = armr.und_r[0];
nkeynes@736
   338
        armr.r[14] = armr.und_r[1];
nkeynes@736
   339
        armr.spsr = armr.und_r[2];
nkeynes@736
   340
        break;
nkeynes@35
   341
    case MODE_IRQ:
nkeynes@736
   342
        armr.r[13] = armr.irq_r[0];
nkeynes@736
   343
        armr.r[14] = armr.irq_r[1];
nkeynes@736
   344
        armr.spsr = armr.irq_r[2];
nkeynes@736
   345
        break;
nkeynes@35
   346
    case MODE_FIQ:
nkeynes@736
   347
        armr.user_r[0] = armr.r[8];
nkeynes@736
   348
        armr.user_r[1] = armr.r[9];
nkeynes@736
   349
        armr.user_r[2] = armr.r[10];
nkeynes@736
   350
        armr.user_r[3] = armr.r[11];
nkeynes@736
   351
        armr.user_r[4] = armr.r[12];
nkeynes@736
   352
        armr.r[8] = armr.fiq_r[0];
nkeynes@736
   353
        armr.r[9] = armr.fiq_r[1];
nkeynes@736
   354
        armr.r[10] = armr.fiq_r[2];
nkeynes@736
   355
        armr.r[11] = armr.fiq_r[3];
nkeynes@736
   356
        armr.r[12] = armr.fiq_r[4];
nkeynes@736
   357
        armr.r[13] = armr.fiq_r[5];
nkeynes@736
   358
        armr.r[14] = armr.fiq_r[6];
nkeynes@736
   359
        armr.spsr = armr.fiq_r[7];
nkeynes@736
   360
        break;
nkeynes@35
   361
    }
nkeynes@35
   362
}
nkeynes@35
   363
nkeynes@5
   364
/* Page references are as per ARM DDI 0100E (June 2000) */
nkeynes@2
   365
nkeynes@11
   366
#define MEM_READ_BYTE( addr ) arm_read_byte(addr)
nkeynes@11
   367
#define MEM_READ_WORD( addr ) arm_read_word(addr)
nkeynes@11
   368
#define MEM_READ_LONG( addr ) arm_read_long(addr)
nkeynes@11
   369
#define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)
nkeynes@11
   370
#define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)
nkeynes@11
   371
#define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)
nkeynes@2
   372
nkeynes@5
   373
nkeynes@5
   374
#define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)
nkeynes@5
   375
#define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)
nkeynes@5
   376
#define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
nkeynes@5
   377
#define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
nkeynes@5
   378
nkeynes@7
   379
#define PC armr.r[15]
nkeynes@2
   380
nkeynes@5
   381
/* Instruction fields */
nkeynes@5
   382
#define COND(ir) (ir>>28)
nkeynes@5
   383
#define GRP(ir) ((ir>>26)&0x03)
nkeynes@5
   384
#define OPCODE(ir) ((ir>>20)&0x1F)
nkeynes@5
   385
#define IFLAG(ir) (ir&0x02000000)
nkeynes@5
   386
#define SFLAG(ir) (ir&0x00100000)
nkeynes@5
   387
#define PFLAG(ir) (ir&0x01000000)
nkeynes@5
   388
#define UFLAG(ir) (ir&0x00800000)
nkeynes@5
   389
#define BFLAG(ir) (ir&0x00400000)
nkeynes@46
   390
#define WFLAG(ir) (ir&0x00200000)
nkeynes@5
   391
#define LFLAG(ir) SFLAG(ir)
nkeynes@5
   392
#define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))
nkeynes@37
   393
#define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))
nkeynes@5
   394
#define RDn(ir) ((ir>>12)&0x0F)
nkeynes@37
   395
#define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))
nkeynes@37
   396
#define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )
nkeynes@5
   397
#define LRN(ir) armr.r[((ir>>16)&0x0F)]
nkeynes@5
   398
#define LRD(ir) armr.r[((ir>>12)&0x0F)]
nkeynes@5
   399
#define LRS(ir) armr.r[((ir>>8)&0x0F)]
nkeynes@5
   400
#define LRM(ir) armr.r[(ir&0x0F)]
nkeynes@5
   401
nkeynes@5
   402
#define IMM8(ir) (ir&0xFF)
nkeynes@5
   403
#define IMM12(ir) (ir&0xFFF)
nkeynes@7
   404
#define SHIFTIMM(ir) ((ir>>7)&0x1F)
nkeynes@7
   405
#define IMMROT(ir) ((ir>>7)&0x1E)
nkeynes@37
   406
#define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
nkeynes@431
   407
#define SIGNEXT24(n) (((n)&0x00800000) ? ((n)|0xFF000000) : ((n)&0x00FFFFFF))
nkeynes@5
   408
#define SHIFT(ir) ((ir>>4)&0x07)
nkeynes@5
   409
#define DISP24(ir) ((ir&0x00FFFFFF))
nkeynes@37
   410
#define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)
nkeynes@46
   411
#define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)
nkeynes@7
   412
nkeynes@37
   413
/**
nkeynes@37
   414
 * Determine the value of the shift-operand for a data processing instruction,
nkeynes@37
   415
 * without determing a value for shift_C (optimized form for instructions that
nkeynes@37
   416
 * don't require shift_C ).
nkeynes@37
   417
 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
nkeynes@37
   418
 */
nkeynes@5
   419
static uint32_t arm_get_shift_operand( uint32_t ir )
nkeynes@5
   420
{
nkeynes@736
   421
    uint32_t operand, tmp;
nkeynes@736
   422
    if( IFLAG(ir) == 0 ) {
nkeynes@736
   423
        operand = RM(ir);
nkeynes@736
   424
        switch(SHIFT(ir)) {
nkeynes@736
   425
        case 0: /* (Rm << imm) */
nkeynes@736
   426
            operand = operand << SHIFTIMM(ir);
nkeynes@736
   427
            break;
nkeynes@736
   428
        case 1: /* (Rm << Rs) */
nkeynes@736
   429
            tmp = RS(ir)&0xFF;
nkeynes@736
   430
            if( tmp > 31 ) operand = 0;
nkeynes@736
   431
            else operand = operand << tmp;
nkeynes@736
   432
            break;
nkeynes@736
   433
        case 2: /* (Rm >> imm) */
nkeynes@736
   434
            operand = operand >> SHIFTIMM(ir);
nkeynes@736
   435
            break;
nkeynes@736
   436
        case 3: /* (Rm >> Rs) */
nkeynes@736
   437
            tmp = RS(ir) & 0xFF;
nkeynes@736
   438
            if( tmp > 31 ) operand = 0;
nkeynes@736
   439
            else operand = operand >> ir;
nkeynes@736
   440
            break;
nkeynes@736
   441
        case 4: /* (Rm >>> imm) */
nkeynes@736
   442
            tmp = SHIFTIMM(ir);
nkeynes@736
   443
            if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
nkeynes@736
   444
            else operand = ((int32_t)operand) >> tmp;
nkeynes@736
   445
            break;
nkeynes@736
   446
        case 5: /* (Rm >>> Rs) */
nkeynes@736
   447
            tmp = RS(ir) & 0xFF;
nkeynes@736
   448
            if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
nkeynes@736
   449
            else operand = ((int32_t)operand) >> tmp;
nkeynes@736
   450
            break;
nkeynes@736
   451
        case 6:
nkeynes@736
   452
            tmp = SHIFTIMM(ir);
nkeynes@736
   453
            if( tmp == 0 ) /* RRX aka rotate with carry */
nkeynes@736
   454
                operand = (operand >> 1) | (armr.c<<31);
nkeynes@736
   455
            else
nkeynes@736
   456
                operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@736
   457
            break;
nkeynes@736
   458
        case 7:
nkeynes@736
   459
            tmp = RS(ir)&0x1F;
nkeynes@736
   460
            operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@736
   461
            break;
nkeynes@736
   462
        }
nkeynes@736
   463
    } else {
nkeynes@736
   464
        operand = IMM8(ir);
nkeynes@736
   465
        tmp = IMMROT(ir);
nkeynes@736
   466
        operand = ROTATE_RIGHT_LONG(operand, tmp);
nkeynes@736
   467
    }
nkeynes@736
   468
    return operand;
nkeynes@5
   469
}
nkeynes@5
   470
nkeynes@5
   471
/**
nkeynes@37
   472
 * Determine the value of the shift-operand for a data processing instruction,
nkeynes@37
   473
 * and set armr.shift_c accordingly.
nkeynes@37
   474
 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
nkeynes@5
   475
 */
nkeynes@5
   476
static uint32_t arm_get_shift_operand_s( uint32_t ir )
nkeynes@5
   477
{
nkeynes@736
   478
    uint32_t operand, tmp;
nkeynes@736
   479
    if( IFLAG(ir) == 0 ) {
nkeynes@736
   480
        operand = RM(ir);
nkeynes@736
   481
        switch(SHIFT(ir)) {
nkeynes@736
   482
        case 0: /* (Rm << imm) */
nkeynes@736
   483
            tmp = SHIFTIMM(ir);
nkeynes@736
   484
            if( tmp == 0 ) { /* Rm */
nkeynes@736
   485
                armr.shift_c = armr.c;
nkeynes@736
   486
            } else { /* Rm << imm */
nkeynes@736
   487
                armr.shift_c = (operand >> (32-tmp)) & 0x01;
nkeynes@736
   488
                operand = operand << tmp;
nkeynes@736
   489
            }
nkeynes@736
   490
            break;
nkeynes@736
   491
        case 1: /* (Rm << Rs) */
nkeynes@736
   492
            tmp = RS(ir)&0xFF;
nkeynes@736
   493
            if( tmp == 0 ) {
nkeynes@736
   494
                armr.shift_c = armr.c;
nkeynes@736
   495
            } else {
nkeynes@736
   496
                if( tmp <= 32 )
nkeynes@736
   497
                    armr.shift_c = (operand >> (32-tmp)) & 0x01;
nkeynes@736
   498
                else armr.shift_c = 0;
nkeynes@736
   499
                if( tmp < 32 )
nkeynes@736
   500
                    operand = operand << tmp;
nkeynes@736
   501
                else operand = 0;
nkeynes@736
   502
            }
nkeynes@736
   503
            break;
nkeynes@736
   504
        case 2: /* (Rm >> imm) */
nkeynes@736
   505
            tmp = SHIFTIMM(ir);
nkeynes@736
   506
            if( tmp == 0 ) {
nkeynes@736
   507
                armr.shift_c = operand >> 31;
nkeynes@736
   508
                operand = 0;
nkeynes@736
   509
            } else {
nkeynes@736
   510
                armr.shift_c = (operand >> (tmp-1)) & 0x01;
nkeynes@736
   511
                operand = RM(ir) >> tmp;
nkeynes@736
   512
            }
nkeynes@736
   513
            break;
nkeynes@736
   514
        case 3: /* (Rm >> Rs) */
nkeynes@736
   515
            tmp = RS(ir) & 0xFF;
nkeynes@736
   516
            if( tmp == 0 ) {
nkeynes@736
   517
                armr.shift_c = armr.c;
nkeynes@736
   518
            } else {
nkeynes@736
   519
                if( tmp <= 32 )
nkeynes@736
   520
                    armr.shift_c = (operand >> (tmp-1))&0x01;
nkeynes@736
   521
                else armr.shift_c = 0;
nkeynes@736
   522
                if( tmp < 32 )
nkeynes@736
   523
                    operand = operand >> tmp;
nkeynes@736
   524
                else operand = 0;
nkeynes@736
   525
            }
nkeynes@736
   526
            break;
nkeynes@736
   527
        case 4: /* (Rm >>> imm) */
nkeynes@736
   528
            tmp = SHIFTIMM(ir);
nkeynes@736
   529
            if( tmp == 0 ) {
nkeynes@736
   530
                armr.shift_c = operand >> 31;
nkeynes@736
   531
                operand = -armr.shift_c;
nkeynes@736
   532
            } else {
nkeynes@736
   533
                armr.shift_c = (operand >> (tmp-1)) & 0x01;
nkeynes@736
   534
                operand = ((int32_t)operand) >> tmp;
nkeynes@736
   535
            }
nkeynes@736
   536
            break;
nkeynes@736
   537
        case 5: /* (Rm >>> Rs) */
nkeynes@736
   538
            tmp = RS(ir) & 0xFF;
nkeynes@736
   539
            if( tmp == 0 ) {
nkeynes@736
   540
                armr.shift_c = armr.c;
nkeynes@736
   541
            } else {
nkeynes@736
   542
                if( tmp < 32 ) {
nkeynes@736
   543
                    armr.shift_c = (operand >> (tmp-1))&0x01;
nkeynes@736
   544
                    operand = ((int32_t)operand) >> tmp;
nkeynes@736
   545
                } else {
nkeynes@736
   546
                    armr.shift_c = operand >> 31;
nkeynes@736
   547
                    operand = ((int32_t)operand) >> 31;
nkeynes@736
   548
                }
nkeynes@736
   549
            }
nkeynes@736
   550
            break;
nkeynes@736
   551
        case 6:
nkeynes@736
   552
            tmp = SHIFTIMM(ir);
nkeynes@736
   553
            if( tmp == 0 ) { /* RRX aka rotate with carry */
nkeynes@736
   554
                armr.shift_c = operand&0x01;
nkeynes@736
   555
                operand = (operand >> 1) | (armr.c<<31);
nkeynes@736
   556
            } else {
nkeynes@736
   557
                armr.shift_c = operand>>(tmp-1);
nkeynes@736
   558
                operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@736
   559
            }
nkeynes@736
   560
            break;
nkeynes@736
   561
        case 7:
nkeynes@736
   562
            tmp = RS(ir)&0xFF;
nkeynes@736
   563
            if( tmp == 0 ) {
nkeynes@736
   564
                armr.shift_c = armr.c;
nkeynes@736
   565
            } else {
nkeynes@736
   566
                tmp &= 0x1F;
nkeynes@736
   567
                if( tmp == 0 ) {
nkeynes@736
   568
                    armr.shift_c = operand>>31;
nkeynes@736
   569
                } else {
nkeynes@736
   570
                    armr.shift_c = (operand>>(tmp-1))&0x1;
nkeynes@736
   571
                    operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@736
   572
                }
nkeynes@736
   573
            }
nkeynes@736
   574
            break;
nkeynes@736
   575
        }
nkeynes@736
   576
    } else {
nkeynes@736
   577
        operand = IMM8(ir);
nkeynes@736
   578
        tmp = IMMROT(ir);
nkeynes@736
   579
        if( tmp == 0 ) {
nkeynes@736
   580
            armr.shift_c = armr.c;
nkeynes@736
   581
        } else {
nkeynes@736
   582
            operand = ROTATE_RIGHT_LONG(operand, tmp);
nkeynes@736
   583
            armr.shift_c = operand>>31;
nkeynes@736
   584
        }
nkeynes@736
   585
    }
nkeynes@736
   586
    return operand;
nkeynes@5
   587
}
nkeynes@5
   588
nkeynes@5
   589
/**
nkeynes@5
   590
 * Another variant of the shifter code for index-based memory addressing.
nkeynes@5
   591
 * Distinguished by the fact that it doesn't support register shifts, and
nkeynes@5
   592
 * ignores the I flag (WTF do the load/store instructions use the I flag to
nkeynes@5
   593
 * mean the _exact opposite_ of what it means for the data processing 
nkeynes@5
   594
 * instructions ???)
nkeynes@5
   595
 */
nkeynes@5
   596
static uint32_t arm_get_address_index( uint32_t ir )
nkeynes@5
   597
{
nkeynes@736
   598
    uint32_t operand = RM(ir);
nkeynes@736
   599
    uint32_t tmp;
nkeynes@736
   600
nkeynes@736
   601
    switch(SHIFT(ir)) {
nkeynes@736
   602
    case 0: /* (Rm << imm) */
nkeynes@736
   603
        operand = operand << SHIFTIMM(ir);
nkeynes@736
   604
        break;
nkeynes@736
   605
    case 2: /* (Rm >> imm) */
nkeynes@736
   606
        operand = operand >> SHIFTIMM(ir);
nkeynes@736
   607
        break;
nkeynes@736
   608
    case 4: /* (Rm >>> imm) */
nkeynes@736
   609
        tmp = SHIFTIMM(ir);
nkeynes@736
   610
        if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
nkeynes@736
   611
        else operand = ((int32_t)operand) >> tmp;
nkeynes@736
   612
        break;
nkeynes@736
   613
    case 6:
nkeynes@736
   614
        tmp = SHIFTIMM(ir);
nkeynes@736
   615
        if( tmp == 0 ) /* RRX aka rotate with carry */
nkeynes@736
   616
            operand = (operand >> 1) | (armr.c<<31);
nkeynes@736
   617
        else
nkeynes@736
   618
            operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@736
   619
        break;
nkeynes@736
   620
    default: UNIMP(ir);
nkeynes@736
   621
    }
nkeynes@736
   622
    return operand;	
nkeynes@5
   623
}
nkeynes@5
   624
nkeynes@37
   625
/**
nkeynes@37
   626
 * Determine the address operand of a load/store instruction, including
nkeynes@37
   627
 * applying any pre/post adjustments to the address registers.
nkeynes@37
   628
 * @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
nkeynes@37
   629
 * @param The instruction word.
nkeynes@37
   630
 * @return The calculated address
nkeynes@37
   631
 */
nkeynes@5
   632
static uint32_t arm_get_address_operand( uint32_t ir )
nkeynes@5
   633
{
nkeynes@736
   634
    uint32_t addr=0;
nkeynes@736
   635
nkeynes@736
   636
    /* I P U . W */
nkeynes@736
   637
    switch( (ir>>21)&0x1D ) {
nkeynes@736
   638
    case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
nkeynes@736
   639
    case 1:
nkeynes@736
   640
        addr = RN(ir);
nkeynes@736
   641
        LRN(ir) = addr - IMM12(ir);
nkeynes@736
   642
        break;
nkeynes@736
   643
    case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
nkeynes@736
   644
    case 5:
nkeynes@736
   645
        addr = RN(ir);
nkeynes@736
   646
        LRN(ir) = addr + IMM12(ir);
nkeynes@736
   647
        break;
nkeynes@736
   648
    case 8: /* Rn - imm offset  [5.2.2 A5-20] */
nkeynes@736
   649
        addr = RN(ir) - IMM12(ir);
nkeynes@736
   650
        break;
nkeynes@736
   651
    case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
nkeynes@736
   652
        addr = RN(ir) - IMM12(ir);
nkeynes@736
   653
        LRN(ir) = addr;
nkeynes@736
   654
        break;
nkeynes@736
   655
    case 12: /* Rn + imm offset  [5.2.2 A5-20] */
nkeynes@736
   656
        addr = RN(ir) + IMM12(ir);
nkeynes@736
   657
        break;
nkeynes@736
   658
    case 13: /* Rn += imm offset  [5.2.5 A5-24 ] */
nkeynes@736
   659
        addr = RN(ir) + IMM12(ir);
nkeynes@736
   660
        LRN(ir) = addr;
nkeynes@736
   661
        break;
nkeynes@736
   662
    case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
nkeynes@736
   663
    case 17:
nkeynes@736
   664
        addr = RN(ir);
nkeynes@736
   665
        LRN(ir) = addr - arm_get_address_index(ir);
nkeynes@736
   666
        break;
nkeynes@736
   667
    case 20: /* Rn += Rm (post-indexed)  [5.2.10 A5-32 ] */
nkeynes@736
   668
    case 21:
nkeynes@736
   669
        addr = RN(ir);
nkeynes@736
   670
        LRN(ir) = addr - arm_get_address_index(ir);
nkeynes@736
   671
        break;
nkeynes@736
   672
    case 24: /* Rn - Rm  [5.2.4 A5-23] */
nkeynes@736
   673
        addr = RN(ir) - arm_get_address_index(ir);
nkeynes@736
   674
        break;
nkeynes@736
   675
    case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
nkeynes@736
   676
        addr = RN(ir) - arm_get_address_index(ir);
nkeynes@736
   677
        LRN(ir) = addr;
nkeynes@736
   678
        break;
nkeynes@736
   679
    case 28: /* Rn + Rm  [5.2.4 A5-23] */
nkeynes@736
   680
        addr = RN(ir) + arm_get_address_index(ir);
nkeynes@736
   681
        break;
nkeynes@736
   682
    case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
nkeynes@736
   683
        addr = RN(ir) + arm_get_address_index(ir);
nkeynes@736
   684
        LRN(ir) = addr;
nkeynes@736
   685
        break;
nkeynes@736
   686
    }
nkeynes@736
   687
    return addr;
nkeynes@5
   688
}
nkeynes@5
   689
nkeynes@30
   690
gboolean arm_execute_instruction( void ) 
nkeynes@2
   691
{
nkeynes@59
   692
    uint32_t pc;
nkeynes@59
   693
    uint32_t ir;
nkeynes@49
   694
    uint32_t operand, operand2, tmp, tmp2, cond;
nkeynes@66
   695
    int i;
nkeynes@2
   696
nkeynes@52
   697
    tmp = armr.int_pending & (~armr.cpsr);
nkeynes@51
   698
    if( tmp ) {
nkeynes@736
   699
        if( tmp & CPSR_F ) {
nkeynes@736
   700
            arm_raise_exception( EXC_FAST_IRQ );
nkeynes@736
   701
        } else {
nkeynes@736
   702
            arm_raise_exception( EXC_IRQ );
nkeynes@736
   703
        }
nkeynes@51
   704
    }
nkeynes@51
   705
nkeynes@59
   706
    ir = MEM_READ_LONG(PC);
nkeynes@59
   707
    pc = PC + 4;
nkeynes@37
   708
    PC = pc;
nkeynes@2
   709
nkeynes@37
   710
    /** 
nkeynes@37
   711
     * Check the condition bits first - if the condition fails return 
nkeynes@37
   712
     * immediately without actually looking at the rest of the instruction.
nkeynes@37
   713
     */
nkeynes@37
   714
    switch( COND(ir) ) {
nkeynes@37
   715
    case 0: /* EQ */ 
nkeynes@736
   716
        cond = armr.z;
nkeynes@736
   717
        break;
nkeynes@37
   718
    case 1: /* NE */
nkeynes@736
   719
        cond = !armr.z;
nkeynes@736
   720
        break;
nkeynes@37
   721
    case 2: /* CS/HS */
nkeynes@736
   722
        cond = armr.c;
nkeynes@736
   723
        break;
nkeynes@37
   724
    case 3: /* CC/LO */
nkeynes@736
   725
        cond = !armr.c;
nkeynes@736
   726
        break;
nkeynes@37
   727
    case 4: /* MI */
nkeynes@736
   728
        cond = armr.n;
nkeynes@736
   729
        break;
nkeynes@37
   730
    case 5: /* PL */
nkeynes@736
   731
        cond = !armr.n;
nkeynes@736
   732
        break;
nkeynes@37
   733
    case 6: /* VS */
nkeynes@736
   734
        cond = armr.v;
nkeynes@736
   735
        break;
nkeynes@37
   736
    case 7: /* VC */
nkeynes@736
   737
        cond = !armr.v;
nkeynes@736
   738
        break;
nkeynes@37
   739
    case 8: /* HI */
nkeynes@736
   740
        cond = armr.c && !armr.z;
nkeynes@736
   741
        break;
nkeynes@37
   742
    case 9: /* LS */
nkeynes@736
   743
        cond = (!armr.c) || armr.z;
nkeynes@736
   744
        break;
nkeynes@37
   745
    case 10: /* GE */
nkeynes@736
   746
        cond = (armr.n == armr.v);
nkeynes@736
   747
        break;
nkeynes@37
   748
    case 11: /* LT */
nkeynes@736
   749
        cond = (armr.n != armr.v);
nkeynes@736
   750
        break;
nkeynes@37
   751
    case 12: /* GT */
nkeynes@736
   752
        cond = (!armr.z) && (armr.n == armr.v);
nkeynes@736
   753
        break;
nkeynes@37
   754
    case 13: /* LE */
nkeynes@736
   755
        cond = armr.z || (armr.n != armr.v);
nkeynes@736
   756
        break;
nkeynes@37
   757
    case 14: /* AL */
nkeynes@736
   758
        cond = 1;
nkeynes@736
   759
        break;
nkeynes@37
   760
    case 15: /* (NV) */
nkeynes@431
   761
    default:
nkeynes@736
   762
        cond = 0;
nkeynes@736
   763
        UNDEF(ir);
nkeynes@37
   764
    }
nkeynes@86
   765
    if( cond ) {
nkeynes@5
   766
nkeynes@736
   767
        /**
nkeynes@736
   768
         * Condition passed, now for the actual instructions...
nkeynes@736
   769
         */
nkeynes@736
   770
        switch( GRP(ir) ) {
nkeynes@736
   771
        case 0:
nkeynes@736
   772
            if( (ir & 0x0D900000) == 0x01000000 ) {
nkeynes@736
   773
                /* Instructions that aren't actual data processing even though
nkeynes@736
   774
                 * they sit in the DP instruction block.
nkeynes@736
   775
                 */
nkeynes@736
   776
                switch( ir & 0x0FF000F0 ) {
nkeynes@736
   777
                case 0x01200010: /* BX Rd */
nkeynes@736
   778
                    armr.t = ir & 0x01;
nkeynes@736
   779
                    armr.r[15] = RM(ir) & 0xFFFFFFFE;
nkeynes@736
   780
                    break;
nkeynes@736
   781
                case 0x01000000: /* MRS Rd, CPSR */
nkeynes@736
   782
                    LRD(ir) = arm_get_cpsr();
nkeynes@736
   783
                    break;
nkeynes@736
   784
                case 0x01400000: /* MRS Rd, SPSR */
nkeynes@736
   785
                    LRD(ir) = armr.spsr;
nkeynes@736
   786
                    break;
nkeynes@736
   787
                case 0x01200000: /* MSR CPSR, Rd */
nkeynes@736
   788
                    arm_set_cpsr( RM(ir), ir );
nkeynes@736
   789
                    break;
nkeynes@736
   790
                case 0x01600000: /* MSR SPSR, Rd */
nkeynes@736
   791
                    arm_set_spsr( RM(ir), ir );
nkeynes@736
   792
                    break;
nkeynes@736
   793
                case 0x03200000: /* MSR CPSR, imm */
nkeynes@736
   794
                    arm_set_cpsr( ROTIMM12(ir), ir );
nkeynes@736
   795
                    break;
nkeynes@736
   796
                case 0x03600000: /* MSR SPSR, imm */
nkeynes@736
   797
                    arm_set_spsr( ROTIMM12(ir), ir );
nkeynes@736
   798
                    break;
nkeynes@736
   799
                default:
nkeynes@736
   800
                    UNIMP(ir);
nkeynes@736
   801
                }
nkeynes@736
   802
            } else if( (ir & 0x0E000090) == 0x00000090 ) {
nkeynes@736
   803
                /* Neither are these */
nkeynes@736
   804
                switch( (ir>>5)&0x03 ) {
nkeynes@736
   805
                case 0:
nkeynes@736
   806
                    /* Arithmetic extension area */
nkeynes@736
   807
                    switch(OPCODE(ir)) {
nkeynes@736
   808
                    case 0: /* MUL */
nkeynes@736
   809
                        LRN(ir) = RM(ir) * RS(ir);
nkeynes@736
   810
                        break;
nkeynes@736
   811
                    case 1: /* MULS */
nkeynes@736
   812
                        tmp = RM(ir) * RS(ir);
nkeynes@736
   813
                        LRN(ir) = tmp;
nkeynes@736
   814
                        armr.n = tmp>>31;
nkeynes@736
   815
                        armr.z = (tmp == 0);
nkeynes@736
   816
                        break;
nkeynes@736
   817
                    case 2: /* MLA */
nkeynes@736
   818
                        LRN(ir) = RM(ir) * RS(ir) + RD(ir);
nkeynes@736
   819
                        break;
nkeynes@736
   820
                    case 3: /* MLAS */
nkeynes@736
   821
                        tmp = RM(ir) * RS(ir) + RD(ir);
nkeynes@736
   822
                        LRN(ir) = tmp;
nkeynes@736
   823
                        armr.n = tmp>>31;
nkeynes@736
   824
                        armr.z = (tmp == 0);
nkeynes@736
   825
                        break;
nkeynes@736
   826
                    case 8: /* UMULL */
nkeynes@736
   827
                    case 9: /* UMULLS */
nkeynes@736
   828
                    case 10: /* UMLAL */
nkeynes@736
   829
                    case 11: /* UMLALS */
nkeynes@736
   830
                    case 12: /* SMULL */
nkeynes@736
   831
                    case 13: /* SMULLS */
nkeynes@736
   832
                    case 14: /* SMLAL */
nkeynes@736
   833
                    case 15: /* SMLALS */
nkeynes@736
   834
                        UNIMP(ir);
nkeynes@736
   835
                        break;
nkeynes@736
   836
                    case 16: /* SWP */
nkeynes@736
   837
                        tmp = arm_read_long( RN(ir) );
nkeynes@736
   838
                        switch( RN(ir) & 0x03 ) {
nkeynes@736
   839
                        case 1:
nkeynes@736
   840
                            tmp = ROTATE_RIGHT_LONG(tmp, 8);
nkeynes@736
   841
                            break;
nkeynes@736
   842
                        case 2:
nkeynes@736
   843
                            tmp = ROTATE_RIGHT_LONG(tmp, 16);
nkeynes@736
   844
                            break;
nkeynes@736
   845
                        case 3:
nkeynes@736
   846
                            tmp = ROTATE_RIGHT_LONG(tmp, 24);
nkeynes@736
   847
                            break;
nkeynes@736
   848
                        }
nkeynes@736
   849
                        arm_write_long( RN(ir), RM(ir) );
nkeynes@736
   850
                        LRD(ir) = tmp;
nkeynes@736
   851
                        break;
nkeynes@736
   852
                        case 20: /* SWPB */
nkeynes@736
   853
                            tmp = arm_read_byte( RN(ir) );
nkeynes@736
   854
                            arm_write_byte( RN(ir), RM(ir) );
nkeynes@736
   855
                            LRD(ir) = tmp;
nkeynes@736
   856
                            break;
nkeynes@736
   857
                        default:
nkeynes@736
   858
                            UNIMP(ir);
nkeynes@736
   859
                    }
nkeynes@736
   860
                    break;
nkeynes@736
   861
                    case 1:
nkeynes@736
   862
                        if( LFLAG(ir) ) {
nkeynes@736
   863
                            /* LDRH */
nkeynes@736
   864
                        } else {
nkeynes@736
   865
                            /* STRH */
nkeynes@736
   866
                        }
nkeynes@736
   867
                        UNIMP(ir);
nkeynes@736
   868
                        break;
nkeynes@736
   869
                    case 2:
nkeynes@736
   870
                        if( LFLAG(ir) ) {
nkeynes@736
   871
                            /* LDRSB */
nkeynes@736
   872
                        } else {
nkeynes@736
   873
                        }
nkeynes@736
   874
                        UNIMP(ir);
nkeynes@736
   875
                        break;
nkeynes@736
   876
                    case 3:
nkeynes@736
   877
                        if( LFLAG(ir) ) {
nkeynes@736
   878
                            /* LDRSH */
nkeynes@736
   879
                        } else {
nkeynes@736
   880
                        }
nkeynes@736
   881
                        UNIMP(ir);
nkeynes@736
   882
                        break;
nkeynes@736
   883
                }
nkeynes@736
   884
            } else {
nkeynes@736
   885
                /* Data processing */
nkeynes@37
   886
nkeynes@736
   887
                switch(OPCODE(ir)) {
nkeynes@736
   888
                case 0: /* AND Rd, Rn, operand */
nkeynes@736
   889
                    LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
nkeynes@736
   890
                    break;
nkeynes@736
   891
                case 1: /* ANDS Rd, Rn, operand */
nkeynes@736
   892
                    operand = arm_get_shift_operand_s(ir) & RN(ir);
nkeynes@736
   893
                    LRD(ir) = operand;
nkeynes@736
   894
                    if( RDn(ir) == 15 ) {
nkeynes@736
   895
                        arm_restore_cpsr();
nkeynes@736
   896
                    } else {
nkeynes@736
   897
                        armr.n = operand>>31;
nkeynes@736
   898
                        armr.z = (operand == 0);
nkeynes@736
   899
                        armr.c = armr.shift_c;
nkeynes@736
   900
                    }
nkeynes@736
   901
                    break;
nkeynes@736
   902
                case 2: /* EOR Rd, Rn, operand */
nkeynes@736
   903
                    LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
nkeynes@736
   904
                    break;
nkeynes@736
   905
                case 3: /* EORS Rd, Rn, operand */
nkeynes@736
   906
                    operand = arm_get_shift_operand_s(ir) ^ RN(ir);
nkeynes@736
   907
                    LRD(ir) = operand;
nkeynes@736
   908
                    if( RDn(ir) == 15 ) {
nkeynes@736
   909
                        arm_restore_cpsr();
nkeynes@736
   910
                    } else {
nkeynes@736
   911
                        armr.n = operand>>31;
nkeynes@736
   912
                        armr.z = (operand == 0);
nkeynes@736
   913
                        armr.c = armr.shift_c;
nkeynes@736
   914
                    }
nkeynes@736
   915
                    break;
nkeynes@736
   916
                case 4: /* SUB Rd, Rn, operand */
nkeynes@736
   917
                    LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
nkeynes@736
   918
                    break;
nkeynes@736
   919
                case 5: /* SUBS Rd, Rn, operand */
nkeynes@736
   920
                    operand = RN(ir);
nkeynes@736
   921
                    operand2 = arm_get_shift_operand(ir);
nkeynes@736
   922
                    tmp = operand - operand2;
nkeynes@736
   923
                    LRD(ir) = tmp;
nkeynes@736
   924
                    if( RDn(ir) == 15 ) {
nkeynes@736
   925
                        arm_restore_cpsr();
nkeynes@736
   926
                    } else {
nkeynes@736
   927
                        armr.n = tmp>>31;
nkeynes@736
   928
                        armr.z = (tmp == 0);
nkeynes@736
   929
                        armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@736
   930
                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@736
   931
                    }
nkeynes@736
   932
                    break;
nkeynes@736
   933
                case 6: /* RSB Rd, operand, Rn */
nkeynes@736
   934
                    LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
nkeynes@736
   935
                    break;
nkeynes@736
   936
                case 7: /* RSBS Rd, operand, Rn */
nkeynes@736
   937
                    operand = arm_get_shift_operand(ir);
nkeynes@736
   938
                    operand2 = RN(ir);
nkeynes@736
   939
                    tmp = operand - operand2;
nkeynes@736
   940
                    LRD(ir) = tmp;
nkeynes@736
   941
                    if( RDn(ir) == 15 ) {
nkeynes@736
   942
                        arm_restore_cpsr();
nkeynes@736
   943
                    } else {
nkeynes@736
   944
                        armr.n = tmp>>31;
nkeynes@736
   945
                        armr.z = (tmp == 0);
nkeynes@736
   946
                        armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@736
   947
                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@736
   948
                    }
nkeynes@736
   949
                    break;
nkeynes@736
   950
                case 8: /* ADD Rd, Rn, operand */
nkeynes@736
   951
                    LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
nkeynes@736
   952
                    break;
nkeynes@736
   953
                case 9: /* ADDS Rd, Rn, operand */
nkeynes@736
   954
                    operand = arm_get_shift_operand(ir);
nkeynes@736
   955
                    operand2 = RN(ir);
nkeynes@736
   956
                    tmp = operand + operand2;
nkeynes@736
   957
                    LRD(ir) = tmp;
nkeynes@736
   958
                    if( RDn(ir) == 15 ) {
nkeynes@736
   959
                        arm_restore_cpsr();
nkeynes@736
   960
                    } else {
nkeynes@736
   961
                        armr.n = tmp>>31;
nkeynes@736
   962
                        armr.z = (tmp == 0);
nkeynes@736
   963
                        armr.c = IS_CARRY(tmp,operand,operand2);
nkeynes@736
   964
                        armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
nkeynes@736
   965
                    }
nkeynes@736
   966
                    break;			
nkeynes@736
   967
                case 10: /* ADC */
nkeynes@736
   968
                    LRD(ir) = RN(ir) + arm_get_shift_operand(ir) + 
nkeynes@736
   969
                    (armr.c ? 1 : 0);
nkeynes@736
   970
                    break;
nkeynes@736
   971
                case 11: /* ADCS */
nkeynes@736
   972
                    operand = arm_get_shift_operand(ir);
nkeynes@736
   973
                    operand2 = RN(ir);
nkeynes@736
   974
                    tmp = operand + operand2;
nkeynes@736
   975
                    tmp2 = tmp + armr.c ? 1 : 0;
nkeynes@736
   976
                    LRD(ir) = tmp2;
nkeynes@736
   977
                    if( RDn(ir) == 15 ) {
nkeynes@736
   978
                        arm_restore_cpsr();
nkeynes@736
   979
                    } else {
nkeynes@736
   980
                        armr.n = tmp >> 31;
nkeynes@736
   981
                        armr.z = (tmp == 0 );
nkeynes@736
   982
                        armr.c = IS_CARRY(tmp,operand,operand2) ||
nkeynes@736
   983
                        (tmp2 < tmp);
nkeynes@736
   984
                        armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
nkeynes@736
   985
                        ((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@736
   986
                    }
nkeynes@736
   987
                    break;
nkeynes@736
   988
                case 12: /* SBC */
nkeynes@736
   989
                    LRD(ir) = RN(ir) - arm_get_shift_operand(ir) - 
nkeynes@736
   990
                    (armr.c ? 0 : 1);
nkeynes@736
   991
                    break;
nkeynes@736
   992
                case 13: /* SBCS */
nkeynes@736
   993
                    operand = RN(ir);
nkeynes@736
   994
                    operand2 = arm_get_shift_operand(ir);
nkeynes@736
   995
                    tmp = operand - operand2;
nkeynes@736
   996
                    tmp2 = tmp - (armr.c ? 0 : 1);
nkeynes@736
   997
                    if( RDn(ir) == 15 ) {
nkeynes@736
   998
                        arm_restore_cpsr();
nkeynes@736
   999
                    } else {
nkeynes@736
  1000
                        armr.n = tmp >> 31;
nkeynes@736
  1001
                        armr.z = (tmp == 0 );
nkeynes@736
  1002
                        armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
nkeynes@736
  1003
                        (tmp2<tmp);
nkeynes@736
  1004
                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
nkeynes@736
  1005
                        ((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@736
  1006
                    }
nkeynes@736
  1007
                    break;
nkeynes@736
  1008
                case 14: /* RSC */
nkeynes@736
  1009
                    LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
nkeynes@736
  1010
                    (armr.c ? 0 : 1);
nkeynes@736
  1011
                    break;
nkeynes@736
  1012
                case 15: /* RSCS */
nkeynes@736
  1013
                    operand = arm_get_shift_operand(ir);
nkeynes@736
  1014
                    operand2 = RN(ir);
nkeynes@736
  1015
                    tmp = operand - operand2;
nkeynes@736
  1016
                    tmp2 = tmp - (armr.c ? 0 : 1);
nkeynes@736
  1017
                    if( RDn(ir) == 15 ) {
nkeynes@736
  1018
                        arm_restore_cpsr();
nkeynes@736
  1019
                    } else {
nkeynes@736
  1020
                        armr.n = tmp >> 31;
nkeynes@736
  1021
                        armr.z = (tmp == 0 );
nkeynes@736
  1022
                        armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
nkeynes@736
  1023
                        (tmp2<tmp);
nkeynes@736
  1024
                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
nkeynes@736
  1025
                        ((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@736
  1026
                    }
nkeynes@736
  1027
                    break;
nkeynes@736
  1028
                case 17: /* TST Rn, operand */
nkeynes@736
  1029
                    operand = arm_get_shift_operand_s(ir) & RN(ir);
nkeynes@736
  1030
                    armr.n = operand>>31;
nkeynes@736
  1031
                    armr.z = (operand == 0);
nkeynes@736
  1032
                    armr.c = armr.shift_c;
nkeynes@736
  1033
                    break;
nkeynes@736
  1034
                case 19: /* TEQ Rn, operand */
nkeynes@736
  1035
                    operand = arm_get_shift_operand_s(ir) ^ RN(ir);
nkeynes@736
  1036
                    armr.n = operand>>31;
nkeynes@736
  1037
                    armr.z = (operand == 0);
nkeynes@736
  1038
                    armr.c = armr.shift_c;
nkeynes@736
  1039
                    break;				
nkeynes@736
  1040
                case 21: /* CMP Rn, operand */
nkeynes@736
  1041
                    operand = RN(ir);
nkeynes@736
  1042
                    operand2 = arm_get_shift_operand(ir);
nkeynes@736
  1043
                    tmp = operand - operand2;
nkeynes@736
  1044
                    armr.n = tmp>>31;
nkeynes@736
  1045
                    armr.z = (tmp == 0);
nkeynes@736
  1046
                    armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@736
  1047
                    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@736
  1048
                    break;
nkeynes@736
  1049
                case 23: /* CMN Rn, operand */
nkeynes@736
  1050
                    operand = RN(ir);
nkeynes@736
  1051
                    operand2 = arm_get_shift_operand(ir);
nkeynes@736
  1052
                    tmp = operand + operand2;
nkeynes@736
  1053
                    armr.n = tmp>>31;
nkeynes@736
  1054
                    armr.z = (tmp == 0);
nkeynes@736
  1055
                    armr.c = IS_CARRY(tmp,operand,operand2);
nkeynes@736
  1056
                    armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
nkeynes@736
  1057
                    break;
nkeynes@736
  1058
                case 24: /* ORR Rd, Rn, operand */
nkeynes@736
  1059
                    LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
nkeynes@736
  1060
                    break;
nkeynes@736
  1061
                case 25: /* ORRS Rd, Rn, operand */
nkeynes@736
  1062
                    operand = arm_get_shift_operand_s(ir) | RN(ir);
nkeynes@736
  1063
                    LRD(ir) = operand;
nkeynes@736
  1064
                    if( RDn(ir) == 15 ) {
nkeynes@736
  1065
                        arm_restore_cpsr();
nkeynes@736
  1066
                    } else {
nkeynes@736
  1067
                        armr.n = operand>>31;
nkeynes@736
  1068
                        armr.z = (operand == 0);
nkeynes@736
  1069
                        armr.c = armr.shift_c;
nkeynes@736
  1070
                    }
nkeynes@736
  1071
                    break;
nkeynes@736
  1072
                case 26: /* MOV Rd, operand */
nkeynes@736
  1073
                    LRD(ir) = arm_get_shift_operand(ir);
nkeynes@736
  1074
                    break;
nkeynes@736
  1075
                case 27: /* MOVS Rd, operand */
nkeynes@736
  1076
                    operand = arm_get_shift_operand_s(ir);
nkeynes@736
  1077
                    LRD(ir) = operand;
nkeynes@736
  1078
                    if( RDn(ir) == 15 ) {
nkeynes@736
  1079
                        arm_restore_cpsr();
nkeynes@736
  1080
                    } else {
nkeynes@736
  1081
                        armr.n = operand>>31;
nkeynes@736
  1082
                        armr.z = (operand == 0);
nkeynes@736
  1083
                        armr.c = armr.shift_c;
nkeynes@736
  1084
                    }
nkeynes@736
  1085
                    break;
nkeynes@736
  1086
                case 28: /* BIC Rd, Rn, operand */
nkeynes@736
  1087
                    LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
nkeynes@736
  1088
                    break;
nkeynes@736
  1089
                case 29: /* BICS Rd, Rn, operand */
nkeynes@736
  1090
                    operand = RN(ir) & (~arm_get_shift_operand_s(ir));
nkeynes@736
  1091
                    LRD(ir) = operand;
nkeynes@736
  1092
                    if( RDn(ir) == 15 ) {
nkeynes@736
  1093
                        arm_restore_cpsr();
nkeynes@736
  1094
                    } else {
nkeynes@736
  1095
                        armr.n = operand>>31;
nkeynes@736
  1096
                        armr.z = (operand == 0);
nkeynes@736
  1097
                        armr.c = armr.shift_c;
nkeynes@736
  1098
                    }
nkeynes@736
  1099
                    break;
nkeynes@736
  1100
                case 30: /* MVN Rd, operand */
nkeynes@736
  1101
                    LRD(ir) = ~arm_get_shift_operand(ir);
nkeynes@736
  1102
                    break;
nkeynes@736
  1103
                case 31: /* MVNS Rd, operand */
nkeynes@736
  1104
                    operand = ~arm_get_shift_operand_s(ir);
nkeynes@736
  1105
                    LRD(ir) = operand;
nkeynes@736
  1106
                    if( RDn(ir) == 15 ) {
nkeynes@736
  1107
                        arm_restore_cpsr();
nkeynes@736
  1108
                    } else {
nkeynes@736
  1109
                        armr.n = operand>>31;
nkeynes@736
  1110
                        armr.z = (operand == 0);
nkeynes@736
  1111
                        armr.c = armr.shift_c;
nkeynes@736
  1112
                    }
nkeynes@736
  1113
                    break;
nkeynes@736
  1114
                default:
nkeynes@736
  1115
                    UNIMP(ir);
nkeynes@736
  1116
                }
nkeynes@736
  1117
            }
nkeynes@736
  1118
            break;
nkeynes@736
  1119
        case 1: /* Load/store */
nkeynes@736
  1120
            operand = arm_get_address_operand(ir);
nkeynes@736
  1121
            switch( (ir>>20)&0x17 ) {
nkeynes@736
  1122
            case 0: case 16: case 18: /* STR Rd, address */
nkeynes@736
  1123
                arm_write_long( operand, RD(ir) );
nkeynes@736
  1124
                break;
nkeynes@736
  1125
            case 1: case 17: case 19: /* LDR Rd, address */
nkeynes@736
  1126
                LRD(ir) = arm_read_long(operand);
nkeynes@736
  1127
                break;
nkeynes@736
  1128
            case 2: /* STRT Rd, address */
nkeynes@736
  1129
                arm_write_long_user( operand, RD(ir) );
nkeynes@736
  1130
                break;
nkeynes@736
  1131
            case 3: /* LDRT Rd, address */
nkeynes@736
  1132
                LRD(ir) = arm_read_long_user( operand );
nkeynes@736
  1133
                break;
nkeynes@736
  1134
            case 4: case 20: case 22: /* STRB Rd, address */
nkeynes@736
  1135
                arm_write_byte( operand, RD(ir) );
nkeynes@736
  1136
                break;
nkeynes@736
  1137
            case 5: case 21: case 23: /* LDRB Rd, address */
nkeynes@736
  1138
                LRD(ir) = arm_read_byte( operand );
nkeynes@736
  1139
                break;
nkeynes@736
  1140
            case 6: /* STRBT Rd, address */
nkeynes@736
  1141
                arm_write_byte_user( operand, RD(ir) );
nkeynes@736
  1142
                break;
nkeynes@736
  1143
            case 7: /* LDRBT Rd, address */
nkeynes@736
  1144
                LRD(ir) = arm_read_byte_user( operand );
nkeynes@736
  1145
                break;
nkeynes@736
  1146
            }
nkeynes@736
  1147
            break;
nkeynes@736
  1148
            case 2: /* Load/store multiple, branch*/
nkeynes@736
  1149
                if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
nkeynes@736
  1150
                    operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
nkeynes@736
  1151
                    if( (ir & 0x01000000) == 0x01000000 ) { 
nkeynes@736
  1152
                        armr.r[14] = pc; /* BL */
nkeynes@736
  1153
                    }
nkeynes@736
  1154
                    armr.r[15] = pc + 4 + operand;
nkeynes@736
  1155
                } else { /* Load/store multiple */
nkeynes@736
  1156
                    gboolean needRestore = FALSE;
nkeynes@736
  1157
                    operand = RN(ir);
nkeynes@736
  1158
nkeynes@736
  1159
                    switch( (ir & 0x01D00000) >> 20 ) {
nkeynes@736
  1160
                    case 0: /* STMDA */
nkeynes@736
  1161
                        if( ir & 0x8000 ) {
nkeynes@736
  1162
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1163
                            operand -= 4;
nkeynes@736
  1164
                        }
nkeynes@736
  1165
                        for( i=14; i>= 0; i-- ) {
nkeynes@736
  1166
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1167
                                arm_write_long( operand, armr.r[i] );
nkeynes@736
  1168
                                operand -= 4;
nkeynes@736
  1169
                            }
nkeynes@736
  1170
                        }
nkeynes@736
  1171
                        break;
nkeynes@736
  1172
                    case 1: /* LDMDA */
nkeynes@736
  1173
                        for( i=15; i>= 0; i-- ) {
nkeynes@736
  1174
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1175
                                armr.r[i] = arm_read_long( operand );
nkeynes@736
  1176
                                operand -= 4;
nkeynes@736
  1177
                            }
nkeynes@736
  1178
                        }
nkeynes@736
  1179
                        break;
nkeynes@736
  1180
                    case 4: /* STMDA (S) */
nkeynes@736
  1181
                        if( ir & 0x8000 ) {
nkeynes@736
  1182
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1183
                            operand -= 4;
nkeynes@736
  1184
                        }
nkeynes@736
  1185
                        for( i=14; i>= 0; i-- ) {
nkeynes@736
  1186
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1187
                                arm_write_long( operand, USER_R(i) );
nkeynes@736
  1188
                                operand -= 4;
nkeynes@736
  1189
                            }
nkeynes@736
  1190
                        }
nkeynes@736
  1191
                        break;
nkeynes@736
  1192
                    case 5: /* LDMDA (S) */
nkeynes@736
  1193
                        if( (ir&0x00008000) ) { /* Load PC */
nkeynes@736
  1194
                            for( i=15; i>= 0; i-- ) {
nkeynes@736
  1195
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1196
                                    armr.r[i] = arm_read_long( operand );
nkeynes@736
  1197
                                    operand -= 4;
nkeynes@736
  1198
                                }
nkeynes@736
  1199
                            }
nkeynes@736
  1200
                            needRestore = TRUE;
nkeynes@736
  1201
                        } else {
nkeynes@736
  1202
                            for( i=15; i>= 0; i-- ) {
nkeynes@736
  1203
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1204
                                    USER_R(i) = arm_read_long( operand );
nkeynes@736
  1205
                                    operand -= 4;
nkeynes@736
  1206
                                }
nkeynes@736
  1207
                            }
nkeynes@736
  1208
                        }
nkeynes@736
  1209
                        break;
nkeynes@736
  1210
                    case 8: /* STMIA */
nkeynes@736
  1211
                        for( i=0; i< 15; i++ ) {
nkeynes@736
  1212
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1213
                                arm_write_long( operand, armr.r[i] );
nkeynes@736
  1214
                                operand += 4;
nkeynes@736
  1215
                            }
nkeynes@736
  1216
                        }
nkeynes@736
  1217
                        if( ir & 0x8000 ) {
nkeynes@736
  1218
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1219
                            operand += 4;
nkeynes@736
  1220
                        }
nkeynes@736
  1221
                        break;
nkeynes@736
  1222
                    case 9: /* LDMIA */
nkeynes@736
  1223
                        for( i=0; i< 16; i++ ) {
nkeynes@736
  1224
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1225
                                armr.r[i] = arm_read_long( operand );
nkeynes@736
  1226
                                operand += 4;
nkeynes@736
  1227
                            }
nkeynes@736
  1228
                        }
nkeynes@736
  1229
                        break;
nkeynes@736
  1230
                    case 12: /* STMIA (S) */
nkeynes@736
  1231
                        for( i=0; i< 15; i++ ) {
nkeynes@736
  1232
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1233
                                arm_write_long( operand, USER_R(i) );
nkeynes@736
  1234
                                operand += 4;
nkeynes@736
  1235
                            }
nkeynes@736
  1236
                        }
nkeynes@736
  1237
                        if( ir & 0x8000 ) {
nkeynes@736
  1238
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1239
                            operand += 4;
nkeynes@736
  1240
                        }
nkeynes@736
  1241
                        break;
nkeynes@736
  1242
                    case 13: /* LDMIA (S) */
nkeynes@736
  1243
                        if( (ir&0x00008000) ) { /* Load PC */
nkeynes@736
  1244
                            for( i=0; i < 16; i++ ) {
nkeynes@736
  1245
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1246
                                    armr.r[i] = arm_read_long( operand );
nkeynes@736
  1247
                                    operand += 4;
nkeynes@736
  1248
                                }
nkeynes@736
  1249
                            }
nkeynes@736
  1250
                            needRestore = TRUE;
nkeynes@736
  1251
                        } else {
nkeynes@736
  1252
                            for( i=0; i < 16; i++ ) {
nkeynes@736
  1253
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1254
                                    USER_R(i) = arm_read_long( operand );
nkeynes@736
  1255
                                    operand += 4;
nkeynes@736
  1256
                                }
nkeynes@736
  1257
                            }
nkeynes@736
  1258
                        }
nkeynes@736
  1259
                        break;
nkeynes@736
  1260
                    case 16: /* STMDB */
nkeynes@736
  1261
                        if( ir & 0x8000 ) {
nkeynes@736
  1262
                            operand -= 4;
nkeynes@736
  1263
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1264
                        }
nkeynes@736
  1265
                        for( i=14; i>= 0; i-- ) {
nkeynes@736
  1266
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1267
                                operand -= 4;
nkeynes@736
  1268
                                arm_write_long( operand, armr.r[i] );
nkeynes@736
  1269
                            }
nkeynes@736
  1270
                        }
nkeynes@736
  1271
                        break;
nkeynes@736
  1272
                    case 17: /* LDMDB */
nkeynes@736
  1273
                        for( i=15; i>= 0; i-- ) {
nkeynes@736
  1274
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1275
                                operand -= 4;
nkeynes@736
  1276
                                armr.r[i] = arm_read_long( operand );
nkeynes@736
  1277
                            }
nkeynes@736
  1278
                        }
nkeynes@736
  1279
                        break;
nkeynes@736
  1280
                    case 20: /* STMDB (S) */
nkeynes@736
  1281
                        if( ir & 0x8000 ) {
nkeynes@736
  1282
                            operand -= 4;
nkeynes@736
  1283
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1284
                        }
nkeynes@736
  1285
                        for( i=14; i>= 0; i-- ) {
nkeynes@736
  1286
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1287
                                operand -= 4;
nkeynes@736
  1288
                                arm_write_long( operand, USER_R(i) );
nkeynes@736
  1289
                            }
nkeynes@736
  1290
                        }
nkeynes@736
  1291
                        break;
nkeynes@736
  1292
                    case 21: /* LDMDB (S) */
nkeynes@736
  1293
                        if( (ir&0x00008000) ) { /* Load PC */
nkeynes@736
  1294
                            for( i=15; i>= 0; i-- ) {
nkeynes@736
  1295
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1296
                                    operand -= 4;
nkeynes@736
  1297
                                    armr.r[i] = arm_read_long( operand );
nkeynes@736
  1298
                                }
nkeynes@736
  1299
                            }
nkeynes@736
  1300
                            needRestore = TRUE;
nkeynes@736
  1301
                        } else {
nkeynes@736
  1302
                            for( i=15; i>= 0; i-- ) {
nkeynes@736
  1303
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1304
                                    operand -= 4;
nkeynes@736
  1305
                                    USER_R(i) = arm_read_long( operand );
nkeynes@736
  1306
                                }
nkeynes@736
  1307
                            }
nkeynes@736
  1308
                        }
nkeynes@736
  1309
                        break;
nkeynes@736
  1310
                    case 24: /* STMIB */
nkeynes@736
  1311
                        for( i=0; i< 15; i++ ) {
nkeynes@736
  1312
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1313
                                operand += 4;
nkeynes@736
  1314
                                arm_write_long( operand, armr.r[i] );
nkeynes@736
  1315
                            }
nkeynes@736
  1316
                        }
nkeynes@736
  1317
                        if( ir & 0x8000 ) {
nkeynes@736
  1318
                            operand += 4;
nkeynes@736
  1319
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1320
                        }
nkeynes@736
  1321
                        break;
nkeynes@736
  1322
                    case 25: /* LDMIB */
nkeynes@736
  1323
                        for( i=0; i< 16; i++ ) {
nkeynes@736
  1324
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1325
                                operand += 4;
nkeynes@736
  1326
                                armr.r[i] = arm_read_long( operand );
nkeynes@736
  1327
                            }
nkeynes@736
  1328
                        }
nkeynes@736
  1329
                        break;
nkeynes@736
  1330
                    case 28: /* STMIB (S) */
nkeynes@736
  1331
                        for( i=0; i< 15; i++ ) {
nkeynes@736
  1332
                            if( (ir & (1<<i)) ) {
nkeynes@736
  1333
                                operand += 4;
nkeynes@736
  1334
                                arm_write_long( operand, USER_R(i) );
nkeynes@736
  1335
                            }
nkeynes@736
  1336
                        }
nkeynes@736
  1337
                        if( ir & 0x8000 ) {
nkeynes@736
  1338
                            operand += 4;
nkeynes@736
  1339
                            arm_write_long( operand, armr.r[15]+4 );
nkeynes@736
  1340
                        }
nkeynes@736
  1341
                        break;
nkeynes@736
  1342
                    case 29: /* LDMIB (S) */
nkeynes@736
  1343
                        if( (ir&0x00008000) ) { /* Load PC */
nkeynes@736
  1344
                            for( i=0; i < 16; i++ ) {
nkeynes@736
  1345
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1346
                                    operand += 4;
nkeynes@736
  1347
                                    armr.r[i] = arm_read_long( operand );
nkeynes@736
  1348
                                }
nkeynes@736
  1349
                            }
nkeynes@736
  1350
                            needRestore = TRUE;
nkeynes@736
  1351
                        } else {
nkeynes@736
  1352
                            for( i=0; i < 16; i++ ) {
nkeynes@736
  1353
                                if( (ir & (1<<i)) ) {
nkeynes@736
  1354
                                    operand += 4;
nkeynes@736
  1355
                                    USER_R(i) = arm_read_long( operand );
nkeynes@736
  1356
                                }
nkeynes@736
  1357
                            }
nkeynes@736
  1358
                        }
nkeynes@736
  1359
                        break;
nkeynes@736
  1360
                    }
nkeynes@736
  1361
nkeynes@736
  1362
                    if( WFLAG(ir) ) 
nkeynes@736
  1363
                        LRN(ir) = operand;
nkeynes@736
  1364
                    if( needRestore ) 
nkeynes@736
  1365
                        arm_restore_cpsr();
nkeynes@736
  1366
                }
nkeynes@736
  1367
                break;
nkeynes@736
  1368
            case 3: /* Copro */
nkeynes@736
  1369
                if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
nkeynes@736
  1370
                    arm_raise_exception( EXC_SOFTWARE );
nkeynes@736
  1371
                } else {
nkeynes@736
  1372
                    UNIMP(ir);
nkeynes@736
  1373
                }
nkeynes@736
  1374
                break;
nkeynes@736
  1375
        }
nkeynes@86
  1376
nkeynes@86
  1377
    }
nkeynes@86
  1378
nkeynes@86
  1379
    if( armr.r[15] >= 0x00200000 ) {
nkeynes@736
  1380
        armr.running = FALSE;
nkeynes@736
  1381
        WARN( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
nkeynes@736
  1382
        return FALSE;
nkeynes@81
  1383
    }
nkeynes@37
  1384
    return TRUE;
nkeynes@2
  1385
}
.