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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 736:a02d1475ccfd
prev728:4dfc293b9d96
next753:1fe39c3a9bbc
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "sh4/sh4.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "pvr2/pvr2.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static uint32_t asic_run_slice( uint32_t nanosecs );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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        NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 60
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#define G2_BIT4_TICKS 160
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#define G2_BIT0_ON_TICKS 120
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#define G2_BIT0_OFF_TICKS 420
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struct asic_g2_state {
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    int bit5_off_timer;
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    int bit4_on_timer;
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    int bit4_off_timer;
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    int bit0_on_timer;
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    int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static uint32_t asic_run_slice( uint32_t nanosecs )
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{
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    g2_update_fifo_status(nanosecs);
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    if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit5_off_timer = -1;
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    } else {
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        g2_state.bit5_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit4_off_timer = -1;
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    } else {
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        g2_state.bit4_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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        g2_state.bit4_on_timer = -1;
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    } else {
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        g2_state.bit4_on_timer -= nanosecs;
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    }
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    if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit0_off_timer = -1;
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    } else {
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        g2_state.bit0_off_timer -= nanosecs;
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    }
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    if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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        g2_state.bit0_on_timer = -1;
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    } else {
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        g2_state.bit0_on_timer -= nanosecs;
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    }
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    return nanosecs;
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}
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0xFF, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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        return 1;
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    else
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        return 0;
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}
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/**
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 * Setup the timers for the 3 FIFO status bits following a write through the G2
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 * bus from the SH4 side. The timing is roughly as follows: (times are
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 * approximate based on software readings - I wouldn't take this as gospel but
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 * it seems to be enough to fool most programs). 
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 *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
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 *   40ns: Bit 5 goes low and bit 4 goes high
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 *  120ns: Bit 4 goes low, bit 0 goes high
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 *  240ns: Bit 0 goes low.
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 *
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 * Additional writes while the FIFO is in operation extend the time that the
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 * bits remain high as one might expect, without altering the time at which
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 * they initially go high.
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 */
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void asic_g2_write_word()
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{
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    if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    } else {
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        g2_state.bit5_off_timer += G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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    } else {
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        g2_state.bit4_off_timer += G2_BIT4_TICKS;
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    }
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    if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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    }
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    if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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        g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_update_fifo_status( uint32_t nanos )
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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        val = val & (~0x20);
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        g2_state.bit5_off_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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        val = val | 0x10;
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        g2_state.bit4_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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        val = val & (~0x10);
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        g2_state.bit4_off_timer = -1;
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    } 
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    if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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        val = val | 0x01;
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        g2_state.bit0_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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        val = val & (~0x01);
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        g2_state.bit0_off_timer = -1;
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    } 
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    MMIO_WRITE( ASIC, G2STATUS, val );
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    return val;
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}   
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static int g2_read_status() {
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    return g2_update_fifo_status( sh4r.slice_cycle );
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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    if( event >= 64 ) { /* Third word */
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        asic_event( EVENT_CASCADE2 );
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    } else if( event >= 32 ) { /* Second word */
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        asic_event( EVENT_CASCADE1 );
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    }
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    if( result == 0 ) {
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        /* clear cascades if necessary */
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        if( event >= 64 ) {
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            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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        } else if( event >= 32 ) {
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            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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        }
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    }
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<12; i+=4 ) {
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        bits = MMIO_READ( ASIC, PIRQ0 + i );
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        setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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        setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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        setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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        intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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        intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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        intc_clear_interrupt( INT_IRQ9 );
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}
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void asic_event_mask_changed( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<12; i+=4 ) {
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        bits = MMIO_READ( ASIC, PIRQ0 + i );
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        setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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        setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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        setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 ) 
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        intc_clear_interrupt( INT_IRQ13 );
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    else
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        intc_raise_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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        intc_clear_interrupt( INT_IRQ11 );
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    else
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        intc_raise_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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        intc_clear_interrupt( INT_IRQ9 );
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    else
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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{
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    uint32_t offset = channel << 5;
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    if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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        if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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            uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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            uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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            uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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            uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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            // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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            unsigned char buf[length];
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            if( dir == 0 ) { /* SH4 to device */
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                mem_copy_from_sh4( buf, sh4addr, length );
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                mem_copy_to_sh4( extaddr, buf, length );
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            } else { /* Device to SH4 */
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                mem_copy_from_sh4( buf, extaddr, length );
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                mem_copy_to_sh4( sh4addr, buf, length );
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            }
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            MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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            asic_event( EVENT_G2_DMA0 + channel );
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        } else {
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            MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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        }
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    }
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}
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void asic_ide_dma_transfer( )
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{	
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    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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        if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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            MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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            uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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            uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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            // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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            uint32_t xfer = ide_read_data_dma( addr, length );
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            MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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            MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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        } else { /* 0 */
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            MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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        }
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    }
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}
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void pvr_dma_transfer( )
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{
nkeynes@325
   336
    sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
nkeynes@325
   337
    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@430
   338
    unsigned char *data = alloca( count );
nkeynes@325
   339
    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@325
   340
    if( rcount != count )
nkeynes@736
   341
        WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@736
   342
nkeynes@325
   343
    pvr2_dma_write( destaddr, data, rcount );
nkeynes@736
   344
nkeynes@325
   345
    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@325
   346
    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@325
   347
    if( destaddr & 0x01000000 ) { /* Write to texture RAM */
nkeynes@736
   348
        MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
nkeynes@325
   349
    }
nkeynes@325
   350
    asic_event( EVENT_PVR_DMA );
nkeynes@325
   351
}
nkeynes@155
   352
nkeynes@728
   353
void sort_dma_transfer( )
nkeynes@728
   354
{
nkeynes@728
   355
    sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
nkeynes@728
   356
    sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
nkeynes@728
   357
    int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
nkeynes@728
   358
    int data_size = MMIO_READ( ASIC, SORTDMADSIZ );
nkeynes@736
   359
nkeynes@728
   360
    WARN( "Sort DMA not implemented" );
nkeynes@728
   361
}
nkeynes@728
   362
nkeynes@1
   363
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
nkeynes@1
   364
{
nkeynes@1
   365
    switch( reg ) {
nkeynes@125
   366
    case PIRQ1:
nkeynes@736
   367
        break; /* Treat this as read-only for the moment */
nkeynes@56
   368
    case PIRQ0:
nkeynes@736
   369
        val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
nkeynes@736
   370
        MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
nkeynes@736
   371
        asic_check_cleared_events();
nkeynes@736
   372
        break;
nkeynes@56
   373
    case PIRQ2:
nkeynes@736
   374
        /* Clear any events */
nkeynes@736
   375
        val = MMIO_READ(ASIC, reg)&(~val);
nkeynes@736
   376
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   377
        if( val == 0 ) { /* all clear - clear the cascade bit */
nkeynes@736
   378
            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
nkeynes@736
   379
        }
nkeynes@736
   380
        asic_check_cleared_events();
nkeynes@736
   381
        break;
nkeynes@594
   382
    case IRQA0:
nkeynes@594
   383
    case IRQA1:
nkeynes@594
   384
    case IRQA2:
nkeynes@594
   385
    case IRQB0:
nkeynes@594
   386
    case IRQB1:
nkeynes@594
   387
    case IRQB2:
nkeynes@594
   388
    case IRQC0:
nkeynes@594
   389
    case IRQC1:
nkeynes@594
   390
    case IRQC2:
nkeynes@736
   391
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   392
        asic_event_mask_changed();
nkeynes@736
   393
        break;
nkeynes@244
   394
    case SYSRESET:
nkeynes@736
   395
        if( val == 0x7611 ) {
nkeynes@736
   396
            dreamcast_reset();
nkeynes@736
   397
        } else {
nkeynes@736
   398
            WARN( "Unknown value %08X written to SYSRESET port", val );
nkeynes@736
   399
        }
nkeynes@736
   400
        break;
nkeynes@56
   401
    case MAPLE_STATE:
nkeynes@736
   402
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   403
        if( val & 1 ) {
nkeynes@736
   404
            uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@736
   405
            maple_handle_buffer( maple_addr );
nkeynes@736
   406
            MMIO_WRITE( ASIC, reg, 0 );
nkeynes@736
   407
        }
nkeynes@736
   408
        break;
nkeynes@325
   409
    case PVRDMADEST:
nkeynes@736
   410
        MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
nkeynes@736
   411
        break;
nkeynes@325
   412
    case PVRDMACNT: 
nkeynes@736
   413
        MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
nkeynes@736
   414
        break;
nkeynes@56
   415
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@736
   416
        val = val & 0x01;
nkeynes@736
   417
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   418
        if( val == 1 ) {
nkeynes@736
   419
            pvr_dma_transfer();
nkeynes@736
   420
        }
nkeynes@736
   421
        break;
nkeynes@728
   422
    case SORTDMATBL: case SORTDMADATA:
nkeynes@728
   423
        MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
nkeynes@728
   424
        break;
nkeynes@728
   425
    case SORTDMATSIZ: case SORTDMADSIZ:
nkeynes@728
   426
        MMIO_WRITE( ASIC, reg, (val & 1) );
nkeynes@728
   427
        break;
nkeynes@728
   428
    case SORTDMACTL:
nkeynes@728
   429
        val = val & 1;
nkeynes@728
   430
        MMIO_WRITE( ASIC, reg, val );
nkeynes@728
   431
        if( val == 1 ) {
nkeynes@728
   432
            sort_dma_transfer();
nkeynes@728
   433
        }
nkeynes@728
   434
        break;
nkeynes@325
   435
    case MAPLE_DMA:
nkeynes@736
   436
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   437
        break;
nkeynes@56
   438
    default:
nkeynes@736
   439
        MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   440
    }
nkeynes@1
   441
}
nkeynes@1
   442
nkeynes@1
   443
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   444
{
nkeynes@1
   445
    int32_t val;
nkeynes@1
   446
    switch( reg ) {
nkeynes@94
   447
    case PIRQ0:
nkeynes@94
   448
    case PIRQ1:
nkeynes@94
   449
    case PIRQ2:
nkeynes@94
   450
    case IRQA0:
nkeynes@94
   451
    case IRQA1:
nkeynes@94
   452
    case IRQA2:
nkeynes@94
   453
    case IRQB0:
nkeynes@94
   454
    case IRQB1:
nkeynes@94
   455
    case IRQB2:
nkeynes@94
   456
    case IRQC0:
nkeynes@94
   457
    case IRQC1:
nkeynes@94
   458
    case IRQC2:
nkeynes@158
   459
    case MAPLE_STATE:
nkeynes@736
   460
        val = MMIO_READ(ASIC, reg);
nkeynes@736
   461
        return val;            
nkeynes@94
   462
    case G2STATUS:
nkeynes@736
   463
        return g2_read_status();
nkeynes@94
   464
    default:
nkeynes@736
   465
        val = MMIO_READ(ASIC, reg);
nkeynes@736
   466
        return val;
nkeynes@1
   467
    }
nkeynes@736
   468
nkeynes@1
   469
}
nkeynes@1
   470
nkeynes@1
   471
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   472
{
nkeynes@244
   473
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@736
   474
        return; /* disabled */
nkeynes@244
   475
    }
nkeynes@244
   476
nkeynes@2
   477
    switch( reg ) {
nkeynes@125
   478
    case IDEALTSTATUS: /* Device control */
nkeynes@736
   479
        ide_write_control( val );
nkeynes@736
   480
        break;
nkeynes@125
   481
    case IDEDATA:
nkeynes@736
   482
        ide_write_data_pio( val );
nkeynes@736
   483
        break;
nkeynes@125
   484
    case IDEFEAT:
nkeynes@736
   485
        if( ide_can_write_regs() )
nkeynes@736
   486
            idereg.feature = (uint8_t)val;
nkeynes@736
   487
        break;
nkeynes@125
   488
    case IDECOUNT:
nkeynes@736
   489
        if( ide_can_write_regs() )
nkeynes@736
   490
            idereg.count = (uint8_t)val;
nkeynes@736
   491
        break;
nkeynes@125
   492
    case IDELBA0:
nkeynes@736
   493
        if( ide_can_write_regs() )
nkeynes@736
   494
            idereg.lba0 = (uint8_t)val;
nkeynes@736
   495
        break;
nkeynes@125
   496
    case IDELBA1:
nkeynes@736
   497
        if( ide_can_write_regs() )
nkeynes@736
   498
            idereg.lba1 = (uint8_t)val;
nkeynes@736
   499
        break;
nkeynes@125
   500
    case IDELBA2:
nkeynes@736
   501
        if( ide_can_write_regs() )
nkeynes@736
   502
            idereg.lba2 = (uint8_t)val;
nkeynes@736
   503
        break;
nkeynes@125
   504
    case IDEDEV:
nkeynes@736
   505
        if( ide_can_write_regs() )
nkeynes@736
   506
            idereg.device = (uint8_t)val;
nkeynes@736
   507
        break;
nkeynes@125
   508
    case IDECMD:
nkeynes@736
   509
        if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@736
   510
            ide_write_command( (uint8_t)val );
nkeynes@736
   511
        }
nkeynes@736
   512
        break;
nkeynes@334
   513
    case IDEDMASH4:
nkeynes@736
   514
        MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
nkeynes@736
   515
        break;
nkeynes@334
   516
    case IDEDMASIZ:
nkeynes@736
   517
        MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
nkeynes@736
   518
        break;
nkeynes@549
   519
    case IDEDMADIR:
nkeynes@736
   520
        MMIO_WRITE( EXTDMA, reg, val & 1 );
nkeynes@736
   521
        break;
nkeynes@125
   522
    case IDEDMACTL1:
nkeynes@125
   523
    case IDEDMACTL2:
nkeynes@736
   524
        MMIO_WRITE( EXTDMA, reg, val & 0x01 );
nkeynes@736
   525
        asic_ide_dma_transfer( );
nkeynes@736
   526
        break;
nkeynes@244
   527
    case IDEACTIVATE:
nkeynes@736
   528
        if( val == 0x001FFFFF ) {
nkeynes@736
   529
            idereg.interface_enabled = TRUE;
nkeynes@736
   530
            /* Conventional wisdom says that this is necessary but not
nkeynes@736
   531
             * sufficient to enable the IDE interface.
nkeynes@736
   532
             */
nkeynes@736
   533
        } else if( val == 0x000042FE ) {
nkeynes@736
   534
            idereg.interface_enabled = FALSE;
nkeynes@736
   535
        }
nkeynes@736
   536
        break;
nkeynes@549
   537
    case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
nkeynes@549
   538
    case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
nkeynes@549
   539
    case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
nkeynes@549
   540
    case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
nkeynes@736
   541
        MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
nkeynes@736
   542
        break;
nkeynes@549
   543
    case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
nkeynes@736
   544
        MMIO_WRITE( EXTDMA, reg, val & 0x07 );
nkeynes@736
   545
        break;
nkeynes@549
   546
    case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
nkeynes@736
   547
        MMIO_WRITE( EXTDMA, reg, val & 0x01 );
nkeynes@736
   548
        break;
nkeynes@302
   549
    case G2DMA0CTL1:
nkeynes@302
   550
    case G2DMA0CTL2:
nkeynes@736
   551
        MMIO_WRITE( EXTDMA, reg, val & 1);
nkeynes@736
   552
        g2_dma_transfer( 0 );
nkeynes@736
   553
        break;
nkeynes@302
   554
    case G2DMA0STOP:
nkeynes@736
   555
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   556
        break;
nkeynes@302
   557
    case G2DMA1CTL1:
nkeynes@302
   558
    case G2DMA1CTL2:
nkeynes@736
   559
        MMIO_WRITE( EXTDMA, reg, val & 1);
nkeynes@736
   560
        g2_dma_transfer( 1 );
nkeynes@736
   561
        break;
nkeynes@279
   562
nkeynes@302
   563
    case G2DMA1STOP:
nkeynes@736
   564
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   565
        break;
nkeynes@302
   566
    case G2DMA2CTL1:
nkeynes@302
   567
    case G2DMA2CTL2:
nkeynes@736
   568
        MMIO_WRITE( EXTDMA, reg, val &1 );
nkeynes@736
   569
        g2_dma_transfer( 2 );
nkeynes@736
   570
        break;
nkeynes@302
   571
    case G2DMA2STOP:
nkeynes@736
   572
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   573
        break;
nkeynes@302
   574
    case G2DMA3CTL1:
nkeynes@302
   575
    case G2DMA3CTL2:
nkeynes@736
   576
        MMIO_WRITE( EXTDMA, reg, val &1 );
nkeynes@736
   577
        g2_dma_transfer( 3 );
nkeynes@736
   578
        break;
nkeynes@302
   579
    case G2DMA3STOP:
nkeynes@736
   580
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   581
        break;
nkeynes@279
   582
    case PVRDMA2CTL1:
nkeynes@279
   583
    case PVRDMA2CTL2:
nkeynes@736
   584
        if( val != 0 ) {
nkeynes@736
   585
            ERROR( "Write to unimplemented DMA control register %08X", reg );
nkeynes@736
   586
        }
nkeynes@736
   587
        break;
nkeynes@125
   588
    default:
nkeynes@736
   589
        MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   590
    }
nkeynes@1
   591
}
nkeynes@1
   592
nkeynes@1
   593
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   594
{
nkeynes@56
   595
    uint32_t val;
nkeynes@244
   596
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@736
   597
        return 0xFFFFFFFF; /* disabled */
nkeynes@244
   598
    }
nkeynes@244
   599
nkeynes@1
   600
    switch( reg ) {
nkeynes@158
   601
    case IDEALTSTATUS: 
nkeynes@736
   602
        val = idereg.status;
nkeynes@736
   603
        return val;
nkeynes@158
   604
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   605
    case IDEFEAT: return idereg.error;
nkeynes@158
   606
    case IDECOUNT:return idereg.count;
nkeynes@342
   607
    case IDELBA0: return ide_get_drive_status();
nkeynes@158
   608
    case IDELBA1: return idereg.lba1;
nkeynes@158
   609
    case IDELBA2: return idereg.lba2;
nkeynes@158
   610
    case IDEDEV: return idereg.device;
nkeynes@158
   611
    case IDECMD:
nkeynes@736
   612
        val = ide_read_status();
nkeynes@736
   613
        return val;
nkeynes@158
   614
    default:
nkeynes@736
   615
        val = MMIO_READ( EXTDMA, reg );
nkeynes@736
   616
        return val;
nkeynes@1
   617
    }
nkeynes@1
   618
}
nkeynes@1
   619
.