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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 790:a0c7d28bbb0c
prev740:dd11269ee48b
next822:6e0536758465
author nkeynes
date Wed Jul 30 00:11:32 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Don't invoke sh4_translate_flush_cache() when we're not actually using the translator
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 parent module for all CPU modes and SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <math.h>
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#include <setjmp.h>
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#include <assert.h>
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#include "lxdream.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "clock.h"
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#include "eventq.h"
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#include "syscall.h"
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#include "sh4/intc.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4trans.h"
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#include "sh4/xltcache.h"
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void sh4_init( void );
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void sh4_xlat_init( void );
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void sh4_reset( void );
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void sh4_start( void );
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void sh4_stop( void );
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void sh4_save_state( FILE *f );
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int sh4_load_state( FILE *f );
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uint32_t sh4_run_slice( uint32_t );
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uint32_t sh4_xlat_run_slice( uint32_t );
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struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
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        sh4_start, sh4_run_slice, sh4_stop,
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        sh4_save_state, sh4_load_state };
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struct sh4_registers sh4r;
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struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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int sh4_breakpoint_count = 0;
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sh4ptr_t sh4_main_ram;
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gboolean sh4_starting = FALSE;
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static gboolean sh4_use_translator = FALSE;
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static jmp_buf sh4_exit_jmp_buf;
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static gboolean sh4_running = FALSE;
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struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
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void sh4_translate_set_enabled( gboolean use )
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{
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    // No-op if the translator was not built
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#ifdef SH4_TRANSLATOR
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    xlat_cache_init();
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    if( use ) {
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        sh4_translate_init();
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    }
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    sh4_use_translator = use;
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#endif
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}
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gboolean sh4_translate_is_enabled()
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{
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    return sh4_use_translator;
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}
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void sh4_init(void)
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{
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    register_io_regions( mmio_list_sh4mmio );
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    sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
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    MMU_init();
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    TMU_init();
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    sh4_reset();
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#ifdef ENABLE_SH4STATS
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    sh4_stats_reset();
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#endif
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}
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void sh4_start(void)
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{
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    sh4_starting = TRUE;
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}
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void sh4_reset(void)
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{
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    if(	sh4_use_translator ) {
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        xlat_flush_cache();
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    }
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    /* zero everything out, for the sake of having a consistent state. */
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    memset( &sh4r, 0, sizeof(sh4r) );
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    /* Resume running if we were halted */
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    sh4r.sh4_state = SH4_STATE_RUNNING;
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    sh4r.pc    = 0xA0000000;
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    sh4r.new_pc= 0xA0000002;
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    sh4r.vbr   = 0x00000000;
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    sh4r.fpscr = 0x00040001;
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    sh4r.sr    = 0x700000F0;
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    /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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    /* Peripheral modules */
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    CPG_reset();
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    INTC_reset();
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    MMU_reset();
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    TMU_reset();
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    SCIF_reset();
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#ifdef ENABLE_SH4STATS
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    sh4_stats_reset();
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#endif
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}
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void sh4_stop(void)
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{
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    if(	sh4_use_translator ) {
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        /* If we were running with the translator, update new_pc and in_delay_slot */
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        sh4r.new_pc = sh4r.pc+2;
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        sh4r.in_delay_slot = FALSE;
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    }
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}
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/**
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 * Execute a timeslice using translated code only (ie translate/execute loop)
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 */
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uint32_t sh4_run_slice( uint32_t nanosecs ) 
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{
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    sh4r.slice_cycle = 0;
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    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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        sh4_sleep_run_slice(nanosecs);
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    }
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    /* Setup for sudden vm exits */
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    switch( setjmp(sh4_exit_jmp_buf) ) {
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    case CORE_EXIT_BREAKPOINT:
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        sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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        /* fallthrough */
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    case CORE_EXIT_HALT:
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        if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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            TMU_run_slice( sh4r.slice_cycle );
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            SCIF_run_slice( sh4r.slice_cycle );
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            dreamcast_stop();
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            return sh4r.slice_cycle;
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        }
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    case CORE_EXIT_SYSRESET:
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        dreamcast_reset();
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        break;
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    case CORE_EXIT_SLEEP:
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        sh4_sleep_run_slice(nanosecs);
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        break;  
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    case CORE_EXIT_FLUSH_ICACHE:
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#ifdef SH4_TRANSLATOR
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        xlat_flush_cache();
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#endif
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        break;
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    }
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    sh4_running = TRUE;
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    /* Execute the core's real slice */
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#ifdef SH4_TRANSLATOR
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    if( sh4_use_translator ) {
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        sh4_translate_run_slice(nanosecs);
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    } else {
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        sh4_emulate_run_slice(nanosecs);
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    }
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#else
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    sh4_emulate_run_slice(nanosecs);
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#endif
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    /* And finish off the peripherals afterwards */
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    sh4_running = FALSE;
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    sh4_starting = FALSE;
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    sh4r.slice_cycle = nanosecs;
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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        TMU_run_slice( nanosecs );
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        SCIF_run_slice( nanosecs );
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    }
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    return nanosecs;   
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}
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void sh4_core_exit( int exit_code )
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{
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    if( sh4_running ) {
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#ifdef SH4_TRANSLATOR
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        if( sh4_use_translator ) {
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            sh4_translate_exit_recover();
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        }
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#endif
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        // longjmp back into sh4_run_slice
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        sh4_running = FALSE;
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        longjmp(sh4_exit_jmp_buf, exit_code);
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    }
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}
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void sh4_flush_icache()
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{
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#ifdef SH4_TRANSLATOR
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    // FIXME: Special case needs to be generalized
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    if( sh4_use_translator ) {
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        if( sh4_translate_flush_cache() ) {
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            longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
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        }
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    }
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#endif
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}
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void sh4_save_state( FILE *f )
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{
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    if(	sh4_use_translator ) {
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        /* If we were running with the translator, update new_pc and in_delay_slot */
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        sh4r.new_pc = sh4r.pc+2;
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        sh4r.in_delay_slot = FALSE;
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    }
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    fwrite( &sh4r, sizeof(sh4r), 1, f );
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    MMU_save_state( f );
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    INTC_save_state( f );
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    TMU_save_state( f );
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    SCIF_save_state( f );
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}
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int sh4_load_state( FILE * f )
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{
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    if(	sh4_use_translator ) {
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        xlat_flush_cache();
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    }
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    fread( &sh4r, sizeof(sh4r), 1, f );
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    MMU_load_state( f );
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    INTC_load_state( f );
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    TMU_load_state( f );
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    return SCIF_load_state( f );
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}
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void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
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{
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    sh4_breakpoints[sh4_breakpoint_count].address = pc;
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    sh4_breakpoints[sh4_breakpoint_count].type = type;
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    if( sh4_use_translator ) {
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        xlat_invalidate_word( pc );
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    }
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    sh4_breakpoint_count++;
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}
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gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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        if( sh4_breakpoints[i].address == pc && 
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                sh4_breakpoints[i].type == type ) {
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            while( ++i < sh4_breakpoint_count ) {
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                sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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                sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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            }
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            if( sh4_use_translator ) {
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                xlat_invalidate_word( pc );
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            }
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            sh4_breakpoint_count--;
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            return TRUE;
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        }
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    }
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    return FALSE;
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}
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int sh4_get_breakpoint( uint32_t pc )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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        if( sh4_breakpoints[i].address == pc )
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            return sh4_breakpoints[i].type;
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    }
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    return 0;
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}
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void sh4_set_pc( int pc )
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{
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    sh4r.pc = pc;
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    sh4r.new_pc = pc+2;
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}
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/******************************* Support methods ***************************/
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static void sh4_switch_banks( )
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{
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    uint32_t tmp[8];
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    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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}
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void sh4_switch_fr_banks()
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{
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    int i;
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    for( i=0; i<16; i++ ) {
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        float tmp = sh4r.fr[0][i];
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        sh4r.fr[0][i] = sh4r.fr[1][i];
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        sh4r.fr[1][i] = tmp;
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    }
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}
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void sh4_write_sr( uint32_t newval )
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{
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    int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
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    int newbank = (newval&SR_MDRB) == SR_MDRB;
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    if( oldbank != newbank )
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        sh4_switch_banks();
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    sh4r.sr = newval;
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    sh4r.t = (newval&SR_T) ? 1 : 0;
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    sh4r.s = (newval&SR_S) ? 1 : 0;
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    sh4r.m = (newval&SR_M) ? 1 : 0;
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    sh4r.q = (newval&SR_Q) ? 1 : 0;
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    intc_mask_changed();
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}
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void sh4_write_fpscr( uint32_t newval )
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{
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    if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
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        sh4_switch_fr_banks();
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    }
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    sh4r.fpscr = newval;
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}
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uint32_t sh4_read_sr( void )
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{
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    /* synchronize sh4r.sr with the various bitflags */
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    sh4r.sr &= SR_MQSTMASK;
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    if( sh4r.t ) sh4r.sr |= SR_T;
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    if( sh4r.s ) sh4r.sr |= SR_S;
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    if( sh4r.m ) sh4r.sr |= SR_M;
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    if( sh4r.q ) sh4r.sr |= SR_Q;
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    return sh4r.sr;
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}
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#define RAISE( x, v ) do{			\
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    if( sh4r.vbr == 0 ) { \
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        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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        sh4_core_exit(CORE_EXIT_HALT); return FALSE;	\
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    } else { \
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        sh4r.spc = sh4r.pc;	\
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        sh4r.ssr = sh4_read_sr(); \
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        sh4r.sgr = sh4r.r[15]; \
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        MMIO_WRITE(MMU,EXPEVT,x); \
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        sh4r.pc = sh4r.vbr + v; \
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        sh4r.new_pc = sh4r.pc + 2; \
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        sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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        if( sh4r.in_delay_slot ) { \
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   371
            sh4r.in_delay_slot = 0; \
nkeynes@736
   372
            sh4r.spc -= 2; \
nkeynes@736
   373
        } \
nkeynes@401
   374
    } \
nkeynes@401
   375
    return TRUE; } while(0)
nkeynes@401
   376
nkeynes@401
   377
/**
nkeynes@401
   378
 * Raise a general CPU exception for the specified exception code.
nkeynes@401
   379
 * (NOT for TRAPA or TLB exceptions)
nkeynes@401
   380
 */
nkeynes@401
   381
gboolean sh4_raise_exception( int code )
nkeynes@401
   382
{
nkeynes@401
   383
    RAISE( code, EXV_EXCEPTION );
nkeynes@401
   384
}
nkeynes@401
   385
nkeynes@586
   386
/**
nkeynes@586
   387
 * Raise a CPU reset exception with the specified exception code.
nkeynes@586
   388
 */
nkeynes@586
   389
gboolean sh4_raise_reset( int code )
nkeynes@586
   390
{
nkeynes@586
   391
    // FIXME: reset modules as per "manual reset"
nkeynes@586
   392
    sh4_reset();
nkeynes@586
   393
    MMIO_WRITE(MMU,EXPEVT,code);
nkeynes@586
   394
    sh4r.vbr = 0;
nkeynes@586
   395
    sh4r.pc = 0xA0000000;
nkeynes@586
   396
    sh4r.new_pc = sh4r.pc + 2;
nkeynes@586
   397
    sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
nkeynes@736
   398
                  &(~SR_FD) );
nkeynes@669
   399
    return TRUE;
nkeynes@586
   400
}
nkeynes@586
   401
nkeynes@401
   402
gboolean sh4_raise_trap( int trap )
nkeynes@401
   403
{
nkeynes@401
   404
    MMIO_WRITE( MMU, TRA, trap<<2 );
nkeynes@586
   405
    RAISE( EXC_TRAP, EXV_EXCEPTION );
nkeynes@401
   406
}
nkeynes@401
   407
nkeynes@401
   408
gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
nkeynes@401
   409
    if( sh4r.in_delay_slot ) {
nkeynes@736
   410
        return sh4_raise_exception(slot_code);
nkeynes@401
   411
    } else {
nkeynes@736
   412
        return sh4_raise_exception(normal_code);
nkeynes@401
   413
    }
nkeynes@401
   414
}
nkeynes@401
   415
nkeynes@401
   416
gboolean sh4_raise_tlb_exception( int code )
nkeynes@401
   417
{
nkeynes@401
   418
    RAISE( code, EXV_TLBMISS );
nkeynes@401
   419
}
nkeynes@401
   420
nkeynes@401
   421
void sh4_accept_interrupt( void )
nkeynes@401
   422
{
nkeynes@401
   423
    uint32_t code = intc_accept_interrupt();
nkeynes@401
   424
    sh4r.ssr = sh4_read_sr();
nkeynes@401
   425
    sh4r.spc = sh4r.pc;
nkeynes@401
   426
    sh4r.sgr = sh4r.r[15];
nkeynes@401
   427
    sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
nkeynes@401
   428
    MMIO_WRITE( MMU, INTEVT, code );
nkeynes@401
   429
    sh4r.pc = sh4r.vbr + 0x600;
nkeynes@401
   430
    sh4r.new_pc = sh4r.pc + 2;
nkeynes@401
   431
    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
nkeynes@401
   432
}
nkeynes@401
   433
nkeynes@401
   434
void signsat48( void )
nkeynes@401
   435
{
nkeynes@401
   436
    if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
nkeynes@736
   437
        sh4r.mac = 0xFFFF800000000000LL;
nkeynes@401
   438
    else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@736
   439
        sh4r.mac = 0x00007FFFFFFFFFFFLL;
nkeynes@401
   440
}
nkeynes@401
   441
nkeynes@401
   442
void sh4_fsca( uint32_t anglei, float *fr )
nkeynes@401
   443
{
nkeynes@401
   444
    float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
nkeynes@401
   445
    *fr++ = cosf(angle);
nkeynes@401
   446
    *fr = sinf(angle);
nkeynes@401
   447
}
nkeynes@401
   448
nkeynes@617
   449
/**
nkeynes@617
   450
 * Enter sleep mode (eg by executing a SLEEP instruction).
nkeynes@617
   451
 * Sets sh4_state appropriately and ensures any stopping peripheral modules
nkeynes@617
   452
 * are up to date.
nkeynes@617
   453
 */
nkeynes@401
   454
void sh4_sleep(void)
nkeynes@401
   455
{
nkeynes@401
   456
    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@736
   457
        sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@736
   458
        /* Bring all running peripheral modules up to date, and then halt them. */
nkeynes@736
   459
        TMU_run_slice( sh4r.slice_cycle );
nkeynes@736
   460
        SCIF_run_slice( sh4r.slice_cycle );
nkeynes@401
   461
    } else {
nkeynes@736
   462
        if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
nkeynes@736
   463
            sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
nkeynes@736
   464
            /* Halt DMAC but other peripherals still running */
nkeynes@736
   465
nkeynes@736
   466
        } else {
nkeynes@736
   467
            sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@736
   468
        }
nkeynes@617
   469
    }
nkeynes@740
   470
    sh4_core_exit( CORE_EXIT_SLEEP );
nkeynes@401
   471
}
nkeynes@401
   472
nkeynes@401
   473
/**
nkeynes@617
   474
 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
nkeynes@617
   475
 * and restarts any peripheral devices that were stopped.
nkeynes@617
   476
 */
nkeynes@617
   477
void sh4_wakeup(void)
nkeynes@617
   478
{
nkeynes@617
   479
    switch( sh4r.sh4_state ) {
nkeynes@617
   480
    case SH4_STATE_STANDBY:
nkeynes@736
   481
        break;
nkeynes@617
   482
    case SH4_STATE_DEEP_SLEEP:
nkeynes@736
   483
        break;
nkeynes@617
   484
    case SH4_STATE_SLEEP:
nkeynes@736
   485
        break;
nkeynes@617
   486
    }
nkeynes@617
   487
    sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@617
   488
}
nkeynes@617
   489
nkeynes@617
   490
/**
nkeynes@617
   491
 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
nkeynes@617
   492
 * Returns when either the SH4 wakes up (interrupt received) or the end of
nkeynes@617
   493
 * the slice is reached. Updates sh4.slice_cycle with the exit time and
nkeynes@617
   494
 * returns the same value.
nkeynes@617
   495
 */
nkeynes@617
   496
uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
nkeynes@617
   497
{
nkeynes@617
   498
    int sleep_state = sh4r.sh4_state;
nkeynes@617
   499
    assert( sleep_state != SH4_STATE_RUNNING );
nkeynes@736
   500
nkeynes@617
   501
    while( sh4r.event_pending < nanosecs ) {
nkeynes@736
   502
        sh4r.slice_cycle = sh4r.event_pending;
nkeynes@736
   503
        if( sh4r.event_types & PENDING_EVENT ) {
nkeynes@736
   504
            event_execute();
nkeynes@736
   505
        }
nkeynes@736
   506
        if( sh4r.event_types & PENDING_IRQ ) {
nkeynes@736
   507
            sh4_wakeup();
nkeynes@736
   508
            return sh4r.slice_cycle;
nkeynes@736
   509
        }
nkeynes@617
   510
    }
nkeynes@617
   511
    sh4r.slice_cycle = nanosecs;
nkeynes@617
   512
    return sh4r.slice_cycle;
nkeynes@617
   513
}
nkeynes@617
   514
nkeynes@617
   515
nkeynes@617
   516
/**
nkeynes@401
   517
 * Compute the matrix tranform of fv given the matrix xf.
nkeynes@401
   518
 * Both fv and xf are word-swapped as per the sh4r.fr banks
nkeynes@401
   519
 */
nkeynes@669
   520
void sh4_ftrv( float *target )
nkeynes@401
   521
{
nkeynes@401
   522
    float fv[4] = { target[1], target[0], target[3], target[2] };
nkeynes@669
   523
    target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
nkeynes@736
   524
    sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
nkeynes@669
   525
    target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
nkeynes@736
   526
    sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
nkeynes@669
   527
    target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
nkeynes@736
   528
    sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
nkeynes@669
   529
    target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
nkeynes@736
   530
    sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
nkeynes@401
   531
}
nkeynes@401
   532
nkeynes@597
   533
gboolean sh4_has_page( sh4vma_t vma )
nkeynes@597
   534
{
nkeynes@597
   535
    sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
nkeynes@597
   536
    return addr != MMU_VMA_ERROR && mem_has_page(addr);
nkeynes@597
   537
}
.