filename | src/sh4/sh4.c |
changeset | 577:a181aeacd6e8 |
prev | 571:9bc09948d0f2 |
next | 585:371342a39c09 |
author | nkeynes |
date | Mon Jan 14 10:23:49 2008 +0000 (16 years ago) |
branch | lxdream-mmu |
permissions | -rw-r--r-- |
last change | Remove asm file and convert to inline (easier to cope with platform conventions) Add breakpoint support Add MMU store-queue support |
file | annotate | diff | log | raw |
nkeynes@378 | 1 | /** |
nkeynes@561 | 2 | * $Id$ |
nkeynes@378 | 3 | * |
nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral |
nkeynes@378 | 5 | * modules. |
nkeynes@378 | 6 | * |
nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@378 | 8 | * |
nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@378 | 12 | * (at your option) any later version. |
nkeynes@378 | 13 | * |
nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@378 | 17 | * GNU General Public License for more details. |
nkeynes@378 | 18 | */ |
nkeynes@378 | 19 | |
nkeynes@378 | 20 | #define MODULE sh4_module |
nkeynes@378 | 21 | #include <math.h> |
nkeynes@378 | 22 | #include "dream.h" |
nkeynes@422 | 23 | #include "dreamcast.h" |
nkeynes@378 | 24 | #include "sh4/sh4core.h" |
nkeynes@378 | 25 | #include "sh4/sh4mmio.h" |
nkeynes@378 | 26 | #include "sh4/intc.h" |
nkeynes@422 | 27 | #include "sh4/xltcache.h" |
nkeynes@422 | 28 | #include "sh4/sh4stat.h" |
nkeynes@378 | 29 | #include "mem.h" |
nkeynes@378 | 30 | #include "clock.h" |
nkeynes@378 | 31 | #include "syscall.h" |
nkeynes@378 | 32 | |
nkeynes@378 | 33 | void sh4_init( void ); |
nkeynes@526 | 34 | void sh4_xlat_init( void ); |
nkeynes@378 | 35 | void sh4_reset( void ); |
nkeynes@378 | 36 | void sh4_start( void ); |
nkeynes@378 | 37 | void sh4_stop( void ); |
nkeynes@378 | 38 | void sh4_save_state( FILE *f ); |
nkeynes@378 | 39 | int sh4_load_state( FILE *f ); |
nkeynes@378 | 40 | |
nkeynes@378 | 41 | uint32_t sh4_run_slice( uint32_t ); |
nkeynes@378 | 42 | uint32_t sh4_xlat_run_slice( uint32_t ); |
nkeynes@378 | 43 | |
nkeynes@378 | 44 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, |
nkeynes@378 | 45 | NULL, sh4_run_slice, sh4_stop, |
nkeynes@378 | 46 | sh4_save_state, sh4_load_state }; |
nkeynes@378 | 47 | |
nkeynes@378 | 48 | struct sh4_registers sh4r; |
nkeynes@378 | 49 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@378 | 50 | int sh4_breakpoint_count = 0; |
nkeynes@569 | 51 | sh4ptr_t sh4_main_ram; |
nkeynes@526 | 52 | static gboolean sh4_use_translator = FALSE; |
nkeynes@569 | 53 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 }; |
nkeynes@566 | 54 | |
nkeynes@378 | 55 | void sh4_set_use_xlat( gboolean use ) |
nkeynes@378 | 56 | { |
nkeynes@526 | 57 | // No-op if the translator was not built |
nkeynes@526 | 58 | #ifdef SH4_TRANSLATOR |
nkeynes@378 | 59 | if( use ) { |
nkeynes@378 | 60 | xlat_cache_init(); |
nkeynes@378 | 61 | sh4_x86_init(); |
nkeynes@378 | 62 | sh4_module.run_time_slice = sh4_xlat_run_slice; |
nkeynes@378 | 63 | } else { |
nkeynes@378 | 64 | sh4_module.run_time_slice = sh4_run_slice; |
nkeynes@378 | 65 | } |
nkeynes@526 | 66 | sh4_use_translator = use; |
nkeynes@526 | 67 | #endif |
nkeynes@378 | 68 | } |
nkeynes@378 | 69 | |
nkeynes@571 | 70 | gboolean sh4_is_using_xlat() |
nkeynes@571 | 71 | { |
nkeynes@571 | 72 | return sh4_use_translator; |
nkeynes@571 | 73 | } |
nkeynes@571 | 74 | |
nkeynes@378 | 75 | void sh4_init(void) |
nkeynes@378 | 76 | { |
nkeynes@378 | 77 | register_io_regions( mmio_list_sh4mmio ); |
nkeynes@418 | 78 | sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN); |
nkeynes@378 | 79 | MMU_init(); |
nkeynes@378 | 80 | sh4_reset(); |
nkeynes@378 | 81 | } |
nkeynes@378 | 82 | |
nkeynes@378 | 83 | void sh4_reset(void) |
nkeynes@378 | 84 | { |
nkeynes@526 | 85 | if( sh4_use_translator ) { |
nkeynes@472 | 86 | xlat_flush_cache(); |
nkeynes@472 | 87 | } |
nkeynes@472 | 88 | |
nkeynes@378 | 89 | /* zero everything out, for the sake of having a consistent state. */ |
nkeynes@378 | 90 | memset( &sh4r, 0, sizeof(sh4r) ); |
nkeynes@378 | 91 | |
nkeynes@378 | 92 | /* Resume running if we were halted */ |
nkeynes@378 | 93 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@378 | 94 | |
nkeynes@378 | 95 | sh4r.pc = 0xA0000000; |
nkeynes@378 | 96 | sh4r.new_pc= 0xA0000002; |
nkeynes@378 | 97 | sh4r.vbr = 0x00000000; |
nkeynes@378 | 98 | sh4r.fpscr = 0x00040001; |
nkeynes@378 | 99 | sh4r.sr = 0x700000F0; |
nkeynes@378 | 100 | sh4r.fr_bank = &sh4r.fr[0][0]; |
nkeynes@378 | 101 | |
nkeynes@378 | 102 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */ |
nkeynes@378 | 103 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); |
nkeynes@378 | 104 | |
nkeynes@378 | 105 | /* Peripheral modules */ |
nkeynes@378 | 106 | CPG_reset(); |
nkeynes@378 | 107 | INTC_reset(); |
nkeynes@378 | 108 | MMU_reset(); |
nkeynes@378 | 109 | TMU_reset(); |
nkeynes@378 | 110 | SCIF_reset(); |
nkeynes@401 | 111 | sh4_stats_reset(); |
nkeynes@378 | 112 | } |
nkeynes@378 | 113 | |
nkeynes@378 | 114 | void sh4_stop(void) |
nkeynes@378 | 115 | { |
nkeynes@526 | 116 | if( sh4_use_translator ) { |
nkeynes@502 | 117 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@502 | 118 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@502 | 119 | sh4r.in_delay_slot = FALSE; |
nkeynes@502 | 120 | } |
nkeynes@378 | 121 | |
nkeynes@378 | 122 | } |
nkeynes@378 | 123 | |
nkeynes@378 | 124 | void sh4_save_state( FILE *f ) |
nkeynes@378 | 125 | { |
nkeynes@526 | 126 | if( sh4_use_translator ) { |
nkeynes@401 | 127 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@401 | 128 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@401 | 129 | sh4r.in_delay_slot = FALSE; |
nkeynes@401 | 130 | } |
nkeynes@401 | 131 | |
nkeynes@378 | 132 | fwrite( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@378 | 133 | MMU_save_state( f ); |
nkeynes@378 | 134 | INTC_save_state( f ); |
nkeynes@378 | 135 | TMU_save_state( f ); |
nkeynes@378 | 136 | SCIF_save_state( f ); |
nkeynes@378 | 137 | } |
nkeynes@378 | 138 | |
nkeynes@378 | 139 | int sh4_load_state( FILE * f ) |
nkeynes@378 | 140 | { |
nkeynes@526 | 141 | if( sh4_use_translator ) { |
nkeynes@472 | 142 | xlat_flush_cache(); |
nkeynes@472 | 143 | } |
nkeynes@378 | 144 | fread( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@412 | 145 | sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer |
nkeynes@378 | 146 | MMU_load_state( f ); |
nkeynes@378 | 147 | INTC_load_state( f ); |
nkeynes@378 | 148 | TMU_load_state( f ); |
nkeynes@378 | 149 | return SCIF_load_state( f ); |
nkeynes@378 | 150 | } |
nkeynes@378 | 151 | |
nkeynes@378 | 152 | |
nkeynes@566 | 153 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 154 | { |
nkeynes@378 | 155 | sh4_breakpoints[sh4_breakpoint_count].address = pc; |
nkeynes@378 | 156 | sh4_breakpoints[sh4_breakpoint_count].type = type; |
nkeynes@577 | 157 | if( sh4_use_translator ) { |
nkeynes@577 | 158 | xlat_invalidate_word( pc ); |
nkeynes@577 | 159 | } |
nkeynes@378 | 160 | sh4_breakpoint_count++; |
nkeynes@378 | 161 | } |
nkeynes@378 | 162 | |
nkeynes@566 | 163 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 164 | { |
nkeynes@378 | 165 | int i; |
nkeynes@378 | 166 | |
nkeynes@378 | 167 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@378 | 168 | if( sh4_breakpoints[i].address == pc && |
nkeynes@378 | 169 | sh4_breakpoints[i].type == type ) { |
nkeynes@378 | 170 | while( ++i < sh4_breakpoint_count ) { |
nkeynes@378 | 171 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address; |
nkeynes@378 | 172 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type; |
nkeynes@378 | 173 | } |
nkeynes@577 | 174 | if( sh4_use_translator ) { |
nkeynes@577 | 175 | xlat_invalidate_word( pc ); |
nkeynes@577 | 176 | } |
nkeynes@378 | 177 | sh4_breakpoint_count--; |
nkeynes@378 | 178 | return TRUE; |
nkeynes@378 | 179 | } |
nkeynes@378 | 180 | } |
nkeynes@378 | 181 | return FALSE; |
nkeynes@378 | 182 | } |
nkeynes@378 | 183 | |
nkeynes@378 | 184 | int sh4_get_breakpoint( uint32_t pc ) |
nkeynes@378 | 185 | { |
nkeynes@378 | 186 | int i; |
nkeynes@378 | 187 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@378 | 188 | if( sh4_breakpoints[i].address == pc ) |
nkeynes@378 | 189 | return sh4_breakpoints[i].type; |
nkeynes@378 | 190 | } |
nkeynes@378 | 191 | return 0; |
nkeynes@378 | 192 | } |
nkeynes@378 | 193 | |
nkeynes@401 | 194 | void sh4_set_pc( int pc ) |
nkeynes@401 | 195 | { |
nkeynes@401 | 196 | sh4r.pc = pc; |
nkeynes@401 | 197 | sh4r.new_pc = pc+2; |
nkeynes@401 | 198 | } |
nkeynes@401 | 199 | |
nkeynes@401 | 200 | |
nkeynes@401 | 201 | /******************************* Support methods ***************************/ |
nkeynes@401 | 202 | |
nkeynes@401 | 203 | static void sh4_switch_banks( ) |
nkeynes@401 | 204 | { |
nkeynes@401 | 205 | uint32_t tmp[8]; |
nkeynes@401 | 206 | |
nkeynes@401 | 207 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); |
nkeynes@401 | 208 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); |
nkeynes@401 | 209 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); |
nkeynes@401 | 210 | } |
nkeynes@401 | 211 | |
nkeynes@401 | 212 | void sh4_write_sr( uint32_t newval ) |
nkeynes@401 | 213 | { |
nkeynes@571 | 214 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB; |
nkeynes@571 | 215 | int newbank = (newval&SR_MDRB) == SR_MDRB; |
nkeynes@571 | 216 | if( oldbank != newbank ) |
nkeynes@401 | 217 | sh4_switch_banks(); |
nkeynes@401 | 218 | sh4r.sr = newval; |
nkeynes@401 | 219 | sh4r.t = (newval&SR_T) ? 1 : 0; |
nkeynes@401 | 220 | sh4r.s = (newval&SR_S) ? 1 : 0; |
nkeynes@401 | 221 | sh4r.m = (newval&SR_M) ? 1 : 0; |
nkeynes@401 | 222 | sh4r.q = (newval&SR_Q) ? 1 : 0; |
nkeynes@401 | 223 | intc_mask_changed(); |
nkeynes@401 | 224 | } |
nkeynes@401 | 225 | |
nkeynes@401 | 226 | uint32_t sh4_read_sr( void ) |
nkeynes@401 | 227 | { |
nkeynes@401 | 228 | /* synchronize sh4r.sr with the various bitflags */ |
nkeynes@401 | 229 | sh4r.sr &= SR_MQSTMASK; |
nkeynes@401 | 230 | if( sh4r.t ) sh4r.sr |= SR_T; |
nkeynes@401 | 231 | if( sh4r.s ) sh4r.sr |= SR_S; |
nkeynes@401 | 232 | if( sh4r.m ) sh4r.sr |= SR_M; |
nkeynes@401 | 233 | if( sh4r.q ) sh4r.sr |= SR_Q; |
nkeynes@401 | 234 | return sh4r.sr; |
nkeynes@401 | 235 | } |
nkeynes@401 | 236 | |
nkeynes@401 | 237 | |
nkeynes@401 | 238 | |
nkeynes@401 | 239 | #define RAISE( x, v ) do{ \ |
nkeynes@401 | 240 | if( sh4r.vbr == 0 ) { \ |
nkeynes@401 | 241 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \ |
nkeynes@401 | 242 | dreamcast_stop(); return FALSE; \ |
nkeynes@401 | 243 | } else { \ |
nkeynes@401 | 244 | sh4r.spc = sh4r.pc; \ |
nkeynes@401 | 245 | sh4r.ssr = sh4_read_sr(); \ |
nkeynes@401 | 246 | sh4r.sgr = sh4r.r[15]; \ |
nkeynes@401 | 247 | MMIO_WRITE(MMU,EXPEVT,x); \ |
nkeynes@401 | 248 | sh4r.pc = sh4r.vbr + v; \ |
nkeynes@401 | 249 | sh4r.new_pc = sh4r.pc + 2; \ |
nkeynes@401 | 250 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \ |
nkeynes@401 | 251 | if( sh4r.in_delay_slot ) { \ |
nkeynes@401 | 252 | sh4r.in_delay_slot = 0; \ |
nkeynes@401 | 253 | sh4r.spc -= 2; \ |
nkeynes@401 | 254 | } \ |
nkeynes@401 | 255 | } \ |
nkeynes@401 | 256 | return TRUE; } while(0) |
nkeynes@401 | 257 | |
nkeynes@401 | 258 | /** |
nkeynes@401 | 259 | * Raise a general CPU exception for the specified exception code. |
nkeynes@401 | 260 | * (NOT for TRAPA or TLB exceptions) |
nkeynes@401 | 261 | */ |
nkeynes@401 | 262 | gboolean sh4_raise_exception( int code ) |
nkeynes@401 | 263 | { |
nkeynes@401 | 264 | RAISE( code, EXV_EXCEPTION ); |
nkeynes@401 | 265 | } |
nkeynes@401 | 266 | |
nkeynes@559 | 267 | /** |
nkeynes@559 | 268 | * Raise a CPU reset exception with the specified exception code. |
nkeynes@559 | 269 | */ |
nkeynes@559 | 270 | gboolean sh4_raise_reset( int code ) |
nkeynes@559 | 271 | { |
nkeynes@559 | 272 | // FIXME: reset modules as per "manual reset" |
nkeynes@559 | 273 | sh4_reset(); |
nkeynes@559 | 274 | MMIO_WRITE(MMU,EXPEVT,code); |
nkeynes@559 | 275 | sh4r.vbr = 0; |
nkeynes@559 | 276 | sh4r.pc = 0xA0000000; |
nkeynes@559 | 277 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@559 | 278 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK) |
nkeynes@559 | 279 | &(~SR_FD) ); |
nkeynes@559 | 280 | } |
nkeynes@559 | 281 | |
nkeynes@401 | 282 | gboolean sh4_raise_trap( int trap ) |
nkeynes@401 | 283 | { |
nkeynes@401 | 284 | MMIO_WRITE( MMU, TRA, trap<<2 ); |
nkeynes@401 | 285 | return sh4_raise_exception( EXC_TRAP ); |
nkeynes@401 | 286 | } |
nkeynes@401 | 287 | |
nkeynes@401 | 288 | gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) { |
nkeynes@401 | 289 | if( sh4r.in_delay_slot ) { |
nkeynes@401 | 290 | return sh4_raise_exception(slot_code); |
nkeynes@401 | 291 | } else { |
nkeynes@401 | 292 | return sh4_raise_exception(normal_code); |
nkeynes@401 | 293 | } |
nkeynes@401 | 294 | } |
nkeynes@401 | 295 | |
nkeynes@401 | 296 | gboolean sh4_raise_tlb_exception( int code ) |
nkeynes@401 | 297 | { |
nkeynes@401 | 298 | RAISE( code, EXV_TLBMISS ); |
nkeynes@401 | 299 | } |
nkeynes@401 | 300 | |
nkeynes@401 | 301 | void sh4_accept_interrupt( void ) |
nkeynes@401 | 302 | { |
nkeynes@401 | 303 | uint32_t code = intc_accept_interrupt(); |
nkeynes@401 | 304 | sh4r.ssr = sh4_read_sr(); |
nkeynes@401 | 305 | sh4r.spc = sh4r.pc; |
nkeynes@401 | 306 | sh4r.sgr = sh4r.r[15]; |
nkeynes@401 | 307 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); |
nkeynes@401 | 308 | MMIO_WRITE( MMU, INTEVT, code ); |
nkeynes@401 | 309 | sh4r.pc = sh4r.vbr + 0x600; |
nkeynes@401 | 310 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@401 | 311 | // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc ); |
nkeynes@401 | 312 | } |
nkeynes@401 | 313 | |
nkeynes@401 | 314 | void signsat48( void ) |
nkeynes@401 | 315 | { |
nkeynes@401 | 316 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL ) |
nkeynes@401 | 317 | sh4r.mac = 0xFFFF800000000000LL; |
nkeynes@401 | 318 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL ) |
nkeynes@401 | 319 | sh4r.mac = 0x00007FFFFFFFFFFFLL; |
nkeynes@401 | 320 | } |
nkeynes@401 | 321 | |
nkeynes@401 | 322 | void sh4_fsca( uint32_t anglei, float *fr ) |
nkeynes@401 | 323 | { |
nkeynes@401 | 324 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI; |
nkeynes@401 | 325 | *fr++ = cosf(angle); |
nkeynes@401 | 326 | *fr = sinf(angle); |
nkeynes@401 | 327 | } |
nkeynes@401 | 328 | |
nkeynes@401 | 329 | void sh4_sleep(void) |
nkeynes@401 | 330 | { |
nkeynes@401 | 331 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) { |
nkeynes@401 | 332 | sh4r.sh4_state = SH4_STATE_STANDBY; |
nkeynes@401 | 333 | } else { |
nkeynes@401 | 334 | sh4r.sh4_state = SH4_STATE_SLEEP; |
nkeynes@401 | 335 | } |
nkeynes@401 | 336 | } |
nkeynes@401 | 337 | |
nkeynes@401 | 338 | /** |
nkeynes@401 | 339 | * Compute the matrix tranform of fv given the matrix xf. |
nkeynes@401 | 340 | * Both fv and xf are word-swapped as per the sh4r.fr banks |
nkeynes@401 | 341 | */ |
nkeynes@401 | 342 | void sh4_ftrv( float *target, float *xf ) |
nkeynes@401 | 343 | { |
nkeynes@401 | 344 | float fv[4] = { target[1], target[0], target[3], target[2] }; |
nkeynes@401 | 345 | target[1] = xf[1] * fv[0] + xf[5]*fv[1] + |
nkeynes@401 | 346 | xf[9]*fv[2] + xf[13]*fv[3]; |
nkeynes@401 | 347 | target[0] = xf[0] * fv[0] + xf[4]*fv[1] + |
nkeynes@401 | 348 | xf[8]*fv[2] + xf[12]*fv[3]; |
nkeynes@401 | 349 | target[3] = xf[3] * fv[0] + xf[7]*fv[1] + |
nkeynes@401 | 350 | xf[11]*fv[2] + xf[15]*fv[3]; |
nkeynes@401 | 351 | target[2] = xf[2] * fv[0] + xf[6]*fv[1] + |
nkeynes@401 | 352 | xf[10]*fv[2] + xf[14]*fv[3]; |
nkeynes@401 | 353 | } |
nkeynes@401 | 354 |
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