filename | src/sh4/sh4x86.in |
changeset | 577:a181aeacd6e8 |
prev | 571:9bc09948d0f2 |
next | 584:5c29dd7297df |
author | nkeynes |
date | Mon Jan 14 10:23:49 2008 +0000 (16 years ago) |
branch | lxdream-mmu |
permissions | -rw-r--r-- |
last change | Remove asm file and convert to inline (easier to cope with platform conventions) Add breakpoint support Add MMU store-queue support |
file | annotate | diff | log | raw |
nkeynes@359 | 1 | /** |
nkeynes@561 | 2 | * $Id$ |
nkeynes@359 | 3 | * |
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just |
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline |
nkeynes@359 | 6 | * to test the optimizing versions against. |
nkeynes@359 | 7 | * |
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes. |
nkeynes@359 | 9 | * |
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify |
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by |
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@359 | 13 | * (at your option) any later version. |
nkeynes@359 | 14 | * |
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful, |
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@359 | 18 | * GNU General Public License for more details. |
nkeynes@359 | 19 | */ |
nkeynes@359 | 20 | |
nkeynes@368 | 21 | #include <assert.h> |
nkeynes@388 | 22 | #include <math.h> |
nkeynes@368 | 23 | |
nkeynes@380 | 24 | #ifndef NDEBUG |
nkeynes@380 | 25 | #define DEBUG_JUMPS 1 |
nkeynes@380 | 26 | #endif |
nkeynes@380 | 27 | |
nkeynes@417 | 28 | #include "sh4/xltcache.h" |
nkeynes@368 | 29 | #include "sh4/sh4core.h" |
nkeynes@368 | 30 | #include "sh4/sh4trans.h" |
nkeynes@388 | 31 | #include "sh4/sh4mmio.h" |
nkeynes@368 | 32 | #include "sh4/x86op.h" |
nkeynes@368 | 33 | #include "clock.h" |
nkeynes@368 | 34 | |
nkeynes@368 | 35 | #define DEFAULT_BACKPATCH_SIZE 4096 |
nkeynes@368 | 36 | |
nkeynes@559 | 37 | struct backpatch_record { |
nkeynes@559 | 38 | uint32_t *fixup_addr; |
nkeynes@559 | 39 | uint32_t fixup_icount; |
nkeynes@559 | 40 | uint32_t exc_code; |
nkeynes@559 | 41 | }; |
nkeynes@559 | 42 | |
nkeynes@571 | 43 | #define MAX_RECOVERY_SIZE 2048 |
nkeynes@571 | 44 | |
nkeynes@368 | 45 | /** |
nkeynes@368 | 46 | * Struct to manage internal translation state. This state is not saved - |
nkeynes@368 | 47 | * it is only valid between calls to sh4_translate_begin_block() and |
nkeynes@368 | 48 | * sh4_translate_end_block() |
nkeynes@368 | 49 | */ |
nkeynes@368 | 50 | struct sh4_x86_state { |
nkeynes@368 | 51 | gboolean in_delay_slot; |
nkeynes@368 | 52 | gboolean priv_checked; /* true if we've already checked the cpu mode. */ |
nkeynes@368 | 53 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */ |
nkeynes@409 | 54 | gboolean branch_taken; /* true if we branched unconditionally */ |
nkeynes@408 | 55 | uint32_t block_start_pc; |
nkeynes@547 | 56 | uint32_t stack_posn; /* Trace stack height for alignment purposes */ |
nkeynes@417 | 57 | int tstate; |
nkeynes@368 | 58 | |
nkeynes@570 | 59 | /* mode flags */ |
nkeynes@570 | 60 | gboolean tlb_on; /* True if tlb translation is active */ |
nkeynes@570 | 61 | |
nkeynes@368 | 62 | /* Allocated memory for the (block-wide) back-patch list */ |
nkeynes@559 | 63 | struct backpatch_record *backpatch_list; |
nkeynes@368 | 64 | uint32_t backpatch_posn; |
nkeynes@368 | 65 | uint32_t backpatch_size; |
nkeynes@571 | 66 | struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE]; |
nkeynes@571 | 67 | uint32_t recovery_posn; |
nkeynes@368 | 68 | }; |
nkeynes@368 | 69 | |
nkeynes@417 | 70 | #define TSTATE_NONE -1 |
nkeynes@417 | 71 | #define TSTATE_O 0 |
nkeynes@417 | 72 | #define TSTATE_C 2 |
nkeynes@417 | 73 | #define TSTATE_E 4 |
nkeynes@417 | 74 | #define TSTATE_NE 5 |
nkeynes@417 | 75 | #define TSTATE_G 0xF |
nkeynes@417 | 76 | #define TSTATE_GE 0xD |
nkeynes@417 | 77 | #define TSTATE_A 7 |
nkeynes@417 | 78 | #define TSTATE_AE 3 |
nkeynes@417 | 79 | |
nkeynes@417 | 80 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */ |
nkeynes@417 | 81 | #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@417 | 82 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@417 | 83 | OP(0x70+sh4_x86.tstate); OP(rel8); \ |
nkeynes@417 | 84 | MARK_JMP(rel8,label) |
nkeynes@417 | 85 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */ |
nkeynes@417 | 86 | #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@417 | 87 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@417 | 88 | OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \ |
nkeynes@417 | 89 | MARK_JMP(rel8, label) |
nkeynes@417 | 90 | |
nkeynes@368 | 91 | static struct sh4_x86_state sh4_x86; |
nkeynes@368 | 92 | |
nkeynes@388 | 93 | static uint32_t max_int = 0x7FFFFFFF; |
nkeynes@388 | 94 | static uint32_t min_int = 0x80000000; |
nkeynes@394 | 95 | static uint32_t save_fcw; /* save value for fpu control word */ |
nkeynes@394 | 96 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */ |
nkeynes@386 | 97 | |
nkeynes@368 | 98 | void sh4_x86_init() |
nkeynes@368 | 99 | { |
nkeynes@368 | 100 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE); |
nkeynes@559 | 101 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record); |
nkeynes@368 | 102 | } |
nkeynes@368 | 103 | |
nkeynes@368 | 104 | |
nkeynes@559 | 105 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code ) |
nkeynes@368 | 106 | { |
nkeynes@368 | 107 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) { |
nkeynes@368 | 108 | sh4_x86.backpatch_size <<= 1; |
nkeynes@559 | 109 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, |
nkeynes@559 | 110 | sh4_x86.backpatch_size * sizeof(struct backpatch_record)); |
nkeynes@368 | 111 | assert( sh4_x86.backpatch_list != NULL ); |
nkeynes@368 | 112 | } |
nkeynes@559 | 113 | if( sh4_x86.in_delay_slot ) { |
nkeynes@559 | 114 | fixup_pc -= 2; |
nkeynes@368 | 115 | } |
nkeynes@559 | 116 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr; |
nkeynes@559 | 117 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1; |
nkeynes@559 | 118 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code; |
nkeynes@559 | 119 | sh4_x86.backpatch_posn++; |
nkeynes@368 | 120 | } |
nkeynes@368 | 121 | |
nkeynes@571 | 122 | void sh4_x86_add_recovery( uint32_t pc ) |
nkeynes@571 | 123 | { |
nkeynes@571 | 124 | xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output; |
nkeynes@571 | 125 | xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1; |
nkeynes@571 | 126 | xlat_recovery_posn++; |
nkeynes@571 | 127 | } |
nkeynes@577 | 128 | |
nkeynes@359 | 129 | /** |
nkeynes@359 | 130 | * Emit an instruction to load an SH4 reg into a real register |
nkeynes@359 | 131 | */ |
nkeynes@359 | 132 | static inline void load_reg( int x86reg, int sh4reg ) |
nkeynes@359 | 133 | { |
nkeynes@359 | 134 | /* mov [bp+n], reg */ |
nkeynes@361 | 135 | OP(0x8B); |
nkeynes@361 | 136 | OP(0x45 + (x86reg<<3)); |
nkeynes@359 | 137 | OP(REG_OFFSET(r[sh4reg])); |
nkeynes@359 | 138 | } |
nkeynes@359 | 139 | |
nkeynes@374 | 140 | static inline void load_reg16s( int x86reg, int sh4reg ) |
nkeynes@368 | 141 | { |
nkeynes@374 | 142 | OP(0x0F); |
nkeynes@374 | 143 | OP(0xBF); |
nkeynes@374 | 144 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); |
nkeynes@368 | 145 | } |
nkeynes@368 | 146 | |
nkeynes@374 | 147 | static inline void load_reg16u( int x86reg, int sh4reg ) |
nkeynes@368 | 148 | { |
nkeynes@374 | 149 | OP(0x0F); |
nkeynes@374 | 150 | OP(0xB7); |
nkeynes@374 | 151 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); |
nkeynes@374 | 152 | |
nkeynes@368 | 153 | } |
nkeynes@368 | 154 | |
nkeynes@380 | 155 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg ) |
nkeynes@380 | 156 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff ) |
nkeynes@359 | 157 | /** |
nkeynes@359 | 158 | * Emit an instruction to load an immediate value into a register |
nkeynes@359 | 159 | */ |
nkeynes@359 | 160 | static inline void load_imm32( int x86reg, uint32_t value ) { |
nkeynes@359 | 161 | /* mov #value, reg */ |
nkeynes@359 | 162 | OP(0xB8 + x86reg); |
nkeynes@359 | 163 | OP32(value); |
nkeynes@359 | 164 | } |
nkeynes@359 | 165 | |
nkeynes@359 | 166 | /** |
nkeynes@527 | 167 | * Load an immediate 64-bit quantity (note: x86-64 only) |
nkeynes@527 | 168 | */ |
nkeynes@527 | 169 | static inline void load_imm64( int x86reg, uint32_t value ) { |
nkeynes@527 | 170 | /* mov #value, reg */ |
nkeynes@527 | 171 | REXW(); |
nkeynes@527 | 172 | OP(0xB8 + x86reg); |
nkeynes@527 | 173 | OP64(value); |
nkeynes@527 | 174 | } |
nkeynes@527 | 175 | |
nkeynes@527 | 176 | |
nkeynes@527 | 177 | /** |
nkeynes@359 | 178 | * Emit an instruction to store an SH4 reg (RN) |
nkeynes@359 | 179 | */ |
nkeynes@359 | 180 | void static inline store_reg( int x86reg, int sh4reg ) { |
nkeynes@359 | 181 | /* mov reg, [bp+n] */ |
nkeynes@361 | 182 | OP(0x89); |
nkeynes@361 | 183 | OP(0x45 + (x86reg<<3)); |
nkeynes@359 | 184 | OP(REG_OFFSET(r[sh4reg])); |
nkeynes@359 | 185 | } |
nkeynes@374 | 186 | |
nkeynes@374 | 187 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank)) |
nkeynes@374 | 188 | |
nkeynes@375 | 189 | /** |
nkeynes@375 | 190 | * Load an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 191 | * register (eg for register-to-register moves) |
nkeynes@375 | 192 | */ |
nkeynes@375 | 193 | void static inline load_fr( int bankreg, int x86reg, int frm ) |
nkeynes@375 | 194 | { |
nkeynes@375 | 195 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2); |
nkeynes@375 | 196 | } |
nkeynes@375 | 197 | |
nkeynes@375 | 198 | /** |
nkeynes@375 | 199 | * Store an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 200 | * register (eg for register-to-register moves) |
nkeynes@375 | 201 | */ |
nkeynes@375 | 202 | void static inline store_fr( int bankreg, int x86reg, int frn ) |
nkeynes@375 | 203 | { |
nkeynes@375 | 204 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2); |
nkeynes@375 | 205 | } |
nkeynes@375 | 206 | |
nkeynes@375 | 207 | |
nkeynes@375 | 208 | /** |
nkeynes@375 | 209 | * Load a pointer to the back fp back into the specified x86 register. The |
nkeynes@375 | 210 | * bankreg must have been previously loaded with FPSCR. |
nkeynes@388 | 211 | * NB: 12 bytes |
nkeynes@375 | 212 | */ |
nkeynes@374 | 213 | static inline void load_xf_bank( int bankreg ) |
nkeynes@374 | 214 | { |
nkeynes@386 | 215 | NOT_r32( bankreg ); |
nkeynes@374 | 216 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size |
nkeynes@374 | 217 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction |
nkeynes@374 | 218 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg |
nkeynes@374 | 219 | } |
nkeynes@374 | 220 | |
nkeynes@375 | 221 | /** |
nkeynes@386 | 222 | * Update the fr_bank pointer based on the current fpscr value. |
nkeynes@386 | 223 | */ |
nkeynes@386 | 224 | static inline void update_fr_bank( int fpscrreg ) |
nkeynes@386 | 225 | { |
nkeynes@386 | 226 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size |
nkeynes@386 | 227 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction |
nkeynes@386 | 228 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg |
nkeynes@386 | 229 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) ); |
nkeynes@386 | 230 | } |
nkeynes@386 | 231 | /** |
nkeynes@377 | 232 | * Push FPUL (as a 32-bit float) onto the FPU stack |
nkeynes@377 | 233 | */ |
nkeynes@377 | 234 | static inline void push_fpul( ) |
nkeynes@377 | 235 | { |
nkeynes@377 | 236 | OP(0xD9); OP(0x45); OP(R_FPUL); |
nkeynes@377 | 237 | } |
nkeynes@377 | 238 | |
nkeynes@377 | 239 | /** |
nkeynes@377 | 240 | * Pop FPUL (as a 32-bit float) from the FPU stack |
nkeynes@377 | 241 | */ |
nkeynes@377 | 242 | static inline void pop_fpul( ) |
nkeynes@377 | 243 | { |
nkeynes@377 | 244 | OP(0xD9); OP(0x5D); OP(R_FPUL); |
nkeynes@377 | 245 | } |
nkeynes@377 | 246 | |
nkeynes@377 | 247 | /** |
nkeynes@375 | 248 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded |
nkeynes@375 | 249 | * with the location of the current fp bank. |
nkeynes@375 | 250 | */ |
nkeynes@374 | 251 | static inline void push_fr( int bankreg, int frm ) |
nkeynes@374 | 252 | { |
nkeynes@374 | 253 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4] |
nkeynes@374 | 254 | } |
nkeynes@374 | 255 | |
nkeynes@375 | 256 | /** |
nkeynes@375 | 257 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank, |
nkeynes@375 | 258 | * with bankreg previously loaded with the location of the current fp bank. |
nkeynes@375 | 259 | */ |
nkeynes@374 | 260 | static inline void pop_fr( int bankreg, int frm ) |
nkeynes@374 | 261 | { |
nkeynes@374 | 262 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4] |
nkeynes@374 | 263 | } |
nkeynes@374 | 264 | |
nkeynes@375 | 265 | /** |
nkeynes@375 | 266 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded |
nkeynes@375 | 267 | * with the location of the current fp bank. |
nkeynes@375 | 268 | */ |
nkeynes@374 | 269 | static inline void push_dr( int bankreg, int frm ) |
nkeynes@374 | 270 | { |
nkeynes@375 | 271 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4] |
nkeynes@374 | 272 | } |
nkeynes@374 | 273 | |
nkeynes@374 | 274 | static inline void pop_dr( int bankreg, int frm ) |
nkeynes@374 | 275 | { |
nkeynes@375 | 276 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4] |
nkeynes@374 | 277 | } |
nkeynes@374 | 278 | |
nkeynes@368 | 279 | /* Exception checks - Note that all exception checks will clobber EAX */ |
nkeynes@416 | 280 | |
nkeynes@416 | 281 | #define check_priv( ) \ |
nkeynes@416 | 282 | if( !sh4_x86.priv_checked ) { \ |
nkeynes@416 | 283 | sh4_x86.priv_checked = TRUE;\ |
nkeynes@416 | 284 | load_spreg( R_EAX, R_SR );\ |
nkeynes@416 | 285 | AND_imm32_r32( SR_MD, R_EAX );\ |
nkeynes@416 | 286 | if( sh4_x86.in_delay_slot ) {\ |
nkeynes@559 | 287 | JE_exc( EXC_SLOT_ILLEGAL );\ |
nkeynes@416 | 288 | } else {\ |
nkeynes@559 | 289 | JE_exc( EXC_ILLEGAL );\ |
nkeynes@416 | 290 | }\ |
nkeynes@416 | 291 | }\ |
nkeynes@416 | 292 | |
nkeynes@416 | 293 | #define check_fpuen( ) \ |
nkeynes@416 | 294 | if( !sh4_x86.fpuen_checked ) {\ |
nkeynes@416 | 295 | sh4_x86.fpuen_checked = TRUE;\ |
nkeynes@416 | 296 | load_spreg( R_EAX, R_SR );\ |
nkeynes@416 | 297 | AND_imm32_r32( SR_FD, R_EAX );\ |
nkeynes@416 | 298 | if( sh4_x86.in_delay_slot ) {\ |
nkeynes@559 | 299 | JNE_exc(EXC_SLOT_FPU_DISABLED);\ |
nkeynes@416 | 300 | } else {\ |
nkeynes@559 | 301 | JNE_exc(EXC_FPU_DISABLED);\ |
nkeynes@416 | 302 | }\ |
nkeynes@416 | 303 | } |
nkeynes@416 | 304 | |
nkeynes@559 | 305 | #define check_ralign16( x86reg ) \ |
nkeynes@559 | 306 | TEST_imm32_r32( 0x00000001, x86reg ); \ |
nkeynes@559 | 307 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@416 | 308 | |
nkeynes@559 | 309 | #define check_walign16( x86reg ) \ |
nkeynes@559 | 310 | TEST_imm32_r32( 0x00000001, x86reg ); \ |
nkeynes@559 | 311 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 312 | |
nkeynes@559 | 313 | #define check_ralign32( x86reg ) \ |
nkeynes@559 | 314 | TEST_imm32_r32( 0x00000003, x86reg ); \ |
nkeynes@559 | 315 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@368 | 316 | |
nkeynes@559 | 317 | #define check_walign32( x86reg ) \ |
nkeynes@559 | 318 | TEST_imm32_r32( 0x00000003, x86reg ); \ |
nkeynes@559 | 319 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 320 | |
nkeynes@361 | 321 | #define UNDEF() |
nkeynes@361 | 322 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); } |
nkeynes@571 | 323 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@571 | 324 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@571 | 325 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@571 | 326 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg) |
nkeynes@571 | 327 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg) |
nkeynes@571 | 328 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg) |
nkeynes@361 | 329 | |
nkeynes@571 | 330 | /** |
nkeynes@571 | 331 | * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned |
nkeynes@571 | 332 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error. |
nkeynes@571 | 333 | */ |
nkeynes@571 | 334 | #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); } |
nkeynes@571 | 335 | /** |
nkeynes@571 | 336 | * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned |
nkeynes@571 | 337 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error. |
nkeynes@571 | 338 | */ |
nkeynes@571 | 339 | #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); } |
nkeynes@570 | 340 | |
nkeynes@571 | 341 | #define MEM_READ_SIZE (CALL_FUNC1_SIZE) |
nkeynes@571 | 342 | #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE) |
nkeynes@571 | 343 | #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 ) |
nkeynes@559 | 344 | |
nkeynes@559 | 345 | #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1; |
nkeynes@368 | 346 | |
nkeynes@539 | 347 | /****** Import appropriate calling conventions ******/ |
nkeynes@539 | 348 | #if SH4_TRANSLATOR == TARGET_X86_64 |
nkeynes@539 | 349 | #include "sh4/ia64abi.h" |
nkeynes@539 | 350 | #else /* SH4_TRANSLATOR == TARGET_X86 */ |
nkeynes@539 | 351 | #ifdef APPLE_BUILD |
nkeynes@539 | 352 | #include "sh4/ia32mac.h" |
nkeynes@539 | 353 | #else |
nkeynes@539 | 354 | #include "sh4/ia32abi.h" |
nkeynes@539 | 355 | #endif |
nkeynes@539 | 356 | #endif |
nkeynes@539 | 357 | |
nkeynes@577 | 358 | void sh4_translate_emit_breakpoint( sh4vma_t pc ) |
nkeynes@577 | 359 | { |
nkeynes@577 | 360 | load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT ); |
nkeynes@577 | 361 | call_func1( sh4_translate_exit, R_EAX ); |
nkeynes@577 | 362 | } |
nkeynes@577 | 363 | |
nkeynes@539 | 364 | |
nkeynes@359 | 365 | /** |
nkeynes@359 | 366 | * Translate a single instruction. Delayed branches are handled specially |
nkeynes@359 | 367 | * by translating both branch and delayed instruction as a single unit (as |
nkeynes@359 | 368 | * |
nkeynes@577 | 369 | * The instruction MUST be in the icache (assert check) |
nkeynes@359 | 370 | * |
nkeynes@359 | 371 | * @return true if the instruction marks the end of a basic block |
nkeynes@359 | 372 | * (eg a branch or |
nkeynes@359 | 373 | */ |
nkeynes@526 | 374 | uint32_t sh4_translate_instruction( sh4addr_t pc ) |
nkeynes@359 | 375 | { |
nkeynes@388 | 376 | uint32_t ir; |
nkeynes@577 | 377 | /* Read instruction from icache */ |
nkeynes@577 | 378 | assert( IS_IN_ICACHE(pc) ); |
nkeynes@577 | 379 | ir = *(uint16_t *)GET_ICACHE_PTR(pc); |
nkeynes@577 | 380 | |
nkeynes@577 | 381 | /* PC is not in the current icache - this usually means we're running |
nkeynes@577 | 382 | * with MMU on, and we've gone past the end of the page. And since |
nkeynes@577 | 383 | * sh4_translate_block is pretty careful about this, it means we're |
nkeynes@577 | 384 | * almost certainly in a delay slot. |
nkeynes@577 | 385 | * |
nkeynes@577 | 386 | * Since we can't assume the page is present (and we can't fault it in |
nkeynes@577 | 387 | * at this point, inline a call to sh4_execute_instruction (with a few |
nkeynes@577 | 388 | * small repairs to cope with the different environment). |
nkeynes@577 | 389 | */ |
nkeynes@569 | 390 | ir = sh4_read_word(pc); |
nkeynes@577 | 391 | |
nkeynes@571 | 392 | if( !sh4_x86.in_delay_slot ) { |
nkeynes@571 | 393 | sh4_x86_add_recovery(pc); |
nkeynes@571 | 394 | } |
nkeynes@359 | 395 | %% |
nkeynes@359 | 396 | /* ALU operations */ |
nkeynes@359 | 397 | ADD Rm, Rn {: |
nkeynes@359 | 398 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 399 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 400 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 401 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 402 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 403 | :} |
nkeynes@359 | 404 | ADD #imm, Rn {: |
nkeynes@359 | 405 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 406 | ADD_imm8s_r32( imm, R_EAX ); |
nkeynes@359 | 407 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 408 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 409 | :} |
nkeynes@359 | 410 | ADDC Rm, Rn {: |
nkeynes@417 | 411 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 412 | LDC_t(); |
nkeynes@417 | 413 | } |
nkeynes@359 | 414 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 415 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 416 | ADC_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 417 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 418 | SETC_t(); |
nkeynes@417 | 419 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 420 | :} |
nkeynes@359 | 421 | ADDV Rm, Rn {: |
nkeynes@359 | 422 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 423 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 424 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 425 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 426 | SETO_t(); |
nkeynes@417 | 427 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 428 | :} |
nkeynes@359 | 429 | AND Rm, Rn {: |
nkeynes@359 | 430 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 431 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 432 | AND_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 433 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 434 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 435 | :} |
nkeynes@359 | 436 | AND #imm, R0 {: |
nkeynes@359 | 437 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 438 | AND_imm32_r32(imm, R_EAX); |
nkeynes@359 | 439 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 440 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 441 | :} |
nkeynes@359 | 442 | AND.B #imm, @(R0, GBR) {: |
nkeynes@359 | 443 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 444 | load_spreg( R_ECX, R_GBR ); |
nkeynes@571 | 445 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 446 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 447 | PUSH_realigned_r32(R_EAX); |
nkeynes@571 | 448 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@547 | 449 | POP_realigned_r32(R_ECX); |
nkeynes@386 | 450 | AND_imm32_r32(imm, R_EAX ); |
nkeynes@359 | 451 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@417 | 452 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 453 | :} |
nkeynes@359 | 454 | CMP/EQ Rm, Rn {: |
nkeynes@359 | 455 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 456 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 457 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 458 | SETE_t(); |
nkeynes@417 | 459 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 460 | :} |
nkeynes@359 | 461 | CMP/EQ #imm, R0 {: |
nkeynes@359 | 462 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 463 | CMP_imm8s_r32(imm, R_EAX); |
nkeynes@359 | 464 | SETE_t(); |
nkeynes@417 | 465 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 466 | :} |
nkeynes@359 | 467 | CMP/GE Rm, Rn {: |
nkeynes@359 | 468 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 469 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 470 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 471 | SETGE_t(); |
nkeynes@417 | 472 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 473 | :} |
nkeynes@359 | 474 | CMP/GT Rm, Rn {: |
nkeynes@359 | 475 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 476 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 477 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 478 | SETG_t(); |
nkeynes@417 | 479 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 480 | :} |
nkeynes@359 | 481 | CMP/HI Rm, Rn {: |
nkeynes@359 | 482 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 483 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 484 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 485 | SETA_t(); |
nkeynes@417 | 486 | sh4_x86.tstate = TSTATE_A; |
nkeynes@359 | 487 | :} |
nkeynes@359 | 488 | CMP/HS Rm, Rn {: |
nkeynes@359 | 489 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 490 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 491 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 492 | SETAE_t(); |
nkeynes@417 | 493 | sh4_x86.tstate = TSTATE_AE; |
nkeynes@359 | 494 | :} |
nkeynes@359 | 495 | CMP/PL Rn {: |
nkeynes@359 | 496 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 497 | CMP_imm8s_r32( 0, R_EAX ); |
nkeynes@359 | 498 | SETG_t(); |
nkeynes@417 | 499 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 500 | :} |
nkeynes@359 | 501 | CMP/PZ Rn {: |
nkeynes@359 | 502 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 503 | CMP_imm8s_r32( 0, R_EAX ); |
nkeynes@359 | 504 | SETGE_t(); |
nkeynes@417 | 505 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 506 | :} |
nkeynes@361 | 507 | CMP/STR Rm, Rn {: |
nkeynes@368 | 508 | load_reg( R_EAX, Rm ); |
nkeynes@368 | 509 | load_reg( R_ECX, Rn ); |
nkeynes@368 | 510 | XOR_r32_r32( R_ECX, R_EAX ); |
nkeynes@368 | 511 | TEST_r8_r8( R_AL, R_AL ); |
nkeynes@380 | 512 | JE_rel8(13, target1); |
nkeynes@368 | 513 | TEST_r8_r8( R_AH, R_AH ); // 2 |
nkeynes@380 | 514 | JE_rel8(9, target2); |
nkeynes@368 | 515 | SHR_imm8_r32( 16, R_EAX ); // 3 |
nkeynes@368 | 516 | TEST_r8_r8( R_AL, R_AL ); // 2 |
nkeynes@380 | 517 | JE_rel8(2, target3); |
nkeynes@368 | 518 | TEST_r8_r8( R_AH, R_AH ); // 2 |
nkeynes@380 | 519 | JMP_TARGET(target1); |
nkeynes@380 | 520 | JMP_TARGET(target2); |
nkeynes@380 | 521 | JMP_TARGET(target3); |
nkeynes@368 | 522 | SETE_t(); |
nkeynes@417 | 523 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 524 | :} |
nkeynes@361 | 525 | DIV0S Rm, Rn {: |
nkeynes@361 | 526 | load_reg( R_EAX, Rm ); |
nkeynes@386 | 527 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 528 | SHR_imm8_r32( 31, R_EAX ); |
nkeynes@361 | 529 | SHR_imm8_r32( 31, R_ECX ); |
nkeynes@361 | 530 | store_spreg( R_EAX, R_M ); |
nkeynes@361 | 531 | store_spreg( R_ECX, R_Q ); |
nkeynes@361 | 532 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@386 | 533 | SETNE_t(); |
nkeynes@417 | 534 | sh4_x86.tstate = TSTATE_NE; |
nkeynes@361 | 535 | :} |
nkeynes@361 | 536 | DIV0U {: |
nkeynes@361 | 537 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@361 | 538 | store_spreg( R_EAX, R_Q ); |
nkeynes@361 | 539 | store_spreg( R_EAX, R_M ); |
nkeynes@361 | 540 | store_spreg( R_EAX, R_T ); |
nkeynes@417 | 541 | sh4_x86.tstate = TSTATE_C; // works for DIV1 |
nkeynes@361 | 542 | :} |
nkeynes@386 | 543 | DIV1 Rm, Rn {: |
nkeynes@386 | 544 | load_spreg( R_ECX, R_M ); |
nkeynes@386 | 545 | load_reg( R_EAX, Rn ); |
nkeynes@417 | 546 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 547 | LDC_t(); |
nkeynes@417 | 548 | } |
nkeynes@386 | 549 | RCL1_r32( R_EAX ); |
nkeynes@386 | 550 | SETC_r8( R_DL ); // Q' |
nkeynes@386 | 551 | CMP_sh4r_r32( R_Q, R_ECX ); |
nkeynes@386 | 552 | JE_rel8(5, mqequal); |
nkeynes@386 | 553 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); |
nkeynes@386 | 554 | JMP_rel8(3, end); |
nkeynes@380 | 555 | JMP_TARGET(mqequal); |
nkeynes@386 | 556 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); |
nkeynes@386 | 557 | JMP_TARGET(end); |
nkeynes@386 | 558 | store_reg( R_EAX, Rn ); // Done with Rn now |
nkeynes@386 | 559 | SETC_r8(R_AL); // tmp1 |
nkeynes@386 | 560 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1 |
nkeynes@386 | 561 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M |
nkeynes@386 | 562 | store_spreg( R_ECX, R_Q ); |
nkeynes@386 | 563 | XOR_imm8s_r32( 1, R_AL ); // T = !Q' |
nkeynes@386 | 564 | MOVZX_r8_r32( R_AL, R_EAX ); |
nkeynes@386 | 565 | store_spreg( R_EAX, R_T ); |
nkeynes@417 | 566 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 567 | :} |
nkeynes@361 | 568 | DMULS.L Rm, Rn {: |
nkeynes@361 | 569 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 570 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 571 | IMUL_r32(R_ECX); |
nkeynes@361 | 572 | store_spreg( R_EDX, R_MACH ); |
nkeynes@361 | 573 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 574 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 575 | :} |
nkeynes@361 | 576 | DMULU.L Rm, Rn {: |
nkeynes@361 | 577 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 578 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 579 | MUL_r32(R_ECX); |
nkeynes@361 | 580 | store_spreg( R_EDX, R_MACH ); |
nkeynes@361 | 581 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 582 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 583 | :} |
nkeynes@359 | 584 | DT Rn {: |
nkeynes@359 | 585 | load_reg( R_EAX, Rn ); |
nkeynes@382 | 586 | ADD_imm8s_r32( -1, R_EAX ); |
nkeynes@359 | 587 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 588 | SETE_t(); |
nkeynes@417 | 589 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 590 | :} |
nkeynes@359 | 591 | EXTS.B Rm, Rn {: |
nkeynes@359 | 592 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 593 | MOVSX_r8_r32( R_EAX, R_EAX ); |
nkeynes@359 | 594 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 595 | :} |
nkeynes@361 | 596 | EXTS.W Rm, Rn {: |
nkeynes@361 | 597 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 598 | MOVSX_r16_r32( R_EAX, R_EAX ); |
nkeynes@361 | 599 | store_reg( R_EAX, Rn ); |
nkeynes@361 | 600 | :} |
nkeynes@361 | 601 | EXTU.B Rm, Rn {: |
nkeynes@361 | 602 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 603 | MOVZX_r8_r32( R_EAX, R_EAX ); |
nkeynes@361 | 604 | store_reg( R_EAX, Rn ); |
nkeynes@361 | 605 | :} |
nkeynes@361 | 606 | EXTU.W Rm, Rn {: |
nkeynes@361 | 607 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 608 | MOVZX_r16_r32( R_EAX, R_EAX ); |
nkeynes@361 | 609 | store_reg( R_EAX, Rn ); |
nkeynes@361 | 610 | :} |
nkeynes@571 | 611 | MAC.L @Rm+, @Rn+ {: |
nkeynes@571 | 612 | if( Rm == Rn ) { |
nkeynes@571 | 613 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 614 | check_ralign32( R_EAX ); |
nkeynes@571 | 615 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 616 | PUSH_realigned_r32( R_EAX ); |
nkeynes@571 | 617 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 618 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@571 | 619 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 620 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 621 | // Note translate twice in case of page boundaries. Maybe worth |
nkeynes@571 | 622 | // adding a page-boundary check to skip the second translation |
nkeynes@571 | 623 | } else { |
nkeynes@571 | 624 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 625 | check_ralign32( R_EAX ); |
nkeynes@571 | 626 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 627 | PUSH_realigned_r32( R_EAX ); |
nkeynes@571 | 628 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 629 | check_ralign32( R_EAX ); |
nkeynes@571 | 630 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 631 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 632 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 633 | } |
nkeynes@571 | 634 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@571 | 635 | POP_r32( R_ECX ); |
nkeynes@571 | 636 | PUSH_r32( R_EAX ); |
nkeynes@386 | 637 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@547 | 638 | POP_realigned_r32( R_ECX ); |
nkeynes@571 | 639 | |
nkeynes@386 | 640 | IMUL_r32( R_ECX ); |
nkeynes@386 | 641 | ADD_r32_sh4r( R_EAX, R_MACL ); |
nkeynes@386 | 642 | ADC_r32_sh4r( R_EDX, R_MACH ); |
nkeynes@386 | 643 | |
nkeynes@386 | 644 | load_spreg( R_ECX, R_S ); |
nkeynes@386 | 645 | TEST_r32_r32(R_ECX, R_ECX); |
nkeynes@527 | 646 | JE_rel8( CALL_FUNC0_SIZE, nosat ); |
nkeynes@386 | 647 | call_func0( signsat48 ); |
nkeynes@386 | 648 | JMP_TARGET( nosat ); |
nkeynes@417 | 649 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 650 | :} |
nkeynes@386 | 651 | MAC.W @Rm+, @Rn+ {: |
nkeynes@571 | 652 | if( Rm == Rn ) { |
nkeynes@571 | 653 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 654 | check_ralign16( R_EAX ); |
nkeynes@571 | 655 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 656 | PUSH_realigned_r32( R_EAX ); |
nkeynes@571 | 657 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 658 | ADD_imm8s_r32( 2, R_EAX ); |
nkeynes@571 | 659 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 660 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 661 | // Note translate twice in case of page boundaries. Maybe worth |
nkeynes@571 | 662 | // adding a page-boundary check to skip the second translation |
nkeynes@571 | 663 | } else { |
nkeynes@571 | 664 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 665 | check_ralign16( R_EAX ); |
nkeynes@571 | 666 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 667 | PUSH_realigned_r32( R_EAX ); |
nkeynes@571 | 668 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 669 | check_ralign16( R_EAX ); |
nkeynes@571 | 670 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 671 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 672 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 673 | } |
nkeynes@571 | 674 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@571 | 675 | POP_r32( R_ECX ); |
nkeynes@571 | 676 | PUSH_r32( R_EAX ); |
nkeynes@386 | 677 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@547 | 678 | POP_realigned_r32( R_ECX ); |
nkeynes@386 | 679 | IMUL_r32( R_ECX ); |
nkeynes@386 | 680 | |
nkeynes@386 | 681 | load_spreg( R_ECX, R_S ); |
nkeynes@386 | 682 | TEST_r32_r32( R_ECX, R_ECX ); |
nkeynes@386 | 683 | JE_rel8( 47, nosat ); |
nkeynes@386 | 684 | |
nkeynes@386 | 685 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6 |
nkeynes@386 | 686 | JNO_rel8( 51, end ); // 2 |
nkeynes@386 | 687 | load_imm32( R_EDX, 1 ); // 5 |
nkeynes@386 | 688 | store_spreg( R_EDX, R_MACH ); // 6 |
nkeynes@386 | 689 | JS_rel8( 13, positive ); // 2 |
nkeynes@386 | 690 | load_imm32( R_EAX, 0x80000000 );// 5 |
nkeynes@386 | 691 | store_spreg( R_EAX, R_MACL ); // 6 |
nkeynes@386 | 692 | JMP_rel8( 25, end2 ); // 2 |
nkeynes@386 | 693 | |
nkeynes@386 | 694 | JMP_TARGET(positive); |
nkeynes@386 | 695 | load_imm32( R_EAX, 0x7FFFFFFF );// 5 |
nkeynes@386 | 696 | store_spreg( R_EAX, R_MACL ); // 6 |
nkeynes@386 | 697 | JMP_rel8( 12, end3); // 2 |
nkeynes@386 | 698 | |
nkeynes@386 | 699 | JMP_TARGET(nosat); |
nkeynes@386 | 700 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6 |
nkeynes@386 | 701 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6 |
nkeynes@386 | 702 | JMP_TARGET(end); |
nkeynes@386 | 703 | JMP_TARGET(end2); |
nkeynes@386 | 704 | JMP_TARGET(end3); |
nkeynes@417 | 705 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 706 | :} |
nkeynes@359 | 707 | MOVT Rn {: |
nkeynes@359 | 708 | load_spreg( R_EAX, R_T ); |
nkeynes@359 | 709 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 710 | :} |
nkeynes@361 | 711 | MUL.L Rm, Rn {: |
nkeynes@361 | 712 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 713 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 714 | MUL_r32( R_ECX ); |
nkeynes@361 | 715 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 716 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 717 | :} |
nkeynes@374 | 718 | MULS.W Rm, Rn {: |
nkeynes@374 | 719 | load_reg16s( R_EAX, Rm ); |
nkeynes@374 | 720 | load_reg16s( R_ECX, Rn ); |
nkeynes@374 | 721 | MUL_r32( R_ECX ); |
nkeynes@374 | 722 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 723 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 724 | :} |
nkeynes@374 | 725 | MULU.W Rm, Rn {: |
nkeynes@374 | 726 | load_reg16u( R_EAX, Rm ); |
nkeynes@374 | 727 | load_reg16u( R_ECX, Rn ); |
nkeynes@374 | 728 | MUL_r32( R_ECX ); |
nkeynes@374 | 729 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 730 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 731 | :} |
nkeynes@359 | 732 | NEG Rm, Rn {: |
nkeynes@359 | 733 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 734 | NEG_r32( R_EAX ); |
nkeynes@359 | 735 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 736 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 737 | :} |
nkeynes@359 | 738 | NEGC Rm, Rn {: |
nkeynes@359 | 739 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 740 | XOR_r32_r32( R_ECX, R_ECX ); |
nkeynes@359 | 741 | LDC_t(); |
nkeynes@359 | 742 | SBB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 743 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 744 | SETC_t(); |
nkeynes@417 | 745 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 746 | :} |
nkeynes@359 | 747 | NOT Rm, Rn {: |
nkeynes@359 | 748 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 749 | NOT_r32( R_EAX ); |
nkeynes@359 | 750 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 751 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 752 | :} |
nkeynes@359 | 753 | OR Rm, Rn {: |
nkeynes@359 | 754 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 755 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 756 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 757 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 758 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 759 | :} |
nkeynes@359 | 760 | OR #imm, R0 {: |
nkeynes@359 | 761 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 762 | OR_imm32_r32(imm, R_EAX); |
nkeynes@359 | 763 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 764 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 765 | :} |
nkeynes@374 | 766 | OR.B #imm, @(R0, GBR) {: |
nkeynes@374 | 767 | load_reg( R_EAX, 0 ); |
nkeynes@374 | 768 | load_spreg( R_ECX, R_GBR ); |
nkeynes@571 | 769 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 770 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 771 | PUSH_realigned_r32(R_EAX); |
nkeynes@571 | 772 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@547 | 773 | POP_realigned_r32(R_ECX); |
nkeynes@386 | 774 | OR_imm32_r32(imm, R_EAX ); |
nkeynes@374 | 775 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@417 | 776 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 777 | :} |
nkeynes@359 | 778 | ROTCL Rn {: |
nkeynes@359 | 779 | load_reg( R_EAX, Rn ); |
nkeynes@417 | 780 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 781 | LDC_t(); |
nkeynes@417 | 782 | } |
nkeynes@359 | 783 | RCL1_r32( R_EAX ); |
nkeynes@359 | 784 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 785 | SETC_t(); |
nkeynes@417 | 786 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 787 | :} |
nkeynes@359 | 788 | ROTCR Rn {: |
nkeynes@359 | 789 | load_reg( R_EAX, Rn ); |
nkeynes@417 | 790 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 791 | LDC_t(); |
nkeynes@417 | 792 | } |
nkeynes@359 | 793 | RCR1_r32( R_EAX ); |
nkeynes@359 | 794 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 795 | SETC_t(); |
nkeynes@417 | 796 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 797 | :} |
nkeynes@359 | 798 | ROTL Rn {: |
nkeynes@359 | 799 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 800 | ROL1_r32( R_EAX ); |
nkeynes@359 | 801 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 802 | SETC_t(); |
nkeynes@417 | 803 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 804 | :} |
nkeynes@359 | 805 | ROTR Rn {: |
nkeynes@359 | 806 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 807 | ROR1_r32( R_EAX ); |
nkeynes@359 | 808 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 809 | SETC_t(); |
nkeynes@417 | 810 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 811 | :} |
nkeynes@359 | 812 | SHAD Rm, Rn {: |
nkeynes@359 | 813 | /* Annoyingly enough, not directly convertible */ |
nkeynes@361 | 814 | load_reg( R_EAX, Rn ); |
nkeynes@361 | 815 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 816 | CMP_imm32_r32( 0, R_ECX ); |
nkeynes@386 | 817 | JGE_rel8(16, doshl); |
nkeynes@361 | 818 | |
nkeynes@361 | 819 | NEG_r32( R_ECX ); // 2 |
nkeynes@361 | 820 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@386 | 821 | JE_rel8( 4, emptysar); // 2 |
nkeynes@361 | 822 | SAR_r32_CL( R_EAX ); // 2 |
nkeynes@386 | 823 | JMP_rel8(10, end); // 2 |
nkeynes@386 | 824 | |
nkeynes@386 | 825 | JMP_TARGET(emptysar); |
nkeynes@386 | 826 | SAR_imm8_r32(31, R_EAX ); // 3 |
nkeynes@386 | 827 | JMP_rel8(5, end2); |
nkeynes@382 | 828 | |
nkeynes@380 | 829 | JMP_TARGET(doshl); |
nkeynes@361 | 830 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@361 | 831 | SHL_r32_CL( R_EAX ); // 2 |
nkeynes@380 | 832 | JMP_TARGET(end); |
nkeynes@386 | 833 | JMP_TARGET(end2); |
nkeynes@361 | 834 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 835 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 836 | :} |
nkeynes@359 | 837 | SHLD Rm, Rn {: |
nkeynes@368 | 838 | load_reg( R_EAX, Rn ); |
nkeynes@368 | 839 | load_reg( R_ECX, Rm ); |
nkeynes@382 | 840 | CMP_imm32_r32( 0, R_ECX ); |
nkeynes@386 | 841 | JGE_rel8(15, doshl); |
nkeynes@368 | 842 | |
nkeynes@382 | 843 | NEG_r32( R_ECX ); // 2 |
nkeynes@382 | 844 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@386 | 845 | JE_rel8( 4, emptyshr ); |
nkeynes@382 | 846 | SHR_r32_CL( R_EAX ); // 2 |
nkeynes@386 | 847 | JMP_rel8(9, end); // 2 |
nkeynes@386 | 848 | |
nkeynes@386 | 849 | JMP_TARGET(emptyshr); |
nkeynes@386 | 850 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@386 | 851 | JMP_rel8(5, end2); |
nkeynes@382 | 852 | |
nkeynes@382 | 853 | JMP_TARGET(doshl); |
nkeynes@382 | 854 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@382 | 855 | SHL_r32_CL( R_EAX ); // 2 |
nkeynes@382 | 856 | JMP_TARGET(end); |
nkeynes@386 | 857 | JMP_TARGET(end2); |
nkeynes@368 | 858 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 859 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 860 | :} |
nkeynes@359 | 861 | SHAL Rn {: |
nkeynes@359 | 862 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 863 | SHL1_r32( R_EAX ); |
nkeynes@397 | 864 | SETC_t(); |
nkeynes@359 | 865 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 866 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 867 | :} |
nkeynes@359 | 868 | SHAR Rn {: |
nkeynes@359 | 869 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 870 | SAR1_r32( R_EAX ); |
nkeynes@397 | 871 | SETC_t(); |
nkeynes@359 | 872 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 873 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 874 | :} |
nkeynes@359 | 875 | SHLL Rn {: |
nkeynes@359 | 876 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 877 | SHL1_r32( R_EAX ); |
nkeynes@397 | 878 | SETC_t(); |
nkeynes@359 | 879 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 880 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 881 | :} |
nkeynes@359 | 882 | SHLL2 Rn {: |
nkeynes@359 | 883 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 884 | SHL_imm8_r32( 2, R_EAX ); |
nkeynes@359 | 885 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 886 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 887 | :} |
nkeynes@359 | 888 | SHLL8 Rn {: |
nkeynes@359 | 889 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 890 | SHL_imm8_r32( 8, R_EAX ); |
nkeynes@359 | 891 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 892 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 893 | :} |
nkeynes@359 | 894 | SHLL16 Rn {: |
nkeynes@359 | 895 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 896 | SHL_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 897 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 898 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 899 | :} |
nkeynes@359 | 900 | SHLR Rn {: |
nkeynes@359 | 901 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 902 | SHR1_r32( R_EAX ); |
nkeynes@397 | 903 | SETC_t(); |
nkeynes@359 | 904 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 905 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 906 | :} |
nkeynes@359 | 907 | SHLR2 Rn {: |
nkeynes@359 | 908 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 909 | SHR_imm8_r32( 2, R_EAX ); |
nkeynes@359 | 910 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 911 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 912 | :} |
nkeynes@359 | 913 | SHLR8 Rn {: |
nkeynes@359 | 914 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 915 | SHR_imm8_r32( 8, R_EAX ); |
nkeynes@359 | 916 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 917 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 918 | :} |
nkeynes@359 | 919 | SHLR16 Rn {: |
nkeynes@359 | 920 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 921 | SHR_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 922 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 923 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 924 | :} |
nkeynes@359 | 925 | SUB Rm, Rn {: |
nkeynes@359 | 926 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 927 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 928 | SUB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 929 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 930 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 931 | :} |
nkeynes@359 | 932 | SUBC Rm, Rn {: |
nkeynes@359 | 933 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 934 | load_reg( R_ECX, Rn ); |
nkeynes@417 | 935 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 936 | LDC_t(); |
nkeynes@417 | 937 | } |
nkeynes@359 | 938 | SBB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 939 | store_reg( R_ECX, Rn ); |
nkeynes@394 | 940 | SETC_t(); |
nkeynes@417 | 941 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 942 | :} |
nkeynes@359 | 943 | SUBV Rm, Rn {: |
nkeynes@359 | 944 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 945 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 946 | SUB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 947 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 948 | SETO_t(); |
nkeynes@417 | 949 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 950 | :} |
nkeynes@359 | 951 | SWAP.B Rm, Rn {: |
nkeynes@359 | 952 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 953 | XCHG_r8_r8( R_AL, R_AH ); |
nkeynes@359 | 954 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 955 | :} |
nkeynes@359 | 956 | SWAP.W Rm, Rn {: |
nkeynes@359 | 957 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 958 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 959 | SHL_imm8_r32( 16, R_ECX ); |
nkeynes@359 | 960 | SHR_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 961 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 962 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 963 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 964 | :} |
nkeynes@361 | 965 | TAS.B @Rn {: |
nkeynes@571 | 966 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 967 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 968 | PUSH_realigned_r32( R_EAX ); |
nkeynes@571 | 969 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@361 | 970 | TEST_r8_r8( R_AL, R_AL ); |
nkeynes@361 | 971 | SETE_t(); |
nkeynes@361 | 972 | OR_imm8_r8( 0x80, R_AL ); |
nkeynes@571 | 973 | POP_realigned_r32( R_ECX ); |
nkeynes@361 | 974 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@417 | 975 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 976 | :} |
nkeynes@361 | 977 | TST Rm, Rn {: |
nkeynes@361 | 978 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 979 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 980 | TEST_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 981 | SETE_t(); |
nkeynes@417 | 982 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 983 | :} |
nkeynes@368 | 984 | TST #imm, R0 {: |
nkeynes@368 | 985 | load_reg( R_EAX, 0 ); |
nkeynes@368 | 986 | TEST_imm32_r32( imm, R_EAX ); |
nkeynes@368 | 987 | SETE_t(); |
nkeynes@417 | 988 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 989 | :} |
nkeynes@368 | 990 | TST.B #imm, @(R0, GBR) {: |
nkeynes@368 | 991 | load_reg( R_EAX, 0); |
nkeynes@368 | 992 | load_reg( R_ECX, R_GBR); |
nkeynes@571 | 993 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 994 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 995 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@394 | 996 | TEST_imm8_r8( imm, R_AL ); |
nkeynes@368 | 997 | SETE_t(); |
nkeynes@417 | 998 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 999 | :} |
nkeynes@359 | 1000 | XOR Rm, Rn {: |
nkeynes@359 | 1001 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1002 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1003 | XOR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1004 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 1005 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1006 | :} |
nkeynes@359 | 1007 | XOR #imm, R0 {: |
nkeynes@359 | 1008 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 1009 | XOR_imm32_r32( imm, R_EAX ); |
nkeynes@359 | 1010 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1011 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1012 | :} |
nkeynes@359 | 1013 | XOR.B #imm, @(R0, GBR) {: |
nkeynes@359 | 1014 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 1015 | load_spreg( R_ECX, R_GBR ); |
nkeynes@571 | 1016 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1017 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1018 | PUSH_realigned_r32(R_EAX); |
nkeynes@571 | 1019 | MEM_READ_BYTE(R_EAX, R_EAX); |
nkeynes@547 | 1020 | POP_realigned_r32(R_ECX); |
nkeynes@359 | 1021 | XOR_imm32_r32( imm, R_EAX ); |
nkeynes@359 | 1022 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@417 | 1023 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1024 | :} |
nkeynes@361 | 1025 | XTRCT Rm, Rn {: |
nkeynes@361 | 1026 | load_reg( R_EAX, Rm ); |
nkeynes@394 | 1027 | load_reg( R_ECX, Rn ); |
nkeynes@394 | 1028 | SHL_imm8_r32( 16, R_EAX ); |
nkeynes@394 | 1029 | SHR_imm8_r32( 16, R_ECX ); |
nkeynes@361 | 1030 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 1031 | store_reg( R_ECX, Rn ); |
nkeynes@417 | 1032 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1033 | :} |
nkeynes@359 | 1034 | |
nkeynes@359 | 1035 | /* Data move instructions */ |
nkeynes@359 | 1036 | MOV Rm, Rn {: |
nkeynes@359 | 1037 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1038 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1039 | :} |
nkeynes@359 | 1040 | MOV #imm, Rn {: |
nkeynes@359 | 1041 | load_imm32( R_EAX, imm ); |
nkeynes@359 | 1042 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1043 | :} |
nkeynes@359 | 1044 | MOV.B Rm, @Rn {: |
nkeynes@571 | 1045 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1046 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1047 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1048 | MEM_WRITE_BYTE( R_EAX, R_EDX ); |
nkeynes@417 | 1049 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1050 | :} |
nkeynes@359 | 1051 | MOV.B Rm, @-Rn {: |
nkeynes@571 | 1052 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1053 | ADD_imm8s_r32( -1, R_EAX ); |
nkeynes@571 | 1054 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1055 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1056 | ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 1057 | MEM_WRITE_BYTE( R_EAX, R_EDX ); |
nkeynes@417 | 1058 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1059 | :} |
nkeynes@359 | 1060 | MOV.B Rm, @(R0, Rn) {: |
nkeynes@359 | 1061 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 1062 | load_reg( R_ECX, Rn ); |
nkeynes@571 | 1063 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1064 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1065 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1066 | MEM_WRITE_BYTE( R_EAX, R_EDX ); |
nkeynes@417 | 1067 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1068 | :} |
nkeynes@359 | 1069 | MOV.B R0, @(disp, GBR) {: |
nkeynes@571 | 1070 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1071 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1072 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1073 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1074 | MEM_WRITE_BYTE( R_EAX, R_EDX ); |
nkeynes@417 | 1075 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1076 | :} |
nkeynes@359 | 1077 | MOV.B R0, @(disp, Rn) {: |
nkeynes@571 | 1078 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1079 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1080 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1081 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1082 | MEM_WRITE_BYTE( R_EAX, R_EDX ); |
nkeynes@417 | 1083 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1084 | :} |
nkeynes@359 | 1085 | MOV.B @Rm, Rn {: |
nkeynes@571 | 1086 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1087 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1088 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@386 | 1089 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1090 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1091 | :} |
nkeynes@359 | 1092 | MOV.B @Rm+, Rn {: |
nkeynes@571 | 1093 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1094 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1095 | ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1096 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@359 | 1097 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1098 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1099 | :} |
nkeynes@359 | 1100 | MOV.B @(R0, Rm), Rn {: |
nkeynes@359 | 1101 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 1102 | load_reg( R_ECX, Rm ); |
nkeynes@571 | 1103 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1104 | MMU_TRANSLATE_READ( R_EAX ) |
nkeynes@571 | 1105 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@359 | 1106 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1107 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1108 | :} |
nkeynes@359 | 1109 | MOV.B @(disp, GBR), R0 {: |
nkeynes@571 | 1110 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1111 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1112 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1113 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@359 | 1114 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1115 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1116 | :} |
nkeynes@359 | 1117 | MOV.B @(disp, Rm), R0 {: |
nkeynes@571 | 1118 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1119 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1120 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1121 | MEM_READ_BYTE( R_EAX, R_EAX ); |
nkeynes@359 | 1122 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1123 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1124 | :} |
nkeynes@374 | 1125 | MOV.L Rm, @Rn {: |
nkeynes@571 | 1126 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1127 | check_walign32(R_EAX); |
nkeynes@571 | 1128 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1129 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1130 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1131 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1132 | :} |
nkeynes@361 | 1133 | MOV.L Rm, @-Rn {: |
nkeynes@571 | 1134 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1135 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 1136 | check_walign32( R_EAX ); |
nkeynes@571 | 1137 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1138 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1139 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 1140 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1141 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1142 | :} |
nkeynes@361 | 1143 | MOV.L Rm, @(R0, Rn) {: |
nkeynes@361 | 1144 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 1145 | load_reg( R_ECX, Rn ); |
nkeynes@571 | 1146 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1147 | check_walign32( R_EAX ); |
nkeynes@571 | 1148 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1149 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1150 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1151 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1152 | :} |
nkeynes@361 | 1153 | MOV.L R0, @(disp, GBR) {: |
nkeynes@571 | 1154 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1155 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1156 | check_walign32( R_EAX ); |
nkeynes@571 | 1157 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1158 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1159 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1160 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1161 | :} |
nkeynes@361 | 1162 | MOV.L Rm, @(disp, Rn) {: |
nkeynes@571 | 1163 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1164 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1165 | check_walign32( R_EAX ); |
nkeynes@571 | 1166 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1167 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1168 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1169 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1170 | :} |
nkeynes@361 | 1171 | MOV.L @Rm, Rn {: |
nkeynes@571 | 1172 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1173 | check_ralign32( R_EAX ); |
nkeynes@571 | 1174 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1175 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@361 | 1176 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1177 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1178 | :} |
nkeynes@361 | 1179 | MOV.L @Rm+, Rn {: |
nkeynes@361 | 1180 | load_reg( R_EAX, Rm ); |
nkeynes@382 | 1181 | check_ralign32( R_EAX ); |
nkeynes@571 | 1182 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1183 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1184 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@361 | 1185 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1186 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1187 | :} |
nkeynes@361 | 1188 | MOV.L @(R0, Rm), Rn {: |
nkeynes@361 | 1189 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 1190 | load_reg( R_ECX, Rm ); |
nkeynes@571 | 1191 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1192 | check_ralign32( R_EAX ); |
nkeynes@571 | 1193 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1194 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@361 | 1195 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1196 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1197 | :} |
nkeynes@361 | 1198 | MOV.L @(disp, GBR), R0 {: |
nkeynes@571 | 1199 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1200 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1201 | check_ralign32( R_EAX ); |
nkeynes@571 | 1202 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1203 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@361 | 1204 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1205 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1206 | :} |
nkeynes@361 | 1207 | MOV.L @(disp, PC), Rn {: |
nkeynes@374 | 1208 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1209 | SLOTILLEGAL(); |
nkeynes@374 | 1210 | } else { |
nkeynes@388 | 1211 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4; |
nkeynes@569 | 1212 | if( IS_IN_ICACHE(target) ) { |
nkeynes@569 | 1213 | // If the target address is in the same page as the code, it's |
nkeynes@569 | 1214 | // pretty safe to just ref it directly and circumvent the whole |
nkeynes@569 | 1215 | // memory subsystem. (this is a big performance win) |
nkeynes@569 | 1216 | |
nkeynes@569 | 1217 | // FIXME: There's a corner-case that's not handled here when |
nkeynes@569 | 1218 | // the current code-page is in the ITLB but not in the UTLB. |
nkeynes@569 | 1219 | // (should generate a TLB miss although need to test SH4 |
nkeynes@569 | 1220 | // behaviour to confirm) Unlikely to be anyone depending on this |
nkeynes@569 | 1221 | // behaviour though. |
nkeynes@569 | 1222 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@527 | 1223 | MOV_moff32_EAX( ptr ); |
nkeynes@388 | 1224 | } else { |
nkeynes@569 | 1225 | // Note: we use sh4r.pc for the calc as we could be running at a |
nkeynes@569 | 1226 | // different virtual address than the translation was done with, |
nkeynes@569 | 1227 | // but we can safely assume that the low bits are the same. |
nkeynes@571 | 1228 | load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); |
nkeynes@571 | 1229 | ADD_sh4r_r32( R_PC, R_EAX ); |
nkeynes@571 | 1230 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1231 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@569 | 1232 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@388 | 1233 | } |
nkeynes@382 | 1234 | store_reg( R_EAX, Rn ); |
nkeynes@374 | 1235 | } |
nkeynes@361 | 1236 | :} |
nkeynes@361 | 1237 | MOV.L @(disp, Rm), Rn {: |
nkeynes@571 | 1238 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1239 | ADD_imm8s_r32( disp, R_EAX ); |
nkeynes@571 | 1240 | check_ralign32( R_EAX ); |
nkeynes@571 | 1241 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1242 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@361 | 1243 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1244 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1245 | :} |
nkeynes@361 | 1246 | MOV.W Rm, @Rn {: |
nkeynes@571 | 1247 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1248 | check_walign16( R_EAX ); |
nkeynes@571 | 1249 | MMU_TRANSLATE_WRITE( R_EAX ) |
nkeynes@571 | 1250 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1251 | MEM_WRITE_WORD( R_EAX, R_EDX ); |
nkeynes@417 | 1252 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1253 | :} |
nkeynes@361 | 1254 | MOV.W Rm, @-Rn {: |
nkeynes@571 | 1255 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1256 | ADD_imm8s_r32( -2, R_EAX ); |
nkeynes@571 | 1257 | check_walign16( R_EAX ); |
nkeynes@571 | 1258 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1259 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1260 | ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 1261 | MEM_WRITE_WORD( R_EAX, R_EDX ); |
nkeynes@417 | 1262 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1263 | :} |
nkeynes@361 | 1264 | MOV.W Rm, @(R0, Rn) {: |
nkeynes@361 | 1265 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 1266 | load_reg( R_ECX, Rn ); |
nkeynes@571 | 1267 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1268 | check_walign16( R_EAX ); |
nkeynes@571 | 1269 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1270 | load_reg( R_EDX, Rm ); |
nkeynes@571 | 1271 | MEM_WRITE_WORD( R_EAX, R_EDX ); |
nkeynes@417 | 1272 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1273 | :} |
nkeynes@361 | 1274 | MOV.W R0, @(disp, GBR) {: |
nkeynes@571 | 1275 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1276 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1277 | check_walign16( R_EAX ); |
nkeynes@571 | 1278 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1279 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1280 | MEM_WRITE_WORD( R_EAX, R_EDX ); |
nkeynes@417 | 1281 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1282 | :} |
nkeynes@361 | 1283 | MOV.W R0, @(disp, Rn) {: |
nkeynes@571 | 1284 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1285 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1286 | check_walign16( R_EAX ); |
nkeynes@571 | 1287 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1288 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1289 | MEM_WRITE_WORD( R_EAX, R_EDX ); |
nkeynes@417 | 1290 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1291 | :} |
nkeynes@361 | 1292 | MOV.W @Rm, Rn {: |
nkeynes@571 | 1293 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1294 | check_ralign16( R_EAX ); |
nkeynes@571 | 1295 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1296 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@361 | 1297 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1298 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1299 | :} |
nkeynes@361 | 1300 | MOV.W @Rm+, Rn {: |
nkeynes@361 | 1301 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1302 | check_ralign16( R_EAX ); |
nkeynes@571 | 1303 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1304 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1305 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@361 | 1306 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1307 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1308 | :} |
nkeynes@361 | 1309 | MOV.W @(R0, Rm), Rn {: |
nkeynes@361 | 1310 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 1311 | load_reg( R_ECX, Rm ); |
nkeynes@571 | 1312 | ADD_r32_r32( R_ECX, R_EAX ); |
nkeynes@571 | 1313 | check_ralign16( R_EAX ); |
nkeynes@571 | 1314 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1315 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@361 | 1316 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 1317 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1318 | :} |
nkeynes@361 | 1319 | MOV.W @(disp, GBR), R0 {: |
nkeynes@571 | 1320 | load_spreg( R_EAX, R_GBR ); |
nkeynes@571 | 1321 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1322 | check_ralign16( R_EAX ); |
nkeynes@571 | 1323 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1324 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@361 | 1325 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1326 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1327 | :} |
nkeynes@361 | 1328 | MOV.W @(disp, PC), Rn {: |
nkeynes@374 | 1329 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1330 | SLOTILLEGAL(); |
nkeynes@374 | 1331 | } else { |
nkeynes@569 | 1332 | // See comments for MOV.L @(disp, PC), Rn |
nkeynes@569 | 1333 | uint32_t target = pc + disp + 4; |
nkeynes@569 | 1334 | if( IS_IN_ICACHE(target) ) { |
nkeynes@569 | 1335 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@569 | 1336 | MOV_moff32_EAX( ptr ); |
nkeynes@569 | 1337 | MOVSX_r16_r32( R_EAX, R_EAX ); |
nkeynes@569 | 1338 | } else { |
nkeynes@571 | 1339 | load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 ); |
nkeynes@571 | 1340 | ADD_sh4r_r32( R_PC, R_EAX ); |
nkeynes@571 | 1341 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1342 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@569 | 1343 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@569 | 1344 | } |
nkeynes@374 | 1345 | store_reg( R_EAX, Rn ); |
nkeynes@374 | 1346 | } |
nkeynes@361 | 1347 | :} |
nkeynes@361 | 1348 | MOV.W @(disp, Rm), R0 {: |
nkeynes@571 | 1349 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1350 | ADD_imm32_r32( disp, R_EAX ); |
nkeynes@571 | 1351 | check_ralign16( R_EAX ); |
nkeynes@571 | 1352 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 1353 | MEM_READ_WORD( R_EAX, R_EAX ); |
nkeynes@361 | 1354 | store_reg( R_EAX, 0 ); |
nkeynes@417 | 1355 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1356 | :} |
nkeynes@361 | 1357 | MOVA @(disp, PC), R0 {: |
nkeynes@374 | 1358 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1359 | SLOTILLEGAL(); |
nkeynes@374 | 1360 | } else { |
nkeynes@569 | 1361 | load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); |
nkeynes@569 | 1362 | ADD_sh4r_r32( R_PC, R_ECX ); |
nkeynes@374 | 1363 | store_reg( R_ECX, 0 ); |
nkeynes@571 | 1364 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1365 | } |
nkeynes@361 | 1366 | :} |
nkeynes@361 | 1367 | MOVCA.L R0, @Rn {: |
nkeynes@571 | 1368 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1369 | check_walign32( R_EAX ); |
nkeynes@571 | 1370 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 1371 | load_reg( R_EDX, 0 ); |
nkeynes@571 | 1372 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 1373 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1374 | :} |
nkeynes@359 | 1375 | |
nkeynes@359 | 1376 | /* Control transfer instructions */ |
nkeynes@374 | 1377 | BF disp {: |
nkeynes@374 | 1378 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1379 | SLOTILLEGAL(); |
nkeynes@374 | 1380 | } else { |
nkeynes@571 | 1381 | sh4vma_t target = disp + pc + 4; |
nkeynes@571 | 1382 | JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken ); |
nkeynes@571 | 1383 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1384 | JMP_TARGET(nottaken); |
nkeynes@408 | 1385 | return 2; |
nkeynes@374 | 1386 | } |
nkeynes@374 | 1387 | :} |
nkeynes@374 | 1388 | BF/S disp {: |
nkeynes@374 | 1389 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1390 | SLOTILLEGAL(); |
nkeynes@374 | 1391 | } else { |
nkeynes@571 | 1392 | sh4vma_t target = disp + pc + 4; |
nkeynes@408 | 1393 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@417 | 1394 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@417 | 1395 | CMP_imm8s_sh4r( 1, R_T ); |
nkeynes@417 | 1396 | sh4_x86.tstate = TSTATE_E; |
nkeynes@417 | 1397 | } |
nkeynes@417 | 1398 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32 |
nkeynes@526 | 1399 | sh4_translate_instruction(pc+2); |
nkeynes@571 | 1400 | exit_block_rel( target, pc+4 ); |
nkeynes@408 | 1401 | // not taken |
nkeynes@408 | 1402 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@526 | 1403 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1404 | return 4; |
nkeynes@374 | 1405 | } |
nkeynes@374 | 1406 | :} |
nkeynes@374 | 1407 | BRA disp {: |
nkeynes@374 | 1408 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1409 | SLOTILLEGAL(); |
nkeynes@374 | 1410 | } else { |
nkeynes@374 | 1411 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@526 | 1412 | sh4_translate_instruction( pc + 2 ); |
nkeynes@571 | 1413 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@409 | 1414 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1415 | return 4; |
nkeynes@374 | 1416 | } |
nkeynes@374 | 1417 | :} |
nkeynes@374 | 1418 | BRAF Rn {: |
nkeynes@374 | 1419 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1420 | SLOTILLEGAL(); |
nkeynes@374 | 1421 | } else { |
nkeynes@408 | 1422 | load_reg( R_EAX, Rn ); |
nkeynes@408 | 1423 | ADD_imm32_r32( pc + 4, R_EAX ); |
nkeynes@408 | 1424 | store_spreg( R_EAX, REG_OFFSET(pc) ); |
nkeynes@374 | 1425 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@417 | 1426 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@526 | 1427 | sh4_translate_instruction( pc + 2 ); |
nkeynes@408 | 1428 | exit_block_pcset(pc+2); |
nkeynes@409 | 1429 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1430 | return 4; |
nkeynes@374 | 1431 | } |
nkeynes@374 | 1432 | :} |
nkeynes@374 | 1433 | BSR disp {: |
nkeynes@374 | 1434 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1435 | SLOTILLEGAL(); |
nkeynes@374 | 1436 | } else { |
nkeynes@374 | 1437 | load_imm32( R_EAX, pc + 4 ); |
nkeynes@374 | 1438 | store_spreg( R_EAX, R_PR ); |
nkeynes@374 | 1439 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@526 | 1440 | sh4_translate_instruction( pc + 2 ); |
nkeynes@571 | 1441 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@409 | 1442 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1443 | return 4; |
nkeynes@374 | 1444 | } |
nkeynes@374 | 1445 | :} |
nkeynes@374 | 1446 | BSRF Rn {: |
nkeynes@374 | 1447 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1448 | SLOTILLEGAL(); |
nkeynes@374 | 1449 | } else { |
nkeynes@408 | 1450 | load_imm32( R_ECX, pc + 4 ); |
nkeynes@408 | 1451 | store_spreg( R_ECX, R_PR ); |
nkeynes@408 | 1452 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX ); |
nkeynes@408 | 1453 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@374 | 1454 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@417 | 1455 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@526 | 1456 | sh4_translate_instruction( pc + 2 ); |
nkeynes@408 | 1457 | exit_block_pcset(pc+2); |
nkeynes@409 | 1458 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1459 | return 4; |
nkeynes@374 | 1460 | } |
nkeynes@374 | 1461 | :} |
nkeynes@374 | 1462 | BT disp {: |
nkeynes@374 | 1463 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1464 | SLOTILLEGAL(); |
nkeynes@374 | 1465 | } else { |
nkeynes@571 | 1466 | sh4vma_t target = disp + pc + 4; |
nkeynes@571 | 1467 | JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken ); |
nkeynes@571 | 1468 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1469 | JMP_TARGET(nottaken); |
nkeynes@408 | 1470 | return 2; |
nkeynes@374 | 1471 | } |
nkeynes@374 | 1472 | :} |
nkeynes@374 | 1473 | BT/S disp {: |
nkeynes@374 | 1474 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1475 | SLOTILLEGAL(); |
nkeynes@374 | 1476 | } else { |
nkeynes@408 | 1477 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@417 | 1478 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@417 | 1479 | CMP_imm8s_sh4r( 1, R_T ); |
nkeynes@417 | 1480 | sh4_x86.tstate = TSTATE_E; |
nkeynes@417 | 1481 | } |
nkeynes@417 | 1482 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32 |
nkeynes@526 | 1483 | sh4_translate_instruction(pc+2); |
nkeynes@571 | 1484 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@408 | 1485 | // not taken |
nkeynes@408 | 1486 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@526 | 1487 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1488 | return 4; |
nkeynes@374 | 1489 | } |
nkeynes@374 | 1490 | :} |
nkeynes@374 | 1491 | JMP @Rn {: |
nkeynes@374 | 1492 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1493 | SLOTILLEGAL(); |
nkeynes@374 | 1494 | } else { |
nkeynes@408 | 1495 | load_reg( R_ECX, Rn ); |
nkeynes@408 | 1496 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@374 | 1497 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@526 | 1498 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1499 | exit_block_pcset(pc+2); |
nkeynes@409 | 1500 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1501 | return 4; |
nkeynes@374 | 1502 | } |
nkeynes@374 | 1503 | :} |
nkeynes@374 | 1504 | JSR @Rn {: |
nkeynes@374 | 1505 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1506 | SLOTILLEGAL(); |
nkeynes@374 | 1507 | } else { |
nkeynes@374 | 1508 | load_imm32( R_EAX, pc + 4 ); |
nkeynes@374 | 1509 | store_spreg( R_EAX, R_PR ); |
nkeynes@408 | 1510 | load_reg( R_ECX, Rn ); |
nkeynes@408 | 1511 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@374 | 1512 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@526 | 1513 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1514 | exit_block_pcset(pc+2); |
nkeynes@409 | 1515 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1516 | return 4; |
nkeynes@374 | 1517 | } |
nkeynes@374 | 1518 | :} |
nkeynes@374 | 1519 | RTE {: |
nkeynes@374 | 1520 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1521 | SLOTILLEGAL(); |
nkeynes@374 | 1522 | } else { |
nkeynes@408 | 1523 | check_priv(); |
nkeynes@408 | 1524 | load_spreg( R_ECX, R_SPC ); |
nkeynes@408 | 1525 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@374 | 1526 | load_spreg( R_EAX, R_SSR ); |
nkeynes@374 | 1527 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@374 | 1528 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@377 | 1529 | sh4_x86.priv_checked = FALSE; |
nkeynes@377 | 1530 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 1531 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@526 | 1532 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1533 | exit_block_pcset(pc+2); |
nkeynes@409 | 1534 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1535 | return 4; |
nkeynes@374 | 1536 | } |
nkeynes@374 | 1537 | :} |
nkeynes@374 | 1538 | RTS {: |
nkeynes@374 | 1539 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1540 | SLOTILLEGAL(); |
nkeynes@374 | 1541 | } else { |
nkeynes@408 | 1542 | load_spreg( R_ECX, R_PR ); |
nkeynes@408 | 1543 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@374 | 1544 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@526 | 1545 | sh4_translate_instruction(pc+2); |
nkeynes@408 | 1546 | exit_block_pcset(pc+2); |
nkeynes@409 | 1547 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1548 | return 4; |
nkeynes@374 | 1549 | } |
nkeynes@374 | 1550 | :} |
nkeynes@374 | 1551 | TRAPA #imm {: |
nkeynes@374 | 1552 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1553 | SLOTILLEGAL(); |
nkeynes@374 | 1554 | } else { |
nkeynes@533 | 1555 | load_imm32( R_ECX, pc+2 ); |
nkeynes@533 | 1556 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@527 | 1557 | load_imm32( R_EAX, imm ); |
nkeynes@527 | 1558 | call_func1( sh4_raise_trap, R_EAX ); |
nkeynes@417 | 1559 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@408 | 1560 | exit_block_pcset(pc); |
nkeynes@409 | 1561 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 1562 | return 2; |
nkeynes@374 | 1563 | } |
nkeynes@374 | 1564 | :} |
nkeynes@374 | 1565 | UNDEF {: |
nkeynes@374 | 1566 | if( sh4_x86.in_delay_slot ) { |
nkeynes@382 | 1567 | SLOTILLEGAL(); |
nkeynes@374 | 1568 | } else { |
nkeynes@559 | 1569 | JMP_exc(EXC_ILLEGAL); |
nkeynes@408 | 1570 | return 2; |
nkeynes@374 | 1571 | } |
nkeynes@368 | 1572 | :} |
nkeynes@374 | 1573 | |
nkeynes@374 | 1574 | CLRMAC {: |
nkeynes@374 | 1575 | XOR_r32_r32(R_EAX, R_EAX); |
nkeynes@374 | 1576 | store_spreg( R_EAX, R_MACL ); |
nkeynes@374 | 1577 | store_spreg( R_EAX, R_MACH ); |
nkeynes@417 | 1578 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@368 | 1579 | :} |
nkeynes@374 | 1580 | CLRS {: |
nkeynes@374 | 1581 | CLC(); |
nkeynes@374 | 1582 | SETC_sh4r(R_S); |
nkeynes@417 | 1583 | sh4_x86.tstate = TSTATE_C; |
nkeynes@368 | 1584 | :} |
nkeynes@374 | 1585 | CLRT {: |
nkeynes@374 | 1586 | CLC(); |
nkeynes@374 | 1587 | SETC_t(); |
nkeynes@417 | 1588 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1589 | :} |
nkeynes@374 | 1590 | SETS {: |
nkeynes@374 | 1591 | STC(); |
nkeynes@374 | 1592 | SETC_sh4r(R_S); |
nkeynes@417 | 1593 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1594 | :} |
nkeynes@374 | 1595 | SETT {: |
nkeynes@374 | 1596 | STC(); |
nkeynes@374 | 1597 | SETC_t(); |
nkeynes@417 | 1598 | sh4_x86.tstate = TSTATE_C; |
nkeynes@374 | 1599 | :} |
nkeynes@359 | 1600 | |
nkeynes@375 | 1601 | /* Floating point moves */ |
nkeynes@375 | 1602 | FMOV FRm, FRn {: |
nkeynes@375 | 1603 | /* As horrible as this looks, it's actually covering 5 separate cases: |
nkeynes@375 | 1604 | * 1. 32-bit fr-to-fr (PR=0) |
nkeynes@375 | 1605 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 ) |
nkeynes@375 | 1606 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 ) |
nkeynes@375 | 1607 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 ) |
nkeynes@375 | 1608 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 ) |
nkeynes@375 | 1609 | */ |
nkeynes@377 | 1610 | check_fpuen(); |
nkeynes@375 | 1611 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1612 | load_fr_bank( R_EDX ); |
nkeynes@375 | 1613 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 1614 | JNE_rel8(8, doublesize); |
nkeynes@375 | 1615 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch |
nkeynes@375 | 1616 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@375 | 1617 | if( FRm&1 ) { |
nkeynes@386 | 1618 | JMP_rel8(24, end); |
nkeynes@380 | 1619 | JMP_TARGET(doublesize); |
nkeynes@375 | 1620 | load_xf_bank( R_ECX ); |
nkeynes@375 | 1621 | load_fr( R_ECX, R_EAX, FRm-1 ); |
nkeynes@375 | 1622 | if( FRn&1 ) { |
nkeynes@375 | 1623 | load_fr( R_ECX, R_EDX, FRm ); |
nkeynes@375 | 1624 | store_fr( R_ECX, R_EAX, FRn-1 ); |
nkeynes@375 | 1625 | store_fr( R_ECX, R_EDX, FRn ); |
nkeynes@375 | 1626 | } else /* FRn&1 == 0 */ { |
nkeynes@375 | 1627 | load_fr( R_ECX, R_ECX, FRm ); |
nkeynes@388 | 1628 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@388 | 1629 | store_fr( R_EDX, R_ECX, FRn+1 ); |
nkeynes@375 | 1630 | } |
nkeynes@380 | 1631 | JMP_TARGET(end); |
nkeynes@375 | 1632 | } else /* FRm&1 == 0 */ { |
nkeynes@375 | 1633 | if( FRn&1 ) { |
nkeynes@386 | 1634 | JMP_rel8(24, end); |
nkeynes@375 | 1635 | load_xf_bank( R_ECX ); |
nkeynes@375 | 1636 | load_fr( R_EDX, R_EAX, FRm ); |
nkeynes@375 | 1637 | load_fr( R_EDX, R_EDX, FRm+1 ); |
nkeynes@375 | 1638 | store_fr( R_ECX, R_EAX, FRn-1 ); |
nkeynes@375 | 1639 | store_fr( R_ECX, R_EDX, FRn ); |
nkeynes@380 | 1640 | JMP_TARGET(end); |
nkeynes@375 | 1641 | } else /* FRn&1 == 0 */ { |
nkeynes@380 | 1642 | JMP_rel8(12, end); |
nkeynes@375 | 1643 | load_fr( R_EDX, R_EAX, FRm ); |
nkeynes@375 | 1644 | load_fr( R_EDX, R_ECX, FRm+1 ); |
nkeynes@375 | 1645 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@375 | 1646 | store_fr( R_EDX, R_ECX, FRn+1 ); |
nkeynes@380 | 1647 | JMP_TARGET(end); |
nkeynes@375 | 1648 | } |
nkeynes@375 | 1649 | } |
nkeynes@417 | 1650 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 1651 | :} |
nkeynes@416 | 1652 | FMOV FRm, @Rn {: |
nkeynes@559 | 1653 | check_fpuen(); |
nkeynes@571 | 1654 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1655 | check_walign32( R_EAX ); |
nkeynes@571 | 1656 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@416 | 1657 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1658 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@559 | 1659 | JNE_rel8(8 + MEM_WRITE_SIZE, doublesize); |
nkeynes@416 | 1660 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1661 | load_fr( R_EDX, R_ECX, FRm ); |
nkeynes@571 | 1662 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12 |
nkeynes@375 | 1663 | if( FRm&1 ) { |
nkeynes@527 | 1664 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end ); |
nkeynes@380 | 1665 | JMP_TARGET(doublesize); |
nkeynes@416 | 1666 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1667 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1668 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1669 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1670 | JMP_TARGET(end); |
nkeynes@375 | 1671 | } else { |
nkeynes@527 | 1672 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end ); |
nkeynes@380 | 1673 | JMP_TARGET(doublesize); |
nkeynes@416 | 1674 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1675 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1676 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1677 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1678 | JMP_TARGET(end); |
nkeynes@375 | 1679 | } |
nkeynes@417 | 1680 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 1681 | :} |
nkeynes@375 | 1682 | FMOV @Rm, FRn {: |
nkeynes@559 | 1683 | check_fpuen(); |
nkeynes@571 | 1684 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1685 | check_ralign32( R_EAX ); |
nkeynes@571 | 1686 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@416 | 1687 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1688 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@559 | 1689 | JNE_rel8(8 + MEM_READ_SIZE, doublesize); |
nkeynes@571 | 1690 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@416 | 1691 | load_fr_bank( R_EDX ); |
nkeynes@416 | 1692 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@375 | 1693 | if( FRn&1 ) { |
nkeynes@527 | 1694 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@380 | 1695 | JMP_TARGET(doublesize); |
nkeynes@571 | 1696 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1697 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@416 | 1698 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1699 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1700 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1701 | JMP_TARGET(end); |
nkeynes@375 | 1702 | } else { |
nkeynes@527 | 1703 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@380 | 1704 | JMP_TARGET(doublesize); |
nkeynes@571 | 1705 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1706 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1707 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1708 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1709 | JMP_TARGET(end); |
nkeynes@375 | 1710 | } |
nkeynes@417 | 1711 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 1712 | :} |
nkeynes@377 | 1713 | FMOV FRm, @-Rn {: |
nkeynes@559 | 1714 | check_fpuen(); |
nkeynes@571 | 1715 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1716 | check_walign32( R_EAX ); |
nkeynes@416 | 1717 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1718 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@571 | 1719 | JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize); |
nkeynes@571 | 1720 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 1721 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@416 | 1722 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1723 | load_fr( R_EDX, R_ECX, FRm ); |
nkeynes@571 | 1724 | ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn])); |
nkeynes@571 | 1725 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12 |
nkeynes@377 | 1726 | if( FRm&1 ) { |
nkeynes@571 | 1727 | JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end ); |
nkeynes@380 | 1728 | JMP_TARGET(doublesize); |
nkeynes@571 | 1729 | ADD_imm8s_r32(-8,R_EAX); |
nkeynes@571 | 1730 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@416 | 1731 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1732 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1733 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1734 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn])); |
nkeynes@571 | 1735 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1736 | JMP_TARGET(end); |
nkeynes@377 | 1737 | } else { |
nkeynes@571 | 1738 | JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end ); |
nkeynes@380 | 1739 | JMP_TARGET(doublesize); |
nkeynes@571 | 1740 | ADD_imm8s_r32(-8,R_EAX); |
nkeynes@571 | 1741 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@416 | 1742 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1743 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1744 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1745 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn])); |
nkeynes@571 | 1746 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1747 | JMP_TARGET(end); |
nkeynes@377 | 1748 | } |
nkeynes@417 | 1749 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1750 | :} |
nkeynes@416 | 1751 | FMOV @Rm+, FRn {: |
nkeynes@559 | 1752 | check_fpuen(); |
nkeynes@571 | 1753 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1754 | check_ralign32( R_EAX ); |
nkeynes@571 | 1755 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@416 | 1756 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1757 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@571 | 1758 | JNE_rel8(12 + MEM_READ_SIZE, doublesize); |
nkeynes@571 | 1759 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1760 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@416 | 1761 | load_fr_bank( R_EDX ); |
nkeynes@416 | 1762 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@377 | 1763 | if( FRn&1 ) { |
nkeynes@571 | 1764 | JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@380 | 1765 | JMP_TARGET(doublesize); |
nkeynes@571 | 1766 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1767 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1768 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@416 | 1769 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1770 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1771 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1772 | JMP_TARGET(end); |
nkeynes@377 | 1773 | } else { |
nkeynes@571 | 1774 | JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@571 | 1775 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 1776 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1777 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1778 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1779 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1780 | JMP_TARGET(end); |
nkeynes@377 | 1781 | } |
nkeynes@417 | 1782 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1783 | :} |
nkeynes@377 | 1784 | FMOV FRm, @(R0, Rn) {: |
nkeynes@559 | 1785 | check_fpuen(); |
nkeynes@571 | 1786 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 1787 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); |
nkeynes@571 | 1788 | check_walign32( R_EAX ); |
nkeynes@571 | 1789 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@416 | 1790 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1791 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@559 | 1792 | JNE_rel8(8 + MEM_WRITE_SIZE, doublesize); |
nkeynes@416 | 1793 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1794 | load_fr( R_EDX, R_ECX, FRm ); |
nkeynes@571 | 1795 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12 |
nkeynes@377 | 1796 | if( FRm&1 ) { |
nkeynes@527 | 1797 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end ); |
nkeynes@380 | 1798 | JMP_TARGET(doublesize); |
nkeynes@416 | 1799 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1800 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1801 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1802 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1803 | JMP_TARGET(end); |
nkeynes@377 | 1804 | } else { |
nkeynes@527 | 1805 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end ); |
nkeynes@380 | 1806 | JMP_TARGET(doublesize); |
nkeynes@416 | 1807 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1808 | load_fr( R_EDX, R_ECX, FRm&0x0E ); |
nkeynes@416 | 1809 | load_fr( R_EDX, R_EDX, FRm|0x01 ); |
nkeynes@571 | 1810 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX ); |
nkeynes@380 | 1811 | JMP_TARGET(end); |
nkeynes@377 | 1812 | } |
nkeynes@417 | 1813 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1814 | :} |
nkeynes@377 | 1815 | FMOV @(R0, Rm), FRn {: |
nkeynes@559 | 1816 | check_fpuen(); |
nkeynes@571 | 1817 | load_reg( R_EAX, Rm ); |
nkeynes@571 | 1818 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); |
nkeynes@571 | 1819 | check_ralign32( R_EAX ); |
nkeynes@571 | 1820 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@416 | 1821 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@416 | 1822 | TEST_imm32_r32( FPSCR_SZ, R_EDX ); |
nkeynes@559 | 1823 | JNE_rel8(8 + MEM_READ_SIZE, doublesize); |
nkeynes@571 | 1824 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@416 | 1825 | load_fr_bank( R_EDX ); |
nkeynes@416 | 1826 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@377 | 1827 | if( FRn&1 ) { |
nkeynes@527 | 1828 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@380 | 1829 | JMP_TARGET(doublesize); |
nkeynes@571 | 1830 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1831 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@416 | 1832 | load_xf_bank( R_EDX ); |
nkeynes@571 | 1833 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1834 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1835 | JMP_TARGET(end); |
nkeynes@377 | 1836 | } else { |
nkeynes@527 | 1837 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end); |
nkeynes@380 | 1838 | JMP_TARGET(doublesize); |
nkeynes@571 | 1839 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX ); |
nkeynes@416 | 1840 | load_fr_bank( R_EDX ); |
nkeynes@571 | 1841 | store_fr( R_EDX, R_ECX, FRn&0x0E ); |
nkeynes@571 | 1842 | store_fr( R_EDX, R_EAX, FRn|0x01 ); |
nkeynes@380 | 1843 | JMP_TARGET(end); |
nkeynes@377 | 1844 | } |
nkeynes@417 | 1845 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1846 | :} |
nkeynes@377 | 1847 | FLDI0 FRn {: /* IFF PR=0 */ |
nkeynes@377 | 1848 | check_fpuen(); |
nkeynes@377 | 1849 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1850 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1851 | JNE_rel8(8, end); |
nkeynes@377 | 1852 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@377 | 1853 | load_spreg( R_ECX, REG_OFFSET(fr_bank) ); |
nkeynes@377 | 1854 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@380 | 1855 | JMP_TARGET(end); |
nkeynes@417 | 1856 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1857 | :} |
nkeynes@377 | 1858 | FLDI1 FRn {: /* IFF PR=0 */ |
nkeynes@377 | 1859 | check_fpuen(); |
nkeynes@377 | 1860 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1861 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1862 | JNE_rel8(11, end); |
nkeynes@377 | 1863 | load_imm32(R_EAX, 0x3F800000); |
nkeynes@377 | 1864 | load_spreg( R_ECX, REG_OFFSET(fr_bank) ); |
nkeynes@377 | 1865 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@380 | 1866 | JMP_TARGET(end); |
nkeynes@417 | 1867 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1868 | :} |
nkeynes@377 | 1869 | |
nkeynes@377 | 1870 | FLOAT FPUL, FRn {: |
nkeynes@377 | 1871 | check_fpuen(); |
nkeynes@377 | 1872 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1873 | load_spreg(R_EDX, REG_OFFSET(fr_bank)); |
nkeynes@377 | 1874 | FILD_sh4r(R_FPUL); |
nkeynes@377 | 1875 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1876 | JNE_rel8(5, doubleprec); |
nkeynes@377 | 1877 | pop_fr( R_EDX, FRn ); |
nkeynes@380 | 1878 | JMP_rel8(3, end); |
nkeynes@380 | 1879 | JMP_TARGET(doubleprec); |
nkeynes@377 | 1880 | pop_dr( R_EDX, FRn ); |
nkeynes@380 | 1881 | JMP_TARGET(end); |
nkeynes@417 | 1882 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1883 | :} |
nkeynes@377 | 1884 | FTRC FRm, FPUL {: |
nkeynes@377 | 1885 | check_fpuen(); |
nkeynes@388 | 1886 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@388 | 1887 | load_fr_bank( R_EDX ); |
nkeynes@388 | 1888 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@388 | 1889 | JNE_rel8(5, doubleprec); |
nkeynes@388 | 1890 | push_fr( R_EDX, FRm ); |
nkeynes@388 | 1891 | JMP_rel8(3, doop); |
nkeynes@388 | 1892 | JMP_TARGET(doubleprec); |
nkeynes@388 | 1893 | push_dr( R_EDX, FRm ); |
nkeynes@388 | 1894 | JMP_TARGET( doop ); |
nkeynes@388 | 1895 | load_imm32( R_ECX, (uint32_t)&max_int ); |
nkeynes@388 | 1896 | FILD_r32ind( R_ECX ); |
nkeynes@388 | 1897 | FCOMIP_st(1); |
nkeynes@394 | 1898 | JNA_rel8( 32, sat ); |
nkeynes@388 | 1899 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5 |
nkeynes@388 | 1900 | FILD_r32ind( R_ECX ); // 2 |
nkeynes@388 | 1901 | FCOMIP_st(1); // 2 |
nkeynes@394 | 1902 | JAE_rel8( 21, sat2 ); // 2 |
nkeynes@394 | 1903 | load_imm32( R_EAX, (uint32_t)&save_fcw ); |
nkeynes@394 | 1904 | FNSTCW_r32ind( R_EAX ); |
nkeynes@394 | 1905 | load_imm32( R_EDX, (uint32_t)&trunc_fcw ); |
nkeynes@394 | 1906 | FLDCW_r32ind( R_EDX ); |
nkeynes@388 | 1907 | FISTP_sh4r(R_FPUL); // 3 |
nkeynes@394 | 1908 | FLDCW_r32ind( R_EAX ); |
nkeynes@388 | 1909 | JMP_rel8( 9, end ); // 2 |
nkeynes@388 | 1910 | |
nkeynes@388 | 1911 | JMP_TARGET(sat); |
nkeynes@388 | 1912 | JMP_TARGET(sat2); |
nkeynes@388 | 1913 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2 |
nkeynes@388 | 1914 | store_spreg( R_ECX, R_FPUL ); |
nkeynes@388 | 1915 | FPOP_st(); |
nkeynes@388 | 1916 | JMP_TARGET(end); |
nkeynes@417 | 1917 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1918 | :} |
nkeynes@377 | 1919 | FLDS FRm, FPUL {: |
nkeynes@377 | 1920 | check_fpuen(); |
nkeynes@377 | 1921 | load_fr_bank( R_ECX ); |
nkeynes@377 | 1922 | load_fr( R_ECX, R_EAX, FRm ); |
nkeynes@377 | 1923 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@417 | 1924 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1925 | :} |
nkeynes@377 | 1926 | FSTS FPUL, FRn {: |
nkeynes@377 | 1927 | check_fpuen(); |
nkeynes@377 | 1928 | load_fr_bank( R_ECX ); |
nkeynes@377 | 1929 | load_spreg( R_EAX, R_FPUL ); |
nkeynes@377 | 1930 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@417 | 1931 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1932 | :} |
nkeynes@377 | 1933 | FCNVDS FRm, FPUL {: |
nkeynes@377 | 1934 | check_fpuen(); |
nkeynes@377 | 1935 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1936 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1937 | JE_rel8(9, end); // only when PR=1 |
nkeynes@377 | 1938 | load_fr_bank( R_ECX ); |
nkeynes@377 | 1939 | push_dr( R_ECX, FRm ); |
nkeynes@377 | 1940 | pop_fpul(); |
nkeynes@380 | 1941 | JMP_TARGET(end); |
nkeynes@417 | 1942 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1943 | :} |
nkeynes@377 | 1944 | FCNVSD FPUL, FRn {: |
nkeynes@377 | 1945 | check_fpuen(); |
nkeynes@377 | 1946 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1947 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1948 | JE_rel8(9, end); // only when PR=1 |
nkeynes@377 | 1949 | load_fr_bank( R_ECX ); |
nkeynes@377 | 1950 | push_fpul(); |
nkeynes@377 | 1951 | pop_dr( R_ECX, FRn ); |
nkeynes@380 | 1952 | JMP_TARGET(end); |
nkeynes@417 | 1953 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 1954 | :} |
nkeynes@375 | 1955 | |
nkeynes@359 | 1956 | /* Floating point instructions */ |
nkeynes@374 | 1957 | FABS FRn {: |
nkeynes@377 | 1958 | check_fpuen(); |
nkeynes@374 | 1959 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 1960 | load_fr_bank( R_EDX ); |
nkeynes@374 | 1961 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 1962 | JNE_rel8(10, doubleprec); |
nkeynes@374 | 1963 | push_fr(R_EDX, FRn); // 3 |
nkeynes@374 | 1964 | FABS_st0(); // 2 |
nkeynes@374 | 1965 | pop_fr( R_EDX, FRn); //3 |
nkeynes@380 | 1966 | JMP_rel8(8,end); // 2 |
nkeynes@380 | 1967 | JMP_TARGET(doubleprec); |
nkeynes@374 | 1968 | push_dr(R_EDX, FRn); |
nkeynes@374 | 1969 | FABS_st0(); |
nkeynes@374 | 1970 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 1971 | JMP_TARGET(end); |
nkeynes@417 | 1972 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1973 | :} |
nkeynes@377 | 1974 | FADD FRm, FRn {: |
nkeynes@377 | 1975 | check_fpuen(); |
nkeynes@375 | 1976 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@375 | 1977 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 1978 | load_fr_bank( R_EDX ); |
nkeynes@380 | 1979 | JNE_rel8(13,doubleprec); |
nkeynes@377 | 1980 | push_fr(R_EDX, FRm); |
nkeynes@377 | 1981 | push_fr(R_EDX, FRn); |
nkeynes@377 | 1982 | FADDP_st(1); |
nkeynes@377 | 1983 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 1984 | JMP_rel8(11,end); |
nkeynes@380 | 1985 | JMP_TARGET(doubleprec); |
nkeynes@377 | 1986 | push_dr(R_EDX, FRm); |
nkeynes@377 | 1987 | push_dr(R_EDX, FRn); |
nkeynes@377 | 1988 | FADDP_st(1); |
nkeynes@377 | 1989 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 1990 | JMP_TARGET(end); |
nkeynes@417 | 1991 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 1992 | :} |
nkeynes@377 | 1993 | FDIV FRm, FRn {: |
nkeynes@377 | 1994 | check_fpuen(); |
nkeynes@375 | 1995 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@375 | 1996 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 1997 | load_fr_bank( R_EDX ); |
nkeynes@380 | 1998 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 1999 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2000 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2001 | FDIVP_st(1); |
nkeynes@377 | 2002 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2003 | JMP_rel8(11, end); |
nkeynes@380 | 2004 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2005 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2006 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2007 | FDIVP_st(1); |
nkeynes@377 | 2008 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2009 | JMP_TARGET(end); |
nkeynes@417 | 2010 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2011 | :} |
nkeynes@375 | 2012 | FMAC FR0, FRm, FRn {: |
nkeynes@377 | 2013 | check_fpuen(); |
nkeynes@375 | 2014 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@375 | 2015 | load_spreg( R_EDX, REG_OFFSET(fr_bank)); |
nkeynes@375 | 2016 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2017 | JNE_rel8(18, doubleprec); |
nkeynes@375 | 2018 | push_fr( R_EDX, 0 ); |
nkeynes@375 | 2019 | push_fr( R_EDX, FRm ); |
nkeynes@375 | 2020 | FMULP_st(1); |
nkeynes@375 | 2021 | push_fr( R_EDX, FRn ); |
nkeynes@375 | 2022 | FADDP_st(1); |
nkeynes@375 | 2023 | pop_fr( R_EDX, FRn ); |
nkeynes@380 | 2024 | JMP_rel8(16, end); |
nkeynes@380 | 2025 | JMP_TARGET(doubleprec); |
nkeynes@375 | 2026 | push_dr( R_EDX, 0 ); |
nkeynes@375 | 2027 | push_dr( R_EDX, FRm ); |
nkeynes@375 | 2028 | FMULP_st(1); |
nkeynes@375 | 2029 | push_dr( R_EDX, FRn ); |
nkeynes@375 | 2030 | FADDP_st(1); |
nkeynes@375 | 2031 | pop_dr( R_EDX, FRn ); |
nkeynes@380 | 2032 | JMP_TARGET(end); |
nkeynes@417 | 2033 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2034 | :} |
nkeynes@375 | 2035 | |
nkeynes@377 | 2036 | FMUL FRm, FRn {: |
nkeynes@377 | 2037 | check_fpuen(); |
nkeynes@377 | 2038 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2039 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2040 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2041 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 2042 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2043 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2044 | FMULP_st(1); |
nkeynes@377 | 2045 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2046 | JMP_rel8(11, end); |
nkeynes@380 | 2047 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2048 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2049 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2050 | FMULP_st(1); |
nkeynes@377 | 2051 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2052 | JMP_TARGET(end); |
nkeynes@417 | 2053 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2054 | :} |
nkeynes@377 | 2055 | FNEG FRn {: |
nkeynes@377 | 2056 | check_fpuen(); |
nkeynes@377 | 2057 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2058 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2059 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2060 | JNE_rel8(10, doubleprec); |
nkeynes@377 | 2061 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2062 | FCHS_st0(); |
nkeynes@377 | 2063 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2064 | JMP_rel8(8, end); |
nkeynes@380 | 2065 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2066 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2067 | FCHS_st0(); |
nkeynes@377 | 2068 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2069 | JMP_TARGET(end); |
nkeynes@417 | 2070 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2071 | :} |
nkeynes@377 | 2072 | FSRRA FRn {: |
nkeynes@377 | 2073 | check_fpuen(); |
nkeynes@377 | 2074 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2075 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2076 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2077 | JNE_rel8(12, end); // PR=0 only |
nkeynes@377 | 2078 | FLD1_st0(); |
nkeynes@377 | 2079 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2080 | FSQRT_st0(); |
nkeynes@377 | 2081 | FDIVP_st(1); |
nkeynes@377 | 2082 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2083 | JMP_TARGET(end); |
nkeynes@417 | 2084 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2085 | :} |
nkeynes@377 | 2086 | FSQRT FRn {: |
nkeynes@377 | 2087 | check_fpuen(); |
nkeynes@377 | 2088 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2089 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2090 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2091 | JNE_rel8(10, doubleprec); |
nkeynes@377 | 2092 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2093 | FSQRT_st0(); |
nkeynes@377 | 2094 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2095 | JMP_rel8(8, end); |
nkeynes@380 | 2096 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2097 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2098 | FSQRT_st0(); |
nkeynes@377 | 2099 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2100 | JMP_TARGET(end); |
nkeynes@417 | 2101 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2102 | :} |
nkeynes@377 | 2103 | FSUB FRm, FRn {: |
nkeynes@377 | 2104 | check_fpuen(); |
nkeynes@377 | 2105 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2106 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2107 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2108 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 2109 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2110 | push_fr(R_EDX, FRm); |
nkeynes@388 | 2111 | FSUBP_st(1); |
nkeynes@377 | 2112 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2113 | JMP_rel8(11, end); |
nkeynes@380 | 2114 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2115 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2116 | push_dr(R_EDX, FRm); |
nkeynes@388 | 2117 | FSUBP_st(1); |
nkeynes@377 | 2118 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2119 | JMP_TARGET(end); |
nkeynes@417 | 2120 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2121 | :} |
nkeynes@377 | 2122 | |
nkeynes@377 | 2123 | FCMP/EQ FRm, FRn {: |
nkeynes@377 | 2124 | check_fpuen(); |
nkeynes@377 | 2125 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2126 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2127 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2128 | JNE_rel8(8, doubleprec); |
nkeynes@377 | 2129 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2130 | push_fr(R_EDX, FRn); |
nkeynes@380 | 2131 | JMP_rel8(6, end); |
nkeynes@380 | 2132 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2133 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2134 | push_dr(R_EDX, FRn); |
nkeynes@382 | 2135 | JMP_TARGET(end); |
nkeynes@377 | 2136 | FCOMIP_st(1); |
nkeynes@377 | 2137 | SETE_t(); |
nkeynes@377 | 2138 | FPOP_st(); |
nkeynes@417 | 2139 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2140 | :} |
nkeynes@377 | 2141 | FCMP/GT FRm, FRn {: |
nkeynes@377 | 2142 | check_fpuen(); |
nkeynes@377 | 2143 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2144 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2145 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2146 | JNE_rel8(8, doubleprec); |
nkeynes@377 | 2147 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2148 | push_fr(R_EDX, FRn); |
nkeynes@380 | 2149 | JMP_rel8(6, end); |
nkeynes@380 | 2150 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2151 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2152 | push_dr(R_EDX, FRn); |
nkeynes@380 | 2153 | JMP_TARGET(end); |
nkeynes@377 | 2154 | FCOMIP_st(1); |
nkeynes@377 | 2155 | SETA_t(); |
nkeynes@377 | 2156 | FPOP_st(); |
nkeynes@417 | 2157 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2158 | :} |
nkeynes@377 | 2159 | |
nkeynes@377 | 2160 | FSCA FPUL, FRn {: |
nkeynes@377 | 2161 | check_fpuen(); |
nkeynes@388 | 2162 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@388 | 2163 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@527 | 2164 | JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec ); |
nkeynes@388 | 2165 | load_fr_bank( R_ECX ); |
nkeynes@388 | 2166 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX ); |
nkeynes@388 | 2167 | load_spreg( R_EDX, R_FPUL ); |
nkeynes@388 | 2168 | call_func2( sh4_fsca, R_EDX, R_ECX ); |
nkeynes@388 | 2169 | JMP_TARGET(doubleprec); |
nkeynes@417 | 2170 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2171 | :} |
nkeynes@377 | 2172 | FIPR FVm, FVn {: |
nkeynes@377 | 2173 | check_fpuen(); |
nkeynes@388 | 2174 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@388 | 2175 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@388 | 2176 | JNE_rel8(44, doubleprec); |
nkeynes@388 | 2177 | |
nkeynes@388 | 2178 | load_fr_bank( R_ECX ); |
nkeynes@388 | 2179 | push_fr( R_ECX, FVm<<2 ); |
nkeynes@388 | 2180 | push_fr( R_ECX, FVn<<2 ); |
nkeynes@388 | 2181 | FMULP_st(1); |
nkeynes@388 | 2182 | push_fr( R_ECX, (FVm<<2)+1); |
nkeynes@388 | 2183 | push_fr( R_ECX, (FVn<<2)+1); |
nkeynes@388 | 2184 | FMULP_st(1); |
nkeynes@388 | 2185 | FADDP_st(1); |
nkeynes@388 | 2186 | push_fr( R_ECX, (FVm<<2)+2); |
nkeynes@388 | 2187 | push_fr( R_ECX, (FVn<<2)+2); |
nkeynes@388 | 2188 | FMULP_st(1); |
nkeynes@388 | 2189 | FADDP_st(1); |
nkeynes@388 | 2190 | push_fr( R_ECX, (FVm<<2)+3); |
nkeynes@388 | 2191 | push_fr( R_ECX, (FVn<<2)+3); |
nkeynes@388 | 2192 | FMULP_st(1); |
nkeynes@388 | 2193 | FADDP_st(1); |
nkeynes@388 | 2194 | pop_fr( R_ECX, (FVn<<2)+3); |
nkeynes@388 | 2195 | JMP_TARGET(doubleprec); |
nkeynes@417 | 2196 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2197 | :} |
nkeynes@377 | 2198 | FTRV XMTRX, FVn {: |
nkeynes@377 | 2199 | check_fpuen(); |
nkeynes@388 | 2200 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@388 | 2201 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@527 | 2202 | JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec ); |
nkeynes@388 | 2203 | load_fr_bank( R_EDX ); // 3 |
nkeynes@388 | 2204 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3 |
nkeynes@388 | 2205 | load_xf_bank( R_ECX ); // 12 |
nkeynes@388 | 2206 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12 |
nkeynes@388 | 2207 | JMP_TARGET(doubleprec); |
nkeynes@417 | 2208 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2209 | :} |
nkeynes@377 | 2210 | |
nkeynes@377 | 2211 | FRCHG {: |
nkeynes@377 | 2212 | check_fpuen(); |
nkeynes@377 | 2213 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2214 | XOR_imm32_r32( FPSCR_FR, R_ECX ); |
nkeynes@377 | 2215 | store_spreg( R_ECX, R_FPSCR ); |
nkeynes@386 | 2216 | update_fr_bank( R_ECX ); |
nkeynes@417 | 2217 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2218 | :} |
nkeynes@377 | 2219 | FSCHG {: |
nkeynes@377 | 2220 | check_fpuen(); |
nkeynes@377 | 2221 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2222 | XOR_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@377 | 2223 | store_spreg( R_ECX, R_FPSCR ); |
nkeynes@417 | 2224 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2225 | :} |
nkeynes@359 | 2226 | |
nkeynes@359 | 2227 | /* Processor control instructions */ |
nkeynes@368 | 2228 | LDC Rm, SR {: |
nkeynes@386 | 2229 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2230 | SLOTILLEGAL(); |
nkeynes@386 | 2231 | } else { |
nkeynes@386 | 2232 | check_priv(); |
nkeynes@386 | 2233 | load_reg( R_EAX, Rm ); |
nkeynes@386 | 2234 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@386 | 2235 | sh4_x86.priv_checked = FALSE; |
nkeynes@386 | 2236 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2237 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 2238 | } |
nkeynes@368 | 2239 | :} |
nkeynes@359 | 2240 | LDC Rm, GBR {: |
nkeynes@359 | 2241 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2242 | store_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 2243 | :} |
nkeynes@359 | 2244 | LDC Rm, VBR {: |
nkeynes@386 | 2245 | check_priv(); |
nkeynes@359 | 2246 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2247 | store_spreg( R_EAX, R_VBR ); |
nkeynes@417 | 2248 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2249 | :} |
nkeynes@359 | 2250 | LDC Rm, SSR {: |
nkeynes@386 | 2251 | check_priv(); |
nkeynes@359 | 2252 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2253 | store_spreg( R_EAX, R_SSR ); |
nkeynes@417 | 2254 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2255 | :} |
nkeynes@359 | 2256 | LDC Rm, SGR {: |
nkeynes@386 | 2257 | check_priv(); |
nkeynes@359 | 2258 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2259 | store_spreg( R_EAX, R_SGR ); |
nkeynes@417 | 2260 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2261 | :} |
nkeynes@359 | 2262 | LDC Rm, SPC {: |
nkeynes@386 | 2263 | check_priv(); |
nkeynes@359 | 2264 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2265 | store_spreg( R_EAX, R_SPC ); |
nkeynes@417 | 2266 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2267 | :} |
nkeynes@359 | 2268 | LDC Rm, DBR {: |
nkeynes@386 | 2269 | check_priv(); |
nkeynes@359 | 2270 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2271 | store_spreg( R_EAX, R_DBR ); |
nkeynes@417 | 2272 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2273 | :} |
nkeynes@374 | 2274 | LDC Rm, Rn_BANK {: |
nkeynes@386 | 2275 | check_priv(); |
nkeynes@374 | 2276 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 2277 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2278 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2279 | :} |
nkeynes@359 | 2280 | LDC.L @Rm+, GBR {: |
nkeynes@359 | 2281 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2282 | check_ralign32( R_EAX ); |
nkeynes@571 | 2283 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2284 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2285 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2286 | store_spreg( R_EAX, R_GBR ); |
nkeynes@417 | 2287 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2288 | :} |
nkeynes@368 | 2289 | LDC.L @Rm+, SR {: |
nkeynes@386 | 2290 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2291 | SLOTILLEGAL(); |
nkeynes@386 | 2292 | } else { |
nkeynes@559 | 2293 | check_priv(); |
nkeynes@386 | 2294 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2295 | check_ralign32( R_EAX ); |
nkeynes@571 | 2296 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2297 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2298 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@386 | 2299 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@386 | 2300 | sh4_x86.priv_checked = FALSE; |
nkeynes@386 | 2301 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2302 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 2303 | } |
nkeynes@359 | 2304 | :} |
nkeynes@359 | 2305 | LDC.L @Rm+, VBR {: |
nkeynes@559 | 2306 | check_priv(); |
nkeynes@359 | 2307 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2308 | check_ralign32( R_EAX ); |
nkeynes@571 | 2309 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2310 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2311 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2312 | store_spreg( R_EAX, R_VBR ); |
nkeynes@417 | 2313 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2314 | :} |
nkeynes@359 | 2315 | LDC.L @Rm+, SSR {: |
nkeynes@559 | 2316 | check_priv(); |
nkeynes@359 | 2317 | load_reg( R_EAX, Rm ); |
nkeynes@416 | 2318 | check_ralign32( R_EAX ); |
nkeynes@571 | 2319 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2320 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2321 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2322 | store_spreg( R_EAX, R_SSR ); |
nkeynes@417 | 2323 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2324 | :} |
nkeynes@359 | 2325 | LDC.L @Rm+, SGR {: |
nkeynes@559 | 2326 | check_priv(); |
nkeynes@359 | 2327 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2328 | check_ralign32( R_EAX ); |
nkeynes@571 | 2329 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2330 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2331 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2332 | store_spreg( R_EAX, R_SGR ); |
nkeynes@417 | 2333 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2334 | :} |
nkeynes@359 | 2335 | LDC.L @Rm+, SPC {: |
nkeynes@559 | 2336 | check_priv(); |
nkeynes@359 | 2337 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2338 | check_ralign32( R_EAX ); |
nkeynes@571 | 2339 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2340 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2341 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2342 | store_spreg( R_EAX, R_SPC ); |
nkeynes@417 | 2343 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2344 | :} |
nkeynes@359 | 2345 | LDC.L @Rm+, DBR {: |
nkeynes@559 | 2346 | check_priv(); |
nkeynes@359 | 2347 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2348 | check_ralign32( R_EAX ); |
nkeynes@571 | 2349 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2350 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2351 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2352 | store_spreg( R_EAX, R_DBR ); |
nkeynes@417 | 2353 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2354 | :} |
nkeynes@359 | 2355 | LDC.L @Rm+, Rn_BANK {: |
nkeynes@559 | 2356 | check_priv(); |
nkeynes@374 | 2357 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2358 | check_ralign32( R_EAX ); |
nkeynes@571 | 2359 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2360 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2361 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@374 | 2362 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2363 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2364 | :} |
nkeynes@359 | 2365 | LDS Rm, FPSCR {: |
nkeynes@359 | 2366 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2367 | store_spreg( R_EAX, R_FPSCR ); |
nkeynes@386 | 2368 | update_fr_bank( R_EAX ); |
nkeynes@417 | 2369 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2370 | :} |
nkeynes@359 | 2371 | LDS.L @Rm+, FPSCR {: |
nkeynes@359 | 2372 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2373 | check_ralign32( R_EAX ); |
nkeynes@571 | 2374 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2375 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2376 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2377 | store_spreg( R_EAX, R_FPSCR ); |
nkeynes@386 | 2378 | update_fr_bank( R_EAX ); |
nkeynes@417 | 2379 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2380 | :} |
nkeynes@359 | 2381 | LDS Rm, FPUL {: |
nkeynes@359 | 2382 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2383 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 2384 | :} |
nkeynes@359 | 2385 | LDS.L @Rm+, FPUL {: |
nkeynes@359 | 2386 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2387 | check_ralign32( R_EAX ); |
nkeynes@571 | 2388 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2389 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2390 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2391 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@417 | 2392 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2393 | :} |
nkeynes@359 | 2394 | LDS Rm, MACH {: |
nkeynes@359 | 2395 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2396 | store_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 2397 | :} |
nkeynes@359 | 2398 | LDS.L @Rm+, MACH {: |
nkeynes@359 | 2399 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2400 | check_ralign32( R_EAX ); |
nkeynes@571 | 2401 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2402 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2403 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2404 | store_spreg( R_EAX, R_MACH ); |
nkeynes@417 | 2405 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2406 | :} |
nkeynes@359 | 2407 | LDS Rm, MACL {: |
nkeynes@359 | 2408 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2409 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 2410 | :} |
nkeynes@359 | 2411 | LDS.L @Rm+, MACL {: |
nkeynes@359 | 2412 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2413 | check_ralign32( R_EAX ); |
nkeynes@571 | 2414 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2415 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2416 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2417 | store_spreg( R_EAX, R_MACL ); |
nkeynes@417 | 2418 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2419 | :} |
nkeynes@359 | 2420 | LDS Rm, PR {: |
nkeynes@359 | 2421 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 2422 | store_spreg( R_EAX, R_PR ); |
nkeynes@359 | 2423 | :} |
nkeynes@359 | 2424 | LDS.L @Rm+, PR {: |
nkeynes@359 | 2425 | load_reg( R_EAX, Rm ); |
nkeynes@395 | 2426 | check_ralign32( R_EAX ); |
nkeynes@571 | 2427 | MMU_TRANSLATE_READ( R_EAX ); |
nkeynes@571 | 2428 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@571 | 2429 | MEM_READ_LONG( R_EAX, R_EAX ); |
nkeynes@359 | 2430 | store_spreg( R_EAX, R_PR ); |
nkeynes@417 | 2431 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2432 | :} |
nkeynes@550 | 2433 | LDTLB {: |
nkeynes@553 | 2434 | call_func0( MMU_ldtlb ); |
nkeynes@550 | 2435 | :} |
nkeynes@359 | 2436 | OCBI @Rn {: :} |
nkeynes@359 | 2437 | OCBP @Rn {: :} |
nkeynes@359 | 2438 | OCBWB @Rn {: :} |
nkeynes@374 | 2439 | PREF @Rn {: |
nkeynes@374 | 2440 | load_reg( R_EAX, Rn ); |
nkeynes@532 | 2441 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 2442 | AND_imm32_r32( 0xFC000000, R_EAX ); |
nkeynes@374 | 2443 | CMP_imm32_r32( 0xE0000000, R_EAX ); |
nkeynes@577 | 2444 | JNE_rel8(8+CALL_FUNC1_SIZE, end); |
nkeynes@532 | 2445 | call_func1( sh4_flush_store_queue, R_ECX ); |
nkeynes@577 | 2446 | TEST_r32_r32( R_EAX, R_EAX ); |
nkeynes@577 | 2447 | JE_exc(-1); |
nkeynes@380 | 2448 | JMP_TARGET(end); |
nkeynes@417 | 2449 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2450 | :} |
nkeynes@388 | 2451 | SLEEP {: |
nkeynes@388 | 2452 | check_priv(); |
nkeynes@388 | 2453 | call_func0( sh4_sleep ); |
nkeynes@417 | 2454 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@388 | 2455 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@408 | 2456 | return 2; |
nkeynes@388 | 2457 | :} |
nkeynes@386 | 2458 | STC SR, Rn {: |
nkeynes@386 | 2459 | check_priv(); |
nkeynes@386 | 2460 | call_func0(sh4_read_sr); |
nkeynes@386 | 2461 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2462 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2463 | :} |
nkeynes@359 | 2464 | STC GBR, Rn {: |
nkeynes@359 | 2465 | load_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 2466 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2467 | :} |
nkeynes@359 | 2468 | STC VBR, Rn {: |
nkeynes@386 | 2469 | check_priv(); |
nkeynes@359 | 2470 | load_spreg( R_EAX, R_VBR ); |
nkeynes@359 | 2471 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2472 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2473 | :} |
nkeynes@359 | 2474 | STC SSR, Rn {: |
nkeynes@386 | 2475 | check_priv(); |
nkeynes@359 | 2476 | load_spreg( R_EAX, R_SSR ); |
nkeynes@359 | 2477 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2478 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2479 | :} |
nkeynes@359 | 2480 | STC SPC, Rn {: |
nkeynes@386 | 2481 | check_priv(); |
nkeynes@359 | 2482 | load_spreg( R_EAX, R_SPC ); |
nkeynes@359 | 2483 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2484 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2485 | :} |
nkeynes@359 | 2486 | STC SGR, Rn {: |
nkeynes@386 | 2487 | check_priv(); |
nkeynes@359 | 2488 | load_spreg( R_EAX, R_SGR ); |
nkeynes@359 | 2489 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2490 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2491 | :} |
nkeynes@359 | 2492 | STC DBR, Rn {: |
nkeynes@386 | 2493 | check_priv(); |
nkeynes@359 | 2494 | load_spreg( R_EAX, R_DBR ); |
nkeynes@359 | 2495 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2496 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2497 | :} |
nkeynes@374 | 2498 | STC Rm_BANK, Rn {: |
nkeynes@386 | 2499 | check_priv(); |
nkeynes@374 | 2500 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) ); |
nkeynes@374 | 2501 | store_reg( R_EAX, Rn ); |
nkeynes@417 | 2502 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2503 | :} |
nkeynes@374 | 2504 | STC.L SR, @-Rn {: |
nkeynes@559 | 2505 | check_priv(); |
nkeynes@571 | 2506 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2507 | check_walign32( R_EAX ); |
nkeynes@571 | 2508 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2509 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2510 | PUSH_realigned_r32( R_EAX ); |
nkeynes@395 | 2511 | call_func0( sh4_read_sr ); |
nkeynes@571 | 2512 | POP_realigned_r32( R_ECX ); |
nkeynes@571 | 2513 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@368 | 2514 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@417 | 2515 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2516 | :} |
nkeynes@359 | 2517 | STC.L VBR, @-Rn {: |
nkeynes@559 | 2518 | check_priv(); |
nkeynes@571 | 2519 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2520 | check_walign32( R_EAX ); |
nkeynes@571 | 2521 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2522 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2523 | load_spreg( R_EDX, R_VBR ); |
nkeynes@571 | 2524 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2525 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2526 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2527 | :} |
nkeynes@359 | 2528 | STC.L SSR, @-Rn {: |
nkeynes@559 | 2529 | check_priv(); |
nkeynes@571 | 2530 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2531 | check_walign32( R_EAX ); |
nkeynes@571 | 2532 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2533 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2534 | load_spreg( R_EDX, R_SSR ); |
nkeynes@571 | 2535 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2536 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2537 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2538 | :} |
nkeynes@416 | 2539 | STC.L SPC, @-Rn {: |
nkeynes@559 | 2540 | check_priv(); |
nkeynes@571 | 2541 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2542 | check_walign32( R_EAX ); |
nkeynes@571 | 2543 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2544 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2545 | load_spreg( R_EDX, R_SPC ); |
nkeynes@571 | 2546 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2547 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2548 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2549 | :} |
nkeynes@359 | 2550 | STC.L SGR, @-Rn {: |
nkeynes@559 | 2551 | check_priv(); |
nkeynes@571 | 2552 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2553 | check_walign32( R_EAX ); |
nkeynes@571 | 2554 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2555 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2556 | load_spreg( R_EDX, R_SGR ); |
nkeynes@571 | 2557 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2558 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2559 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2560 | :} |
nkeynes@359 | 2561 | STC.L DBR, @-Rn {: |
nkeynes@559 | 2562 | check_priv(); |
nkeynes@571 | 2563 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2564 | check_walign32( R_EAX ); |
nkeynes@571 | 2565 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2566 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2567 | load_spreg( R_EDX, R_DBR ); |
nkeynes@571 | 2568 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2569 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2570 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2571 | :} |
nkeynes@374 | 2572 | STC.L Rm_BANK, @-Rn {: |
nkeynes@559 | 2573 | check_priv(); |
nkeynes@571 | 2574 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2575 | check_walign32( R_EAX ); |
nkeynes@571 | 2576 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2577 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2578 | load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) ); |
nkeynes@571 | 2579 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2580 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2581 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2582 | :} |
nkeynes@359 | 2583 | STC.L GBR, @-Rn {: |
nkeynes@571 | 2584 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2585 | check_walign32( R_EAX ); |
nkeynes@571 | 2586 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2587 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2588 | load_spreg( R_EDX, R_GBR ); |
nkeynes@571 | 2589 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2590 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2591 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2592 | :} |
nkeynes@359 | 2593 | STS FPSCR, Rn {: |
nkeynes@359 | 2594 | load_spreg( R_EAX, R_FPSCR ); |
nkeynes@359 | 2595 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2596 | :} |
nkeynes@359 | 2597 | STS.L FPSCR, @-Rn {: |
nkeynes@571 | 2598 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2599 | check_walign32( R_EAX ); |
nkeynes@571 | 2600 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2601 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2602 | load_spreg( R_EDX, R_FPSCR ); |
nkeynes@571 | 2603 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2604 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2605 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2606 | :} |
nkeynes@359 | 2607 | STS FPUL, Rn {: |
nkeynes@359 | 2608 | load_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 2609 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2610 | :} |
nkeynes@359 | 2611 | STS.L FPUL, @-Rn {: |
nkeynes@571 | 2612 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2613 | check_walign32( R_EAX ); |
nkeynes@571 | 2614 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2615 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2616 | load_spreg( R_EDX, R_FPUL ); |
nkeynes@571 | 2617 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2618 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2619 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2620 | :} |
nkeynes@359 | 2621 | STS MACH, Rn {: |
nkeynes@359 | 2622 | load_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 2623 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2624 | :} |
nkeynes@359 | 2625 | STS.L MACH, @-Rn {: |
nkeynes@571 | 2626 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2627 | check_walign32( R_EAX ); |
nkeynes@571 | 2628 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2629 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2630 | load_spreg( R_EDX, R_MACH ); |
nkeynes@571 | 2631 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2632 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2633 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2634 | :} |
nkeynes@359 | 2635 | STS MACL, Rn {: |
nkeynes@359 | 2636 | load_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 2637 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2638 | :} |
nkeynes@359 | 2639 | STS.L MACL, @-Rn {: |
nkeynes@571 | 2640 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2641 | check_walign32( R_EAX ); |
nkeynes@571 | 2642 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2643 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2644 | load_spreg( R_EDX, R_MACL ); |
nkeynes@571 | 2645 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2646 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2647 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2648 | :} |
nkeynes@359 | 2649 | STS PR, Rn {: |
nkeynes@359 | 2650 | load_spreg( R_EAX, R_PR ); |
nkeynes@359 | 2651 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2652 | :} |
nkeynes@359 | 2653 | STS.L PR, @-Rn {: |
nkeynes@571 | 2654 | load_reg( R_EAX, Rn ); |
nkeynes@571 | 2655 | check_walign32( R_EAX ); |
nkeynes@571 | 2656 | ADD_imm8s_r32( -4, R_EAX ); |
nkeynes@571 | 2657 | MMU_TRANSLATE_WRITE( R_EAX ); |
nkeynes@571 | 2658 | load_spreg( R_EDX, R_PR ); |
nkeynes@571 | 2659 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@571 | 2660 | MEM_WRITE_LONG( R_EAX, R_EDX ); |
nkeynes@417 | 2661 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2662 | :} |
nkeynes@359 | 2663 | |
nkeynes@359 | 2664 | NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :} |
nkeynes@359 | 2665 | %% |
nkeynes@416 | 2666 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@359 | 2667 | return 0; |
nkeynes@359 | 2668 | } |
.