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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 569:a1c49e1e8776
prev561:533f6b478071
next570:d2893980fbf5
author nkeynes
date Fri Jan 04 11:54:17 2008 +0000 (13 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Bring icache partially into line with the mmu, a little less slow with AT off
now.
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_READ_SIZE  (CALL_FUNC1_SIZE+8)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE+8)
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SH4_TRANSLATOR == TARGET_X86_64
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#include "sh4/ia64abi.h"
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#else /* SH4_TRANSLATOR == TARGET_X86 */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
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#endif
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   333
/**
nkeynes@359
   334
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   335
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   336
 * 
nkeynes@359
   337
 *
nkeynes@359
   338
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   339
 * (eg a branch or 
nkeynes@359
   340
 */
nkeynes@526
   341
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   342
{
nkeynes@388
   343
    uint32_t ir;
nkeynes@388
   344
    /* Read instruction */
nkeynes@569
   345
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   346
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   347
    } else {
nkeynes@569
   348
	ir = sh4_read_word(pc);
nkeynes@388
   349
    }
nkeynes@359
   350
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   351
            case 0x0:
nkeynes@359
   352
                switch( ir&0xF ) {
nkeynes@359
   353
                    case 0x2:
nkeynes@359
   354
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   355
                            case 0x0:
nkeynes@359
   356
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   357
                                    case 0x0:
nkeynes@359
   358
                                        { /* STC SR, Rn */
nkeynes@359
   359
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   360
                                        check_priv();
nkeynes@374
   361
                                        call_func0(sh4_read_sr);
nkeynes@368
   362
                                        store_reg( R_EAX, Rn );
nkeynes@417
   363
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   364
                                        }
nkeynes@359
   365
                                        break;
nkeynes@359
   366
                                    case 0x1:
nkeynes@359
   367
                                        { /* STC GBR, Rn */
nkeynes@359
   368
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   369
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   370
                                        store_reg( R_EAX, Rn );
nkeynes@359
   371
                                        }
nkeynes@359
   372
                                        break;
nkeynes@359
   373
                                    case 0x2:
nkeynes@359
   374
                                        { /* STC VBR, Rn */
nkeynes@359
   375
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   376
                                        check_priv();
nkeynes@359
   377
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   378
                                        store_reg( R_EAX, Rn );
nkeynes@417
   379
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   380
                                        }
nkeynes@359
   381
                                        break;
nkeynes@359
   382
                                    case 0x3:
nkeynes@359
   383
                                        { /* STC SSR, Rn */
nkeynes@359
   384
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   385
                                        check_priv();
nkeynes@359
   386
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   387
                                        store_reg( R_EAX, Rn );
nkeynes@417
   388
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   389
                                        }
nkeynes@359
   390
                                        break;
nkeynes@359
   391
                                    case 0x4:
nkeynes@359
   392
                                        { /* STC SPC, Rn */
nkeynes@359
   393
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   394
                                        check_priv();
nkeynes@359
   395
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   396
                                        store_reg( R_EAX, Rn );
nkeynes@417
   397
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   398
                                        }
nkeynes@359
   399
                                        break;
nkeynes@359
   400
                                    default:
nkeynes@359
   401
                                        UNDEF();
nkeynes@359
   402
                                        break;
nkeynes@359
   403
                                }
nkeynes@359
   404
                                break;
nkeynes@359
   405
                            case 0x1:
nkeynes@359
   406
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   407
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   408
                                check_priv();
nkeynes@374
   409
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   410
                                store_reg( R_EAX, Rn );
nkeynes@417
   411
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   412
                                }
nkeynes@359
   413
                                break;
nkeynes@359
   414
                        }
nkeynes@359
   415
                        break;
nkeynes@359
   416
                    case 0x3:
nkeynes@359
   417
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   418
                            case 0x0:
nkeynes@359
   419
                                { /* BSRF Rn */
nkeynes@359
   420
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   421
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   422
                            	SLOTILLEGAL();
nkeynes@374
   423
                                } else {
nkeynes@408
   424
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   425
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   426
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   427
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   428
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   429
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   430
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   431
                            	exit_block_pcset(pc+2);
nkeynes@409
   432
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   433
                            	return 4;
nkeynes@374
   434
                                }
nkeynes@359
   435
                                }
nkeynes@359
   436
                                break;
nkeynes@359
   437
                            case 0x2:
nkeynes@359
   438
                                { /* BRAF Rn */
nkeynes@359
   439
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   440
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   441
                            	SLOTILLEGAL();
nkeynes@374
   442
                                } else {
nkeynes@408
   443
                            	load_reg( R_EAX, Rn );
nkeynes@408
   444
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   445
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   446
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   447
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   448
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   449
                            	exit_block_pcset(pc+2);
nkeynes@409
   450
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   451
                            	return 4;
nkeynes@374
   452
                                }
nkeynes@359
   453
                                }
nkeynes@359
   454
                                break;
nkeynes@359
   455
                            case 0x8:
nkeynes@359
   456
                                { /* PREF @Rn */
nkeynes@359
   457
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   458
                                load_reg( R_EAX, Rn );
nkeynes@532
   459
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   460
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   461
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
   462
                                JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
   463
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
   464
                                JMP_TARGET(end);
nkeynes@417
   465
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   466
                                }
nkeynes@359
   467
                                break;
nkeynes@359
   468
                            case 0x9:
nkeynes@359
   469
                                { /* OCBI @Rn */
nkeynes@359
   470
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   471
                                }
nkeynes@359
   472
                                break;
nkeynes@359
   473
                            case 0xA:
nkeynes@359
   474
                                { /* OCBP @Rn */
nkeynes@359
   475
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   476
                                }
nkeynes@359
   477
                                break;
nkeynes@359
   478
                            case 0xB:
nkeynes@359
   479
                                { /* OCBWB @Rn */
nkeynes@359
   480
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   481
                                }
nkeynes@359
   482
                                break;
nkeynes@359
   483
                            case 0xC:
nkeynes@359
   484
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   485
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   486
                                load_reg( R_EAX, 0 );
nkeynes@361
   487
                                load_reg( R_ECX, Rn );
nkeynes@374
   488
                                check_walign32( R_ECX );
nkeynes@361
   489
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   490
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   491
                                }
nkeynes@359
   492
                                break;
nkeynes@359
   493
                            default:
nkeynes@359
   494
                                UNDEF();
nkeynes@359
   495
                                break;
nkeynes@359
   496
                        }
nkeynes@359
   497
                        break;
nkeynes@359
   498
                    case 0x4:
nkeynes@359
   499
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   500
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   501
                        load_reg( R_EAX, 0 );
nkeynes@359
   502
                        load_reg( R_ECX, Rn );
nkeynes@359
   503
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   504
                        load_reg( R_EAX, Rm );
nkeynes@359
   505
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   506
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   507
                        }
nkeynes@359
   508
                        break;
nkeynes@359
   509
                    case 0x5:
nkeynes@359
   510
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   511
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   512
                        load_reg( R_EAX, 0 );
nkeynes@361
   513
                        load_reg( R_ECX, Rn );
nkeynes@361
   514
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   515
                        check_walign16( R_ECX );
nkeynes@361
   516
                        load_reg( R_EAX, Rm );
nkeynes@361
   517
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   518
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   519
                        }
nkeynes@359
   520
                        break;
nkeynes@359
   521
                    case 0x6:
nkeynes@359
   522
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   523
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   524
                        load_reg( R_EAX, 0 );
nkeynes@361
   525
                        load_reg( R_ECX, Rn );
nkeynes@361
   526
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   527
                        check_walign32( R_ECX );
nkeynes@361
   528
                        load_reg( R_EAX, Rm );
nkeynes@361
   529
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   530
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   531
                        }
nkeynes@359
   532
                        break;
nkeynes@359
   533
                    case 0x7:
nkeynes@359
   534
                        { /* MUL.L Rm, Rn */
nkeynes@359
   535
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   536
                        load_reg( R_EAX, Rm );
nkeynes@361
   537
                        load_reg( R_ECX, Rn );
nkeynes@361
   538
                        MUL_r32( R_ECX );
nkeynes@361
   539
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   540
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   541
                        }
nkeynes@359
   542
                        break;
nkeynes@359
   543
                    case 0x8:
nkeynes@359
   544
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   545
                            case 0x0:
nkeynes@359
   546
                                { /* CLRT */
nkeynes@374
   547
                                CLC();
nkeynes@374
   548
                                SETC_t();
nkeynes@417
   549
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   550
                                }
nkeynes@359
   551
                                break;
nkeynes@359
   552
                            case 0x1:
nkeynes@359
   553
                                { /* SETT */
nkeynes@374
   554
                                STC();
nkeynes@374
   555
                                SETC_t();
nkeynes@417
   556
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   557
                                }
nkeynes@359
   558
                                break;
nkeynes@359
   559
                            case 0x2:
nkeynes@359
   560
                                { /* CLRMAC */
nkeynes@374
   561
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   562
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   563
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   564
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   565
                                }
nkeynes@359
   566
                                break;
nkeynes@359
   567
                            case 0x3:
nkeynes@359
   568
                                { /* LDTLB */
nkeynes@553
   569
                                call_func0( MMU_ldtlb );
nkeynes@359
   570
                                }
nkeynes@359
   571
                                break;
nkeynes@359
   572
                            case 0x4:
nkeynes@359
   573
                                { /* CLRS */
nkeynes@374
   574
                                CLC();
nkeynes@374
   575
                                SETC_sh4r(R_S);
nkeynes@417
   576
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   577
                                }
nkeynes@359
   578
                                break;
nkeynes@359
   579
                            case 0x5:
nkeynes@359
   580
                                { /* SETS */
nkeynes@374
   581
                                STC();
nkeynes@374
   582
                                SETC_sh4r(R_S);
nkeynes@417
   583
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   584
                                }
nkeynes@359
   585
                                break;
nkeynes@359
   586
                            default:
nkeynes@359
   587
                                UNDEF();
nkeynes@359
   588
                                break;
nkeynes@359
   589
                        }
nkeynes@359
   590
                        break;
nkeynes@359
   591
                    case 0x9:
nkeynes@359
   592
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   593
                            case 0x0:
nkeynes@359
   594
                                { /* NOP */
nkeynes@359
   595
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   596
                                }
nkeynes@359
   597
                                break;
nkeynes@359
   598
                            case 0x1:
nkeynes@359
   599
                                { /* DIV0U */
nkeynes@361
   600
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   601
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   602
                                store_spreg( R_EAX, R_M );
nkeynes@361
   603
                                store_spreg( R_EAX, R_T );
nkeynes@417
   604
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   605
                                }
nkeynes@359
   606
                                break;
nkeynes@359
   607
                            case 0x2:
nkeynes@359
   608
                                { /* MOVT Rn */
nkeynes@359
   609
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   610
                                load_spreg( R_EAX, R_T );
nkeynes@359
   611
                                store_reg( R_EAX, Rn );
nkeynes@359
   612
                                }
nkeynes@359
   613
                                break;
nkeynes@359
   614
                            default:
nkeynes@359
   615
                                UNDEF();
nkeynes@359
   616
                                break;
nkeynes@359
   617
                        }
nkeynes@359
   618
                        break;
nkeynes@359
   619
                    case 0xA:
nkeynes@359
   620
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   621
                            case 0x0:
nkeynes@359
   622
                                { /* STS MACH, Rn */
nkeynes@359
   623
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   624
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   625
                                store_reg( R_EAX, Rn );
nkeynes@359
   626
                                }
nkeynes@359
   627
                                break;
nkeynes@359
   628
                            case 0x1:
nkeynes@359
   629
                                { /* STS MACL, Rn */
nkeynes@359
   630
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   631
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   632
                                store_reg( R_EAX, Rn );
nkeynes@359
   633
                                }
nkeynes@359
   634
                                break;
nkeynes@359
   635
                            case 0x2:
nkeynes@359
   636
                                { /* STS PR, Rn */
nkeynes@359
   637
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   638
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   639
                                store_reg( R_EAX, Rn );
nkeynes@359
   640
                                }
nkeynes@359
   641
                                break;
nkeynes@359
   642
                            case 0x3:
nkeynes@359
   643
                                { /* STC SGR, Rn */
nkeynes@359
   644
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   645
                                check_priv();
nkeynes@359
   646
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   647
                                store_reg( R_EAX, Rn );
nkeynes@417
   648
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   649
                                }
nkeynes@359
   650
                                break;
nkeynes@359
   651
                            case 0x5:
nkeynes@359
   652
                                { /* STS FPUL, Rn */
nkeynes@359
   653
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   654
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   655
                                store_reg( R_EAX, Rn );
nkeynes@359
   656
                                }
nkeynes@359
   657
                                break;
nkeynes@359
   658
                            case 0x6:
nkeynes@359
   659
                                { /* STS FPSCR, Rn */
nkeynes@359
   660
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   661
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   662
                                store_reg( R_EAX, Rn );
nkeynes@359
   663
                                }
nkeynes@359
   664
                                break;
nkeynes@359
   665
                            case 0xF:
nkeynes@359
   666
                                { /* STC DBR, Rn */
nkeynes@359
   667
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   668
                                check_priv();
nkeynes@359
   669
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   670
                                store_reg( R_EAX, Rn );
nkeynes@417
   671
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   672
                                }
nkeynes@359
   673
                                break;
nkeynes@359
   674
                            default:
nkeynes@359
   675
                                UNDEF();
nkeynes@359
   676
                                break;
nkeynes@359
   677
                        }
nkeynes@359
   678
                        break;
nkeynes@359
   679
                    case 0xB:
nkeynes@359
   680
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   681
                            case 0x0:
nkeynes@359
   682
                                { /* RTS */
nkeynes@374
   683
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   684
                            	SLOTILLEGAL();
nkeynes@374
   685
                                } else {
nkeynes@408
   686
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
   687
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   688
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
   689
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   690
                            	exit_block_pcset(pc+2);
nkeynes@409
   691
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   692
                            	return 4;
nkeynes@374
   693
                                }
nkeynes@359
   694
                                }
nkeynes@359
   695
                                break;
nkeynes@359
   696
                            case 0x1:
nkeynes@359
   697
                                { /* SLEEP */
nkeynes@388
   698
                                check_priv();
nkeynes@388
   699
                                call_func0( sh4_sleep );
nkeynes@417
   700
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
   701
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
   702
                                return 2;
nkeynes@359
   703
                                }
nkeynes@359
   704
                                break;
nkeynes@359
   705
                            case 0x2:
nkeynes@359
   706
                                { /* RTE */
nkeynes@374
   707
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   708
                            	SLOTILLEGAL();
nkeynes@374
   709
                                } else {
nkeynes@408
   710
                            	check_priv();
nkeynes@408
   711
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
   712
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   713
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   714
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   715
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   716
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   717
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   718
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   719
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   720
                            	exit_block_pcset(pc+2);
nkeynes@409
   721
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   722
                            	return 4;
nkeynes@374
   723
                                }
nkeynes@359
   724
                                }
nkeynes@359
   725
                                break;
nkeynes@359
   726
                            default:
nkeynes@359
   727
                                UNDEF();
nkeynes@359
   728
                                break;
nkeynes@359
   729
                        }
nkeynes@359
   730
                        break;
nkeynes@359
   731
                    case 0xC:
nkeynes@359
   732
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   733
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   734
                        load_reg( R_EAX, 0 );
nkeynes@359
   735
                        load_reg( R_ECX, Rm );
nkeynes@359
   736
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   737
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   738
                        store_reg( R_EAX, Rn );
nkeynes@417
   739
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   740
                        }
nkeynes@359
   741
                        break;
nkeynes@359
   742
                    case 0xD:
nkeynes@359
   743
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   744
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   745
                        load_reg( R_EAX, 0 );
nkeynes@361
   746
                        load_reg( R_ECX, Rm );
nkeynes@361
   747
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   748
                        check_ralign16( R_ECX );
nkeynes@361
   749
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   750
                        store_reg( R_EAX, Rn );
nkeynes@417
   751
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   752
                        }
nkeynes@359
   753
                        break;
nkeynes@359
   754
                    case 0xE:
nkeynes@359
   755
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   756
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   757
                        load_reg( R_EAX, 0 );
nkeynes@361
   758
                        load_reg( R_ECX, Rm );
nkeynes@361
   759
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   760
                        check_ralign32( R_ECX );
nkeynes@361
   761
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   762
                        store_reg( R_EAX, Rn );
nkeynes@417
   763
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   764
                        }
nkeynes@359
   765
                        break;
nkeynes@359
   766
                    case 0xF:
nkeynes@359
   767
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   768
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   769
                        load_reg( R_ECX, Rm );
nkeynes@386
   770
                        check_ralign32( R_ECX );
nkeynes@386
   771
                        load_reg( R_ECX, Rn );
nkeynes@386
   772
                        check_ralign32( R_ECX );
nkeynes@386
   773
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   774
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   775
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
   776
                        load_reg( R_ECX, Rm );
nkeynes@386
   777
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   778
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   779
                        POP_realigned_r32( R_ECX );
nkeynes@386
   780
                        IMUL_r32( R_ECX );
nkeynes@386
   781
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   782
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   783
                    
nkeynes@386
   784
                        load_spreg( R_ECX, R_S );
nkeynes@386
   785
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   786
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   787
                        call_func0( signsat48 );
nkeynes@386
   788
                        JMP_TARGET( nosat );
nkeynes@417
   789
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   790
                        }
nkeynes@359
   791
                        break;
nkeynes@359
   792
                    default:
nkeynes@359
   793
                        UNDEF();
nkeynes@359
   794
                        break;
nkeynes@359
   795
                }
nkeynes@359
   796
                break;
nkeynes@359
   797
            case 0x1:
nkeynes@359
   798
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   799
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   800
                load_reg( R_ECX, Rn );
nkeynes@361
   801
                load_reg( R_EAX, Rm );
nkeynes@361
   802
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   803
                check_walign32( R_ECX );
nkeynes@361
   804
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   805
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   806
                }
nkeynes@359
   807
                break;
nkeynes@359
   808
            case 0x2:
nkeynes@359
   809
                switch( ir&0xF ) {
nkeynes@359
   810
                    case 0x0:
nkeynes@359
   811
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   812
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   813
                        load_reg( R_EAX, Rm );
nkeynes@359
   814
                        load_reg( R_ECX, Rn );
nkeynes@359
   815
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   816
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   817
                        }
nkeynes@359
   818
                        break;
nkeynes@359
   819
                    case 0x1:
nkeynes@359
   820
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   821
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   822
                        load_reg( R_ECX, Rn );
nkeynes@374
   823
                        check_walign16( R_ECX );
nkeynes@386
   824
                        load_reg( R_EAX, Rm );
nkeynes@386
   825
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   826
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   827
                        }
nkeynes@359
   828
                        break;
nkeynes@359
   829
                    case 0x2:
nkeynes@359
   830
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   831
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   832
                        load_reg( R_EAX, Rm );
nkeynes@361
   833
                        load_reg( R_ECX, Rn );
nkeynes@374
   834
                        check_walign32(R_ECX);
nkeynes@361
   835
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   836
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   837
                        }
nkeynes@359
   838
                        break;
nkeynes@359
   839
                    case 0x4:
nkeynes@359
   840
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   841
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   842
                        load_reg( R_EAX, Rm );
nkeynes@359
   843
                        load_reg( R_ECX, Rn );
nkeynes@386
   844
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   845
                        store_reg( R_ECX, Rn );
nkeynes@359
   846
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   847
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   848
                        }
nkeynes@359
   849
                        break;
nkeynes@359
   850
                    case 0x5:
nkeynes@359
   851
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   852
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   853
                        load_reg( R_ECX, Rn );
nkeynes@374
   854
                        check_walign16( R_ECX );
nkeynes@361
   855
                        load_reg( R_EAX, Rm );
nkeynes@361
   856
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
   857
                        store_reg( R_ECX, Rn );
nkeynes@361
   858
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   859
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   860
                        }
nkeynes@359
   861
                        break;
nkeynes@359
   862
                    case 0x6:
nkeynes@359
   863
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   864
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   865
                        load_reg( R_EAX, Rm );
nkeynes@361
   866
                        load_reg( R_ECX, Rn );
nkeynes@374
   867
                        check_walign32( R_ECX );
nkeynes@361
   868
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   869
                        store_reg( R_ECX, Rn );
nkeynes@361
   870
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   871
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   872
                        }
nkeynes@359
   873
                        break;
nkeynes@359
   874
                    case 0x7:
nkeynes@359
   875
                        { /* DIV0S Rm, Rn */
nkeynes@359
   876
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   877
                        load_reg( R_EAX, Rm );
nkeynes@386
   878
                        load_reg( R_ECX, Rn );
nkeynes@361
   879
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   880
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   881
                        store_spreg( R_EAX, R_M );
nkeynes@361
   882
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   883
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   884
                        SETNE_t();
nkeynes@417
   885
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   886
                        }
nkeynes@359
   887
                        break;
nkeynes@359
   888
                    case 0x8:
nkeynes@359
   889
                        { /* TST Rm, Rn */
nkeynes@359
   890
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   891
                        load_reg( R_EAX, Rm );
nkeynes@361
   892
                        load_reg( R_ECX, Rn );
nkeynes@361
   893
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   894
                        SETE_t();
nkeynes@417
   895
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   896
                        }
nkeynes@359
   897
                        break;
nkeynes@359
   898
                    case 0x9:
nkeynes@359
   899
                        { /* AND Rm, Rn */
nkeynes@359
   900
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   901
                        load_reg( R_EAX, Rm );
nkeynes@359
   902
                        load_reg( R_ECX, Rn );
nkeynes@359
   903
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   904
                        store_reg( R_ECX, Rn );
nkeynes@417
   905
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   906
                        }
nkeynes@359
   907
                        break;
nkeynes@359
   908
                    case 0xA:
nkeynes@359
   909
                        { /* XOR Rm, Rn */
nkeynes@359
   910
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   911
                        load_reg( R_EAX, Rm );
nkeynes@359
   912
                        load_reg( R_ECX, Rn );
nkeynes@359
   913
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   914
                        store_reg( R_ECX, Rn );
nkeynes@417
   915
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   916
                        }
nkeynes@359
   917
                        break;
nkeynes@359
   918
                    case 0xB:
nkeynes@359
   919
                        { /* OR Rm, Rn */
nkeynes@359
   920
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   921
                        load_reg( R_EAX, Rm );
nkeynes@359
   922
                        load_reg( R_ECX, Rn );
nkeynes@359
   923
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   924
                        store_reg( R_ECX, Rn );
nkeynes@417
   925
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   926
                        }
nkeynes@359
   927
                        break;
nkeynes@359
   928
                    case 0xC:
nkeynes@359
   929
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   930
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   931
                        load_reg( R_EAX, Rm );
nkeynes@368
   932
                        load_reg( R_ECX, Rn );
nkeynes@368
   933
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   934
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   935
                        JE_rel8(13, target1);
nkeynes@368
   936
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   937
                        JE_rel8(9, target2);
nkeynes@368
   938
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   939
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   940
                        JE_rel8(2, target3);
nkeynes@368
   941
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   942
                        JMP_TARGET(target1);
nkeynes@380
   943
                        JMP_TARGET(target2);
nkeynes@380
   944
                        JMP_TARGET(target3);
nkeynes@368
   945
                        SETE_t();
nkeynes@417
   946
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   947
                        }
nkeynes@359
   948
                        break;
nkeynes@359
   949
                    case 0xD:
nkeynes@359
   950
                        { /* XTRCT Rm, Rn */
nkeynes@359
   951
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   952
                        load_reg( R_EAX, Rm );
nkeynes@394
   953
                        load_reg( R_ECX, Rn );
nkeynes@394
   954
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   955
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   956
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   957
                        store_reg( R_ECX, Rn );
nkeynes@417
   958
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   959
                        }
nkeynes@359
   960
                        break;
nkeynes@359
   961
                    case 0xE:
nkeynes@359
   962
                        { /* MULU.W Rm, Rn */
nkeynes@359
   963
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   964
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   965
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   966
                        MUL_r32( R_ECX );
nkeynes@374
   967
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   968
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   969
                        }
nkeynes@359
   970
                        break;
nkeynes@359
   971
                    case 0xF:
nkeynes@359
   972
                        { /* MULS.W Rm, Rn */
nkeynes@359
   973
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   974
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   975
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   976
                        MUL_r32( R_ECX );
nkeynes@374
   977
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   978
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   979
                        }
nkeynes@359
   980
                        break;
nkeynes@359
   981
                    default:
nkeynes@359
   982
                        UNDEF();
nkeynes@359
   983
                        break;
nkeynes@359
   984
                }
nkeynes@359
   985
                break;
nkeynes@359
   986
            case 0x3:
nkeynes@359
   987
                switch( ir&0xF ) {
nkeynes@359
   988
                    case 0x0:
nkeynes@359
   989
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   990
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   991
                        load_reg( R_EAX, Rm );
nkeynes@359
   992
                        load_reg( R_ECX, Rn );
nkeynes@359
   993
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
                        SETE_t();
nkeynes@417
   995
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   996
                        }
nkeynes@359
   997
                        break;
nkeynes@359
   998
                    case 0x2:
nkeynes@359
   999
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1000
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1001
                        load_reg( R_EAX, Rm );
nkeynes@359
  1002
                        load_reg( R_ECX, Rn );
nkeynes@359
  1003
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
                        SETAE_t();
nkeynes@417
  1005
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1006
                        }
nkeynes@359
  1007
                        break;
nkeynes@359
  1008
                    case 0x3:
nkeynes@359
  1009
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1010
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1011
                        load_reg( R_EAX, Rm );
nkeynes@359
  1012
                        load_reg( R_ECX, Rn );
nkeynes@359
  1013
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1014
                        SETGE_t();
nkeynes@417
  1015
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1016
                        }
nkeynes@359
  1017
                        break;
nkeynes@359
  1018
                    case 0x4:
nkeynes@359
  1019
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1020
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1021
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1022
                        load_reg( R_EAX, Rn );
nkeynes@417
  1023
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1024
                    	LDC_t();
nkeynes@417
  1025
                        }
nkeynes@386
  1026
                        RCL1_r32( R_EAX );
nkeynes@386
  1027
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1028
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1029
                        JE_rel8(5, mqequal);
nkeynes@386
  1030
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1031
                        JMP_rel8(3, end);
nkeynes@380
  1032
                        JMP_TARGET(mqequal);
nkeynes@386
  1033
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1034
                        JMP_TARGET(end);
nkeynes@386
  1035
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1036
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1037
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1038
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1039
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1040
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1041
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1042
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1043
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1044
                        }
nkeynes@359
  1045
                        break;
nkeynes@359
  1046
                    case 0x5:
nkeynes@359
  1047
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1048
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1049
                        load_reg( R_EAX, Rm );
nkeynes@361
  1050
                        load_reg( R_ECX, Rn );
nkeynes@361
  1051
                        MUL_r32(R_ECX);
nkeynes@361
  1052
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1053
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1054
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1055
                        }
nkeynes@359
  1056
                        break;
nkeynes@359
  1057
                    case 0x6:
nkeynes@359
  1058
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1059
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1060
                        load_reg( R_EAX, Rm );
nkeynes@359
  1061
                        load_reg( R_ECX, Rn );
nkeynes@359
  1062
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1063
                        SETA_t();
nkeynes@417
  1064
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1065
                        }
nkeynes@359
  1066
                        break;
nkeynes@359
  1067
                    case 0x7:
nkeynes@359
  1068
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1069
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1070
                        load_reg( R_EAX, Rm );
nkeynes@359
  1071
                        load_reg( R_ECX, Rn );
nkeynes@359
  1072
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1073
                        SETG_t();
nkeynes@417
  1074
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1075
                        }
nkeynes@359
  1076
                        break;
nkeynes@359
  1077
                    case 0x8:
nkeynes@359
  1078
                        { /* SUB Rm, Rn */
nkeynes@359
  1079
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1080
                        load_reg( R_EAX, Rm );
nkeynes@359
  1081
                        load_reg( R_ECX, Rn );
nkeynes@359
  1082
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1083
                        store_reg( R_ECX, Rn );
nkeynes@417
  1084
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1085
                        }
nkeynes@359
  1086
                        break;
nkeynes@359
  1087
                    case 0xA:
nkeynes@359
  1088
                        { /* SUBC Rm, Rn */
nkeynes@359
  1089
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1090
                        load_reg( R_EAX, Rm );
nkeynes@359
  1091
                        load_reg( R_ECX, Rn );
nkeynes@417
  1092
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1093
                    	LDC_t();
nkeynes@417
  1094
                        }
nkeynes@359
  1095
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1096
                        store_reg( R_ECX, Rn );
nkeynes@394
  1097
                        SETC_t();
nkeynes@417
  1098
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1099
                        }
nkeynes@359
  1100
                        break;
nkeynes@359
  1101
                    case 0xB:
nkeynes@359
  1102
                        { /* SUBV Rm, Rn */
nkeynes@359
  1103
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1104
                        load_reg( R_EAX, Rm );
nkeynes@359
  1105
                        load_reg( R_ECX, Rn );
nkeynes@359
  1106
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1107
                        store_reg( R_ECX, Rn );
nkeynes@359
  1108
                        SETO_t();
nkeynes@417
  1109
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1110
                        }
nkeynes@359
  1111
                        break;
nkeynes@359
  1112
                    case 0xC:
nkeynes@359
  1113
                        { /* ADD Rm, Rn */
nkeynes@359
  1114
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1115
                        load_reg( R_EAX, Rm );
nkeynes@359
  1116
                        load_reg( R_ECX, Rn );
nkeynes@359
  1117
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1118
                        store_reg( R_ECX, Rn );
nkeynes@417
  1119
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1120
                        }
nkeynes@359
  1121
                        break;
nkeynes@359
  1122
                    case 0xD:
nkeynes@359
  1123
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1124
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1125
                        load_reg( R_EAX, Rm );
nkeynes@361
  1126
                        load_reg( R_ECX, Rn );
nkeynes@361
  1127
                        IMUL_r32(R_ECX);
nkeynes@361
  1128
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1129
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1130
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
                        }
nkeynes@359
  1132
                        break;
nkeynes@359
  1133
                    case 0xE:
nkeynes@359
  1134
                        { /* ADDC Rm, Rn */
nkeynes@359
  1135
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1136
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1137
                    	LDC_t();
nkeynes@417
  1138
                        }
nkeynes@359
  1139
                        load_reg( R_EAX, Rm );
nkeynes@359
  1140
                        load_reg( R_ECX, Rn );
nkeynes@359
  1141
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1142
                        store_reg( R_ECX, Rn );
nkeynes@359
  1143
                        SETC_t();
nkeynes@417
  1144
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1145
                        }
nkeynes@359
  1146
                        break;
nkeynes@359
  1147
                    case 0xF:
nkeynes@359
  1148
                        { /* ADDV Rm, Rn */
nkeynes@359
  1149
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1150
                        load_reg( R_EAX, Rm );
nkeynes@359
  1151
                        load_reg( R_ECX, Rn );
nkeynes@359
  1152
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1153
                        store_reg( R_ECX, Rn );
nkeynes@359
  1154
                        SETO_t();
nkeynes@417
  1155
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1156
                        }
nkeynes@359
  1157
                        break;
nkeynes@359
  1158
                    default:
nkeynes@359
  1159
                        UNDEF();
nkeynes@359
  1160
                        break;
nkeynes@359
  1161
                }
nkeynes@359
  1162
                break;
nkeynes@359
  1163
            case 0x4:
nkeynes@359
  1164
                switch( ir&0xF ) {
nkeynes@359
  1165
                    case 0x0:
nkeynes@359
  1166
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1167
                            case 0x0:
nkeynes@359
  1168
                                { /* SHLL Rn */
nkeynes@359
  1169
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1170
                                load_reg( R_EAX, Rn );
nkeynes@359
  1171
                                SHL1_r32( R_EAX );
nkeynes@397
  1172
                                SETC_t();
nkeynes@359
  1173
                                store_reg( R_EAX, Rn );
nkeynes@417
  1174
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1175
                                }
nkeynes@359
  1176
                                break;
nkeynes@359
  1177
                            case 0x1:
nkeynes@359
  1178
                                { /* DT Rn */
nkeynes@359
  1179
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1180
                                load_reg( R_EAX, Rn );
nkeynes@386
  1181
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1182
                                store_reg( R_EAX, Rn );
nkeynes@359
  1183
                                SETE_t();
nkeynes@417
  1184
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1185
                                }
nkeynes@359
  1186
                                break;
nkeynes@359
  1187
                            case 0x2:
nkeynes@359
  1188
                                { /* SHAL Rn */
nkeynes@359
  1189
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1190
                                load_reg( R_EAX, Rn );
nkeynes@359
  1191
                                SHL1_r32( R_EAX );
nkeynes@397
  1192
                                SETC_t();
nkeynes@359
  1193
                                store_reg( R_EAX, Rn );
nkeynes@417
  1194
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1195
                                }
nkeynes@359
  1196
                                break;
nkeynes@359
  1197
                            default:
nkeynes@359
  1198
                                UNDEF();
nkeynes@359
  1199
                                break;
nkeynes@359
  1200
                        }
nkeynes@359
  1201
                        break;
nkeynes@359
  1202
                    case 0x1:
nkeynes@359
  1203
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1204
                            case 0x0:
nkeynes@359
  1205
                                { /* SHLR Rn */
nkeynes@359
  1206
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1207
                                load_reg( R_EAX, Rn );
nkeynes@359
  1208
                                SHR1_r32( R_EAX );
nkeynes@397
  1209
                                SETC_t();
nkeynes@359
  1210
                                store_reg( R_EAX, Rn );
nkeynes@417
  1211
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1212
                                }
nkeynes@359
  1213
                                break;
nkeynes@359
  1214
                            case 0x1:
nkeynes@359
  1215
                                { /* CMP/PZ Rn */
nkeynes@359
  1216
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1217
                                load_reg( R_EAX, Rn );
nkeynes@359
  1218
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1219
                                SETGE_t();
nkeynes@417
  1220
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1221
                                }
nkeynes@359
  1222
                                break;
nkeynes@359
  1223
                            case 0x2:
nkeynes@359
  1224
                                { /* SHAR Rn */
nkeynes@359
  1225
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1226
                                load_reg( R_EAX, Rn );
nkeynes@359
  1227
                                SAR1_r32( R_EAX );
nkeynes@397
  1228
                                SETC_t();
nkeynes@359
  1229
                                store_reg( R_EAX, Rn );
nkeynes@417
  1230
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1231
                                }
nkeynes@359
  1232
                                break;
nkeynes@359
  1233
                            default:
nkeynes@359
  1234
                                UNDEF();
nkeynes@359
  1235
                                break;
nkeynes@359
  1236
                        }
nkeynes@359
  1237
                        break;
nkeynes@359
  1238
                    case 0x2:
nkeynes@359
  1239
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1240
                            case 0x0:
nkeynes@359
  1241
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1242
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1243
                                load_reg( R_ECX, Rn );
nkeynes@395
  1244
                                check_walign32( R_ECX );
nkeynes@386
  1245
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1246
                                store_reg( R_ECX, Rn );
nkeynes@359
  1247
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1248
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1249
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1250
                                }
nkeynes@359
  1251
                                break;
nkeynes@359
  1252
                            case 0x1:
nkeynes@359
  1253
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1254
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1255
                                load_reg( R_ECX, Rn );
nkeynes@395
  1256
                                check_walign32( R_ECX );
nkeynes@386
  1257
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1258
                                store_reg( R_ECX, Rn );
nkeynes@359
  1259
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1260
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1261
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1262
                                }
nkeynes@359
  1263
                                break;
nkeynes@359
  1264
                            case 0x2:
nkeynes@359
  1265
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1266
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1267
                                load_reg( R_ECX, Rn );
nkeynes@395
  1268
                                check_walign32( R_ECX );
nkeynes@386
  1269
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1270
                                store_reg( R_ECX, Rn );
nkeynes@359
  1271
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1272
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1273
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1274
                                }
nkeynes@359
  1275
                                break;
nkeynes@359
  1276
                            case 0x3:
nkeynes@359
  1277
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1278
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1279
                                check_priv();
nkeynes@359
  1280
                                load_reg( R_ECX, Rn );
nkeynes@395
  1281
                                check_walign32( R_ECX );
nkeynes@386
  1282
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1283
                                store_reg( R_ECX, Rn );
nkeynes@359
  1284
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1285
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1286
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1287
                                }
nkeynes@359
  1288
                                break;
nkeynes@359
  1289
                            case 0x5:
nkeynes@359
  1290
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1291
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1292
                                load_reg( R_ECX, Rn );
nkeynes@395
  1293
                                check_walign32( R_ECX );
nkeynes@386
  1294
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1295
                                store_reg( R_ECX, Rn );
nkeynes@359
  1296
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1297
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1298
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1299
                                }
nkeynes@359
  1300
                                break;
nkeynes@359
  1301
                            case 0x6:
nkeynes@359
  1302
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1303
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1304
                                load_reg( R_ECX, Rn );
nkeynes@395
  1305
                                check_walign32( R_ECX );
nkeynes@386
  1306
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1307
                                store_reg( R_ECX, Rn );
nkeynes@359
  1308
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1309
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1310
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1311
                                }
nkeynes@359
  1312
                                break;
nkeynes@359
  1313
                            case 0xF:
nkeynes@359
  1314
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1315
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1316
                                check_priv();
nkeynes@359
  1317
                                load_reg( R_ECX, Rn );
nkeynes@395
  1318
                                check_walign32( R_ECX );
nkeynes@386
  1319
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1320
                                store_reg( R_ECX, Rn );
nkeynes@359
  1321
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1322
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1323
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1324
                                }
nkeynes@359
  1325
                                break;
nkeynes@359
  1326
                            default:
nkeynes@359
  1327
                                UNDEF();
nkeynes@359
  1328
                                break;
nkeynes@359
  1329
                        }
nkeynes@359
  1330
                        break;
nkeynes@359
  1331
                    case 0x3:
nkeynes@359
  1332
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1333
                            case 0x0:
nkeynes@359
  1334
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1335
                                    case 0x0:
nkeynes@359
  1336
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1337
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1338
                                        check_priv();
nkeynes@395
  1339
                                        call_func0( sh4_read_sr );
nkeynes@374
  1340
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1341
                                        check_walign32( R_ECX );
nkeynes@386
  1342
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1343
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1344
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1345
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1346
                                        }
nkeynes@359
  1347
                                        break;
nkeynes@359
  1348
                                    case 0x1:
nkeynes@359
  1349
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1350
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1351
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1352
                                        check_walign32( R_ECX );
nkeynes@386
  1353
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1354
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1355
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1356
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1357
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1358
                                        }
nkeynes@359
  1359
                                        break;
nkeynes@359
  1360
                                    case 0x2:
nkeynes@359
  1361
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1362
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1363
                                        check_priv();
nkeynes@359
  1364
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1365
                                        check_walign32( R_ECX );
nkeynes@386
  1366
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1367
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1368
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1369
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1370
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1371
                                        }
nkeynes@359
  1372
                                        break;
nkeynes@359
  1373
                                    case 0x3:
nkeynes@359
  1374
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1375
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1376
                                        check_priv();
nkeynes@359
  1377
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1378
                                        check_walign32( R_ECX );
nkeynes@386
  1379
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1380
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1381
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1382
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1383
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1384
                                        }
nkeynes@359
  1385
                                        break;
nkeynes@359
  1386
                                    case 0x4:
nkeynes@359
  1387
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1388
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1389
                                        check_priv();
nkeynes@359
  1390
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1391
                                        check_walign32( R_ECX );
nkeynes@386
  1392
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1393
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1394
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1395
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1396
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1397
                                        }
nkeynes@359
  1398
                                        break;
nkeynes@359
  1399
                                    default:
nkeynes@359
  1400
                                        UNDEF();
nkeynes@359
  1401
                                        break;
nkeynes@359
  1402
                                }
nkeynes@359
  1403
                                break;
nkeynes@359
  1404
                            case 0x1:
nkeynes@359
  1405
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1406
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1407
                                check_priv();
nkeynes@374
  1408
                                load_reg( R_ECX, Rn );
nkeynes@395
  1409
                                check_walign32( R_ECX );
nkeynes@386
  1410
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1411
                                store_reg( R_ECX, Rn );
nkeynes@374
  1412
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1413
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1414
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1415
                                }
nkeynes@359
  1416
                                break;
nkeynes@359
  1417
                        }
nkeynes@359
  1418
                        break;
nkeynes@359
  1419
                    case 0x4:
nkeynes@359
  1420
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1421
                            case 0x0:
nkeynes@359
  1422
                                { /* ROTL Rn */
nkeynes@359
  1423
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1424
                                load_reg( R_EAX, Rn );
nkeynes@359
  1425
                                ROL1_r32( R_EAX );
nkeynes@359
  1426
                                store_reg( R_EAX, Rn );
nkeynes@359
  1427
                                SETC_t();
nkeynes@417
  1428
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1429
                                }
nkeynes@359
  1430
                                break;
nkeynes@359
  1431
                            case 0x2:
nkeynes@359
  1432
                                { /* ROTCL Rn */
nkeynes@359
  1433
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1434
                                load_reg( R_EAX, Rn );
nkeynes@417
  1435
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1436
                            	LDC_t();
nkeynes@417
  1437
                                }
nkeynes@359
  1438
                                RCL1_r32( R_EAX );
nkeynes@359
  1439
                                store_reg( R_EAX, Rn );
nkeynes@359
  1440
                                SETC_t();
nkeynes@417
  1441
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1442
                                }
nkeynes@359
  1443
                                break;
nkeynes@359
  1444
                            default:
nkeynes@359
  1445
                                UNDEF();
nkeynes@359
  1446
                                break;
nkeynes@359
  1447
                        }
nkeynes@359
  1448
                        break;
nkeynes@359
  1449
                    case 0x5:
nkeynes@359
  1450
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1451
                            case 0x0:
nkeynes@359
  1452
                                { /* ROTR Rn */
nkeynes@359
  1453
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1454
                                load_reg( R_EAX, Rn );
nkeynes@359
  1455
                                ROR1_r32( R_EAX );
nkeynes@359
  1456
                                store_reg( R_EAX, Rn );
nkeynes@359
  1457
                                SETC_t();
nkeynes@417
  1458
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1459
                                }
nkeynes@359
  1460
                                break;
nkeynes@359
  1461
                            case 0x1:
nkeynes@359
  1462
                                { /* CMP/PL Rn */
nkeynes@359
  1463
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1464
                                load_reg( R_EAX, Rn );
nkeynes@359
  1465
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1466
                                SETG_t();
nkeynes@417
  1467
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1468
                                }
nkeynes@359
  1469
                                break;
nkeynes@359
  1470
                            case 0x2:
nkeynes@359
  1471
                                { /* ROTCR Rn */
nkeynes@359
  1472
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1473
                                load_reg( R_EAX, Rn );
nkeynes@417
  1474
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1475
                            	LDC_t();
nkeynes@417
  1476
                                }
nkeynes@359
  1477
                                RCR1_r32( R_EAX );
nkeynes@359
  1478
                                store_reg( R_EAX, Rn );
nkeynes@359
  1479
                                SETC_t();
nkeynes@417
  1480
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1481
                                }
nkeynes@359
  1482
                                break;
nkeynes@359
  1483
                            default:
nkeynes@359
  1484
                                UNDEF();
nkeynes@359
  1485
                                break;
nkeynes@359
  1486
                        }
nkeynes@359
  1487
                        break;
nkeynes@359
  1488
                    case 0x6:
nkeynes@359
  1489
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1490
                            case 0x0:
nkeynes@359
  1491
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1492
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1493
                                load_reg( R_EAX, Rm );
nkeynes@395
  1494
                                check_ralign32( R_EAX );
nkeynes@359
  1495
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1496
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1497
                                store_reg( R_EAX, Rm );
nkeynes@359
  1498
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1499
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1500
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1501
                                }
nkeynes@359
  1502
                                break;
nkeynes@359
  1503
                            case 0x1:
nkeynes@359
  1504
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1505
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1506
                                load_reg( R_EAX, Rm );
nkeynes@395
  1507
                                check_ralign32( R_EAX );
nkeynes@359
  1508
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1509
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1510
                                store_reg( R_EAX, Rm );
nkeynes@359
  1511
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1512
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1513
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1514
                                }
nkeynes@359
  1515
                                break;
nkeynes@359
  1516
                            case 0x2:
nkeynes@359
  1517
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1518
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1519
                                load_reg( R_EAX, Rm );
nkeynes@395
  1520
                                check_ralign32( R_EAX );
nkeynes@359
  1521
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1522
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1523
                                store_reg( R_EAX, Rm );
nkeynes@359
  1524
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1525
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1526
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1527
                                }
nkeynes@359
  1528
                                break;
nkeynes@359
  1529
                            case 0x3:
nkeynes@359
  1530
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1531
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1532
                                check_priv();
nkeynes@359
  1533
                                load_reg( R_EAX, Rm );
nkeynes@395
  1534
                                check_ralign32( R_EAX );
nkeynes@359
  1535
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1536
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1537
                                store_reg( R_EAX, Rm );
nkeynes@359
  1538
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1539
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1540
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1541
                                }
nkeynes@359
  1542
                                break;
nkeynes@359
  1543
                            case 0x5:
nkeynes@359
  1544
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1545
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1546
                                load_reg( R_EAX, Rm );
nkeynes@395
  1547
                                check_ralign32( R_EAX );
nkeynes@359
  1548
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1549
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1550
                                store_reg( R_EAX, Rm );
nkeynes@359
  1551
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1552
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1553
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1554
                                }
nkeynes@359
  1555
                                break;
nkeynes@359
  1556
                            case 0x6:
nkeynes@359
  1557
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1558
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1559
                                load_reg( R_EAX, Rm );
nkeynes@395
  1560
                                check_ralign32( R_EAX );
nkeynes@359
  1561
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1562
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1563
                                store_reg( R_EAX, Rm );
nkeynes@359
  1564
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1565
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1566
                                update_fr_bank( R_EAX );
nkeynes@417
  1567
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1568
                                }
nkeynes@359
  1569
                                break;
nkeynes@359
  1570
                            case 0xF:
nkeynes@359
  1571
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1572
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1573
                                check_priv();
nkeynes@359
  1574
                                load_reg( R_EAX, Rm );
nkeynes@395
  1575
                                check_ralign32( R_EAX );
nkeynes@359
  1576
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1577
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1578
                                store_reg( R_EAX, Rm );
nkeynes@359
  1579
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1580
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1581
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1582
                                }
nkeynes@359
  1583
                                break;
nkeynes@359
  1584
                            default:
nkeynes@359
  1585
                                UNDEF();
nkeynes@359
  1586
                                break;
nkeynes@359
  1587
                        }
nkeynes@359
  1588
                        break;
nkeynes@359
  1589
                    case 0x7:
nkeynes@359
  1590
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1591
                            case 0x0:
nkeynes@359
  1592
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1593
                                    case 0x0:
nkeynes@359
  1594
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1595
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1596
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1597
                                    	SLOTILLEGAL();
nkeynes@386
  1598
                                        } else {
nkeynes@559
  1599
                                    	check_priv();
nkeynes@386
  1600
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1601
                                    	check_ralign32( R_EAX );
nkeynes@386
  1602
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1603
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1604
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1605
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1606
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1607
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1608
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1609
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1610
                                        }
nkeynes@359
  1611
                                        }
nkeynes@359
  1612
                                        break;
nkeynes@359
  1613
                                    case 0x1:
nkeynes@359
  1614
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1615
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1616
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1617
                                        check_ralign32( R_EAX );
nkeynes@359
  1618
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1619
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1620
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1621
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1622
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1623
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1624
                                        }
nkeynes@359
  1625
                                        break;
nkeynes@359
  1626
                                    case 0x2:
nkeynes@359
  1627
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1628
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1629
                                        check_priv();
nkeynes@359
  1630
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1631
                                        check_ralign32( R_EAX );
nkeynes@359
  1632
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1633
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1634
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1635
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1636
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1637
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1638
                                        }
nkeynes@359
  1639
                                        break;
nkeynes@359
  1640
                                    case 0x3:
nkeynes@359
  1641
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1642
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1643
                                        check_priv();
nkeynes@359
  1644
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1645
                                        check_ralign32( R_EAX );
nkeynes@359
  1646
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1647
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1648
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1649
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1650
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1651
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1652
                                        }
nkeynes@359
  1653
                                        break;
nkeynes@359
  1654
                                    case 0x4:
nkeynes@359
  1655
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1656
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1657
                                        check_priv();
nkeynes@359
  1658
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1659
                                        check_ralign32( R_EAX );
nkeynes@359
  1660
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1661
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1662
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1663
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1664
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1665
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1666
                                        }
nkeynes@359
  1667
                                        break;
nkeynes@359
  1668
                                    default:
nkeynes@359
  1669
                                        UNDEF();
nkeynes@359
  1670
                                        break;
nkeynes@359
  1671
                                }
nkeynes@359
  1672
                                break;
nkeynes@359
  1673
                            case 0x1:
nkeynes@359
  1674
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1675
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1676
                                check_priv();
nkeynes@374
  1677
                                load_reg( R_EAX, Rm );
nkeynes@395
  1678
                                check_ralign32( R_EAX );
nkeynes@374
  1679
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1680
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1681
                                store_reg( R_EAX, Rm );
nkeynes@374
  1682
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1683
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1684
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1685
                                }
nkeynes@359
  1686
                                break;
nkeynes@359
  1687
                        }
nkeynes@359
  1688
                        break;
nkeynes@359
  1689
                    case 0x8:
nkeynes@359
  1690
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1691
                            case 0x0:
nkeynes@359
  1692
                                { /* SHLL2 Rn */
nkeynes@359
  1693
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1694
                                load_reg( R_EAX, Rn );
nkeynes@359
  1695
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1696
                                store_reg( R_EAX, Rn );
nkeynes@417
  1697
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1698
                                }
nkeynes@359
  1699
                                break;
nkeynes@359
  1700
                            case 0x1:
nkeynes@359
  1701
                                { /* SHLL8 Rn */
nkeynes@359
  1702
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1703
                                load_reg( R_EAX, Rn );
nkeynes@359
  1704
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1705
                                store_reg( R_EAX, Rn );
nkeynes@417
  1706
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1707
                                }
nkeynes@359
  1708
                                break;
nkeynes@359
  1709
                            case 0x2:
nkeynes@359
  1710
                                { /* SHLL16 Rn */
nkeynes@359
  1711
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1712
                                load_reg( R_EAX, Rn );
nkeynes@359
  1713
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1714
                                store_reg( R_EAX, Rn );
nkeynes@417
  1715
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1716
                                }
nkeynes@359
  1717
                                break;
nkeynes@359
  1718
                            default:
nkeynes@359
  1719
                                UNDEF();
nkeynes@359
  1720
                                break;
nkeynes@359
  1721
                        }
nkeynes@359
  1722
                        break;
nkeynes@359
  1723
                    case 0x9:
nkeynes@359
  1724
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1725
                            case 0x0:
nkeynes@359
  1726
                                { /* SHLR2 Rn */
nkeynes@359
  1727
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1728
                                load_reg( R_EAX, Rn );
nkeynes@359
  1729
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1730
                                store_reg( R_EAX, Rn );
nkeynes@417
  1731
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1732
                                }
nkeynes@359
  1733
                                break;
nkeynes@359
  1734
                            case 0x1:
nkeynes@359
  1735
                                { /* SHLR8 Rn */
nkeynes@359
  1736
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1737
                                load_reg( R_EAX, Rn );
nkeynes@359
  1738
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1739
                                store_reg( R_EAX, Rn );
nkeynes@417
  1740
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1741
                                }
nkeynes@359
  1742
                                break;
nkeynes@359
  1743
                            case 0x2:
nkeynes@359
  1744
                                { /* SHLR16 Rn */
nkeynes@359
  1745
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1746
                                load_reg( R_EAX, Rn );
nkeynes@359
  1747
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1748
                                store_reg( R_EAX, Rn );
nkeynes@417
  1749
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1750
                                }
nkeynes@359
  1751
                                break;
nkeynes@359
  1752
                            default:
nkeynes@359
  1753
                                UNDEF();
nkeynes@359
  1754
                                break;
nkeynes@359
  1755
                        }
nkeynes@359
  1756
                        break;
nkeynes@359
  1757
                    case 0xA:
nkeynes@359
  1758
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1759
                            case 0x0:
nkeynes@359
  1760
                                { /* LDS Rm, MACH */
nkeynes@359
  1761
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1762
                                load_reg( R_EAX, Rm );
nkeynes@359
  1763
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1764
                                }
nkeynes@359
  1765
                                break;
nkeynes@359
  1766
                            case 0x1:
nkeynes@359
  1767
                                { /* LDS Rm, MACL */
nkeynes@359
  1768
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1769
                                load_reg( R_EAX, Rm );
nkeynes@359
  1770
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1771
                                }
nkeynes@359
  1772
                                break;
nkeynes@359
  1773
                            case 0x2:
nkeynes@359
  1774
                                { /* LDS Rm, PR */
nkeynes@359
  1775
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1776
                                load_reg( R_EAX, Rm );
nkeynes@359
  1777
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1778
                                }
nkeynes@359
  1779
                                break;
nkeynes@359
  1780
                            case 0x3:
nkeynes@359
  1781
                                { /* LDC Rm, SGR */
nkeynes@359
  1782
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1783
                                check_priv();
nkeynes@359
  1784
                                load_reg( R_EAX, Rm );
nkeynes@359
  1785
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1786
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1787
                                }
nkeynes@359
  1788
                                break;
nkeynes@359
  1789
                            case 0x5:
nkeynes@359
  1790
                                { /* LDS Rm, FPUL */
nkeynes@359
  1791
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1792
                                load_reg( R_EAX, Rm );
nkeynes@359
  1793
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1794
                                }
nkeynes@359
  1795
                                break;
nkeynes@359
  1796
                            case 0x6:
nkeynes@359
  1797
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1798
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1799
                                load_reg( R_EAX, Rm );
nkeynes@359
  1800
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1801
                                update_fr_bank( R_EAX );
nkeynes@417
  1802
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1803
                                }
nkeynes@359
  1804
                                break;
nkeynes@359
  1805
                            case 0xF:
nkeynes@359
  1806
                                { /* LDC Rm, DBR */
nkeynes@359
  1807
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1808
                                check_priv();
nkeynes@359
  1809
                                load_reg( R_EAX, Rm );
nkeynes@359
  1810
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1811
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1812
                                }
nkeynes@359
  1813
                                break;
nkeynes@359
  1814
                            default:
nkeynes@359
  1815
                                UNDEF();
nkeynes@359
  1816
                                break;
nkeynes@359
  1817
                        }
nkeynes@359
  1818
                        break;
nkeynes@359
  1819
                    case 0xB:
nkeynes@359
  1820
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1821
                            case 0x0:
nkeynes@359
  1822
                                { /* JSR @Rn */
nkeynes@359
  1823
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1824
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1825
                            	SLOTILLEGAL();
nkeynes@374
  1826
                                } else {
nkeynes@374
  1827
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1828
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1829
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1830
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1831
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1832
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1833
                            	exit_block_pcset(pc+2);
nkeynes@409
  1834
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1835
                            	return 4;
nkeynes@374
  1836
                                }
nkeynes@359
  1837
                                }
nkeynes@359
  1838
                                break;
nkeynes@359
  1839
                            case 0x1:
nkeynes@359
  1840
                                { /* TAS.B @Rn */
nkeynes@359
  1841
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1842
                                load_reg( R_ECX, Rn );
nkeynes@361
  1843
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1844
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1845
                                SETE_t();
nkeynes@361
  1846
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1847
                                load_reg( R_ECX, Rn );
nkeynes@361
  1848
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1849
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1850
                                }
nkeynes@359
  1851
                                break;
nkeynes@359
  1852
                            case 0x2:
nkeynes@359
  1853
                                { /* JMP @Rn */
nkeynes@359
  1854
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1855
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1856
                            	SLOTILLEGAL();
nkeynes@374
  1857
                                } else {
nkeynes@408
  1858
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1859
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1860
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1861
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1862
                            	exit_block_pcset(pc+2);
nkeynes@409
  1863
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1864
                            	return 4;
nkeynes@374
  1865
                                }
nkeynes@359
  1866
                                }
nkeynes@359
  1867
                                break;
nkeynes@359
  1868
                            default:
nkeynes@359
  1869
                                UNDEF();
nkeynes@359
  1870
                                break;
nkeynes@359
  1871
                        }
nkeynes@359
  1872
                        break;
nkeynes@359
  1873
                    case 0xC:
nkeynes@359
  1874
                        { /* SHAD Rm, Rn */
nkeynes@359
  1875
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1876
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1877
                        load_reg( R_EAX, Rn );
nkeynes@361
  1878
                        load_reg( R_ECX, Rm );
nkeynes@361
  1879
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1880
                        JGE_rel8(16, doshl);
nkeynes@361
  1881
                                        
nkeynes@361
  1882
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1883
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1884
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1885
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1886
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1887
                    
nkeynes@386
  1888
                        JMP_TARGET(emptysar);
nkeynes@386
  1889
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1890
                        JMP_rel8(5, end2);
nkeynes@386
  1891
                    
nkeynes@380
  1892
                        JMP_TARGET(doshl);
nkeynes@361
  1893
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1894
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1895
                        JMP_TARGET(end);
nkeynes@386
  1896
                        JMP_TARGET(end2);
nkeynes@361
  1897
                        store_reg( R_EAX, Rn );
nkeynes@417
  1898
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1899
                        }
nkeynes@359
  1900
                        break;
nkeynes@359
  1901
                    case 0xD:
nkeynes@359
  1902
                        { /* SHLD Rm, Rn */
nkeynes@359
  1903
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1904
                        load_reg( R_EAX, Rn );
nkeynes@368
  1905
                        load_reg( R_ECX, Rm );
nkeynes@386
  1906
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1907
                        JGE_rel8(15, doshl);
nkeynes@368
  1908
                    
nkeynes@386
  1909
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1910
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1911
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1912
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1913
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1914
                    
nkeynes@386
  1915
                        JMP_TARGET(emptyshr);
nkeynes@386
  1916
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1917
                        JMP_rel8(5, end2);
nkeynes@386
  1918
                    
nkeynes@386
  1919
                        JMP_TARGET(doshl);
nkeynes@386
  1920
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1921
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1922
                        JMP_TARGET(end);
nkeynes@386
  1923
                        JMP_TARGET(end2);
nkeynes@368
  1924
                        store_reg( R_EAX, Rn );
nkeynes@417
  1925
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1926
                        }
nkeynes@359
  1927
                        break;
nkeynes@359
  1928
                    case 0xE:
nkeynes@359
  1929
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1930
                            case 0x0:
nkeynes@359
  1931
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1932
                                    case 0x0:
nkeynes@359
  1933
                                        { /* LDC Rm, SR */
nkeynes@359
  1934
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1935
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1936
                                    	SLOTILLEGAL();
nkeynes@386
  1937
                                        } else {
nkeynes@386
  1938
                                    	check_priv();
nkeynes@386
  1939
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1940
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1941
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1942
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1943
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1944
                                        }
nkeynes@359
  1945
                                        }
nkeynes@359
  1946
                                        break;
nkeynes@359
  1947
                                    case 0x1:
nkeynes@359
  1948
                                        { /* LDC Rm, GBR */
nkeynes@359
  1949
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1950
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1951
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1952
                                        }
nkeynes@359
  1953
                                        break;
nkeynes@359
  1954
                                    case 0x2:
nkeynes@359
  1955
                                        { /* LDC Rm, VBR */
nkeynes@359
  1956
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1957
                                        check_priv();
nkeynes@359
  1958
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1959
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1960
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1961
                                        }
nkeynes@359
  1962
                                        break;
nkeynes@359
  1963
                                    case 0x3:
nkeynes@359
  1964
                                        { /* LDC Rm, SSR */
nkeynes@359
  1965
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1966
                                        check_priv();
nkeynes@359
  1967
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1968
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1969
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1970
                                        }
nkeynes@359
  1971
                                        break;
nkeynes@359
  1972
                                    case 0x4:
nkeynes@359
  1973
                                        { /* LDC Rm, SPC */
nkeynes@359
  1974
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1975
                                        check_priv();
nkeynes@359
  1976
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1977
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1978
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1979
                                        }
nkeynes@359
  1980
                                        break;
nkeynes@359
  1981
                                    default:
nkeynes@359
  1982
                                        UNDEF();
nkeynes@359
  1983
                                        break;
nkeynes@359
  1984
                                }
nkeynes@359
  1985
                                break;
nkeynes@359
  1986
                            case 0x1:
nkeynes@359
  1987
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1988
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1989
                                check_priv();
nkeynes@374
  1990
                                load_reg( R_EAX, Rm );
nkeynes@374
  1991
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1992
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1993
                                }
nkeynes@359
  1994
                                break;
nkeynes@359
  1995
                        }
nkeynes@359
  1996
                        break;
nkeynes@359
  1997
                    case 0xF:
nkeynes@359
  1998
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1999
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  2000
                        load_reg( R_ECX, Rm );
nkeynes@386
  2001
                        check_ralign16( R_ECX );
nkeynes@386
  2002
                        load_reg( R_ECX, Rn );
nkeynes@386
  2003
                        check_ralign16( R_ECX );
nkeynes@386
  2004
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  2005
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2006
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
  2007
                        load_reg( R_ECX, Rm );
nkeynes@386
  2008
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  2009
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2010
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2011
                        IMUL_r32( R_ECX );
nkeynes@386
  2012
                    
nkeynes@386
  2013
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2014
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2015
                        JE_rel8( 47, nosat );
nkeynes@386
  2016
                    
nkeynes@386
  2017
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2018
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2019
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2020
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2021
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2022
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2023
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2024
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2025
                    
nkeynes@386
  2026
                        JMP_TARGET(positive);
nkeynes@386
  2027
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2028
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2029
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2030
                    
nkeynes@386
  2031
                        JMP_TARGET(nosat);
nkeynes@386
  2032
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2033
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2034
                        JMP_TARGET(end);
nkeynes@386
  2035
                        JMP_TARGET(end2);
nkeynes@386
  2036
                        JMP_TARGET(end3);
nkeynes@417
  2037
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2038
                        }
nkeynes@359
  2039
                        break;
nkeynes@359
  2040
                }
nkeynes@359
  2041
                break;
nkeynes@359
  2042
            case 0x5:
nkeynes@359
  2043
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2044
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2045
                load_reg( R_ECX, Rm );
nkeynes@361
  2046
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  2047
                check_ralign32( R_ECX );
nkeynes@361
  2048
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2049
                store_reg( R_EAX, Rn );
nkeynes@417
  2050
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2051
                }
nkeynes@359
  2052
                break;
nkeynes@359
  2053
            case 0x6:
nkeynes@359
  2054
                switch( ir&0xF ) {
nkeynes@359
  2055
                    case 0x0:
nkeynes@359
  2056
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2057
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2058
                        load_reg( R_ECX, Rm );
nkeynes@359
  2059
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2060
                        store_reg( R_EAX, Rn );
nkeynes@417
  2061
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2062
                        }
nkeynes@359
  2063
                        break;
nkeynes@359
  2064
                    case 0x1:
nkeynes@359
  2065
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2066
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2067
                        load_reg( R_ECX, Rm );
nkeynes@374
  2068
                        check_ralign16( R_ECX );
nkeynes@361
  2069
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2070
                        store_reg( R_EAX, Rn );
nkeynes@417
  2071
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2072
                        }
nkeynes@359
  2073
                        break;
nkeynes@359
  2074
                    case 0x2:
nkeynes@359
  2075
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2076
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2077
                        load_reg( R_ECX, Rm );
nkeynes@374
  2078
                        check_ralign32( R_ECX );
nkeynes@361
  2079
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2080
                        store_reg( R_EAX, Rn );
nkeynes@417
  2081
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2082
                        }
nkeynes@359
  2083
                        break;
nkeynes@359
  2084
                    case 0x3:
nkeynes@359
  2085
                        { /* MOV Rm, Rn */
nkeynes@359
  2086
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2087
                        load_reg( R_EAX, Rm );
nkeynes@359
  2088
                        store_reg( R_EAX, Rn );
nkeynes@359
  2089
                        }
nkeynes@359
  2090
                        break;
nkeynes@359
  2091
                    case 0x4:
nkeynes@359
  2092
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2093
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2094
                        load_reg( R_ECX, Rm );
nkeynes@359
  2095
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2096
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2097
                        store_reg( R_EAX, Rm );
nkeynes@359
  2098
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2099
                        store_reg( R_EAX, Rn );
nkeynes@417
  2100
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2101
                        }
nkeynes@359
  2102
                        break;
nkeynes@359
  2103
                    case 0x5:
nkeynes@359
  2104
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2105
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2106
                        load_reg( R_EAX, Rm );
nkeynes@374
  2107
                        check_ralign16( R_EAX );
nkeynes@361
  2108
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2109
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2110
                        store_reg( R_EAX, Rm );
nkeynes@361
  2111
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2112
                        store_reg( R_EAX, Rn );
nkeynes@417
  2113
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2114
                        }
nkeynes@359
  2115
                        break;
nkeynes@359
  2116
                    case 0x6:
nkeynes@359
  2117
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2118
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2119
                        load_reg( R_EAX, Rm );
nkeynes@386
  2120
                        check_ralign32( R_EAX );
nkeynes@361
  2121
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2122
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2123
                        store_reg( R_EAX, Rm );
nkeynes@361
  2124
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2125
                        store_reg( R_EAX, Rn );
nkeynes@417
  2126
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2127
                        }
nkeynes@359
  2128
                        break;
nkeynes@359
  2129
                    case 0x7:
nkeynes@359
  2130
                        { /* NOT Rm, Rn */
nkeynes@359
  2131
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2132
                        load_reg( R_EAX, Rm );
nkeynes@359
  2133
                        NOT_r32( R_EAX );
nkeynes@359
  2134
                        store_reg( R_EAX, Rn );
nkeynes@417
  2135
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2136
                        }
nkeynes@359
  2137
                        break;
nkeynes@359
  2138
                    case 0x8:
nkeynes@359
  2139
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2140
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2141
                        load_reg( R_EAX, Rm );
nkeynes@359
  2142
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2143
                        store_reg( R_EAX, Rn );
nkeynes@359
  2144
                        }
nkeynes@359
  2145
                        break;
nkeynes@359
  2146
                    case 0x9:
nkeynes@359
  2147
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2148
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2149
                        load_reg( R_EAX, Rm );
nkeynes@359
  2150
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2151
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2152
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2153
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2154
                        store_reg( R_ECX, Rn );
nkeynes@417
  2155
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2156
                        }
nkeynes@359
  2157
                        break;
nkeynes@359
  2158
                    case 0xA:
nkeynes@359
  2159
                        { /* NEGC Rm, Rn */
nkeynes@359
  2160
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2161
                        load_reg( R_EAX, Rm );
nkeynes@359
  2162
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2163
                        LDC_t();
nkeynes@359
  2164
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2165
                        store_reg( R_ECX, Rn );
nkeynes@359
  2166
                        SETC_t();
nkeynes@417
  2167
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2168
                        }
nkeynes@359
  2169
                        break;
nkeynes@359
  2170
                    case 0xB:
nkeynes@359
  2171
                        { /* NEG Rm, Rn */
nkeynes@359
  2172
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2173
                        load_reg( R_EAX, Rm );
nkeynes@359
  2174
                        NEG_r32( R_EAX );
nkeynes@359
  2175
                        store_reg( R_EAX, Rn );
nkeynes@417
  2176
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2177
                        }
nkeynes@359
  2178
                        break;
nkeynes@359
  2179
                    case 0xC:
nkeynes@359
  2180
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2181
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2182
                        load_reg( R_EAX, Rm );
nkeynes@361
  2183
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2184
                        store_reg( R_EAX, Rn );
nkeynes@359
  2185
                        }
nkeynes@359
  2186
                        break;
nkeynes@359
  2187
                    case 0xD:
nkeynes@359
  2188
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2189
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2190
                        load_reg( R_EAX, Rm );
nkeynes@361
  2191
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2192
                        store_reg( R_EAX, Rn );
nkeynes@359
  2193
                        }
nkeynes@359
  2194
                        break;
nkeynes@359
  2195
                    case 0xE:
nkeynes@359
  2196
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2197
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2198
                        load_reg( R_EAX, Rm );
nkeynes@359
  2199
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2200
                        store_reg( R_EAX, Rn );
nkeynes@359
  2201
                        }
nkeynes@359
  2202
                        break;
nkeynes@359
  2203
                    case 0xF:
nkeynes@359
  2204
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2205
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2206
                        load_reg( R_EAX, Rm );
nkeynes@361
  2207
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2208
                        store_reg( R_EAX, Rn );
nkeynes@359
  2209
                        }
nkeynes@359
  2210
                        break;
nkeynes@359
  2211
                }
nkeynes@359
  2212
                break;
nkeynes@359
  2213
            case 0x7:
nkeynes@359
  2214
                { /* ADD #imm, Rn */
nkeynes@359
  2215
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2216
                load_reg( R_EAX, Rn );
nkeynes@359
  2217
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2218
                store_reg( R_EAX, Rn );
nkeynes@417
  2219
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2220
                }
nkeynes@359
  2221
                break;
nkeynes@359
  2222
            case 0x8:
nkeynes@359
  2223
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2224
                    case 0x0:
nkeynes@359
  2225
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2226
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2227
                        load_reg( R_EAX, 0 );
nkeynes@359
  2228
                        load_reg( R_ECX, Rn );
nkeynes@359
  2229
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2230
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2231
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2232
                        }
nkeynes@359
  2233
                        break;
nkeynes@359
  2234
                    case 0x1:
nkeynes@359
  2235
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2236
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2237
                        load_reg( R_ECX, Rn );
nkeynes@361
  2238
                        load_reg( R_EAX, 0 );
nkeynes@361
  2239
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2240
                        check_walign16( R_ECX );
nkeynes@361
  2241
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2242
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2243
                        }
nkeynes@359
  2244
                        break;
nkeynes@359
  2245
                    case 0x4:
nkeynes@359
  2246
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2247
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2248
                        load_reg( R_ECX, Rm );
nkeynes@359
  2249
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2250
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2251
                        store_reg( R_EAX, 0 );
nkeynes@417
  2252
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2253
                        }
nkeynes@359
  2254
                        break;
nkeynes@359
  2255
                    case 0x5:
nkeynes@359
  2256
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2257
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2258
                        load_reg( R_ECX, Rm );
nkeynes@361
  2259
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2260
                        check_ralign16( R_ECX );
nkeynes@361
  2261
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2262
                        store_reg( R_EAX, 0 );
nkeynes@417
  2263
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2264
                        }
nkeynes@359
  2265
                        break;
nkeynes@359
  2266
                    case 0x8:
nkeynes@359
  2267
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2268
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2269
                        load_reg( R_EAX, 0 );
nkeynes@359
  2270
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2271
                        SETE_t();
nkeynes@417
  2272
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2273
                        }
nkeynes@359
  2274
                        break;
nkeynes@359
  2275
                    case 0x9:
nkeynes@359
  2276
                        { /* BT disp */
nkeynes@359
  2277
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2278
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2279
                    	SLOTILLEGAL();
nkeynes@374
  2280
                        } else {
nkeynes@527
  2281
                    	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2282
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2283
                    	JMP_TARGET(nottaken);
nkeynes@408
  2284
                    	return 2;
nkeynes@374
  2285
                        }
nkeynes@359
  2286
                        }
nkeynes@359
  2287
                        break;
nkeynes@359
  2288
                    case 0xB:
nkeynes@359
  2289
                        { /* BF disp */
nkeynes@359
  2290
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2291
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2292
                    	SLOTILLEGAL();
nkeynes@374
  2293
                        } else {
nkeynes@527
  2294
                    	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2295
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2296
                    	JMP_TARGET(nottaken);
nkeynes@408
  2297
                    	return 2;
nkeynes@374
  2298
                        }
nkeynes@359
  2299
                        }
nkeynes@359
  2300
                        break;
nkeynes@359
  2301
                    case 0xD:
nkeynes@359
  2302
                        { /* BT/S disp */
nkeynes@359
  2303
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2304
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2305
                    	SLOTILLEGAL();
nkeynes@374
  2306
                        } else {
nkeynes@408
  2307
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2308
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2309
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2310
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2311
                    	}
nkeynes@417
  2312
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2313
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2314
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2315
                    	// not taken
nkeynes@408
  2316
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2317
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2318
                    	return 4;
nkeynes@374
  2319
                        }
nkeynes@359
  2320
                        }
nkeynes@359
  2321
                        break;
nkeynes@359
  2322
                    case 0xF:
nkeynes@359
  2323
                        { /* BF/S disp */
nkeynes@359
  2324
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2325
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2326
                    	SLOTILLEGAL();
nkeynes@374
  2327
                        } else {
nkeynes@408
  2328
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2329
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2330
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2331
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2332
                    	}
nkeynes@417
  2333
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2334
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2335
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2336
                    	// not taken
nkeynes@408
  2337
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2338
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2339
                    	return 4;
nkeynes@374
  2340
                        }
nkeynes@359
  2341
                        }
nkeynes@359
  2342
                        break;
nkeynes@359
  2343
                    default:
nkeynes@359
  2344
                        UNDEF();
nkeynes@359
  2345
                        break;
nkeynes@359
  2346
                }
nkeynes@359
  2347
                break;
nkeynes@359
  2348
            case 0x9:
nkeynes@359
  2349
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2350
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2351
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2352
            	SLOTILLEGAL();
nkeynes@374
  2353
                } else {
nkeynes@569
  2354
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  2355
            	uint32_t target = pc + disp + 4;
nkeynes@569
  2356
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2357
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  2358
            	    MOV_moff32_EAX( ptr );
nkeynes@569
  2359
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  2360
            	} else {
nkeynes@569
  2361
            	    load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@569
  2362
            	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@569
  2363
            	    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@569
  2364
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  2365
            	}
nkeynes@374
  2366
            	store_reg( R_EAX, Rn );
nkeynes@374
  2367
                }
nkeynes@359
  2368
                }
nkeynes@359
  2369
                break;
nkeynes@359
  2370
            case 0xA:
nkeynes@359
  2371
                { /* BRA disp */
nkeynes@359
  2372
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2373
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2374
            	SLOTILLEGAL();
nkeynes@374
  2375
                } else {
nkeynes@374
  2376
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2377
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2378
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2379
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2380
            	return 4;
nkeynes@374
  2381
                }
nkeynes@359
  2382
                }
nkeynes@359
  2383
                break;
nkeynes@359
  2384
            case 0xB:
nkeynes@359
  2385
                { /* BSR disp */
nkeynes@359
  2386
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2387
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2388
            	SLOTILLEGAL();
nkeynes@374
  2389
                } else {
nkeynes@374
  2390
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2391
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2392
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2393
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2394
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2395
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2396
            	return 4;
nkeynes@374
  2397
                }
nkeynes@359
  2398
                }
nkeynes@359
  2399
                break;
nkeynes@359
  2400
            case 0xC:
nkeynes@359
  2401
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2402
                    case 0x0:
nkeynes@359
  2403
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2404
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2405
                        load_reg( R_EAX, 0 );
nkeynes@359
  2406
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2407
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2408
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2409
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2410
                        }
nkeynes@359
  2411
                        break;
nkeynes@359
  2412
                    case 0x1:
nkeynes@359
  2413
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2414
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2415
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2416
                        load_reg( R_EAX, 0 );
nkeynes@361
  2417
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2418
                        check_walign16( R_ECX );
nkeynes@361
  2419
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2420
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2421
                        }
nkeynes@359
  2422
                        break;
nkeynes@359
  2423
                    case 0x2:
nkeynes@359
  2424
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2425
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2426
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2427
                        load_reg( R_EAX, 0 );
nkeynes@361
  2428
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2429
                        check_walign32( R_ECX );
nkeynes@361
  2430
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2431
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2432
                        }
nkeynes@359
  2433
                        break;
nkeynes@359
  2434
                    case 0x3:
nkeynes@359
  2435
                        { /* TRAPA #imm */
nkeynes@359
  2436
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2437
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2438
                    	SLOTILLEGAL();
nkeynes@374
  2439
                        } else {
nkeynes@533
  2440
                    	load_imm32( R_ECX, pc+2 );
nkeynes@533
  2441
                    	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  2442
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2443
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2444
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2445
                    	exit_block_pcset(pc);
nkeynes@409
  2446
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2447
                    	return 2;
nkeynes@374
  2448
                        }
nkeynes@359
  2449
                        }
nkeynes@359
  2450
                        break;
nkeynes@359
  2451
                    case 0x4:
nkeynes@359
  2452
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2453
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2454
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2455
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2456
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2457
                        store_reg( R_EAX, 0 );
nkeynes@417
  2458
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2459
                        }
nkeynes@359
  2460
                        break;
nkeynes@359
  2461
                    case 0x5:
nkeynes@359
  2462
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2463
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2464
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2465
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2466
                        check_ralign16( R_ECX );
nkeynes@361
  2467
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2468
                        store_reg( R_EAX, 0 );
nkeynes@417
  2469
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2470
                        }
nkeynes@359
  2471
                        break;
nkeynes@359
  2472
                    case 0x6:
nkeynes@359
  2473
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2474
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2475
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2476
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2477
                        check_ralign32( R_ECX );
nkeynes@361
  2478
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2479
                        store_reg( R_EAX, 0 );
nkeynes@417
  2480
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2481
                        }
nkeynes@359
  2482
                        break;
nkeynes@359
  2483
                    case 0x7:
nkeynes@359
  2484
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2485
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2486
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2487
                    	SLOTILLEGAL();
nkeynes@374
  2488
                        } else {
nkeynes@569
  2489
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  2490
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2491
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2492
                        }
nkeynes@359
  2493
                        }
nkeynes@359
  2494
                        break;
nkeynes@359
  2495
                    case 0x8:
nkeynes@359
  2496
                        { /* TST #imm, R0 */
nkeynes@359
  2497
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2498
                        load_reg( R_EAX, 0 );
nkeynes@368
  2499
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2500
                        SETE_t();
nkeynes@417
  2501
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2502
                        }
nkeynes@359
  2503
                        break;
nkeynes@359
  2504
                    case 0x9:
nkeynes@359
  2505
                        { /* AND #imm, R0 */
nkeynes@359
  2506
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2507
                        load_reg( R_EAX, 0 );
nkeynes@359
  2508
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2509
                        store_reg( R_EAX, 0 );
nkeynes@417
  2510
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2511
                        }
nkeynes@359
  2512
                        break;
nkeynes@359
  2513
                    case 0xA:
nkeynes@359
  2514
                        { /* XOR #imm, R0 */
nkeynes@359
  2515
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2516
                        load_reg( R_EAX, 0 );
nkeynes@359
  2517
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2518
                        store_reg( R_EAX, 0 );
nkeynes@417
  2519
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2520
                        }
nkeynes@359
  2521
                        break;
nkeynes@359
  2522
                    case 0xB:
nkeynes@359
  2523
                        { /* OR #imm, R0 */
nkeynes@359
  2524
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2525
                        load_reg( R_EAX, 0 );
nkeynes@359
  2526
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2527
                        store_reg( R_EAX, 0 );
nkeynes@417
  2528
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2529
                        }
nkeynes@359
  2530
                        break;
nkeynes@359
  2531
                    case 0xC:
nkeynes@359
  2532
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2533
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2534
                        load_reg( R_EAX, 0);
nkeynes@368
  2535
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2536
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2537
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  2538
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2539
                        SETE_t();
nkeynes@417
  2540
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2541
                        }
nkeynes@359
  2542
                        break;
nkeynes@359
  2543
                    case 0xD:
nkeynes@359
  2544
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2545
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2546
                        load_reg( R_EAX, 0 );
nkeynes@359
  2547
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2548
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2549
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2550
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2551
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2552
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2553
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2554
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2555
                        }
nkeynes@359
  2556
                        break;
nkeynes@359
  2557
                    case 0xE:
nkeynes@359
  2558
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2559
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2560
                        load_reg( R_EAX, 0 );
nkeynes@359
  2561
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2562
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2563
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2564
                        MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
  2565
                        POP_realigned_r32(R_ECX);
nkeynes@359
  2566
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2567
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2568
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2569
                        }
nkeynes@359
  2570
                        break;
nkeynes@359
  2571
                    case 0xF:
nkeynes@359
  2572
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2573
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2574
                        load_reg( R_EAX, 0 );
nkeynes@374
  2575
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2576
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2577
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2578
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2579
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2580
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2581
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2582
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2583
                        }
nkeynes@359
  2584
                        break;
nkeynes@359
  2585
                }
nkeynes@359
  2586
                break;
nkeynes@359
  2587
            case 0xD:
nkeynes@359
  2588
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2589
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2590
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2591
            	SLOTILLEGAL();
nkeynes@374
  2592
                } else {
nkeynes@388
  2593
            	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  2594
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2595
            	    // If the target address is in the same page as the code, it's
nkeynes@569
  2596
            	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  2597
            	    // memory subsystem. (this is a big performance win)
nkeynes@569
  2598
            
nkeynes@569
  2599
            	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  2600
            	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  2601
            	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  2602
            	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  2603
            	    // behaviour though.
nkeynes@569
  2604
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  2605
            	    MOV_moff32_EAX( ptr );
nkeynes@388
  2606
            	} else {
nkeynes@569
  2607
            	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  2608
            	    // different virtual address than the translation was done with,
nkeynes@569
  2609
            	    // but we can safely assume that the low bits are the same.
nkeynes@569
  2610
            	    load_imm32( R_ECX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  2611
            	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@388
  2612
            	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@569
  2613
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2614
            	}
nkeynes@386
  2615
            	store_reg( R_EAX, Rn );
nkeynes@374
  2616
                }
nkeynes@359
  2617
                }
nkeynes@359
  2618
                break;
nkeynes@359
  2619
            case 0xE:
nkeynes@359
  2620
                { /* MOV #imm, Rn */
nkeynes@359
  2621
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2622
                load_imm32( R_EAX, imm );
nkeynes@359
  2623
                store_reg( R_EAX, Rn );
nkeynes@359
  2624
                }
nkeynes@359
  2625
                break;
nkeynes@359
  2626
            case 0xF:
nkeynes@359
  2627
                switch( ir&0xF ) {
nkeynes@359
  2628
                    case 0x0:
nkeynes@359
  2629
                        { /* FADD FRm, FRn */
nkeynes@359
  2630
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2631
                        check_fpuen();
nkeynes@377
  2632
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2633
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2634
                        load_fr_bank( R_EDX );
nkeynes@380
  2635
                        JNE_rel8(13,doubleprec);
nkeynes@377
  2636
                        push_fr(R_EDX, FRm);
nkeynes@377
  2637
                        push_fr(R_EDX, FRn);
nkeynes@377
  2638
                        FADDP_st(1);
nkeynes@377
  2639
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2640
                        JMP_rel8(11,end);
nkeynes@380
  2641
                        JMP_TARGET(doubleprec);
nkeynes@377
  2642
                        push_dr(R_EDX, FRm);
nkeynes@377
  2643
                        push_dr(R_EDX, FRn);
nkeynes@377
  2644
                        FADDP_st(1);
nkeynes@377
  2645
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2646
                        JMP_TARGET(end);
nkeynes@417
  2647
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2648
                        }
nkeynes@359
  2649
                        break;
nkeynes@359
  2650
                    case 0x1:
nkeynes@359
  2651
                        { /* FSUB FRm, FRn */
nkeynes@359
  2652
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2653
                        check_fpuen();
nkeynes@377
  2654
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2655
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2656
                        load_fr_bank( R_EDX );
nkeynes@380
  2657
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2658
                        push_fr(R_EDX, FRn);
nkeynes@377
  2659
                        push_fr(R_EDX, FRm);
nkeynes@388
  2660
                        FSUBP_st(1);
nkeynes@377
  2661
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2662
                        JMP_rel8(11, end);
nkeynes@380
  2663
                        JMP_TARGET(doubleprec);
nkeynes@377
  2664
                        push_dr(R_EDX, FRn);
nkeynes@377
  2665
                        push_dr(R_EDX, FRm);
nkeynes@388
  2666
                        FSUBP_st(1);
nkeynes@377
  2667
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2668
                        JMP_TARGET(end);
nkeynes@417
  2669
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2670
                        }
nkeynes@359
  2671
                        break;
nkeynes@359
  2672
                    case 0x2:
nkeynes@359
  2673
                        { /* FMUL FRm, FRn */
nkeynes@359
  2674
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2675
                        check_fpuen();
nkeynes@377
  2676
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2677
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2678
                        load_fr_bank( R_EDX );
nkeynes@380
  2679
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2680
                        push_fr(R_EDX, FRm);
nkeynes@377
  2681
                        push_fr(R_EDX, FRn);
nkeynes@377
  2682
                        FMULP_st(1);
nkeynes@377
  2683
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2684
                        JMP_rel8(11, end);
nkeynes@380
  2685
                        JMP_TARGET(doubleprec);
nkeynes@377
  2686
                        push_dr(R_EDX, FRm);
nkeynes@377
  2687
                        push_dr(R_EDX, FRn);
nkeynes@377
  2688
                        FMULP_st(1);
nkeynes@377
  2689
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2690
                        JMP_TARGET(end);
nkeynes@417
  2691
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2692
                        }
nkeynes@359
  2693
                        break;
nkeynes@359
  2694
                    case 0x3:
nkeynes@359
  2695
                        { /* FDIV FRm, FRn */
nkeynes@359
  2696
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2697
                        check_fpuen();
nkeynes@377
  2698
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2699
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2700
                        load_fr_bank( R_EDX );
nkeynes@380
  2701
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2702
                        push_fr(R_EDX, FRn);
nkeynes@377
  2703
                        push_fr(R_EDX, FRm);
nkeynes@377
  2704
                        FDIVP_st(1);
nkeynes@377
  2705
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2706
                        JMP_rel8(11, end);