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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 569:a1c49e1e8776
prev561:533f6b478071
next570:d2893980fbf5
author nkeynes
date Fri Jan 04 11:54:17 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Bring icache partially into line with the mmu, a little less slow with AT off
now.
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
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#define MEM_READ_SIZE  (CALL_FUNC1_SIZE+8)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE+8)
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SH4_TRANSLATOR == TARGET_X86_64
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#include "sh4/ia64abi.h"
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#else /* SH4_TRANSLATOR == TARGET_X86 */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
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#endif
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   333
/**
nkeynes@359
   334
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   335
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   336
 * 
nkeynes@359
   337
 *
nkeynes@359
   338
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   339
 * (eg a branch or 
nkeynes@359
   340
 */
nkeynes@526
   341
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   342
{
nkeynes@388
   343
    uint32_t ir;
nkeynes@388
   344
    /* Read instruction */
nkeynes@569
   345
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   346
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   347
    } else {
nkeynes@569
   348
	ir = sh4_read_word(pc);
nkeynes@388
   349
    }
nkeynes@359
   350
%%
nkeynes@359
   351
/* ALU operations */
nkeynes@359
   352
ADD Rm, Rn {:
nkeynes@359
   353
    load_reg( R_EAX, Rm );
nkeynes@359
   354
    load_reg( R_ECX, Rn );
nkeynes@359
   355
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   356
    store_reg( R_ECX, Rn );
nkeynes@417
   357
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   358
:}
nkeynes@359
   359
ADD #imm, Rn {:  
nkeynes@359
   360
    load_reg( R_EAX, Rn );
nkeynes@359
   361
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   362
    store_reg( R_EAX, Rn );
nkeynes@417
   363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   364
:}
nkeynes@359
   365
ADDC Rm, Rn {:
nkeynes@417
   366
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   367
	LDC_t();
nkeynes@417
   368
    }
nkeynes@359
   369
    load_reg( R_EAX, Rm );
nkeynes@359
   370
    load_reg( R_ECX, Rn );
nkeynes@359
   371
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   372
    store_reg( R_ECX, Rn );
nkeynes@359
   373
    SETC_t();
nkeynes@417
   374
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   375
:}
nkeynes@359
   376
ADDV Rm, Rn {:
nkeynes@359
   377
    load_reg( R_EAX, Rm );
nkeynes@359
   378
    load_reg( R_ECX, Rn );
nkeynes@359
   379
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   380
    store_reg( R_ECX, Rn );
nkeynes@359
   381
    SETO_t();
nkeynes@417
   382
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   383
:}
nkeynes@359
   384
AND Rm, Rn {:
nkeynes@359
   385
    load_reg( R_EAX, Rm );
nkeynes@359
   386
    load_reg( R_ECX, Rn );
nkeynes@359
   387
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   388
    store_reg( R_ECX, Rn );
nkeynes@417
   389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   390
:}
nkeynes@359
   391
AND #imm, R0 {:  
nkeynes@359
   392
    load_reg( R_EAX, 0 );
nkeynes@359
   393
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   394
    store_reg( R_EAX, 0 );
nkeynes@417
   395
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   396
:}
nkeynes@359
   397
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   398
    load_reg( R_EAX, 0 );
nkeynes@359
   399
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   400
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   401
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   402
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   403
    POP_realigned_r32(R_ECX);
nkeynes@386
   404
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   405
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   406
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   407
:}
nkeynes@359
   408
CMP/EQ Rm, Rn {:  
nkeynes@359
   409
    load_reg( R_EAX, Rm );
nkeynes@359
   410
    load_reg( R_ECX, Rn );
nkeynes@359
   411
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   412
    SETE_t();
nkeynes@417
   413
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   414
:}
nkeynes@359
   415
CMP/EQ #imm, R0 {:  
nkeynes@359
   416
    load_reg( R_EAX, 0 );
nkeynes@359
   417
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   418
    SETE_t();
nkeynes@417
   419
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   420
:}
nkeynes@359
   421
CMP/GE Rm, Rn {:  
nkeynes@359
   422
    load_reg( R_EAX, Rm );
nkeynes@359
   423
    load_reg( R_ECX, Rn );
nkeynes@359
   424
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   425
    SETGE_t();
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   427
:}
nkeynes@359
   428
CMP/GT Rm, Rn {: 
nkeynes@359
   429
    load_reg( R_EAX, Rm );
nkeynes@359
   430
    load_reg( R_ECX, Rn );
nkeynes@359
   431
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   432
    SETG_t();
nkeynes@417
   433
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   434
:}
nkeynes@359
   435
CMP/HI Rm, Rn {:  
nkeynes@359
   436
    load_reg( R_EAX, Rm );
nkeynes@359
   437
    load_reg( R_ECX, Rn );
nkeynes@359
   438
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   439
    SETA_t();
nkeynes@417
   440
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   441
:}
nkeynes@359
   442
CMP/HS Rm, Rn {: 
nkeynes@359
   443
    load_reg( R_EAX, Rm );
nkeynes@359
   444
    load_reg( R_ECX, Rn );
nkeynes@359
   445
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   446
    SETAE_t();
nkeynes@417
   447
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   448
 :}
nkeynes@359
   449
CMP/PL Rn {: 
nkeynes@359
   450
    load_reg( R_EAX, Rn );
nkeynes@359
   451
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   452
    SETG_t();
nkeynes@417
   453
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   454
:}
nkeynes@359
   455
CMP/PZ Rn {:  
nkeynes@359
   456
    load_reg( R_EAX, Rn );
nkeynes@359
   457
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   458
    SETGE_t();
nkeynes@417
   459
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   460
:}
nkeynes@361
   461
CMP/STR Rm, Rn {:  
nkeynes@368
   462
    load_reg( R_EAX, Rm );
nkeynes@368
   463
    load_reg( R_ECX, Rn );
nkeynes@368
   464
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   465
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   466
    JE_rel8(13, target1);
nkeynes@368
   467
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   468
    JE_rel8(9, target2);
nkeynes@368
   469
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   470
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   471
    JE_rel8(2, target3);
nkeynes@368
   472
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   473
    JMP_TARGET(target1);
nkeynes@380
   474
    JMP_TARGET(target2);
nkeynes@380
   475
    JMP_TARGET(target3);
nkeynes@368
   476
    SETE_t();
nkeynes@417
   477
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   478
:}
nkeynes@361
   479
DIV0S Rm, Rn {:
nkeynes@361
   480
    load_reg( R_EAX, Rm );
nkeynes@386
   481
    load_reg( R_ECX, Rn );
nkeynes@361
   482
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   483
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   484
    store_spreg( R_EAX, R_M );
nkeynes@361
   485
    store_spreg( R_ECX, R_Q );
nkeynes@361
   486
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   487
    SETNE_t();
nkeynes@417
   488
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   489
:}
nkeynes@361
   490
DIV0U {:  
nkeynes@361
   491
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   492
    store_spreg( R_EAX, R_Q );
nkeynes@361
   493
    store_spreg( R_EAX, R_M );
nkeynes@361
   494
    store_spreg( R_EAX, R_T );
nkeynes@417
   495
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   496
:}
nkeynes@386
   497
DIV1 Rm, Rn {:
nkeynes@386
   498
    load_spreg( R_ECX, R_M );
nkeynes@386
   499
    load_reg( R_EAX, Rn );
nkeynes@417
   500
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   501
	LDC_t();
nkeynes@417
   502
    }
nkeynes@386
   503
    RCL1_r32( R_EAX );
nkeynes@386
   504
    SETC_r8( R_DL ); // Q'
nkeynes@386
   505
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   506
    JE_rel8(5, mqequal);
nkeynes@386
   507
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   508
    JMP_rel8(3, end);
nkeynes@380
   509
    JMP_TARGET(mqequal);
nkeynes@386
   510
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   511
    JMP_TARGET(end);
nkeynes@386
   512
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   513
    SETC_r8(R_AL); // tmp1
nkeynes@386
   514
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   515
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   516
    store_spreg( R_ECX, R_Q );
nkeynes@386
   517
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   518
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   519
    store_spreg( R_EAX, R_T );
nkeynes@417
   520
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   521
:}
nkeynes@361
   522
DMULS.L Rm, Rn {:  
nkeynes@361
   523
    load_reg( R_EAX, Rm );
nkeynes@361
   524
    load_reg( R_ECX, Rn );
nkeynes@361
   525
    IMUL_r32(R_ECX);
nkeynes@361
   526
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   527
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   528
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   529
:}
nkeynes@361
   530
DMULU.L Rm, Rn {:  
nkeynes@361
   531
    load_reg( R_EAX, Rm );
nkeynes@361
   532
    load_reg( R_ECX, Rn );
nkeynes@361
   533
    MUL_r32(R_ECX);
nkeynes@361
   534
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   535
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   537
:}
nkeynes@359
   538
DT Rn {:  
nkeynes@359
   539
    load_reg( R_EAX, Rn );
nkeynes@382
   540
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   541
    store_reg( R_EAX, Rn );
nkeynes@359
   542
    SETE_t();
nkeynes@417
   543
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   544
:}
nkeynes@359
   545
EXTS.B Rm, Rn {:  
nkeynes@359
   546
    load_reg( R_EAX, Rm );
nkeynes@359
   547
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   548
    store_reg( R_EAX, Rn );
nkeynes@359
   549
:}
nkeynes@361
   550
EXTS.W Rm, Rn {:  
nkeynes@361
   551
    load_reg( R_EAX, Rm );
nkeynes@361
   552
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   553
    store_reg( R_EAX, Rn );
nkeynes@361
   554
:}
nkeynes@361
   555
EXTU.B Rm, Rn {:  
nkeynes@361
   556
    load_reg( R_EAX, Rm );
nkeynes@361
   557
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   558
    store_reg( R_EAX, Rn );
nkeynes@361
   559
:}
nkeynes@361
   560
EXTU.W Rm, Rn {:  
nkeynes@361
   561
    load_reg( R_EAX, Rm );
nkeynes@361
   562
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   563
    store_reg( R_EAX, Rn );
nkeynes@361
   564
:}
nkeynes@386
   565
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   566
    load_reg( R_ECX, Rm );
nkeynes@386
   567
    check_ralign32( R_ECX );
nkeynes@386
   568
    load_reg( R_ECX, Rn );
nkeynes@386
   569
    check_ralign32( R_ECX );
nkeynes@386
   570
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   571
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   572
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   573
    load_reg( R_ECX, Rm );
nkeynes@386
   574
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   575
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   576
    POP_realigned_r32( R_ECX );
nkeynes@386
   577
    IMUL_r32( R_ECX );
nkeynes@386
   578
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   579
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   580
nkeynes@386
   581
    load_spreg( R_ECX, R_S );
nkeynes@386
   582
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   583
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   584
    call_func0( signsat48 );
nkeynes@386
   585
    JMP_TARGET( nosat );
nkeynes@417
   586
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   587
:}
nkeynes@386
   588
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   589
    load_reg( R_ECX, Rm );
nkeynes@386
   590
    check_ralign16( R_ECX );
nkeynes@386
   591
    load_reg( R_ECX, Rn );
nkeynes@386
   592
    check_ralign16( R_ECX );
nkeynes@386
   593
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   594
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   595
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   596
    load_reg( R_ECX, Rm );
nkeynes@386
   597
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   598
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   599
    POP_realigned_r32( R_ECX );
nkeynes@386
   600
    IMUL_r32( R_ECX );
nkeynes@386
   601
nkeynes@386
   602
    load_spreg( R_ECX, R_S );
nkeynes@386
   603
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   604
    JE_rel8( 47, nosat );
nkeynes@386
   605
nkeynes@386
   606
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   607
    JNO_rel8( 51, end );            // 2
nkeynes@386
   608
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   609
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   610
    JS_rel8( 13, positive );        // 2
nkeynes@386
   611
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   612
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   613
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   614
nkeynes@386
   615
    JMP_TARGET(positive);
nkeynes@386
   616
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   617
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   618
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   619
nkeynes@386
   620
    JMP_TARGET(nosat);
nkeynes@386
   621
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   622
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   623
    JMP_TARGET(end);
nkeynes@386
   624
    JMP_TARGET(end2);
nkeynes@386
   625
    JMP_TARGET(end3);
nkeynes@417
   626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   627
:}
nkeynes@359
   628
MOVT Rn {:  
nkeynes@359
   629
    load_spreg( R_EAX, R_T );
nkeynes@359
   630
    store_reg( R_EAX, Rn );
nkeynes@359
   631
:}
nkeynes@361
   632
MUL.L Rm, Rn {:  
nkeynes@361
   633
    load_reg( R_EAX, Rm );
nkeynes@361
   634
    load_reg( R_ECX, Rn );
nkeynes@361
   635
    MUL_r32( R_ECX );
nkeynes@361
   636
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   637
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   638
:}
nkeynes@374
   639
MULS.W Rm, Rn {:
nkeynes@374
   640
    load_reg16s( R_EAX, Rm );
nkeynes@374
   641
    load_reg16s( R_ECX, Rn );
nkeynes@374
   642
    MUL_r32( R_ECX );
nkeynes@374
   643
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   644
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   645
:}
nkeynes@374
   646
MULU.W Rm, Rn {:  
nkeynes@374
   647
    load_reg16u( R_EAX, Rm );
nkeynes@374
   648
    load_reg16u( R_ECX, Rn );
nkeynes@374
   649
    MUL_r32( R_ECX );
nkeynes@374
   650
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   651
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   652
:}
nkeynes@359
   653
NEG Rm, Rn {:
nkeynes@359
   654
    load_reg( R_EAX, Rm );
nkeynes@359
   655
    NEG_r32( R_EAX );
nkeynes@359
   656
    store_reg( R_EAX, Rn );
nkeynes@417
   657
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   658
:}
nkeynes@359
   659
NEGC Rm, Rn {:  
nkeynes@359
   660
    load_reg( R_EAX, Rm );
nkeynes@359
   661
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   662
    LDC_t();
nkeynes@359
   663
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   664
    store_reg( R_ECX, Rn );
nkeynes@359
   665
    SETC_t();
nkeynes@417
   666
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   667
:}
nkeynes@359
   668
NOT Rm, Rn {:  
nkeynes@359
   669
    load_reg( R_EAX, Rm );
nkeynes@359
   670
    NOT_r32( R_EAX );
nkeynes@359
   671
    store_reg( R_EAX, Rn );
nkeynes@417
   672
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   673
:}
nkeynes@359
   674
OR Rm, Rn {:  
nkeynes@359
   675
    load_reg( R_EAX, Rm );
nkeynes@359
   676
    load_reg( R_ECX, Rn );
nkeynes@359
   677
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   678
    store_reg( R_ECX, Rn );
nkeynes@417
   679
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   680
:}
nkeynes@359
   681
OR #imm, R0 {:
nkeynes@359
   682
    load_reg( R_EAX, 0 );
nkeynes@359
   683
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   684
    store_reg( R_EAX, 0 );
nkeynes@417
   685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   686
:}
nkeynes@374
   687
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   688
    load_reg( R_EAX, 0 );
nkeynes@374
   689
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   690
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   691
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   692
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   693
    POP_realigned_r32(R_ECX);
nkeynes@386
   694
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   695
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   697
:}
nkeynes@359
   698
ROTCL Rn {:
nkeynes@359
   699
    load_reg( R_EAX, Rn );
nkeynes@417
   700
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   701
	LDC_t();
nkeynes@417
   702
    }
nkeynes@359
   703
    RCL1_r32( R_EAX );
nkeynes@359
   704
    store_reg( R_EAX, Rn );
nkeynes@359
   705
    SETC_t();
nkeynes@417
   706
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   707
:}
nkeynes@359
   708
ROTCR Rn {:  
nkeynes@359
   709
    load_reg( R_EAX, Rn );
nkeynes@417
   710
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   711
	LDC_t();
nkeynes@417
   712
    }
nkeynes@359
   713
    RCR1_r32( R_EAX );
nkeynes@359
   714
    store_reg( R_EAX, Rn );
nkeynes@359
   715
    SETC_t();
nkeynes@417
   716
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   717
:}
nkeynes@359
   718
ROTL Rn {:  
nkeynes@359
   719
    load_reg( R_EAX, Rn );
nkeynes@359
   720
    ROL1_r32( R_EAX );
nkeynes@359
   721
    store_reg( R_EAX, Rn );
nkeynes@359
   722
    SETC_t();
nkeynes@417
   723
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   724
:}
nkeynes@359
   725
ROTR Rn {:  
nkeynes@359
   726
    load_reg( R_EAX, Rn );
nkeynes@359
   727
    ROR1_r32( R_EAX );
nkeynes@359
   728
    store_reg( R_EAX, Rn );
nkeynes@359
   729
    SETC_t();
nkeynes@417
   730
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   731
:}
nkeynes@359
   732
SHAD Rm, Rn {:
nkeynes@359
   733
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   734
    load_reg( R_EAX, Rn );
nkeynes@361
   735
    load_reg( R_ECX, Rm );
nkeynes@361
   736
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   737
    JGE_rel8(16, doshl);
nkeynes@361
   738
                    
nkeynes@361
   739
    NEG_r32( R_ECX );      // 2
nkeynes@361
   740
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   741
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   742
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   743
    JMP_rel8(10, end);          // 2
nkeynes@386
   744
nkeynes@386
   745
    JMP_TARGET(emptysar);
nkeynes@386
   746
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   747
    JMP_rel8(5, end2);
nkeynes@382
   748
nkeynes@380
   749
    JMP_TARGET(doshl);
nkeynes@361
   750
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   751
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   752
    JMP_TARGET(end);
nkeynes@386
   753
    JMP_TARGET(end2);
nkeynes@361
   754
    store_reg( R_EAX, Rn );
nkeynes@417
   755
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   756
:}
nkeynes@359
   757
SHLD Rm, Rn {:  
nkeynes@368
   758
    load_reg( R_EAX, Rn );
nkeynes@368
   759
    load_reg( R_ECX, Rm );
nkeynes@382
   760
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   761
    JGE_rel8(15, doshl);
nkeynes@368
   762
nkeynes@382
   763
    NEG_r32( R_ECX );      // 2
nkeynes@382
   764
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   765
    JE_rel8( 4, emptyshr );
nkeynes@382
   766
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   767
    JMP_rel8(9, end);          // 2
nkeynes@386
   768
nkeynes@386
   769
    JMP_TARGET(emptyshr);
nkeynes@386
   770
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   771
    JMP_rel8(5, end2);
nkeynes@382
   772
nkeynes@382
   773
    JMP_TARGET(doshl);
nkeynes@382
   774
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   775
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   776
    JMP_TARGET(end);
nkeynes@386
   777
    JMP_TARGET(end2);
nkeynes@368
   778
    store_reg( R_EAX, Rn );
nkeynes@417
   779
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   780
:}
nkeynes@359
   781
SHAL Rn {: 
nkeynes@359
   782
    load_reg( R_EAX, Rn );
nkeynes@359
   783
    SHL1_r32( R_EAX );
nkeynes@397
   784
    SETC_t();
nkeynes@359
   785
    store_reg( R_EAX, Rn );
nkeynes@417
   786
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   787
:}
nkeynes@359
   788
SHAR Rn {:  
nkeynes@359
   789
    load_reg( R_EAX, Rn );
nkeynes@359
   790
    SAR1_r32( R_EAX );
nkeynes@397
   791
    SETC_t();
nkeynes@359
   792
    store_reg( R_EAX, Rn );
nkeynes@417
   793
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   794
:}
nkeynes@359
   795
SHLL Rn {:  
nkeynes@359
   796
    load_reg( R_EAX, Rn );
nkeynes@359
   797
    SHL1_r32( R_EAX );
nkeynes@397
   798
    SETC_t();
nkeynes@359
   799
    store_reg( R_EAX, Rn );
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   801
:}
nkeynes@359
   802
SHLL2 Rn {:
nkeynes@359
   803
    load_reg( R_EAX, Rn );
nkeynes@359
   804
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   805
    store_reg( R_EAX, Rn );
nkeynes@417
   806
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   807
:}
nkeynes@359
   808
SHLL8 Rn {:  
nkeynes@359
   809
    load_reg( R_EAX, Rn );
nkeynes@359
   810
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   811
    store_reg( R_EAX, Rn );
nkeynes@417
   812
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   813
:}
nkeynes@359
   814
SHLL16 Rn {:  
nkeynes@359
   815
    load_reg( R_EAX, Rn );
nkeynes@359
   816
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   817
    store_reg( R_EAX, Rn );
nkeynes@417
   818
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   819
:}
nkeynes@359
   820
SHLR Rn {:  
nkeynes@359
   821
    load_reg( R_EAX, Rn );
nkeynes@359
   822
    SHR1_r32( R_EAX );
nkeynes@397
   823
    SETC_t();
nkeynes@359
   824
    store_reg( R_EAX, Rn );
nkeynes@417
   825
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   826
:}
nkeynes@359
   827
SHLR2 Rn {:  
nkeynes@359
   828
    load_reg( R_EAX, Rn );
nkeynes@359
   829
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   830
    store_reg( R_EAX, Rn );
nkeynes@417
   831
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   832
:}
nkeynes@359
   833
SHLR8 Rn {:  
nkeynes@359
   834
    load_reg( R_EAX, Rn );
nkeynes@359
   835
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   836
    store_reg( R_EAX, Rn );
nkeynes@417
   837
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   838
:}
nkeynes@359
   839
SHLR16 Rn {:  
nkeynes@359
   840
    load_reg( R_EAX, Rn );
nkeynes@359
   841
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   842
    store_reg( R_EAX, Rn );
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   844
:}
nkeynes@359
   845
SUB Rm, Rn {:  
nkeynes@359
   846
    load_reg( R_EAX, Rm );
nkeynes@359
   847
    load_reg( R_ECX, Rn );
nkeynes@359
   848
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   849
    store_reg( R_ECX, Rn );
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   851
:}
nkeynes@359
   852
SUBC Rm, Rn {:  
nkeynes@359
   853
    load_reg( R_EAX, Rm );
nkeynes@359
   854
    load_reg( R_ECX, Rn );
nkeynes@417
   855
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   856
	LDC_t();
nkeynes@417
   857
    }
nkeynes@359
   858
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   859
    store_reg( R_ECX, Rn );
nkeynes@394
   860
    SETC_t();
nkeynes@417
   861
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   862
:}
nkeynes@359
   863
SUBV Rm, Rn {:  
nkeynes@359
   864
    load_reg( R_EAX, Rm );
nkeynes@359
   865
    load_reg( R_ECX, Rn );
nkeynes@359
   866
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   867
    store_reg( R_ECX, Rn );
nkeynes@359
   868
    SETO_t();
nkeynes@417
   869
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   870
:}
nkeynes@359
   871
SWAP.B Rm, Rn {:  
nkeynes@359
   872
    load_reg( R_EAX, Rm );
nkeynes@359
   873
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   874
    store_reg( R_EAX, Rn );
nkeynes@359
   875
:}
nkeynes@359
   876
SWAP.W Rm, Rn {:  
nkeynes@359
   877
    load_reg( R_EAX, Rm );
nkeynes@359
   878
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   879
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   880
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   881
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   882
    store_reg( R_ECX, Rn );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@361
   885
TAS.B @Rn {:  
nkeynes@361
   886
    load_reg( R_ECX, Rn );
nkeynes@361
   887
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   888
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   889
    SETE_t();
nkeynes@361
   890
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   891
    load_reg( R_ECX, Rn );
nkeynes@361
   892
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   893
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   894
:}
nkeynes@361
   895
TST Rm, Rn {:  
nkeynes@361
   896
    load_reg( R_EAX, Rm );
nkeynes@361
   897
    load_reg( R_ECX, Rn );
nkeynes@361
   898
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   899
    SETE_t();
nkeynes@417
   900
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   901
:}
nkeynes@368
   902
TST #imm, R0 {:  
nkeynes@368
   903
    load_reg( R_EAX, 0 );
nkeynes@368
   904
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   905
    SETE_t();
nkeynes@417
   906
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   907
:}
nkeynes@368
   908
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   909
    load_reg( R_EAX, 0);
nkeynes@368
   910
    load_reg( R_ECX, R_GBR);
nkeynes@368
   911
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   912
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
   913
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   914
    SETE_t();
nkeynes@417
   915
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   916
:}
nkeynes@359
   917
XOR Rm, Rn {:  
nkeynes@359
   918
    load_reg( R_EAX, Rm );
nkeynes@359
   919
    load_reg( R_ECX, Rn );
nkeynes@359
   920
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   921
    store_reg( R_ECX, Rn );
nkeynes@417
   922
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   923
:}
nkeynes@359
   924
XOR #imm, R0 {:  
nkeynes@359
   925
    load_reg( R_EAX, 0 );
nkeynes@359
   926
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   927
    store_reg( R_EAX, 0 );
nkeynes@417
   928
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   929
:}
nkeynes@359
   930
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   931
    load_reg( R_EAX, 0 );
nkeynes@359
   932
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   933
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   934
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   935
    MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
   936
    POP_realigned_r32(R_ECX);
nkeynes@359
   937
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   938
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   939
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   940
:}
nkeynes@361
   941
XTRCT Rm, Rn {:
nkeynes@361
   942
    load_reg( R_EAX, Rm );
nkeynes@394
   943
    load_reg( R_ECX, Rn );
nkeynes@394
   944
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   945
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   946
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   947
    store_reg( R_ECX, Rn );
nkeynes@417
   948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   949
:}
nkeynes@359
   950
nkeynes@359
   951
/* Data move instructions */
nkeynes@359
   952
MOV Rm, Rn {:  
nkeynes@359
   953
    load_reg( R_EAX, Rm );
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@359
   955
:}
nkeynes@359
   956
MOV #imm, Rn {:  
nkeynes@359
   957
    load_imm32( R_EAX, imm );
nkeynes@359
   958
    store_reg( R_EAX, Rn );
nkeynes@359
   959
:}
nkeynes@359
   960
MOV.B Rm, @Rn {:  
nkeynes@359
   961
    load_reg( R_EAX, Rm );
nkeynes@359
   962
    load_reg( R_ECX, Rn );
nkeynes@359
   963
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   964
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
:}
nkeynes@359
   966
MOV.B Rm, @-Rn {:  
nkeynes@359
   967
    load_reg( R_EAX, Rm );
nkeynes@359
   968
    load_reg( R_ECX, Rn );
nkeynes@382
   969
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   970
    store_reg( R_ECX, Rn );
nkeynes@359
   971
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   972
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   973
:}
nkeynes@359
   974
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   975
    load_reg( R_EAX, 0 );
nkeynes@359
   976
    load_reg( R_ECX, Rn );
nkeynes@359
   977
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   978
    load_reg( R_EAX, Rm );
nkeynes@359
   979
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   980
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   981
:}
nkeynes@359
   982
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   983
    load_reg( R_EAX, 0 );
nkeynes@359
   984
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   985
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   986
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   987
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   988
:}
nkeynes@359
   989
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   990
    load_reg( R_EAX, 0 );
nkeynes@359
   991
    load_reg( R_ECX, Rn );
nkeynes@359
   992
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   993
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   995
:}
nkeynes@359
   996
MOV.B @Rm, Rn {:  
nkeynes@359
   997
    load_reg( R_ECX, Rm );
nkeynes@359
   998
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
   999
    store_reg( R_EAX, Rn );
nkeynes@417
  1000
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1001
:}
nkeynes@359
  1002
MOV.B @Rm+, Rn {:  
nkeynes@359
  1003
    load_reg( R_ECX, Rm );
nkeynes@359
  1004
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1005
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1006
    store_reg( R_EAX, Rm );
nkeynes@359
  1007
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1008
    store_reg( R_EAX, Rn );
nkeynes@417
  1009
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1010
:}
nkeynes@359
  1011
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1012
    load_reg( R_EAX, 0 );
nkeynes@359
  1013
    load_reg( R_ECX, Rm );
nkeynes@359
  1014
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1015
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1016
    store_reg( R_EAX, Rn );
nkeynes@417
  1017
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1018
:}
nkeynes@359
  1019
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1020
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1021
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1022
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1023
    store_reg( R_EAX, 0 );
nkeynes@417
  1024
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1025
:}
nkeynes@359
  1026
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1027
    load_reg( R_ECX, Rm );
nkeynes@359
  1028
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1029
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1030
    store_reg( R_EAX, 0 );
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1032
:}
nkeynes@374
  1033
MOV.L Rm, @Rn {:
nkeynes@361
  1034
    load_reg( R_EAX, Rm );
nkeynes@361
  1035
    load_reg( R_ECX, Rn );
nkeynes@374
  1036
    check_walign32(R_ECX);
nkeynes@361
  1037
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1038
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1039
:}
nkeynes@361
  1040
MOV.L Rm, @-Rn {:  
nkeynes@361
  1041
    load_reg( R_EAX, Rm );
nkeynes@361
  1042
    load_reg( R_ECX, Rn );
nkeynes@374
  1043
    check_walign32( R_ECX );
nkeynes@361
  1044
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1045
    store_reg( R_ECX, Rn );
nkeynes@361
  1046
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1048
:}
nkeynes@361
  1049
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1050
    load_reg( R_EAX, 0 );
nkeynes@361
  1051
    load_reg( R_ECX, Rn );
nkeynes@361
  1052
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1053
    check_walign32( R_ECX );
nkeynes@361
  1054
    load_reg( R_EAX, Rm );
nkeynes@361
  1055
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1056
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1057
:}
nkeynes@361
  1058
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1059
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1060
    load_reg( R_EAX, 0 );
nkeynes@361
  1061
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1062
    check_walign32( R_ECX );
nkeynes@361
  1063
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1064
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1065
:}
nkeynes@361
  1066
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1067
    load_reg( R_ECX, Rn );
nkeynes@361
  1068
    load_reg( R_EAX, Rm );
nkeynes@361
  1069
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1070
    check_walign32( R_ECX );
nkeynes@361
  1071
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1072
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1073
:}
nkeynes@361
  1074
MOV.L @Rm, Rn {:  
nkeynes@361
  1075
    load_reg( R_ECX, Rm );
nkeynes@374
  1076
    check_ralign32( R_ECX );
nkeynes@361
  1077
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1078
    store_reg( R_EAX, Rn );
nkeynes@417
  1079
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1080
:}
nkeynes@361
  1081
MOV.L @Rm+, Rn {:  
nkeynes@361
  1082
    load_reg( R_EAX, Rm );
nkeynes@382
  1083
    check_ralign32( R_EAX );
nkeynes@361
  1084
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1085
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1086
    store_reg( R_EAX, Rm );
nkeynes@361
  1087
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1088
    store_reg( R_EAX, Rn );
nkeynes@417
  1089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1090
:}
nkeynes@361
  1091
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1092
    load_reg( R_EAX, 0 );
nkeynes@361
  1093
    load_reg( R_ECX, Rm );
nkeynes@361
  1094
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1095
    check_ralign32( R_ECX );
nkeynes@361
  1096
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1097
    store_reg( R_EAX, Rn );
nkeynes@417
  1098
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1099
:}
nkeynes@361
  1100
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1101
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1102
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1103
    check_ralign32( R_ECX );
nkeynes@361
  1104
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1105
    store_reg( R_EAX, 0 );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1107
:}
nkeynes@361
  1108
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1109
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1110
	SLOTILLEGAL();
nkeynes@374
  1111
    } else {
nkeynes@388
  1112
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  1113
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1114
	    // If the target address is in the same page as the code, it's
nkeynes@569
  1115
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  1116
	    // memory subsystem. (this is a big performance win)
nkeynes@569
  1117
nkeynes@569
  1118
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  1119
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  1120
	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  1121
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  1122
	    // behaviour though.
nkeynes@569
  1123
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1124
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1125
	} else {
nkeynes@569
  1126
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  1127
	    // different virtual address than the translation was done with,
nkeynes@569
  1128
	    // but we can safely assume that the low bits are the same.
nkeynes@569
  1129
	    load_imm32( R_ECX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1130
	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@388
  1131
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@569
  1132
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1133
	}
nkeynes@382
  1134
	store_reg( R_EAX, Rn );
nkeynes@374
  1135
    }
nkeynes@361
  1136
:}
nkeynes@361
  1137
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1138
    load_reg( R_ECX, Rm );
nkeynes@361
  1139
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1140
    check_ralign32( R_ECX );
nkeynes@361
  1141
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1142
    store_reg( R_EAX, Rn );
nkeynes@417
  1143
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1144
:}
nkeynes@361
  1145
MOV.W Rm, @Rn {:  
nkeynes@361
  1146
    load_reg( R_ECX, Rn );
nkeynes@374
  1147
    check_walign16( R_ECX );
nkeynes@382
  1148
    load_reg( R_EAX, Rm );
nkeynes@382
  1149
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1150
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1151
:}
nkeynes@361
  1152
MOV.W Rm, @-Rn {:  
nkeynes@361
  1153
    load_reg( R_ECX, Rn );
nkeynes@374
  1154
    check_walign16( R_ECX );
nkeynes@361
  1155
    load_reg( R_EAX, Rm );
nkeynes@361
  1156
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1157
    store_reg( R_ECX, Rn );
nkeynes@361
  1158
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1159
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1160
:}
nkeynes@361
  1161
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1162
    load_reg( R_EAX, 0 );
nkeynes@361
  1163
    load_reg( R_ECX, Rn );
nkeynes@361
  1164
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1165
    check_walign16( R_ECX );
nkeynes@361
  1166
    load_reg( R_EAX, Rm );
nkeynes@361
  1167
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1168
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1169
:}
nkeynes@361
  1170
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1171
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1172
    load_reg( R_EAX, 0 );
nkeynes@361
  1173
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1174
    check_walign16( R_ECX );
nkeynes@361
  1175
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1176
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1177
:}
nkeynes@361
  1178
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1179
    load_reg( R_ECX, Rn );
nkeynes@361
  1180
    load_reg( R_EAX, 0 );
nkeynes@361
  1181
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1182
    check_walign16( R_ECX );
nkeynes@361
  1183
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1184
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1185
:}
nkeynes@361
  1186
MOV.W @Rm, Rn {:  
nkeynes@361
  1187
    load_reg( R_ECX, Rm );
nkeynes@374
  1188
    check_ralign16( R_ECX );
nkeynes@361
  1189
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1190
    store_reg( R_EAX, Rn );
nkeynes@417
  1191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1192
:}
nkeynes@361
  1193
MOV.W @Rm+, Rn {:  
nkeynes@361
  1194
    load_reg( R_EAX, Rm );
nkeynes@374
  1195
    check_ralign16( R_EAX );
nkeynes@361
  1196
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1197
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1198
    store_reg( R_EAX, Rm );
nkeynes@361
  1199
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1200
    store_reg( R_EAX, Rn );
nkeynes@417
  1201
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1202
:}
nkeynes@361
  1203
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1204
    load_reg( R_EAX, 0 );
nkeynes@361
  1205
    load_reg( R_ECX, Rm );
nkeynes@361
  1206
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1207
    check_ralign16( R_ECX );
nkeynes@361
  1208
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1209
    store_reg( R_EAX, Rn );
nkeynes@417
  1210
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1211
:}
nkeynes@361
  1212
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1213
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1214
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1215
    check_ralign16( R_ECX );
nkeynes@361
  1216
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1217
    store_reg( R_EAX, 0 );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1219
:}
nkeynes@361
  1220
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1221
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1222
	SLOTILLEGAL();
nkeynes@374
  1223
    } else {
nkeynes@569
  1224
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  1225
	uint32_t target = pc + disp + 4;
nkeynes@569
  1226
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1227
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  1228
	    MOV_moff32_EAX( ptr );
nkeynes@569
  1229
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  1230
	} else {
nkeynes@569
  1231
	    load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@569
  1232
	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@569
  1233
	    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@569
  1234
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  1235
	}
nkeynes@374
  1236
	store_reg( R_EAX, Rn );
nkeynes@374
  1237
    }
nkeynes@361
  1238
:}
nkeynes@361
  1239
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1240
    load_reg( R_ECX, Rm );
nkeynes@361
  1241
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1242
    check_ralign16( R_ECX );
nkeynes@361
  1243
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1244
    store_reg( R_EAX, 0 );
nkeynes@417
  1245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1246
:}
nkeynes@361
  1247
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1248
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1249
	SLOTILLEGAL();
nkeynes@374
  1250
    } else {
nkeynes@569
  1251
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1252
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1253
	store_reg( R_ECX, 0 );
nkeynes@374
  1254
    }
nkeynes@361
  1255
:}
nkeynes@361
  1256
MOVCA.L R0, @Rn {:  
nkeynes@361
  1257
    load_reg( R_EAX, 0 );
nkeynes@361
  1258
    load_reg( R_ECX, Rn );
nkeynes@374
  1259
    check_walign32( R_ECX );
nkeynes@361
  1260
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1261
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1262
:}
nkeynes@359
  1263
nkeynes@359
  1264
/* Control transfer instructions */
nkeynes@374
  1265
BF disp {:
nkeynes@374
  1266
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1267
	SLOTILLEGAL();
nkeynes@374
  1268
    } else {
nkeynes@527
  1269
	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1270
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1271
	JMP_TARGET(nottaken);
nkeynes@408
  1272
	return 2;
nkeynes@374
  1273
    }
nkeynes@374
  1274
:}
nkeynes@374
  1275
BF/S disp {:
nkeynes@374
  1276
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1277
	SLOTILLEGAL();
nkeynes@374
  1278
    } else {
nkeynes@408
  1279
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1280
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1281
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1282
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1283
	}
nkeynes@417
  1284
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1285
	sh4_translate_instruction(pc+2);
nkeynes@408
  1286
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1287
	// not taken
nkeynes@408
  1288
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1289
	sh4_translate_instruction(pc+2);
nkeynes@408
  1290
	return 4;
nkeynes@374
  1291
    }
nkeynes@374
  1292
:}
nkeynes@374
  1293
BRA disp {:  
nkeynes@374
  1294
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1295
	SLOTILLEGAL();
nkeynes@374
  1296
    } else {
nkeynes@374
  1297
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1298
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1299
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1300
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1301
	return 4;
nkeynes@374
  1302
    }
nkeynes@374
  1303
:}
nkeynes@374
  1304
BRAF Rn {:  
nkeynes@374
  1305
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1306
	SLOTILLEGAL();
nkeynes@374
  1307
    } else {
nkeynes@408
  1308
	load_reg( R_EAX, Rn );
nkeynes@408
  1309
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1310
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1311
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1312
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1313
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1314
	exit_block_pcset(pc+2);
nkeynes@409
  1315
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1316
	return 4;
nkeynes@374
  1317
    }
nkeynes@374
  1318
:}
nkeynes@374
  1319
BSR disp {:  
nkeynes@374
  1320
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1321
	SLOTILLEGAL();
nkeynes@374
  1322
    } else {
nkeynes@374
  1323
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1324
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1325
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1326
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1327
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1328
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1329
	return 4;
nkeynes@374
  1330
    }
nkeynes@374
  1331
:}
nkeynes@374
  1332
BSRF Rn {:  
nkeynes@374
  1333
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1334
	SLOTILLEGAL();
nkeynes@374
  1335
    } else {
nkeynes@408
  1336
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1337
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1338
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1339
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1340
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1341
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1342
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1343
	exit_block_pcset(pc+2);
nkeynes@409
  1344
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1345
	return 4;
nkeynes@374
  1346
    }
nkeynes@374
  1347
:}
nkeynes@374
  1348
BT disp {:
nkeynes@374
  1349
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1350
	SLOTILLEGAL();
nkeynes@374
  1351
    } else {
nkeynes@527
  1352
	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1353
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1354
	JMP_TARGET(nottaken);
nkeynes@408
  1355
	return 2;
nkeynes@374
  1356
    }
nkeynes@374
  1357
:}
nkeynes@374
  1358
BT/S disp {:
nkeynes@374
  1359
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1360
	SLOTILLEGAL();
nkeynes@374
  1361
    } else {
nkeynes@408
  1362
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1363
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1364
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1365
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1366
	}
nkeynes@417
  1367
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1368
	sh4_translate_instruction(pc+2);
nkeynes@408
  1369
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1370
	// not taken
nkeynes@408
  1371
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1372
	sh4_translate_instruction(pc+2);
nkeynes@408
  1373
	return 4;
nkeynes@374
  1374
    }
nkeynes@374
  1375
:}
nkeynes@374
  1376
JMP @Rn {:  
nkeynes@374
  1377
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1378
	SLOTILLEGAL();
nkeynes@374
  1379
    } else {
nkeynes@408
  1380
	load_reg( R_ECX, Rn );
nkeynes@408
  1381
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1382
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1383
	sh4_translate_instruction(pc+2);
nkeynes@408
  1384
	exit_block_pcset(pc+2);
nkeynes@409
  1385
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1386
	return 4;
nkeynes@374
  1387
    }
nkeynes@374
  1388
:}
nkeynes@374
  1389
JSR @Rn {:  
nkeynes@374
  1390
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1391
	SLOTILLEGAL();
nkeynes@374
  1392
    } else {
nkeynes@374
  1393
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1394
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1395
	load_reg( R_ECX, Rn );
nkeynes@408
  1396
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1397
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1398
	sh4_translate_instruction(pc+2);
nkeynes@408
  1399
	exit_block_pcset(pc+2);
nkeynes@409
  1400
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1401
	return 4;
nkeynes@374
  1402
    }
nkeynes@374
  1403
:}
nkeynes@374
  1404
RTE {:  
nkeynes@374
  1405
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1406
	SLOTILLEGAL();
nkeynes@374
  1407
    } else {
nkeynes@408
  1408
	check_priv();
nkeynes@408
  1409
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1410
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1411
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1412
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1413
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1414
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1415
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1416
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1417
	sh4_translate_instruction(pc+2);
nkeynes@408
  1418
	exit_block_pcset(pc+2);
nkeynes@409
  1419
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1420
	return 4;
nkeynes@374
  1421
    }
nkeynes@374
  1422
:}
nkeynes@374
  1423
RTS {:  
nkeynes@374
  1424
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1425
	SLOTILLEGAL();
nkeynes@374
  1426
    } else {
nkeynes@408
  1427
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1428
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1429
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1430
	sh4_translate_instruction(pc+2);
nkeynes@408
  1431
	exit_block_pcset(pc+2);
nkeynes@409
  1432
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1433
	return 4;
nkeynes@374
  1434
    }
nkeynes@374
  1435
:}
nkeynes@374
  1436
TRAPA #imm {:  
nkeynes@374
  1437
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1438
	SLOTILLEGAL();
nkeynes@374
  1439
    } else {
nkeynes@533
  1440
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1441
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1442
	load_imm32( R_EAX, imm );
nkeynes@527
  1443
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1444
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1445
	exit_block_pcset(pc);
nkeynes@409
  1446
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1447
	return 2;
nkeynes@374
  1448
    }
nkeynes@374
  1449
:}
nkeynes@374
  1450
UNDEF {:  
nkeynes@374
  1451
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1452
	SLOTILLEGAL();
nkeynes@374
  1453
    } else {
nkeynes@559
  1454
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1455
	return 2;
nkeynes@374
  1456
    }
nkeynes@368
  1457
:}
nkeynes@374
  1458
nkeynes@374
  1459
CLRMAC {:  
nkeynes@374
  1460
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1461
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1462
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1464
:}
nkeynes@374
  1465
CLRS {:
nkeynes@374
  1466
    CLC();
nkeynes@374
  1467
    SETC_sh4r(R_S);
nkeynes@417
  1468
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1469
:}
nkeynes@374
  1470
CLRT {:  
nkeynes@374
  1471
    CLC();
nkeynes@374
  1472
    SETC_t();
nkeynes@417
  1473
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1474
:}
nkeynes@374
  1475
SETS {:  
nkeynes@374
  1476
    STC();
nkeynes@374
  1477
    SETC_sh4r(R_S);
nkeynes@417
  1478
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1479
:}
nkeynes@374
  1480
SETT {:  
nkeynes@374
  1481
    STC();
nkeynes@374
  1482
    SETC_t();
nkeynes@417
  1483
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1484
:}
nkeynes@359
  1485
nkeynes@375
  1486
/* Floating point moves */
nkeynes@375
  1487
FMOV FRm, FRn {:  
nkeynes@375
  1488
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1489
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1490
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1491
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1492
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1493
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1494
     */
nkeynes@377
  1495
    check_fpuen();
nkeynes@375
  1496
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1497
    load_fr_bank( R_EDX );
nkeynes@375
  1498
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1499
    JNE_rel8(8, doublesize);
nkeynes@375
  1500
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1501
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1502
    if( FRm&1 ) {
nkeynes@386
  1503
	JMP_rel8(24, end);
nkeynes@380
  1504
	JMP_TARGET(doublesize);
nkeynes@375
  1505
	load_xf_bank( R_ECX ); 
nkeynes@375
  1506
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1507
	if( FRn&1 ) {
nkeynes@375
  1508
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1509
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1510
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1511
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1512
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1513
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1514
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1515
	}
nkeynes@380
  1516
	JMP_TARGET(end);
nkeynes@375
  1517
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1518
	if( FRn&1 ) {
nkeynes@386
  1519
	    JMP_rel8(24, end);
nkeynes@375
  1520
	    load_xf_bank( R_ECX );
nkeynes@375
  1521
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1522
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1523
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1524
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1525
	    JMP_TARGET(end);
nkeynes@375
  1526
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1527
	    JMP_rel8(12, end);
nkeynes@375
  1528
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1529
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1530
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1531
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1532
	    JMP_TARGET(end);
nkeynes@375
  1533
	}
nkeynes@375
  1534
    }
nkeynes@417
  1535
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1536
:}
nkeynes@416
  1537
FMOV FRm, @Rn {: 
nkeynes@559
  1538
    check_fpuen();
nkeynes@416
  1539
    load_reg( R_ECX, Rn );
nkeynes@416
  1540
    check_walign32( R_ECX );
nkeynes@416
  1541
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1542
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1543
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1544
    load_fr_bank( R_EDX );
nkeynes@416
  1545
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1546
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1547
    if( FRm&1 ) {
nkeynes@527
  1548
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1549
	JMP_TARGET(doublesize);
nkeynes@416
  1550
	load_xf_bank( R_EDX );
nkeynes@416
  1551
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1552
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1553
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1554
	JMP_TARGET(end);
nkeynes@375
  1555
    } else {
nkeynes@527
  1556
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1557
	JMP_TARGET(doublesize);
nkeynes@416
  1558
	load_fr_bank( R_EDX );
nkeynes@416
  1559
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1560
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1561
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1562
	JMP_TARGET(end);
nkeynes@375
  1563
    }
nkeynes@417
  1564
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1565
:}
nkeynes@375
  1566
FMOV @Rm, FRn {:  
nkeynes@559
  1567
    check_fpuen();
nkeynes@416
  1568
    load_reg( R_ECX, Rm );
nkeynes@416
  1569
    check_ralign32( R_ECX );
nkeynes@416
  1570
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1571
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1572
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1573
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1574
    load_fr_bank( R_EDX );
nkeynes@416
  1575
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1576
    if( FRn&1 ) {
nkeynes@527
  1577
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1578
	JMP_TARGET(doublesize);
nkeynes@416
  1579
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1580
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1581
	load_xf_bank( R_EDX );
nkeynes@416
  1582
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1583
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1584
	JMP_TARGET(end);
nkeynes@375
  1585
    } else {
nkeynes@527
  1586
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1587
	JMP_TARGET(doublesize);
nkeynes@416
  1588
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1589
	load_fr_bank( R_EDX );
nkeynes@416
  1590
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1591
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1592
	JMP_TARGET(end);
nkeynes@375
  1593
    }
nkeynes@417
  1594
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1595
:}
nkeynes@377
  1596
FMOV FRm, @-Rn {:  
nkeynes@559
  1597
    check_fpuen();
nkeynes@416
  1598
    load_reg( R_ECX, Rn );
nkeynes@416
  1599
    check_walign32( R_ECX );
nkeynes@416
  1600
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1601
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1602
    JNE_rel8(14 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1603
    load_fr_bank( R_EDX );
nkeynes@416
  1604
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1605
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1606
    store_reg( R_ECX, Rn );
nkeynes@416
  1607
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1608
    if( FRm&1 ) {
nkeynes@527
  1609
	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1610
	JMP_TARGET(doublesize);
nkeynes@416
  1611
	load_xf_bank( R_EDX );
nkeynes@416
  1612
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1613
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1614
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1615
	store_reg( R_ECX, Rn );
nkeynes@416
  1616
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1617
	JMP_TARGET(end);
nkeynes@377
  1618
    } else {
nkeynes@527
  1619
	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1620
	JMP_TARGET(doublesize);
nkeynes@416
  1621
	load_fr_bank( R_EDX );
nkeynes@416
  1622
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1623
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1624
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1625
	store_reg( R_ECX, Rn );
nkeynes@416
  1626
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1627
	JMP_TARGET(end);
nkeynes@377
  1628
    }
nkeynes@417
  1629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1630
:}
nkeynes@416
  1631
FMOV @Rm+, FRn {:
nkeynes@559
  1632
    check_fpuen();
nkeynes@416
  1633
    load_reg( R_ECX, Rm );
nkeynes@416
  1634
    check_ralign32( R_ECX );
nkeynes@416
  1635
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1636
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1637
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1638
    JNE_rel8(14 + MEM_READ_SIZE, doublesize);
nkeynes@377
  1639
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1640
    store_reg( R_EAX, Rm );
nkeynes@416
  1641
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1642
    load_fr_bank( R_EDX );
nkeynes@416
  1643
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1644
    if( FRn&1 ) {
nkeynes@527
  1645
	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1646
	JMP_TARGET(doublesize);
nkeynes@377
  1647
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1648
	store_reg(R_EAX, Rm);
nkeynes@416
  1649
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1650
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1651
	load_xf_bank( R_EDX );
nkeynes@416
  1652
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1653
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1654
	JMP_TARGET(end);
nkeynes@377
  1655
    } else {
nkeynes@527
  1656
	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@377
  1657
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1658
	store_reg(R_EAX, Rm);
nkeynes@416
  1659
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1660
	load_fr_bank( R_EDX );
nkeynes@416
  1661
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1662
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1663
	JMP_TARGET(end);
nkeynes@377
  1664
    }
nkeynes@417
  1665
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1666
:}
nkeynes@377
  1667
FMOV FRm, @(R0, Rn) {:  
nkeynes@559
  1668
    check_fpuen();
nkeynes@416
  1669
    load_reg( R_ECX, Rn );
nkeynes@416
  1670
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1671
    check_walign32( R_ECX );
nkeynes@416
  1672
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1673
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1674
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1675
    load_fr_bank( R_EDX );
nkeynes@416
  1676
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1677
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1678
    if( FRm&1 ) {
nkeynes@527
  1679
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1680
	JMP_TARGET(doublesize);
nkeynes@416
  1681
	load_xf_bank( R_EDX );
nkeynes@416
  1682
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1683
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1684
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1685
	JMP_TARGET(end);
nkeynes@377
  1686
    } else {
nkeynes@527
  1687
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1688
	JMP_TARGET(doublesize);
nkeynes@416
  1689
	load_fr_bank( R_EDX );
nkeynes@416
  1690
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1691
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1692
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1693
	JMP_TARGET(end);
nkeynes@377
  1694
    }
nkeynes@417
  1695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1696
:}
nkeynes@377
  1697
FMOV @(R0, Rm), FRn {:  
nkeynes@559
  1698
    check_fpuen();
nkeynes@416
  1699
    load_reg( R_ECX, Rm );
nkeynes@416
  1700
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1701
    check_ralign32( R_ECX );
nkeynes@416
  1702
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1703
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1704
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1705
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1706
    load_fr_bank( R_EDX );
nkeynes@416
  1707
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1708
    if( FRn&1 ) {
nkeynes@527
  1709
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1710
	JMP_TARGET(doublesize);
nkeynes@416
  1711
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1712
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1713
	load_xf_bank( R_EDX );
nkeynes@416
  1714
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1715
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1716
	JMP_TARGET(end);
nkeynes@377
  1717
    } else {
nkeynes@527
  1718
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1719
	JMP_TARGET(doublesize);
nkeynes@416
  1720
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1721
	load_fr_bank( R_EDX );
nkeynes@416
  1722
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1723
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1724
	JMP_TARGET(end);
nkeynes@377
  1725
    }
nkeynes@417
  1726
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1727
:}
nkeynes@377
  1728
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1729
    check_fpuen();
nkeynes@377
  1730
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1731
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1732
    JNE_rel8(8, end);
nkeynes@377
  1733
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1734
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1735
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1736
    JMP_TARGET(end);
nkeynes@417
  1737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1738
:}
nkeynes@377
  1739
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1740
    check_fpuen();
nkeynes@377
  1741
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1742
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1743
    JNE_rel8(11, end);
nkeynes@377
  1744
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1745
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1746
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1747
    JMP_TARGET(end);
nkeynes@417
  1748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1749
:}
nkeynes@377
  1750
nkeynes@377
  1751
FLOAT FPUL, FRn {:  
nkeynes@377
  1752
    check_fpuen();
nkeynes@377
  1753
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1754
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1755
    FILD_sh4r(R_FPUL);
nkeynes@377
  1756
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1757
    JNE_rel8(5, doubleprec);
nkeynes@377
  1758
    pop_fr( R_EDX, FRn );
nkeynes@380
  1759
    JMP_rel8(3, end);
nkeynes@380
  1760
    JMP_TARGET(doubleprec);
nkeynes@377
  1761
    pop_dr( R_EDX, FRn );
nkeynes@380
  1762
    JMP_TARGET(end);
nkeynes@417
  1763
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1764
:}
nkeynes@377
  1765
FTRC FRm, FPUL {:  
nkeynes@377
  1766
    check_fpuen();
nkeynes@388
  1767
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1768
    load_fr_bank( R_EDX );
nkeynes@388
  1769
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1770
    JNE_rel8(5, doubleprec);
nkeynes@388
  1771
    push_fr( R_EDX, FRm );
nkeynes@388
  1772
    JMP_rel8(3, doop);
nkeynes@388
  1773
    JMP_TARGET(doubleprec);
nkeynes@388
  1774
    push_dr( R_EDX, FRm );
nkeynes@388
  1775
    JMP_TARGET( doop );
nkeynes@388
  1776
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1777
    FILD_r32ind( R_ECX );
nkeynes@388
  1778
    FCOMIP_st(1);
nkeynes@394
  1779
    JNA_rel8( 32, sat );
nkeynes@388
  1780
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1781
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1782
    FCOMIP_st(1);                   // 2
nkeynes@394
  1783
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1784
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1785
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1786
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1787
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1788
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1789
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1790
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1791
nkeynes@388
  1792
    JMP_TARGET(sat);
nkeynes@388
  1793
    JMP_TARGET(sat2);
nkeynes@388
  1794
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1795
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1796
    FPOP_st();
nkeynes@388
  1797
    JMP_TARGET(end);
nkeynes@417
  1798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1799
:}
nkeynes@377
  1800
FLDS FRm, FPUL {:  
nkeynes@377
  1801
    check_fpuen();
nkeynes@377
  1802
    load_fr_bank( R_ECX );
nkeynes@377
  1803
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1804
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1806
:}
nkeynes@377
  1807
FSTS FPUL, FRn {:  
nkeynes@377
  1808
    check_fpuen();
nkeynes@377
  1809
    load_fr_bank( R_ECX );
nkeynes@377
  1810
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1811
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1812
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1813
:}
nkeynes@377
  1814
FCNVDS FRm, FPUL {:  
nkeynes@377
  1815
    check_fpuen();
nkeynes@377
  1816
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1817
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1818
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1819
    load_fr_bank( R_ECX );
nkeynes@377
  1820
    push_dr( R_ECX, FRm );
nkeynes@377
  1821
    pop_fpul();
nkeynes@380
  1822
    JMP_TARGET(end);
nkeynes@417
  1823
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1824
:}
nkeynes@377
  1825
FCNVSD FPUL, FRn {:  
nkeynes@377
  1826
    check_fpuen();
nkeynes@377
  1827
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1828
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1829
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1830
    load_fr_bank( R_ECX );
nkeynes@377
  1831
    push_fpul();
nkeynes@377
  1832
    pop_dr( R_ECX, FRn );
nkeynes@380
  1833
    JMP_TARGET(end);
nkeynes@417
  1834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1835
:}
nkeynes@375
  1836
nkeynes@359
  1837
/* Floating point instructions */
nkeynes@374
  1838
FABS FRn {:  
nkeynes@377
  1839
    check_fpuen();
nkeynes@374
  1840
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1841
    load_fr_bank( R_EDX );
nkeynes@374
  1842
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1843
    JNE_rel8(10, doubleprec);
nkeynes@374
  1844
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1845
    FABS_st0(); // 2
nkeynes@374
  1846
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1847
    JMP_rel8(8,end); // 2
nkeynes@380
  1848
    JMP_TARGET(doubleprec);
nkeynes@374
  1849
    push_dr(R_EDX, FRn);
nkeynes@374
  1850
    FABS_st0();
nkeynes@374
  1851
    pop_dr(R_EDX, FRn);
nkeynes@380
  1852
    JMP_TARGET(end);
nkeynes@417
  1853
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1854
:}
nkeynes@377
  1855
FADD FRm, FRn {:  
nkeynes@377
  1856
    check_fpuen();
nkeynes@375
  1857
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1858
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1859
    load_fr_bank( R_EDX );
nkeynes@380
  1860
    JNE_rel8(13,doubleprec);
nkeynes@377
  1861
    push_fr(R_EDX, FRm);
nkeynes@377
  1862
    push_fr(R_EDX, FRn);
nkeynes@377
  1863
    FADDP_st(1);
nkeynes@377
  1864
    pop_fr(R_EDX, FRn);
nkeynes@380
  1865
    JMP_rel8(11,end);
nkeynes@380
  1866
    JMP_TARGET(doubleprec);
nkeynes@377
  1867
    push_dr(R_EDX, FRm);
nkeynes@377
  1868
    push_dr(R_EDX, FRn);
nkeynes@377
  1869
    FADDP_st(1);
nkeynes@377
  1870
    pop_dr(R_EDX, FRn);
nkeynes@380
  1871
    JMP_TARGET(end);
nkeynes@417
  1872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1873
:}
nkeynes@377
  1874
FDIV FRm, FRn {:  
nkeynes@377
  1875
    check_fpuen();
nkeynes@375
  1876
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1877
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1878
    load_fr_bank( R_EDX );
nkeynes@380
  1879
    JNE_rel8(13, doubleprec);
nkeynes@377
  1880
    push_fr(R_EDX, FRn);
nkeynes@377
  1881
    push_fr(R_EDX, FRm);
nkeynes@377
  1882
    FDIVP_st(1);
nkeynes@377
  1883
    pop_fr(R_EDX, FRn);
nkeynes@380
  1884
    JMP_rel8(11, end);
nkeynes@380
  1885
    JMP_TARGET(doubleprec);
nkeynes@377
  1886
    push_dr(R_EDX, FRn);
nkeynes@377
  1887
    push_dr(R_EDX, FRm);
nkeynes@377
  1888
    FDIVP_st(1);
nkeynes@377
  1889
    pop_dr(R_EDX, FRn);
nkeynes@380
  1890
    JMP_TARGET(end);
nkeynes@417
  1891
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1892
:}
nkeynes@375
  1893
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1894
    check_fpuen();
nkeynes@375
  1895
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1896
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1897
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1898
    JNE_rel8(18, doubleprec);
nkeynes@375
  1899
    push_fr( R_EDX, 0 );
nkeynes@375
  1900
    push_fr( R_EDX, FRm );
nkeynes@375
  1901
    FMULP_st(1);
nkeynes@375
  1902
    push_fr( R_EDX, FRn );
nkeynes@375
  1903
    FADDP_st(1);
nkeynes@375
  1904
    pop_fr( R_EDX, FRn );
nkeynes@380
  1905
    JMP_rel8(16, end);
nkeynes@380
  1906
    JMP_TARGET(doubleprec);
nkeynes@375
  1907
    push_dr( R_EDX, 0 );
nkeynes@375
  1908
    push_dr( R_EDX, FRm );
nkeynes@375
  1909
    FMULP_st(1);
nkeynes@375
  1910
    push_dr( R_EDX, FRn );
nkeynes@375
  1911
    FADDP_st(1);
nkeynes@375
  1912
    pop_dr( R_EDX, FRn );
nkeynes@380
  1913
    JMP_TARGET(end);
nkeynes@417
  1914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1915
:}
nkeynes@375
  1916
nkeynes@377
  1917
FMUL FRm, FRn {:  
nkeynes@377
  1918
    check_fpuen();
nkeynes@377
  1919
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1920
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1921
    load_fr_bank( R_EDX );
nkeynes@380
  1922
    JNE_rel8(13, doubleprec);
nkeynes@377
  1923
    push_fr(R_EDX, FRm);
nkeynes@377
  1924
    push_fr(R_EDX, FRn);
nkeynes@377
  1925
    FMULP_st(1);
nkeynes@377
  1926
    pop_fr(R_EDX, FRn);
nkeynes@380
  1927
    JMP_rel8(11, end);
nkeynes@380
  1928
    JMP_TARGET(doubleprec);
nkeynes@377
  1929
    push_dr(R_EDX, FRm);
nkeynes@377
  1930
    push_dr(R_EDX, FRn);
nkeynes@377
  1931
    FMULP_st(1);
nkeynes@377
  1932
    pop_dr(R_EDX, FRn);
nkeynes@380
  1933
    JMP_TARGET(end);
nkeynes@417
  1934
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1935
:}
nkeynes@377
  1936
FNEG FRn {:  
nkeynes@377
  1937
    check_fpuen();
nkeynes@377
  1938
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1939
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1940
    load_fr_bank( R_EDX );
nkeynes@380
  1941
    JNE_rel8(10, doubleprec);
nkeynes@377
  1942
    push_fr(R_EDX, FRn);
nkeynes@377
  1943
    FCHS_st0();
nkeynes@377
  1944
    pop_fr(R_EDX, FRn);
nkeynes@380
  1945
    JMP_rel8(8, end);
nkeynes@380
  1946
    JMP_TARGET(doubleprec);
nkeynes@377
  1947
    push_dr(R_EDX, FRn);
nkeynes@377
  1948
    FCHS_st0();
nkeynes@377
  1949
    pop_dr(R_EDX, FRn);
nkeynes@380
  1950
    JMP_TARGET(end);
nkeynes@417
  1951
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1952
:}
nkeynes@377
  1953
FSRRA FRn {:  
nkeynes@377
  1954
    check_fpuen();
nkeynes@377
  1955
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1956
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1957
    load_fr_bank( R_EDX );
nkeynes@380
  1958
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1959
    FLD1_st0();
nkeynes@377
  1960
    push_fr(R_EDX, FRn);
nkeynes@377
  1961
    FSQRT_st0();
nkeynes@377
  1962
    FDIVP_st(1);
nkeynes@377
  1963
    pop_fr(R_EDX, FRn);
nkeynes@380
  1964
    JMP_TARGET(end);
nkeynes@417
  1965
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1966
:}
nkeynes@377
  1967
FSQRT FRn {:  
nkeynes@377
  1968
    check_fpuen();
nkeynes@377
  1969
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1970
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1971
    load_fr_bank( R_EDX );
nkeynes@380
  1972
    JNE_rel8(10, doubleprec);
nkeynes@377
  1973
    push_fr(R_EDX, FRn);
nkeynes@377
  1974
    FSQRT_st0();
nkeynes@377
  1975
    pop_fr(R_EDX, FRn);
nkeynes@380
  1976
    JMP_rel8(8, end);
nkeynes@380
  1977
    JMP_TARGET(doubleprec);
nkeynes@377
  1978
    push_dr(R_EDX, FRn);
nkeynes@377
  1979
    FSQRT_st0();
nkeynes@377
  1980
    pop_dr(R_EDX, FRn);
nkeynes@380
  1981
    JMP_TARGET(end);
nkeynes@417
  1982
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1983
:}
nkeynes@377
  1984
FSUB FRm, FRn {:  
nkeynes@377
  1985
    check_fpuen();
nkeynes@377
  1986
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1987
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1988
    load_fr_bank( R_EDX );
nkeynes@380
  1989
    JNE_rel8(13, doubleprec);
nkeynes@377
  1990
    push_fr(R_EDX, FRn);
nkeynes@377
  1991
    push_fr(R_EDX, FRm);
nkeynes@388
  1992
    FSUBP_st(1);
nkeynes@377
  1993
    pop_fr(R_EDX, FRn);
nkeynes@380
  1994
    JMP_rel8(11, end);
nkeynes@380
  1995
    JMP_TARGET(doubleprec);
nkeynes@377
  1996
    push_dr(R_EDX, FRn);
nkeynes@377
  1997
    push_dr(R_EDX, FRm);
nkeynes@388
  1998
    FSUBP_st(1);
nkeynes@377
  1999
    pop_dr(R_EDX, FRn);
nkeynes@380
  2000
    JMP_TARGET(end);
nkeynes@417
  2001
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2002
:}
nkeynes@377
  2003
nkeynes@377
  2004
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2005
    check_fpuen();
nkeynes@377
  2006
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2007
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2008
    load_fr_bank( R_EDX );
nkeynes@380
  2009
    JNE_rel8(8, doubleprec);
nkeynes@377
  2010
    push_fr(R_EDX, FRm);
nkeynes@377
  2011
    push_fr(R_EDX, FRn);
nkeynes@380
  2012
    JMP_rel8(6, end);
nkeynes@380
  2013
    JMP_TARGET(doubleprec);
nkeynes@377
  2014
    push_dr(R_EDX, FRm);
nkeynes@377
  2015
    push_dr(R_EDX, FRn);
nkeynes@382
  2016
    JMP_TARGET(end);
nkeynes@377
  2017
    FCOMIP_st(1);
nkeynes@377
  2018
    SETE_t();
nkeynes@377
  2019
    FPOP_st();
nkeynes@417
  2020
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2021
:}
nkeynes@377
  2022
FCMP/GT FRm, FRn {:  
nkeynes@377
  2023
    check_fpuen();
nkeynes@377
  2024
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2025
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2026
    load_fr_bank( R_EDX );
nkeynes@380
  2027
    JNE_rel8(8, doubleprec);
nkeynes@377
  2028
    push_fr(R_EDX, FRm);
nkeynes@377
  2029
    push_fr(R_EDX, FRn);
nkeynes@380
  2030
    JMP_rel8(6, end);
nkeynes@380
  2031
    JMP_TARGET(doubleprec);
nkeynes@377
  2032
    push_dr(R_EDX, FRm);
nkeynes@377
  2033
    push_dr(R_EDX, FRn);
nkeynes@380
  2034
    JMP_TARGET(end);
nkeynes@377
  2035
    FCOMIP_st(1);
nkeynes@377
  2036
    SETA_t();
nkeynes@377
  2037
    FPOP_st();
nkeynes@417
  2038
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2039
:}
nkeynes@377
  2040
nkeynes@377
  2041
FSCA FPUL, FRn {:  
nkeynes@377
  2042
    check_fpuen();
nkeynes@388
  2043
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2044
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2045
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2046
    load_fr_bank( R_ECX );
nkeynes@388
  2047
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2048
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2049
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2050
    JMP_TARGET(doubleprec);
nkeynes@417
  2051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2052
:}
nkeynes@377
  2053
FIPR FVm, FVn {:  
nkeynes@377
  2054
    check_fpuen();
nkeynes@388
  2055
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2056
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2057
    JNE_rel8(44, doubleprec);
nkeynes@388
  2058
    
nkeynes@388
  2059
    load_fr_bank( R_ECX );
nkeynes@388
  2060
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2061
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2062
    FMULP_st(1);
nkeynes@388
  2063
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2064
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2065
    FMULP_st(1);
nkeynes@388
  2066
    FADDP_st(1);
nkeynes@388
  2067
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2068
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2069
    FMULP_st(1);
nkeynes@388
  2070
    FADDP_st(1);
nkeynes@388
  2071
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2072
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2073
    FMULP_st(1);
nkeynes@388
  2074
    FADDP_st(1);
nkeynes@388
  2075
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2076
    JMP_TARGET(doubleprec);
nkeynes@417
  2077
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2078
:}
nkeynes@377
  2079
FTRV XMTRX, FVn {:  
nkeynes@377
  2080
    check_fpuen();
nkeynes@388
  2081
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2082
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2083
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2084
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2085
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2086
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2087
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2088
    JMP_TARGET(doubleprec);
nkeynes@417
  2089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2090
:}
nkeynes@377
  2091
nkeynes@377
  2092
FRCHG {:  
nkeynes@377
  2093
    check_fpuen();
nkeynes@377
  2094
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2095
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2096
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2097
    update_fr_bank( R_ECX );
nkeynes@417
  2098
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2099
:}
nkeynes@377
  2100
FSCHG {:  
nkeynes@377
  2101
    check_fpuen();
nkeynes@377
  2102
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2103
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2104
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2106
:}
nkeynes@359
  2107
nkeynes@359
  2108
/* Processor control instructions */
nkeynes@368
  2109
LDC Rm, SR {:
nkeynes@386
  2110
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2111
	SLOTILLEGAL();
nkeynes@386
  2112
    } else {
nkeynes@386
  2113
	check_priv();
nkeynes@386
  2114
	load_reg( R_EAX, Rm );
nkeynes@386
  2115
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2116
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2117
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2118
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2119
    }
nkeynes@368
  2120
:}
nkeynes@359
  2121
LDC Rm, GBR {: 
nkeynes@359
  2122
    load_reg( R_EAX, Rm );
nkeynes@359
  2123
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2124
:}
nkeynes@359
  2125
LDC Rm, VBR {:  
nkeynes@386
  2126
    check_priv();
nkeynes@359
  2127
    load_reg( R_EAX, Rm );
nkeynes@359
  2128
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2129
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2130
:}
nkeynes@359
  2131
LDC Rm, SSR {:  
nkeynes@386
  2132
    check_priv();
nkeynes@359
  2133
    load_reg( R_EAX, Rm );
nkeynes@359
  2134
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2136
:}
nkeynes@359
  2137
LDC Rm, SGR {:  
nkeynes@386
  2138
    check_priv();
nkeynes@359
  2139
    load_reg( R_EAX, Rm );
nkeynes@359
  2140
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2141
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2142
:}
nkeynes@359
  2143
LDC Rm, SPC {:  
nkeynes@386
  2144
    check_priv();
nkeynes@359
  2145
    load_reg( R_EAX, Rm );
nkeynes@359
  2146
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2147
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2148
:}
nkeynes@359
  2149
LDC Rm, DBR {:  
nkeynes@386
  2150
    check_priv();
nkeynes@359
  2151
    load_reg( R_EAX, Rm );
nkeynes@359
  2152
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2154
:}
nkeynes@374
  2155
LDC Rm, Rn_BANK {:  
nkeynes@386
  2156
    check_priv();
nkeynes@374
  2157
    load_reg( R_EAX, Rm );
nkeynes@374
  2158
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2159
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2160
:}
nkeynes@359
  2161
LDC.L @Rm+, GBR {:  
nkeynes@359
  2162
    load_reg( R_EAX, Rm );
nkeynes@395
  2163
    check_ralign32( R_EAX );
nkeynes@359
  2164
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2165
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2166
    store_reg( R_EAX, Rm );
nkeynes@359
  2167
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2168
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2169
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2170
:}
nkeynes@368
  2171
LDC.L @Rm+, SR {:
nkeynes@386
  2172
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2173
	SLOTILLEGAL();
nkeynes@386
  2174
    } else {
nkeynes@559
  2175
	check_priv();
nkeynes@386
  2176
	load_reg( R_EAX, Rm );
nkeynes@395
  2177
	check_ralign32( R_EAX );
nkeynes@386
  2178
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2179
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2180
	store_reg( R_EAX, Rm );
nkeynes@386
  2181
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2182
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2183
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2184
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2185
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2186
    }
nkeynes@359
  2187
:}
nkeynes@359
  2188
LDC.L @Rm+, VBR {:  
nkeynes@559
  2189
    check_priv();
nkeynes@359
  2190
    load_reg( R_EAX, Rm );
nkeynes@395
  2191
    check_ralign32( R_EAX );
nkeynes@359
  2192
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2193
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2194
    store_reg( R_EAX, Rm );
nkeynes@359
  2195
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2196
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2197
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2198
:}
nkeynes@359
  2199
LDC.L @Rm+, SSR {:
nkeynes@559
  2200
    check_priv();
nkeynes@359
  2201
    load_reg( R_EAX, Rm );
nkeynes@416
  2202
    check_ralign32( R_EAX );
nkeynes@359
  2203
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2204
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2205
    store_reg( R_EAX, Rm );
nkeynes@359
  2206
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2207
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2209
:}
nkeynes@359
  2210
LDC.L @Rm+, SGR {:  
nkeynes@559
  2211
    check_priv();
nkeynes@359
  2212
    load_reg( R_EAX, Rm );
nkeynes@395
  2213
    check_ralign32( R_EAX );
nkeynes@359
  2214
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2215
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2216
    store_reg( R_EAX, Rm );
nkeynes@359
  2217
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2218
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2219
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2220
:}
nkeynes@359
  2221
LDC.L @Rm+, SPC {:  
nkeynes@559
  2222
    check_priv();
nkeynes@359
  2223
    load_reg( R_EAX, Rm );
nkeynes@395
  2224
    check_ralign32( R_EAX );
nkeynes@359
  2225
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2226
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2227
    store_reg( R_EAX, Rm );
nkeynes@359
  2228
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2229
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2230
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2231
:}
nkeynes@359
  2232
LDC.L @Rm+, DBR {:  
nkeynes@559
  2233
    check_priv();
nkeynes@359
  2234
    load_reg( R_EAX, Rm );
nkeynes@395
  2235
    check_ralign32( R_EAX );
nkeynes@359
  2236
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2237
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2238
    store_reg( R_EAX, Rm );
nkeynes@359
  2239
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2240
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2241
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2242
:}
nkeynes@359
  2243
LDC.L @Rm+, Rn_BANK {:  
nkeynes@559
  2244
    check_priv();
nkeynes@374
  2245
    load_reg( R_EAX, Rm );
nkeynes@395
  2246
    check_ralign32( R_EAX );
nkeynes@374
  2247
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2248
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2249
    store_reg( R_EAX, Rm );
nkeynes@374
  2250
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2251
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2253
:}
nkeynes@359
  2254
LDS Rm, FPSCR {:  
nkeynes@359
  2255
    load_reg( R_EAX, Rm );
nkeynes@359
  2256
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2257
    update_fr_bank( R_EAX );
nkeynes@417
  2258
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2259
:}
nkeynes@359
  2260
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2261
    load_reg( R_EAX, Rm );
nkeynes@395
  2262
    check_ralign32( R_EAX );
nkeynes@359
  2263
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2264
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2265
    store_reg( R_EAX, Rm );
nkeynes@359
  2266
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2267
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2268
    update_fr_bank( R_EAX );
nkeynes@417
  2269
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2270
:}
nkeynes@359
  2271
LDS Rm, FPUL {:  
nkeynes@359
  2272
    load_reg( R_EAX, Rm );
nkeynes@359
  2273
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2274
:}
nkeynes@359
  2275
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2276
    load_reg( R_EAX, Rm );
nkeynes@395
  2277
    check_ralign32( R_EAX );
nkeynes@359
  2278
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2279
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2280
    store_reg( R_EAX, Rm );
nkeynes@359
  2281
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2282
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2284
:}
nkeynes@359
  2285
LDS Rm, MACH {: 
nkeynes@359
  2286
    load_reg( R_EAX, Rm );
nkeynes@359
  2287
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2288
:}
nkeynes@359
  2289
LDS.L @Rm+, MACH {:  
nkeynes@359
  2290
    load_reg( R_EAX, Rm );
nkeynes@395
  2291
    check_ralign32( R_EAX );
nkeynes@359
  2292
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2293
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2294
    store_reg( R_EAX, Rm );
nkeynes@359
  2295
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2296
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2298
:}
nkeynes@359
  2299
LDS Rm, MACL {:  
nkeynes@359
  2300
    load_reg( R_EAX, Rm );
nkeynes@359
  2301
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2302
:}
nkeynes@359
  2303
LDS.L @Rm+, MACL {:  
nkeynes@359
  2304
    load_reg( R_EAX, Rm );
nkeynes@395
  2305
    check_ralign32( R_EAX );
nkeynes@359
  2306
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2307
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2308
    store_reg( R_EAX, Rm );
nkeynes@359
  2309
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2310
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2311
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2312
:}
nkeynes@359
  2313
LDS Rm, PR {:  
nkeynes@359
  2314
    load_reg( R_EAX, Rm );
nkeynes@359
  2315
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2316
:}
nkeynes@359
  2317
LDS.L @Rm+, PR {:  
nkeynes@359
  2318
    load_reg( R_EAX, Rm );
nkeynes@395
  2319
    check_ralign32( R_EAX );
nkeynes@359
  2320
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2321
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2322
    store_reg( R_EAX, Rm );
nkeynes@359
  2323
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2324
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2325
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2326
:}
nkeynes@550
  2327
LDTLB {:  
nkeynes@553
  2328
    call_func0( MMU_ldtlb );
nkeynes@550
  2329
:}
nkeynes@359
  2330
OCBI @Rn {:  :}
nkeynes@359
  2331
OCBP @Rn {:  :}
nkeynes@359
  2332
OCBWB @Rn {:  :}
nkeynes@374
  2333
PREF @Rn {:
nkeynes@374
  2334
    load_reg( R_EAX, Rn );
nkeynes@532
  2335
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2336
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2337
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
  2338
    JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
  2339
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
  2340
    JMP_TARGET(end);
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2342
:}
nkeynes@388
  2343
SLEEP {: 
nkeynes@388
  2344
    check_priv();
nkeynes@388
  2345
    call_func0( sh4_sleep );
nkeynes@417
  2346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2347
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2348
    return 2;
nkeynes@388
  2349
:}
nkeynes@386
  2350
STC SR, Rn {:
nkeynes@386
  2351
    check_priv();
nkeynes@386
  2352
    call_func0(sh4_read_sr);
nkeynes@386
  2353
    store_reg( R_EAX, Rn );
nkeynes@417
  2354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2355
:}
nkeynes@359
  2356
STC GBR, Rn {:  
nkeynes@359
  2357
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2358
    store_reg( R_EAX, Rn );
nkeynes@359
  2359
:}
nkeynes@359
  2360
STC VBR, Rn {:  
nkeynes@386
  2361
    check_priv();
nkeynes@359
  2362
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2363
    store_reg( R_EAX, Rn );
nkeynes@417
  2364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2365
:}
nkeynes@359
  2366
STC SSR, Rn {:  
nkeynes@386
  2367
    check_priv();
nkeynes@359
  2368
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2369
    store_reg( R_EAX, Rn );
nkeynes@417
  2370
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2371
:}
nkeynes@359
  2372
STC SPC, Rn {:  
nkeynes@386
  2373
    check_priv();
nkeynes@359
  2374
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2375
    store_reg( R_EAX, Rn );
nkeynes@417
  2376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2377
:}
nkeynes@359
  2378
STC SGR, Rn {:  
nkeynes@386
  2379
    check_priv();
nkeynes@359
  2380
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2381
    store_reg( R_EAX, Rn );
nkeynes@417
  2382
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2383
:}
nkeynes@359
  2384
STC DBR, Rn {:  
nkeynes@386
  2385
    check_priv();
nkeynes@359
  2386
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2387
    store_reg( R_EAX, Rn );
nkeynes@417
  2388
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2389
:}
nkeynes@374
  2390
STC Rm_BANK, Rn {:
nkeynes@386
  2391
    check_priv();
nkeynes@374
  2392
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2393
    store_reg( R_EAX, Rn );
nkeynes@417
  2394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2395
:}
nkeynes@374
  2396
STC.L SR, @-Rn {:
nkeynes@559
  2397
    check_priv();
nkeynes@395
  2398
    call_func0( sh4_read_sr );
nkeynes@368
  2399
    load_reg( R_ECX, Rn );
nkeynes@395
  2400
    check_walign32( R_ECX );
nkeynes@382
  2401
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2402
    store_reg( R_ECX, Rn );
nkeynes@368
  2403
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2405
:}
nkeynes@359
  2406
STC.L VBR, @-Rn {:  
nkeynes@559
  2407
    check_priv();
nkeynes@359
  2408
    load_reg( R_ECX, Rn );
nkeynes@395
  2409
    check_walign32( R_ECX );
nkeynes@382
  2410
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2411
    store_reg( R_ECX, Rn );
nkeynes@359
  2412
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2413
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2415
:}
nkeynes@359
  2416
STC.L SSR, @-Rn {:  
nkeynes@559
  2417
    check_priv();
nkeynes@359
  2418
    load_reg( R_ECX, Rn );
nkeynes@395
  2419
    check_walign32( R_ECX );
nkeynes@382
  2420
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2421
    store_reg( R_ECX, Rn );
nkeynes@359
  2422
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2423
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2425
:}
nkeynes@416
  2426
STC.L SPC, @-Rn {:
nkeynes@559
  2427
    check_priv();
nkeynes@359
  2428
    load_reg( R_ECX, Rn );
nkeynes@395
  2429
    check_walign32( R_ECX );
nkeynes@382
  2430
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2431
    store_reg( R_ECX, Rn );
nkeynes@359
  2432
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2433
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2434
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2435
:}
nkeynes@359
  2436
STC.L SGR, @-Rn {:  
nkeynes@559
  2437
    check_priv();
nkeynes@359
  2438
    load_reg( R_ECX, Rn );
nkeynes@395
  2439
    check_walign32( R_ECX );
nkeynes@382
  2440
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2441
    store_reg( R_ECX, Rn );
nkeynes@359
  2442
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2443
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2445
:}
nkeynes@359
  2446
STC.L DBR, @-Rn {:  
nkeynes@559
  2447
    check_priv();
nkeynes@359
  2448
    load_reg( R_ECX, Rn );
nkeynes@395
  2449
    check_walign32( R_ECX );
nkeynes@382
  2450
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2451
    store_reg( R_ECX, Rn );
nkeynes@359
  2452
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2453
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2455
:}
nkeynes@374
  2456
STC.L Rm_BANK, @-Rn {:  
nkeynes@559
  2457
    check_priv();
nkeynes@374
  2458
    load_reg( R_ECX, Rn );
nkeynes@395
  2459
    check_walign32( R_ECX );
nkeynes@382
  2460
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2461
    store_reg( R_ECX, Rn );
nkeynes@374
  2462
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2463
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2465
:}
nkeynes@359
  2466
STC.L GBR, @-Rn {:  
nkeynes@359
  2467
    load_reg( R_ECX, Rn );
nkeynes@395
  2468
    check_walign32( R_ECX );
nkeynes@382
  2469
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2470
    store_reg( R_ECX, Rn );
nkeynes@359
  2471
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2472
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2473
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2474
:}
nkeynes@359
  2475
STS FPSCR, Rn {:  
nkeynes@359
  2476
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2477
    store_reg( R_EAX, Rn );
nkeynes@359
  2478
:}
nkeynes@359
  2479
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2480
    load_reg( R_ECX, Rn );
nkeynes@395
  2481
    check_walign32( R_ECX );
nkeynes@382
  2482
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2483
    store_reg( R_ECX, Rn );
nkeynes@359
  2484
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2485
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2486
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2487
:}
nkeynes@359
  2488
STS FPUL, Rn {:  
nkeynes@359
  2489
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2490
    store_reg( R_EAX, Rn );
nkeynes@359
  2491
:}
nkeynes@359
  2492
STS.L FPUL, @-Rn {:  
nkeynes@359
  2493
    load_reg( R_ECX, Rn );
nkeynes@395
  2494
    check_walign32( R_ECX );
nkeynes@382
  2495
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2496
    store_reg( R_ECX, Rn );
nkeynes@359
  2497
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2498
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2499
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2500
:}
nkeynes@359
  2501
STS MACH, Rn {:  
nkeynes@359
  2502
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2503
    store_reg( R_EAX, Rn );
nkeynes@359
  2504
:}
nkeynes@359
  2505
STS.L MACH, @-Rn {:  
nkeynes@359
  2506
    load_reg( R_ECX, Rn );
nkeynes@395
  2507
    check_walign32( R_ECX );
nkeynes@382
  2508
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2509
    store_reg( R_ECX, Rn );
nkeynes@359
  2510
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2511
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2512
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2513
:}
nkeynes@359
  2514
STS MACL, Rn {:  
nkeynes@359
  2515
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2516
    store_reg( R_EAX, Rn );
nkeynes@359
  2517
:}
nkeynes@359
  2518
STS.L MACL, @-Rn {:  
nkeynes@359
  2519
    load_reg( R_ECX, Rn );
nkeynes@395
  2520
    check_walign32( R_ECX );
nkeynes@382
  2521
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2522
    store_reg( R_ECX, Rn );
nkeynes@359
  2523
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2524
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
STS PR, Rn {:  
nkeynes@359
  2528
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2529
    store_reg( R_EAX, Rn );
nkeynes@359
  2530
:}
nkeynes@359
  2531
STS.L PR, @-Rn {:  
nkeynes@359
  2532
    load_reg( R_ECX, Rn );
nkeynes@395
  2533
    check_walign32( R_ECX );
nkeynes@382
  2534
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2535
    store_reg( R_ECX, Rn );
nkeynes@359
  2536
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2537
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2538
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2539
:}
nkeynes@359
  2540
nkeynes@359
  2541
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2542
%%
nkeynes@416
  2543
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2544
    return 0;
nkeynes@359
  2545
}
.