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lxdream.org :: lxdream/src/sh4/x86op.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/x86op.h
changeset 569:a1c49e1e8776
prev561:533f6b478071
author nkeynes
date Fri Jan 04 11:54:17 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Bring icache partially into line with the mmu, a little less slow with AT off
now.
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * Definitions of x86 opcodes for use by the translator.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef __lxdream_x86op_H
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#define __lxdream_x86op_H
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#define R_NONE -1
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6 
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#define R_EDI 7 
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#ifdef DEBUG_JUMPS
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#define MARK_JMP(n,x) uint8_t *_mark_jmp_##x = xlat_output + n
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#define JMP_TARGET(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(n, x)
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#define JMP_TARGET(x)
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#endif
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#define OP(x) *xlat_output++ = (x)
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#define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
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#define OP64(x) *((uint64_t *)xlat_output) = (x); xlat_output+=8
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#if SH4_TRANSLATOR == TARGET_X86_64
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#define OPPTR(x) OP64((uint64_t)(x))
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#define STACK_ALIGN 16
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#define POP_r32(r1)           OP(0x58 + r1);
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#define POP_realigned_r32(r1)   OP(0x58 + r1); REXW(); ADD_imm8s_r32(8,R_ESP)
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#define PUSH_r32(r1)          OP(0x50 + r1);
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#define PUSH_realigned_r32(r1)  REXW(); SUB_imm8s_r32(8, R_ESP); OP(0x50 + r1)
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#define PUSH_imm32(imm)       OP(0x68); OP32(imm);
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#define PUSH_imm64(imm)       REXW(); OP(0x68); OP64(imm);
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#else
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#define OPPTR(x) OP32((uint32_t)(x))
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#define POP_realigned_r32(r1)   POP_r32(r1)
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#define PUSH_realigned_r32(r1)  PUSH_r32(r1)
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#ifdef APPLE_BUILD
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#define STACK_ALIGN 16
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#define POP_r32(r1)           OP(0x58 + r1); sh4_x86.stack_posn -= 4;
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#define PUSH_r32(r1)          OP(0x50 + r1); sh4_x86.stack_posn += 4;
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#define PUSH_imm32(imm)       OP(0x68); OP32(imm); sh4_x86.stack_posn += 4;
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#else
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#define POP_r32(r1)           OP(0x58 + r1)
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#define PUSH_r32(r1)          OP(0x50 + r1)
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#define PUSH_imm32(imm)       OP(0x68); OP32(imm)
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#endif
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#endif
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#ifdef STACK_ALIGN
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#else
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#define POP_r32(r1)           OP(0x58 + r1)
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#define PUSH_r32(r1)          OP(0x50 + r1)
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#endif
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r))
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#define R_T   REG_OFFSET(t)
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#define R_Q   REG_OFFSET(q)
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#define R_S   REG_OFFSET(s)
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#define R_M   REG_OFFSET(m)
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#define R_SR  REG_OFFSET(sr)
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#define R_GBR REG_OFFSET(gbr)
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#define R_SSR REG_OFFSET(ssr)
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#define R_SPC REG_OFFSET(spc)
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#define R_VBR REG_OFFSET(vbr)
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#define R_MACH REG_OFFSET(mac)+4
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#define R_MACL REG_OFFSET(mac)
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#define R_PC REG_OFFSET(pc)
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#define R_PR REG_OFFSET(pr)
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#define R_SGR REG_OFFSET(sgr)
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#define R_FPUL REG_OFFSET(fpul)
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#define R_FPSCR REG_OFFSET(fpscr)
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#define R_DBR REG_OFFSET(dbr)
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/**************** Basic X86 operations *********************/
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/* Note: operands follow SH4 convention (source, dest) rather than x86 
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 * conventions (dest, source)
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 */
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/* Two-reg modrm form - first arg is the r32 reg, second arg is the r/m32 reg */
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#define MODRM_r32_rm32(r1,r2) OP(0xC0 | (r1<<3) | r2)
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#define MODRM_rm32_r32(r1,r2) OP(0xC0 | (r2<<3) | r1)
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/* ebp+disp8 modrm form */
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#define MODRM_r32_ebp8(r1,disp) OP(0x45 | (r1<<3)); OP(disp)
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/* ebp+disp32 modrm form */
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#define MODRM_r32_ebp32(r1,disp) OP(0x85 | (r1<<3)); OP32(disp)
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#define MODRM_r32_sh4r(r1,disp) if(disp>127){ MODRM_r32_ebp32(r1,disp);}else{ MODRM_r32_ebp8(r1,(unsigned char)disp); }
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#define REXW() OP(0x48)
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/* Major opcodes */
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#define ADD_sh4r_r32(disp,r1) OP(0x03); MODRM_r32_sh4r(r1,disp)
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#define ADD_r32_sh4r(r1,disp) OP(0x01); MODRM_r32_sh4r(r1,disp)
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#define ADD_r32_r32(r1,r2) OP(0x03); MODRM_rm32_r32(r1,r2)
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#define ADD_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1, 0); OP(imm)
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#define ADD_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(0,disp); OP(imm)
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#define ADD_imm32_r32(imm32,r1) OP(0x81); MODRM_rm32_r32(r1,0); OP32(imm32)
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#define ADC_r32_r32(r1,r2)    OP(0x13); MODRM_rm32_r32(r1,r2)
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#define ADC_sh4r_r32(disp,r1) OP(0x13); MODRM_r32_sh4r(r1,disp)
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#define ADC_r32_sh4r(r1,disp) OP(0x11); MODRM_r32_sh4r(r1,disp)
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#define AND_r32_r32(r1,r2)    OP(0x23); MODRM_rm32_r32(r1,r2)
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#define AND_imm8_r8(imm8, r1) OP(0x80); MODRM_rm32_r32(r1,4); OP(imm8)
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#define AND_imm8s_r32(imm8,r1) OP(0x83); MODRM_rm32_r32(r1,4); OP(imm8)
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#define AND_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,4); OP32(imm)
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#define CALL_r32(r1)          OP(0xFF); MODRM_rm32_r32(r1,2)
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#define CLC()                 OP(0xF8)
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#define CMC()                 OP(0xF5)
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#define CMP_sh4r_r32(disp,r1)  OP(0x3B); MODRM_r32_sh4r(r1,disp)
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#define CMP_r32_r32(r1,r2)    OP(0x3B); MODRM_rm32_r32(r1,r2)
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#define CMP_imm32_r32(imm32, r1) OP(0x81); MODRM_rm32_r32(r1,7); OP32(imm32)
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#define CMP_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,7); OP(imm)
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#define CMP_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(7,disp) OP(imm)
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#define DEC_r32(r1)           OP(0x48+r1)
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#define IMUL_r32(r1)          OP(0xF7); MODRM_rm32_r32(r1,5)
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#define INC_r32(r1)           OP(0x40+r1)
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#define JMP_rel8(rel, label)  OP(0xEB); OP(rel); MARK_JMP(rel,label)
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#define MOV_r32_r32(r1,r2)    OP(0x89); MODRM_r32_rm32(r1,r2)
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#define MOV_r32_sh4r(r1,disp) OP(0x89); MODRM_r32_sh4r(r1,disp)
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#define MOV_moff32_EAX(off)   OP(0xA1); OPPTR(off)
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#define MOV_sh4r_r32(disp, r1)  OP(0x8B); MODRM_r32_sh4r(r1,disp)
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#define MOV_r32ind_r32(r1,r2) OP(0x8B); OP(0 + (r2<<3) + r1 )
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#define MOVSX_r8_r32(r1,r2)   OP(0x0F); OP(0xBE); MODRM_rm32_r32(r1,r2)
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#define MOVSX_r16_r32(r1,r2)  OP(0x0F); OP(0xBF); MODRM_rm32_r32(r1,r2)
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#define MOVZX_r8_r32(r1,r2)   OP(0x0F); OP(0xB6); MODRM_rm32_r32(r1,r2)
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#define MOVZX_r16_r32(r1,r2)  OP(0x0F); OP(0xB7); MODRM_rm32_r32(r1,r2)
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#define MUL_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,4)
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#define NEG_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,3)
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#define NOT_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,2)
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#define OR_r32_r32(r1,r2)     OP(0x0B); MODRM_rm32_r32(r1,r2)
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#define OR_imm8_r8(imm,r1)    OP(0x80); MODRM_rm32_r32(r1,1); OP(imm)
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#define OR_imm32_r32(imm,r1)  OP(0x81); MODRM_rm32_r32(r1,1); OP32(imm)
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#define OR_sh4r_r32(disp,r1)  OP(0x0B); MODRM_r32_sh4r(r1,disp)
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#define RCL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,2)
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#define RCR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,3)
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#define RET()                 OP(0xC3)
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#define ROL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,0)
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#define ROR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,1)
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#define SAR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,7)
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#define SAR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,7); OP(imm)
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#define SAR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,7)
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#define SBB_r32_r32(r1,r2)    OP(0x1B); MODRM_rm32_r32(r1,r2)
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#define SHL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,4)
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#define SHL_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,4)
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#define SHL_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,4); OP(imm)
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#define SHR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,5)
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#define SHR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,5)
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#define SHR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,5); OP(imm)
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#define STC()                 OP(0xF9)
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#define SUB_r32_r32(r1,r2)    OP(0x2B); MODRM_rm32_r32(r1,r2)
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#define SUB_sh4r_r32(disp,r1)  OP(0x2B); MODRM_r32_sh4r(r1, disp)
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#define SUB_imm8s_r32(imm,r1) ADD_imm8s_r32(-(imm),r1)
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#define TEST_r8_r8(r1,r2)     OP(0x84); MODRM_r32_rm32(r1,r2)
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#define TEST_r32_r32(r1,r2)   OP(0x85); MODRM_rm32_r32(r1,r2)
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#define TEST_imm8_r8(imm8,r1) OP(0xF6); MODRM_rm32_r32(r1,0); OP(imm8)
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#define TEST_imm32_r32(imm,r1) OP(0xF7); MODRM_rm32_r32(r1,0); OP32(imm)
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#define XCHG_r8_r8(r1,r2)     OP(0x86); MODRM_rm32_r32(r1,r2)
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#define XOR_r8_r8(r1,r2)      OP(0x32); MODRM_rm32_r32(r1,r2)
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#define XOR_imm8s_r32(imm,r1)   OP(0x83); MODRM_rm32_r32(r1,6); OP(imm)
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#define XOR_r32_r32(r1,r2)    OP(0x33); MODRM_rm32_r32(r1,r2)
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#define XOR_sh4r_r32(disp,r1)    OP(0x33); MODRM_r32_sh4r(r1,disp)
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#define XOR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,6); OP32(imm)
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/* Floating point ops */
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#define FABS_st0() OP(0xD9); OP(0xE1)
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#define FADDP_st(st) OP(0xDE); OP(0xC0+st)
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#define FCHS_st0() OP(0xD9); OP(0xE0)
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#define FCOMIP_st(st) OP(0xDF); OP(0xF0+st)
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#define FDIVP_st(st) OP(0xDE); OP(0xF8+st)
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#define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)
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#define FILD_r32ind(r32) OP(0xDB); OP(0x00+r32)
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#define FISTP_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(3, disp)
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#define FLD0_st0() OP(0xD9); OP(0xEE);
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#define FLD1_st0() OP(0xD9); OP(0xE8);
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#define FLDCW_r32ind(r32) OP(0xD9); OP(0x28+r32)
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#define FMULP_st(st) OP(0xDE); OP(0xC8+st)
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#define FNSTCW_r32ind(r32) OP(0xD9); OP(0x38+r32)
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#define FPOP_st()  OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
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#define FSUBP_st(st) OP(0xDE); OP(0xE8+st)
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#define FSQRT_st0() OP(0xD9); OP(0xFA)
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/* Conditional branches */
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#define JE_rel8(rel,label)   OP(0x74); OP(rel); MARK_JMP(rel,label)
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#define JA_rel8(rel,label)   OP(0x77); OP(rel); MARK_JMP(rel,label)
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#define JAE_rel8(rel,label)  OP(0x73); OP(rel); MARK_JMP(rel,label)
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#define JG_rel8(rel,label)   OP(0x7F); OP(rel); MARK_JMP(rel,label)
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#define JGE_rel8(rel,label)  OP(0x7D); OP(rel); MARK_JMP(rel,label)
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#define JC_rel8(rel,label)   OP(0x72); OP(rel); MARK_JMP(rel,label)
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#define JO_rel8(rel,label)   OP(0x70); OP(rel); MARK_JMP(rel,label)
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#define JNE_rel8(rel,label)  OP(0x75); OP(rel); MARK_JMP(rel,label)
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#define JNA_rel8(rel,label)  OP(0x76); OP(rel); MARK_JMP(rel,label)
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#define JNAE_rel8(rel,label) OP(0x72); OP(rel); MARK_JMP(rel,label)
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#define JNG_rel8(rel,label)  OP(0x7E); OP(rel); MARK_JMP(rel,label)
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#define JNGE_rel8(rel,label) OP(0x7C); OP(rel); MARK_JMP(rel,label)
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#define JNC_rel8(rel,label)  OP(0x73); OP(rel); MARK_JMP(rel,label)
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#define JNO_rel8(rel,label)  OP(0x71); OP(rel); MARK_JMP(rel,label)
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#define JNS_rel8(rel,label)  OP(0x79); OP(rel); MARK_JMP(rel,label)
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#define JS_rel8(rel,label)   OP(0x78); OP(rel); MARK_JMP(rel,label)
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/** JMP relative 8 or 32 depending on size of rel. rel offset
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 * from the start of the instruction (not end)
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 */
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#define JMP_rel(rel) if((rel)<-126||(rel)>129) { OP(0xE9); OP32((rel)-5); } else { OP(0xEB); OP((rel)-2); }
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/* 32-bit long forms w/ backpatching to an exception routine */
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#define JMP_exc(exc)  OP(0xE9); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JE_exc(exc)  OP(0x0F); OP(0x84); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JA_exc(exc)  OP(0x0F); OP(0x87); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JAE_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JG_exc(exc)  OP(0x0F); OP(0x8F); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JGE_exc(exc) OP(0x0F); OP(0x8D); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JC_exc(exc)  OP(0x0F); OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JO_exc(exc)  OP(0x0F); OP(0x80); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNE_exc(exc) OP(0x0F); OP(0x85); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNA_exc(exc) OP(0x0F); OP(0x86); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNAE_exc(exc) OP(0x0F);OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNG_exc(exc) OP(0x0F); OP(0x8E); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNGE_exc(exc) OP(0x0F);OP(0x8C); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNC_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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#define JNO_exc(exc) OP(0x0F); OP(0x81); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)
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/* Conditional moves ebp-rel */
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#define CMOVE_r32_r32(r1,r2)  OP(0x0F); OP(0x44); MODRM_rm32_r32(r1,r2)
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#define CMOVA_r32_r32(r1,r2)  OP(0x0F); OP(0x47); MODRM_rm32_r32(r1,r2)
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#define CMOVAE_r32_r32(r1,r2) OP(0x0F); OP(0x43); MODRM_rm32_r32(r1,r2)
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#define CMOVG_r32_r32(r1,r2)  OP(0x0F); OP(0x4F); MODRM_rm32_r32(r1,r2)
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#define CMOVGE_r32_r32(r1,r2)  OP(0x0F); OP(0x4D); MODRM_rm32_r32(r1,r2)
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#define CMOVC_r32_r32(r1,r2)  OP(0x0F); OP(0x42); MODRM_rm32_r32(r1,r2)
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#define CMOVO_r32_r32(r1,r2)  OP(0x0F); OP(0x40); MODRM_rm32_r32(r1,r2)
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/* Conditional setcc - writeback to sh4r.t */
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#define SETE_sh4r(disp)    OP(0x0F); OP(0x94); MODRM_r32_sh4r(0, disp);
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#define SETA_sh4r(disp)    OP(0x0F); OP(0x97); MODRM_r32_sh4r(0, disp);
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#define SETAE_sh4r(disp)   OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
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#define SETG_sh4r(disp)    OP(0x0F); OP(0x9F); MODRM_r32_sh4r(0, disp);
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#define SETGE_sh4r(disp)   OP(0x0F); OP(0x9D); MODRM_r32_sh4r(0, disp);
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#define SETC_sh4r(disp)    OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
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#define SETO_sh4r(disp)    OP(0x0F); OP(0x90); MODRM_r32_sh4r(0, disp);
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#define SETNE_sh4r(disp)   OP(0x0F); OP(0x95); MODRM_r32_sh4r(0, disp);
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#define SETNA_sh4r(disp)   OP(0x0F); OP(0x96); MODRM_r32_sh4r(0, disp);
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#define SETNAE_sh4r(disp)  OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
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#define SETNG_sh4r(disp)   OP(0x0F); OP(0x9E); MODRM_r32_sh4r(0, disp);
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#define SETNGE_sh4r(disp)  OP(0x0F); OP(0x9C); MODRM_r32_sh4r(0, disp);
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#define SETNC_sh4r(disp)   OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
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#define SETNO_sh4r(disp)   OP(0x0F); OP(0x91); MODRM_r32_sh4r(0, disp);
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#define SETE_t() SETE_sh4r(R_T)
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#define SETA_t() SETA_sh4r(R_T)
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#define SETAE_t() SETAE_sh4r(R_T)
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#define SETG_t() SETG_sh4r(R_T)
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#define SETGE_t() SETGE_sh4r(R_T)
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#define SETC_t() SETC_sh4r(R_T)
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#define SETO_t() SETO_sh4r(R_T)
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#define SETNE_t() SETNE_sh4r(R_T)
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#define SETC_r8(r1)      OP(0x0F); OP(0x92); MODRM_rm32_r32(r1, 0)
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/* Pseudo-op Load carry from T: CMP [EBP+t], #01 ; CMC */
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#define LDC_t()     OP(0x83); MODRM_r32_sh4r(7,R_T); OP(0x01); CMC()
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#endif /* !__lxdream_x86op_H */
.