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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 433:a4f61551d79d
prev373:0ac2ac96a4c5
next441:0ff0093f3088
author nkeynes
date Tue Oct 09 08:48:28 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix compilation warnings
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/**
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 * $Id: pvr2.c,v 1.46 2007-10-09 08:48:28 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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#define MAX_RENDER_BUFFERS 4
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
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static render_buffer_t pvr2_next_render_buffer( );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gboolean palette_changed; /* TRUE if palette has changed since last render */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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} pvr2_state;
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render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
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int render_buffer_count = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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	}
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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				  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_init( void )
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{
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    int i;
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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    for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
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	render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.palette_changed = FALSE;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    pvr2_ta_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_state.frame_count++;
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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{
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    if( pvr2_state.save_next_render_filename != NULL ) {
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	g_free( pvr2_state.save_next_render_filename );
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    } 
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    pvr2_state.save_next_render_filename = g_strdup(filename);
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    return TRUE;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    if( display_driver == NULL ) {
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	return; /* can't really do anything much */
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    } else if( !bEnabled ) {
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	/* Output disabled == black */
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	display_driver->display_blank( 0 ); 
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    } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
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	/* Enabled but blanked - border colour */
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	uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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	display_driver->display_blank( colour );
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    } else {
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	/* Real output - determine dimensions etc */
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	struct frame_buffer fbuf;
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	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
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	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
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	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
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	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
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	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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	fbuf.size = vid_ppl << 2 * fbuf.height;
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	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
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	/* Determine the field to display, and deinterlace if possible */
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	if( pvr2_state.interlaced ) {
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	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
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		fbuf.height = fbuf.height << 1;
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		fbuf.rowstride = vid_ppl << 2;
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		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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	    } else { 
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		/* Just display the field as is, folks. This is slightly tricky -
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		 * we pick the field based on which frame is about to come through,
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		 * which may not be the same as the odd_even_field.
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		 */
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		gboolean oddfield = pvr2_state.odd_even_field;
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		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
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		    oddfield = !oddfield;
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		}
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		if( oddfield ) {
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		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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		} else {
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		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
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		}
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	    }
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	} else {
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	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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	}
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	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
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   290
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	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
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   292
	if( rbuf != NULL ) {
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	    display_driver->display_render_buffer( rbuf );
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   294
	} else {
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	    fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
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	    display_driver->display_frame_buffer( &fbuf );
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	}
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    }
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}
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/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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 */
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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   309
        return;
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   310
    }
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   311
    
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    switch(reg) {
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    case PVRID:
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   314
    case PVRVER:
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    case GUNPOS: /* Read only registers */
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	break;
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   317
    case PVRRESET:
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   318
	val &= 0x00000007; /* Do stuff? */
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   319
	MMIO_WRITE( PVR2, reg, val );
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   320
	break;
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   321
    case RENDER_START: /* Don't really care what value */
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   322
	if( pvr2_state.save_next_render_filename != NULL ) {
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   323
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
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   324
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
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   325
	    }
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   326
	    g_free( pvr2_state.save_next_render_filename );
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   327
	    pvr2_state.save_next_render_filename = NULL;
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   328
	}
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   329
	render_buffer_t buffer = pvr2_next_render_buffer();
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   330
	if( buffer != NULL ) {
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   331
	    pvr2_render_scene( buffer );
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   332
	}
nkeynes@352
   333
	asic_event( EVENT_PVR_RENDER_DONE );
nkeynes@189
   334
	break;
nkeynes@191
   335
    case RENDER_POLYBASE:
nkeynes@191
   336
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   337
    	break;
nkeynes@191
   338
    case RENDER_TSPCFG:
nkeynes@191
   339
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   340
    	break;
nkeynes@197
   341
    case DISP_BORDER:
nkeynes@191
   342
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   343
    	break;
nkeynes@197
   344
    case DISP_MODE:
nkeynes@191
   345
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   346
    	break;
nkeynes@191
   347
    case RENDER_MODE:
nkeynes@191
   348
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   349
    	break;
nkeynes@191
   350
    case RENDER_SIZE:
nkeynes@191
   351
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   352
    	break;
nkeynes@197
   353
    case DISP_ADDR1:
nkeynes@189
   354
	val &= 0x00FFFFFC;
nkeynes@189
   355
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   356
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@108
   357
	break;
nkeynes@197
   358
    case DISP_ADDR2:
nkeynes@191
   359
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@337
   360
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@191
   361
    	break;
nkeynes@197
   362
    case DISP_SIZE:
nkeynes@191
   363
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   364
    	break;
nkeynes@191
   365
    case RENDER_ADDR1:
nkeynes@191
   366
    case RENDER_ADDR2:
nkeynes@191
   367
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   368
    	break;
nkeynes@191
   369
    case RENDER_HCLIP:
nkeynes@191
   370
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   371
	break;
nkeynes@191
   372
    case RENDER_VCLIP:
nkeynes@191
   373
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   374
	break;
nkeynes@197
   375
    case DISP_HPOSIRQ:
nkeynes@191
   376
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@304
   377
	pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@304
   378
	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@304
   379
	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@304
   380
	switch( pvr2_state.irq_hpos_mode ) {
nkeynes@304
   381
	case 3: /* Reserved - treat as 0 */
nkeynes@304
   382
	case 0: /* Once per frame at specified line */
nkeynes@304
   383
	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@304
   384
	    break;
nkeynes@304
   385
	case 2: /* Once per line - as per-line-count */
nkeynes@304
   386
	    pvr2_state.irq_hpos_line = 1;
nkeynes@304
   387
	    pvr2_state.irq_hpos_mode = 1;
nkeynes@304
   388
	case 1: /* Once per N lines */
nkeynes@304
   389
	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@304
   390
	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@304
   391
		pvr2_state.irq_hpos_line_count;
nkeynes@304
   392
	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@304
   393
		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@304
   394
	    }
nkeynes@304
   395
	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@304
   396
	}
nkeynes@304
   397
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@304
   398
					  pvr2_state.irq_hpos_time_ns );
nkeynes@189
   399
	break;
nkeynes@197
   400
    case DISP_VPOSIRQ:
nkeynes@189
   401
	val = val & 0x03FF03FF;
nkeynes@189
   402
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   403
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   404
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@304
   405
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   406
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@189
   407
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   408
	break;
nkeynes@197
   409
    case RENDER_NEARCLIP:
nkeynes@197
   410
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   411
	break;
nkeynes@191
   412
    case RENDER_SHADOW:
nkeynes@191
   413
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   414
	break;
nkeynes@191
   415
    case RENDER_OBJCFG:
nkeynes@191
   416
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   417
    	break;
nkeynes@191
   418
    case RENDER_TSPCLIP:
nkeynes@191
   419
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   420
    	break;
nkeynes@197
   421
    case RENDER_FARCLIP:
nkeynes@197
   422
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   423
	break;
nkeynes@191
   424
    case RENDER_BGPLANE:
nkeynes@191
   425
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   426
    	break;
nkeynes@191
   427
    case RENDER_ISPCFG:
nkeynes@191
   428
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   429
    	break;
nkeynes@197
   430
    case VRAM_CFG1:
nkeynes@197
   431
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   432
	break;
nkeynes@197
   433
    case VRAM_CFG2:
nkeynes@197
   434
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   435
	break;
nkeynes@197
   436
    case VRAM_CFG3:
nkeynes@197
   437
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   438
	break;
nkeynes@197
   439
    case RENDER_FOGTBLCOL:
nkeynes@197
   440
    case RENDER_FOGVRTCOL:
nkeynes@197
   441
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   442
	break;
nkeynes@197
   443
    case RENDER_FOGCOEFF:
nkeynes@197
   444
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   445
	break;
nkeynes@197
   446
    case RENDER_CLAMPHI:
nkeynes@197
   447
    case RENDER_CLAMPLO:
nkeynes@197
   448
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   449
	break;
nkeynes@261
   450
    case RENDER_TEXSIZE:
nkeynes@261
   451
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   452
	break;
nkeynes@261
   453
    case RENDER_PALETTE:
nkeynes@261
   454
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   455
	break;
nkeynes@261
   456
nkeynes@261
   457
	/********** CRTC registers *************/
nkeynes@197
   458
    case DISP_HBORDER:
nkeynes@197
   459
    case DISP_VBORDER:
nkeynes@197
   460
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   461
	break;
nkeynes@261
   462
    case DISP_TOTAL:
nkeynes@261
   463
	val = val & 0x03FF03FF;
nkeynes@261
   464
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   465
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   466
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   467
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   468
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   469
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   470
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@304
   471
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   472
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@304
   473
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@304
   474
					  pvr2_state.irq_hpos_time_ns );
nkeynes@261
   475
	break;
nkeynes@261
   476
    case DISP_SYNCCFG:
nkeynes@261
   477
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   478
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   479
	break;
nkeynes@261
   480
    case DISP_SYNCTIME:
nkeynes@261
   481
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   482
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   483
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   484
	break;
nkeynes@197
   485
    case DISP_CFG2:
nkeynes@197
   486
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   487
	break;
nkeynes@197
   488
    case DISP_HPOS:
nkeynes@261
   489
	val = val & 0x03FF;
nkeynes@261
   490
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   491
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   492
	break;
nkeynes@197
   493
    case DISP_VPOS:
nkeynes@197
   494
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   495
	break;
nkeynes@261
   496
nkeynes@261
   497
	/*********** Tile accelerator registers ***********/
nkeynes@261
   498
    case TA_POLYPOS:
nkeynes@261
   499
    case TA_LISTPOS:
nkeynes@261
   500
	/* Readonly registers */
nkeynes@197
   501
	break;
nkeynes@189
   502
    case TA_TILEBASE:
nkeynes@193
   503
    case TA_LISTEND:
nkeynes@189
   504
    case TA_LISTBASE:
nkeynes@191
   505
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   506
	break;
nkeynes@191
   507
    case RENDER_TILEBASE:
nkeynes@189
   508
    case TA_POLYBASE:
nkeynes@189
   509
    case TA_POLYEND:
nkeynes@191
   510
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   511
	break;
nkeynes@189
   512
    case TA_TILESIZE:
nkeynes@191
   513
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   514
	break;
nkeynes@189
   515
    case TA_TILECFG:
nkeynes@191
   516
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   517
	break;
nkeynes@261
   518
    case TA_INIT:
nkeynes@261
   519
	if( val & 0x80000000 )
nkeynes@261
   520
	    pvr2_ta_init();
nkeynes@261
   521
	break;
nkeynes@261
   522
    case TA_REINIT:
nkeynes@261
   523
	break;
nkeynes@261
   524
	/**************** Scaler registers? ****************/
nkeynes@335
   525
    case RENDER_SCALER:
nkeynes@261
   526
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   527
	break;
nkeynes@261
   528
nkeynes@197
   529
    case YUV_ADDR:
nkeynes@284
   530
	val = val & 0x00FFFFF8;
nkeynes@284
   531
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   532
	pvr2_yuv_init( val );
nkeynes@197
   533
	break;
nkeynes@197
   534
    case YUV_CFG:
nkeynes@197
   535
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   536
	pvr2_yuv_set_config(val);
nkeynes@197
   537
	break;
nkeynes@261
   538
nkeynes@261
   539
	/**************** Unknowns ***************/
nkeynes@261
   540
    case PVRUNK1:
nkeynes@261
   541
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   542
    	break;
nkeynes@261
   543
    case PVRUNK2:
nkeynes@261
   544
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   545
	break;
nkeynes@261
   546
    case PVRUNK3:
nkeynes@261
   547
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   548
	break;
nkeynes@261
   549
    case PVRUNK5:
nkeynes@261
   550
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   551
	break;
nkeynes@261
   552
    case PVRUNK6:
nkeynes@261
   553
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   554
	break;
nkeynes@197
   555
    case PVRUNK7:
nkeynes@197
   556
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   557
	break;
nkeynes@1
   558
    }
nkeynes@1
   559
}
nkeynes@1
   560
nkeynes@261
   561
/**
nkeynes@261
   562
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   563
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   564
 * The register reads (LSB to MSB) as:
nkeynes@261
   565
 *     0..9  Current scan line
nkeynes@261
   566
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   567
 *     11    Display active (including border and overscan)
nkeynes@261
   568
 *     12    Horizontal sync off
nkeynes@261
   569
 *     13    Vertical sync off
nkeynes@261
   570
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   571
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   572
 */
nkeynes@261
   573
uint32_t pvr2_get_sync_status()
nkeynes@261
   574
{
nkeynes@265
   575
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   576
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   577
nkeynes@265
   578
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   579
	result |= 0x0400;
nkeynes@261
   580
    }
nkeynes@265
   581
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   582
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   583
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   584
	}
nkeynes@265
   585
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   586
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   587
		result |= 0x2800; /* Display active */
nkeynes@261
   588
	    } else {
nkeynes@261
   589
		result |= 0x2000; /* Front porch */
nkeynes@261
   590
	    }
nkeynes@261
   591
	}
nkeynes@261
   592
    } else {
nkeynes@269
   593
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   594
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   595
		result |= 0x3800; /* Display active */
nkeynes@269
   596
	    } else {
nkeynes@269
   597
		result |= 0x3000;
nkeynes@269
   598
	    }
nkeynes@261
   599
	} else {
nkeynes@261
   600
	    result |= 0x1000; /* Back porch */
nkeynes@261
   601
	}
nkeynes@261
   602
    }
nkeynes@261
   603
    return result;
nkeynes@261
   604
}
nkeynes@261
   605
nkeynes@265
   606
/**
nkeynes@265
   607
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   608
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   609
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   610
 * The raster position should be updated before calling this
nkeynes@265
   611
 * method.
nkeynes@304
   612
 * @param eventid Event to fire at the specified time
nkeynes@304
   613
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   614
 *  displays). 
nkeynes@304
   615
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   616
 */
nkeynes@304
   617
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   618
{
nkeynes@265
   619
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   620
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   621
	field = !field;
nkeynes@265
   622
    }
nkeynes@304
   623
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@304
   624
	hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   625
    }
nkeynes@265
   626
nkeynes@265
   627
    line <<= 1;
nkeynes@265
   628
    if( field ) {
nkeynes@265
   629
	line += 1;
nkeynes@265
   630
    }
nkeynes@274
   631
    
nkeynes@274
   632
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   633
	uint32_t lines;
nkeynes@274
   634
	uint32_t time;
nkeynes@274
   635
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   636
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   637
	} else {
nkeynes@274
   638
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   639
	}
nkeynes@274
   640
	if( lines <= minimum_lines ) {
nkeynes@274
   641
	    lines += pvr2_state.total_lines;
nkeynes@274
   642
	}
nkeynes@304
   643
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@274
   644
	event_schedule( eventid, time );
nkeynes@274
   645
    } else {
nkeynes@274
   646
	event_cancel( eventid );
nkeynes@274
   647
    }
nkeynes@265
   648
}
nkeynes@265
   649
nkeynes@1
   650
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   651
{
nkeynes@1
   652
    switch( reg ) {
nkeynes@261
   653
        case DISP_SYNCSTAT:
nkeynes@261
   654
            return pvr2_get_sync_status();
nkeynes@1
   655
        default:
nkeynes@1
   656
            return MMIO_READ( PVR2, reg );
nkeynes@1
   657
    }
nkeynes@1
   658
}
nkeynes@19
   659
nkeynes@337
   660
MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
nkeynes@337
   661
{
nkeynes@337
   662
    MMIO_WRITE( PVR2PAL, reg, val );
nkeynes@337
   663
    pvr2_state.palette_changed = TRUE;
nkeynes@337
   664
}
nkeynes@337
   665
nkeynes@337
   666
void pvr2_check_palette_changed()
nkeynes@337
   667
{
nkeynes@337
   668
    if( pvr2_state.palette_changed ) {
nkeynes@337
   669
	texcache_invalidate_palette();
nkeynes@337
   670
	pvr2_state.palette_changed = FALSE;
nkeynes@337
   671
    }
nkeynes@337
   672
}
nkeynes@337
   673
nkeynes@337
   674
MMIO_REGION_READ_DEFFN( PVR2PAL );
nkeynes@85
   675
nkeynes@19
   676
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   677
{
nkeynes@197
   678
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   679
}
nkeynes@56
   680
nkeynes@56
   681
nkeynes@65
   682
nkeynes@98
   683
nkeynes@56
   684
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   685
{
nkeynes@56
   686
    return 0xFFFFFFFF;
nkeynes@56
   687
}
nkeynes@56
   688
nkeynes@56
   689
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   690
{
nkeynes@433
   691
    pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
nkeynes@56
   692
}
nkeynes@56
   693
nkeynes@352
   694
/**
nkeynes@352
   695
 * Find the render buffer corresponding to the requested output frame
nkeynes@352
   696
 * (does not consider texture renders). 
nkeynes@352
   697
 * @return the render_buffer if found, or null if no such buffer.
nkeynes@352
   698
 *
nkeynes@352
   699
 * Note: Currently does not consider "partial matches", ie partial
nkeynes@352
   700
 * frame overlap - it probably needs to do this.
nkeynes@352
   701
 */
nkeynes@352
   702
render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
nkeynes@352
   703
{
nkeynes@352
   704
    int i;
nkeynes@352
   705
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   706
	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
nkeynes@352
   707
	    return render_buffers[i];
nkeynes@352
   708
	}
nkeynes@352
   709
    }
nkeynes@352
   710
    return NULL;
nkeynes@352
   711
}
nkeynes@352
   712
nkeynes@352
   713
/**
nkeynes@352
   714
 * Determine the next render buffer to write into. The order of preference is:
nkeynes@352
   715
 *   1. An existing buffer with the same address. (not flushed unless the new
nkeynes@352
   716
 * size is smaller than the old one).
nkeynes@352
   717
 *   2. An existing buffer with the same size chosen by LRU order. Old buffer
nkeynes@352
   718
 *       is flushed to vram.
nkeynes@352
   719
 *   3. A new buffer if one can be created.
nkeynes@352
   720
 *   4. The current display buff
nkeynes@352
   721
 * Note: The current display field(s) will never be overwritten except as a last
nkeynes@352
   722
 * resort.
nkeynes@352
   723
 */
nkeynes@352
   724
render_buffer_t pvr2_next_render_buffer()
nkeynes@352
   725
{
nkeynes@352
   726
    render_buffer_t result = NULL;
nkeynes@352
   727
    uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
nkeynes@352
   728
    uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
nkeynes@352
   729
    uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
nkeynes@352
   730
    uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
nkeynes@433
   731
nkeynes@352
   732
    if( render_addr & 0x01000000 ) { /* vram64 */
nkeynes@352
   733
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
nkeynes@352
   734
    } else { /* vram32 */
nkeynes@352
   735
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@352
   736
    }
nkeynes@352
   737
nkeynes@352
   738
    int width, height, i;
nkeynes@352
   739
    int colour_format = pvr2_render_colour_format[render_mode&0x07];
nkeynes@352
   740
    pvr2_render_getsize( &width, &height );
nkeynes@352
   741
nkeynes@352
   742
    /* Check existing buffers for an available buffer */
nkeynes@352
   743
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   744
	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
nkeynes@352
   745
	    /* needs to be the right dimensions */
nkeynes@352
   746
	    if( render_buffers[i]->address == render_addr ) {
nkeynes@352
   747
		/* perfect */
nkeynes@352
   748
		result = render_buffers[i];
nkeynes@352
   749
		break;
nkeynes@352
   750
	    } else if( render_buffers[i]->address == -1 && result == NULL ) {
nkeynes@352
   751
		result = render_buffers[i];
nkeynes@352
   752
	    }
nkeynes@352
   753
	} else if( render_buffers[i]->address == render_addr ) {
nkeynes@352
   754
	    /* right address, wrong size - if it's larger, flush it, otherwise 
nkeynes@352
   755
	     * nuke it quietly */
nkeynes@352
   756
	    if( render_buffers[i]->width * render_buffers[i]->height >
nkeynes@352
   757
		width*height ) {
nkeynes@352
   758
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   759
	    }
nkeynes@433
   760
	    render_buffers[i]->address = -1;
nkeynes@352
   761
	}
nkeynes@352
   762
    }
nkeynes@352
   763
nkeynes@352
   764
    /* Nothing available - make one */
nkeynes@352
   765
    if( result == NULL ) {
nkeynes@352
   766
	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
nkeynes@352
   767
	    /* maximum buffers reached - need to throw one away */
nkeynes@352
   768
	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@352
   769
	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@352
   770
	    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   771
		if( render_buffers[i]->address != field1_addr &&
nkeynes@352
   772
		    render_buffers[i]->address != field2_addr ) {
nkeynes@352
   773
		    /* Never throw away the current "front buffer(s)" */
nkeynes@352
   774
		    result = render_buffers[i];
nkeynes@352
   775
		    pvr2_render_buffer_copy_to_sh4( result );
nkeynes@352
   776
		    if( result->width != width || result->height != height ) {
nkeynes@352
   777
			display_driver->destroy_render_buffer(render_buffers[i]);
nkeynes@352
   778
			result = display_driver->create_render_buffer(width,height);
nkeynes@352
   779
			render_buffers[i] = result;
nkeynes@352
   780
		    }
nkeynes@352
   781
		    break;
nkeynes@352
   782
		}
nkeynes@352
   783
	    }
nkeynes@352
   784
	} else {
nkeynes@352
   785
	    result = display_driver->create_render_buffer(width,height);
nkeynes@352
   786
	    if( result != NULL ) { 
nkeynes@352
   787
		render_buffers[render_buffer_count++] = result;
nkeynes@352
   788
	    } else {
nkeynes@373
   789
		//		ERROR( "Failed to obtain a render buffer!" );
nkeynes@352
   790
		return NULL;
nkeynes@352
   791
	    }
nkeynes@352
   792
	}
nkeynes@352
   793
    }
nkeynes@352
   794
nkeynes@352
   795
    /* Setup the buffer */
nkeynes@352
   796
    result->rowstride = render_stride;
nkeynes@352
   797
    result->colour_format = colour_format;
nkeynes@352
   798
    result->scale = render_scale;
nkeynes@352
   799
    result->size = width * height * colour_formats[colour_format].bpp;
nkeynes@352
   800
    result->address = render_addr;
nkeynes@352
   801
    result->flushed = FALSE;
nkeynes@352
   802
    return result;
nkeynes@352
   803
}
nkeynes@352
   804
nkeynes@352
   805
/**
nkeynes@352
   806
 * Invalidate any caching on the supplied address. Specifically, if it falls
nkeynes@352
   807
 * within any of the render buffers, flush the buffer back to PVR2 ram.
nkeynes@352
   808
 */
nkeynes@352
   809
gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
nkeynes@352
   810
{
nkeynes@352
   811
    int i;
nkeynes@352
   812
    address = address & 0x1FFFFFFF;
nkeynes@352
   813
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   814
	uint32_t bufaddr = render_buffers[i]->address;
nkeynes@352
   815
	if( bufaddr != -1 && bufaddr <= address && 
nkeynes@352
   816
	    (bufaddr + render_buffers[i]->size) > address ) {
nkeynes@352
   817
	    if( !render_buffers[i]->flushed ) {
nkeynes@352
   818
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   819
		render_buffers[i]->flushed = TRUE;
nkeynes@352
   820
	    }
nkeynes@352
   821
	    if( isWrite ) {
nkeynes@352
   822
		render_buffers[i]->address = -1; /* Invalid */
nkeynes@352
   823
	    }
nkeynes@352
   824
	    return TRUE; /* should never have overlapping buffers */
nkeynes@352
   825
	}
nkeynes@352
   826
    }
nkeynes@352
   827
    return FALSE;
nkeynes@352
   828
}
.