nkeynes@359 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@417 | 28 | #include "sh4/xltcache.h"
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nkeynes@368 | 29 | #include "sh4/sh4core.h"
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nkeynes@368 | 30 | #include "sh4/sh4trans.h"
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nkeynes@671 | 31 | #include "sh4/sh4stat.h"
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nkeynes@388 | 32 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 33 | #include "sh4/x86op.h"
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nkeynes@368 | 34 | #include "clock.h"
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nkeynes@368 | 35 |
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nkeynes@368 | 36 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 37 |
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nkeynes@586 | 38 | struct backpatch_record {
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nkeynes@604 | 39 | uint32_t fixup_offset;
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nkeynes@586 | 40 | uint32_t fixup_icount;
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nkeynes@596 | 41 | int32_t exc_code;
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nkeynes@586 | 42 | };
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nkeynes@586 | 43 |
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nkeynes@586 | 44 | #define MAX_RECOVERY_SIZE 2048
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nkeynes@586 | 45 |
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nkeynes@590 | 46 | #define DELAY_NONE 0
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nkeynes@590 | 47 | #define DELAY_PC 1
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nkeynes@590 | 48 | #define DELAY_PC_PR 2
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nkeynes@590 | 49 |
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nkeynes@368 | 50 | /**
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nkeynes@368 | 51 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 52 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 53 | * sh4_translate_end_block()
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nkeynes@368 | 54 | */
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nkeynes@368 | 55 | struct sh4_x86_state {
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nkeynes@590 | 56 | int in_delay_slot;
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nkeynes@368 | 57 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 58 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 59 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 60 | uint32_t block_start_pc;
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nkeynes@547 | 61 | uint32_t stack_posn; /* Trace stack height for alignment purposes */
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nkeynes@417 | 62 | int tstate;
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nkeynes@368 | 63 |
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nkeynes@586 | 64 | /* mode flags */
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nkeynes@586 | 65 | gboolean tlb_on; /* True if tlb translation is active */
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nkeynes@586 | 66 |
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nkeynes@368 | 67 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@586 | 68 | struct backpatch_record *backpatch_list;
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nkeynes@368 | 69 | uint32_t backpatch_posn;
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nkeynes@368 | 70 | uint32_t backpatch_size;
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nkeynes@368 | 71 | };
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nkeynes@368 | 72 |
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nkeynes@417 | 73 | #define TSTATE_NONE -1
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nkeynes@417 | 74 | #define TSTATE_O 0
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nkeynes@417 | 75 | #define TSTATE_C 2
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nkeynes@417 | 76 | #define TSTATE_E 4
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nkeynes@417 | 77 | #define TSTATE_NE 5
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nkeynes@417 | 78 | #define TSTATE_G 0xF
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nkeynes@417 | 79 | #define TSTATE_GE 0xD
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nkeynes@417 | 80 | #define TSTATE_A 7
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nkeynes@417 | 81 | #define TSTATE_AE 3
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nkeynes@417 | 82 |
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nkeynes@671 | 83 | #ifdef ENABLE_SH4STATS
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nkeynes@671 | 84 | #define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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nkeynes@671 | 85 | #else
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nkeynes@671 | 86 | #define COUNT_INST(id)
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nkeynes@671 | 87 | #endif
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nkeynes@671 | 88 |
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nkeynes@417 | 89 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
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nkeynes@669 | 90 | #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 91 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@669 | 92 | OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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nkeynes@669 | 93 |
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nkeynes@417 | 94 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
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nkeynes@669 | 95 | #define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 96 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@669 | 97 | OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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nkeynes@417 | 98 |
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nkeynes@368 | 99 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 100 |
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nkeynes@388 | 101 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 102 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 103 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 104 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 105 |
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nkeynes@669 | 106 | void sh4_translate_init(void)
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nkeynes@368 | 107 | {
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nkeynes@368 | 108 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@586 | 109 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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nkeynes@368 | 110 | }
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nkeynes@368 | 111 |
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nkeynes@368 | 112 |
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nkeynes@586 | 113 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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nkeynes@368 | 114 | {
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nkeynes@368 | 115 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 116 | sh4_x86.backpatch_size <<= 1;
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nkeynes@586 | 117 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
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nkeynes@586 | 118 | sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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nkeynes@368 | 119 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 120 | }
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nkeynes@586 | 121 | if( sh4_x86.in_delay_slot ) {
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nkeynes@586 | 122 | fixup_pc -= 2;
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nkeynes@586 | 123 | }
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nkeynes@604 | 124 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =
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nkeynes@604 | 125 | ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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nkeynes@586 | 126 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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nkeynes@586 | 127 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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nkeynes@586 | 128 | sh4_x86.backpatch_posn++;
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nkeynes@368 | 129 | }
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nkeynes@368 | 130 |
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nkeynes@359 | 131 | /**
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nkeynes@359 | 132 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 133 | */
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nkeynes@359 | 134 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 135 | {
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nkeynes@359 | 136 | /* mov [bp+n], reg */
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nkeynes@361 | 137 | OP(0x8B);
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nkeynes@361 | 138 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 139 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 140 | }
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nkeynes@359 | 141 |
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nkeynes@374 | 142 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 143 | {
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nkeynes@374 | 144 | OP(0x0F);
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nkeynes@374 | 145 | OP(0xBF);
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nkeynes@374 | 146 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 147 | }
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nkeynes@368 | 148 |
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nkeynes@374 | 149 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 150 | {
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nkeynes@374 | 151 | OP(0x0F);
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nkeynes@374 | 152 | OP(0xB7);
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nkeynes@374 | 153 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 154 |
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nkeynes@368 | 155 | }
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nkeynes@368 | 156 |
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nkeynes@380 | 157 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 158 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 159 | /**
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nkeynes@359 | 160 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 161 | */
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nkeynes@359 | 162 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 163 | /* mov #value, reg */
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nkeynes@359 | 164 | OP(0xB8 + x86reg);
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nkeynes@359 | 165 | OP32(value);
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nkeynes@359 | 166 | }
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nkeynes@359 | 167 |
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nkeynes@359 | 168 | /**
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nkeynes@527 | 169 | * Load an immediate 64-bit quantity (note: x86-64 only)
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nkeynes@527 | 170 | */
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nkeynes@527 | 171 | static inline void load_imm64( int x86reg, uint32_t value ) {
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nkeynes@527 | 172 | /* mov #value, reg */
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nkeynes@527 | 173 | REXW();
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nkeynes@527 | 174 | OP(0xB8 + x86reg);
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nkeynes@527 | 175 | OP64(value);
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nkeynes@527 | 176 | }
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nkeynes@527 | 177 |
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nkeynes@527 | 178 | /**
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nkeynes@359 | 179 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 180 | */
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nkeynes@359 | 181 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 182 | /* mov reg, [bp+n] */
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nkeynes@361 | 183 | OP(0x89);
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nkeynes@361 | 184 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 185 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 186 | }
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nkeynes@374 | 187 |
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nkeynes@375 | 188 | /**
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nkeynes@375 | 189 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 190 | * register (eg for register-to-register moves)
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nkeynes@375 | 191 | */
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nkeynes@669 | 192 | #define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 193 | #define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@375 | 194 |
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nkeynes@375 | 195 | /**
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nkeynes@669 | 196 | * Load the low half of a DR register (DR or XD) into an integer x86 register
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nkeynes@669 | 197 | */
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nkeynes@669 | 198 | #define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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nkeynes@669 | 199 | #define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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nkeynes@669 | 200 |
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nkeynes@669 | 201 | /**
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nkeynes@669 | 202 | * Store an FR register (single-precision floating point) from an integer x86+
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nkeynes@375 | 203 | * register (eg for register-to-register moves)
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nkeynes@375 | 204 | */
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nkeynes@669 | 205 | #define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 206 | #define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@375 | 207 |
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nkeynes@669 | 208 | #define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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nkeynes@669 | 209 | #define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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nkeynes@375 | 210 |
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nkeynes@374 | 211 |
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nkeynes@669 | 212 | #define push_fpul() FLDF_sh4r(R_FPUL)
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nkeynes@669 | 213 | #define pop_fpul() FSTPF_sh4r(R_FPUL)
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nkeynes@669 | 214 | #define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 215 | #define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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nkeynes@669 | 216 | #define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@669 | 217 | #define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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nkeynes@669 | 218 | #define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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nkeynes@669 | 219 | #define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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nkeynes@669 | 220 | #define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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nkeynes@669 | 221 | #define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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nkeynes@377 | 222 |
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nkeynes@377 | 223 |
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nkeynes@374 | 224 |
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nkeynes@368 | 225 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@416 | 226 |
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nkeynes@416 | 227 | #define check_priv( ) \
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nkeynes@416 | 228 | if( !sh4_x86.priv_checked ) { \
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nkeynes@416 | 229 | sh4_x86.priv_checked = TRUE;\
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nkeynes@416 | 230 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 231 | AND_imm32_r32( SR_MD, R_EAX );\
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nkeynes@416 | 232 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 233 | JE_exc( EXC_SLOT_ILLEGAL );\
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nkeynes@416 | 234 | } else {\
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nkeynes@586 | 235 | JE_exc( EXC_ILLEGAL );\
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nkeynes@416 | 236 | }\
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nkeynes@416 | 237 | }\
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nkeynes@416 | 238 |
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nkeynes@416 | 239 | #define check_fpuen( ) \
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nkeynes@416 | 240 | if( !sh4_x86.fpuen_checked ) {\
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nkeynes@416 | 241 | sh4_x86.fpuen_checked = TRUE;\
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nkeynes@416 | 242 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 243 | AND_imm32_r32( SR_FD, R_EAX );\
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nkeynes@416 | 244 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 245 | JNE_exc(EXC_SLOT_FPU_DISABLED);\
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nkeynes@416 | 246 | } else {\
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nkeynes@586 | 247 | JNE_exc(EXC_FPU_DISABLED);\
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nkeynes@416 | 248 | }\
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nkeynes@416 | 249 | }
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nkeynes@416 | 250 |
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nkeynes@586 | 251 | #define check_ralign16( x86reg ) \
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nkeynes@586 | 252 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 253 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@416 | 254 |
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nkeynes@586 | 255 | #define check_walign16( x86reg ) \
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nkeynes@586 | 256 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 257 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 258 |
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nkeynes@586 | 259 | #define check_ralign32( x86reg ) \
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nkeynes@586 | 260 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 261 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@368 | 262 |
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nkeynes@586 | 263 | #define check_walign32( x86reg ) \
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nkeynes@586 | 264 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 265 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 266 |
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nkeynes@361 | 267 | #define UNDEF()
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nkeynes@361 | 268 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 269 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 270 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 271 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 272 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 273 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 274 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 275 |
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nkeynes@586 | 276 | /**
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nkeynes@586 | 277 | * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned
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nkeynes@586 | 278 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 279 | */
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nkeynes@586 | 280 | #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@596 | 281 |
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nkeynes@596 | 282 | #define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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nkeynes@586 | 283 | /**
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nkeynes@586 | 284 | * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned
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nkeynes@586 | 285 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 286 | */
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nkeynes@586 | 287 | #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@368 | 288 |
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nkeynes@586 | 289 | #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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nkeynes@586 | 290 | #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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nkeynes@586 | 291 | #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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nkeynes@586 | 292 |
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nkeynes@590 | 293 | #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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nkeynes@388 | 294 |
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nkeynes@539 | 295 | /****** Import appropriate calling conventions ******/
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nkeynes@539 | 296 | #if SH4_TRANSLATOR == TARGET_X86_64
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nkeynes@539 | 297 | #include "sh4/ia64abi.h"
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nkeynes@539 | 298 | #else /* SH4_TRANSLATOR == TARGET_X86 */
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nkeynes@539 | 299 | #ifdef APPLE_BUILD
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nkeynes@539 | 300 | #include "sh4/ia32mac.h"
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nkeynes@539 | 301 | #else
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nkeynes@539 | 302 | #include "sh4/ia32abi.h"
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nkeynes@539 | 303 | #endif
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nkeynes@539 | 304 | #endif
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nkeynes@539 | 305 |
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nkeynes@593 | 306 | uint32_t sh4_translate_end_block_size()
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nkeynes@593 | 307 | {
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nkeynes@596 | 308 | if( sh4_x86.backpatch_posn <= 3 ) {
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nkeynes@596 | 309 | return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
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nkeynes@596 | 310 | } else {
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nkeynes@596 | 311 | return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
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nkeynes@596 | 312 | }
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nkeynes@593 | 313 | }
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nkeynes@593 | 314 |
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nkeynes@593 | 315 |
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nkeynes@590 | 316 | /**
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nkeynes@590 | 317 | * Embed a breakpoint into the generated code
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nkeynes@590 | 318 | */
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nkeynes@586 | 319 | void sh4_translate_emit_breakpoint( sh4vma_t pc )
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nkeynes@586 | 320 | {
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nkeynes@591 | 321 | load_imm32( R_EAX, pc );
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nkeynes@591 | 322 | call_func1( sh4_translate_breakpoint_hit, R_EAX );
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nkeynes@586 | 323 | }
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nkeynes@590 | 324 |
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nkeynes@601 | 325 |
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nkeynes@601 | 326 | #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
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nkeynes@601 | 327 |
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nkeynes@590 | 328 | /**
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nkeynes@590 | 329 | * Embed a call to sh4_execute_instruction for situations that we
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nkeynes@601 | 330 | * can't translate (just page-crossing delay slots at the moment).
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nkeynes@601 | 331 | * Caller is responsible for setting new_pc before calling this function.
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nkeynes@601 | 332 | *
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nkeynes@601 | 333 | * Performs:
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nkeynes@601 | 334 | * Set PC = endpc
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nkeynes@601 | 335 | * Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
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nkeynes@601 | 336 | * Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
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nkeynes@601 | 337 | * Call sh4_execute_instruction
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nkeynes@601 | 338 | * Call xlat_get_code_by_vma / xlat_get_code as for normal exit
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nkeynes@590 | 339 | */
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nkeynes@601 | 340 | void exit_block_emu( sh4vma_t endpc )
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nkeynes@590 | 341 | {
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nkeynes@590 | 342 | load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5
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nkeynes@590 | 343 | ADD_r32_sh4r( R_ECX, R_PC );
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nkeynes@586 | 344 |
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nkeynes@601 | 345 | load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
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nkeynes@590 | 346 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
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nkeynes@590 | 347 | load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
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nkeynes@590 | 348 | store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
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nkeynes@590 | 349 |
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nkeynes@590 | 350 | call_func0( sh4_execute_instruction );
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nkeynes@601 | 351 | load_spreg( R_EAX, R_PC );
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nkeynes@590 | 352 | if( sh4_x86.tlb_on ) {
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nkeynes@590 | 353 | call_func1(xlat_get_code_by_vma,R_EAX);
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nkeynes@590 | 354 | } else {
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nkeynes@590 | 355 | call_func1(xlat_get_code,R_EAX);
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nkeynes@590 | 356 | }
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nkeynes@601 | 357 | AND_imm8s_rptr( 0xFC, R_EAX );
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nkeynes@590 | 358 | POP_r32(R_EBP);
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nkeynes@590 | 359 | RET();
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nkeynes@590 | 360 | }
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nkeynes@539 | 361 |
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nkeynes@359 | 362 | /**
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nkeynes@359 | 363 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 364 | * by translating both branch and delayed instruction as a single unit (as
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nkeynes@359 | 365 | *
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nkeynes@586 | 366 | * The instruction MUST be in the icache (assert check)
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nkeynes@359 | 367 | *
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nkeynes@359 | 368 | * @return true if the instruction marks the end of a basic block
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nkeynes@359 | 369 | * (eg a branch or
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nkeynes@359 | 370 | */
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nkeynes@590 | 371 | uint32_t sh4_translate_instruction( sh4vma_t pc )
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nkeynes@359 | 372 | {
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nkeynes@388 | 373 | uint32_t ir;
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nkeynes@586 | 374 | /* Read instruction from icache */
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nkeynes@586 | 375 | assert( IS_IN_ICACHE(pc) );
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nkeynes@586 | 376 | ir = *(uint16_t *)GET_ICACHE_PTR(pc);
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nkeynes@586 | 377 |
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nkeynes@586 | 378 | /* PC is not in the current icache - this usually means we're running
|
nkeynes@586 | 379 | * with MMU on, and we've gone past the end of the page. And since
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nkeynes@586 | 380 | * sh4_translate_block is pretty careful about this, it means we're
|
nkeynes@586 | 381 | * almost certainly in a delay slot.
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nkeynes@586 | 382 | *
|
nkeynes@586 | 383 | * Since we can't assume the page is present (and we can't fault it in
|
nkeynes@586 | 384 | * at this point, inline a call to sh4_execute_instruction (with a few
|
nkeynes@586 | 385 | * small repairs to cope with the different environment).
|
nkeynes@586 | 386 | */
|
nkeynes@586 | 387 |
|
nkeynes@586 | 388 | if( !sh4_x86.in_delay_slot ) {
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nkeynes@596 | 389 | sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
|
nkeynes@388 | 390 | }
|
nkeynes@359 | 391 | %%
|
nkeynes@359 | 392 | /* ALU operations */
|
nkeynes@359 | 393 | ADD Rm, Rn {:
|
nkeynes@671 | 394 | COUNT_INST(I_ADD);
|
nkeynes@359 | 395 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 396 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 397 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 398 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 399 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 400 | :}
|
nkeynes@359 | 401 | ADD #imm, Rn {:
|
nkeynes@671 | 402 | COUNT_INST(I_ADDI);
|
nkeynes@359 | 403 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 404 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 405 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 406 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 407 | :}
|
nkeynes@359 | 408 | ADDC Rm, Rn {:
|
nkeynes@671 | 409 | COUNT_INST(I_ADDC);
|
nkeynes@417 | 410 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 411 | LDC_t();
|
nkeynes@417 | 412 | }
|
nkeynes@359 | 413 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 414 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 415 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 416 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 417 | SETC_t();
|
nkeynes@417 | 418 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 419 | :}
|
nkeynes@359 | 420 | ADDV Rm, Rn {:
|
nkeynes@671 | 421 | COUNT_INST(I_ADDV);
|
nkeynes@359 | 422 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 423 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 424 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 425 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 426 | SETO_t();
|
nkeynes@417 | 427 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 428 | :}
|
nkeynes@359 | 429 | AND Rm, Rn {:
|
nkeynes@671 | 430 | COUNT_INST(I_AND);
|
nkeynes@359 | 431 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 432 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 433 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 434 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 435 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 436 | :}
|
nkeynes@359 | 437 | AND #imm, R0 {:
|
nkeynes@671 | 438 | COUNT_INST(I_ANDI);
|
nkeynes@359 | 439 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 440 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 441 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 442 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 443 | :}
|
nkeynes@359 | 444 | AND.B #imm, @(R0, GBR) {:
|
nkeynes@671 | 445 | COUNT_INST(I_ANDB);
|
nkeynes@359 | 446 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 447 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 448 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 449 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 450 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 451 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 452 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 453 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 454 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 455 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 456 | :}
|
nkeynes@359 | 457 | CMP/EQ Rm, Rn {:
|
nkeynes@671 | 458 | COUNT_INST(I_CMPEQ);
|
nkeynes@359 | 459 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 460 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 461 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 462 | SETE_t();
|
nkeynes@417 | 463 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 464 | :}
|
nkeynes@359 | 465 | CMP/EQ #imm, R0 {:
|
nkeynes@671 | 466 | COUNT_INST(I_CMPEQI);
|
nkeynes@359 | 467 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 468 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 469 | SETE_t();
|
nkeynes@417 | 470 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 471 | :}
|
nkeynes@359 | 472 | CMP/GE Rm, Rn {:
|
nkeynes@671 | 473 | COUNT_INST(I_CMPGE);
|
nkeynes@359 | 474 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 475 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 476 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 477 | SETGE_t();
|
nkeynes@417 | 478 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 479 | :}
|
nkeynes@359 | 480 | CMP/GT Rm, Rn {:
|
nkeynes@671 | 481 | COUNT_INST(I_CMPGT);
|
nkeynes@359 | 482 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 483 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 484 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 485 | SETG_t();
|
nkeynes@417 | 486 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 487 | :}
|
nkeynes@359 | 488 | CMP/HI Rm, Rn {:
|
nkeynes@671 | 489 | COUNT_INST(I_CMPHI);
|
nkeynes@359 | 490 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 491 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 492 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 493 | SETA_t();
|
nkeynes@417 | 494 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 495 | :}
|
nkeynes@359 | 496 | CMP/HS Rm, Rn {:
|
nkeynes@671 | 497 | COUNT_INST(I_CMPHS);
|
nkeynes@359 | 498 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 499 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 500 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 501 | SETAE_t();
|
nkeynes@417 | 502 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 503 | :}
|
nkeynes@359 | 504 | CMP/PL Rn {:
|
nkeynes@671 | 505 | COUNT_INST(I_CMPPL);
|
nkeynes@359 | 506 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 507 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 508 | SETG_t();
|
nkeynes@417 | 509 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 510 | :}
|
nkeynes@359 | 511 | CMP/PZ Rn {:
|
nkeynes@671 | 512 | COUNT_INST(I_CMPPZ);
|
nkeynes@359 | 513 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 514 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 515 | SETGE_t();
|
nkeynes@417 | 516 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 517 | :}
|
nkeynes@361 | 518 | CMP/STR Rm, Rn {:
|
nkeynes@671 | 519 | COUNT_INST(I_CMPSTR);
|
nkeynes@368 | 520 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 521 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 522 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 523 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@669 | 524 | JE_rel8(target1);
|
nkeynes@669 | 525 | TEST_r8_r8( R_AH, R_AH );
|
nkeynes@669 | 526 | JE_rel8(target2);
|
nkeynes@669 | 527 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@669 | 528 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@669 | 529 | JE_rel8(target3);
|
nkeynes@669 | 530 | TEST_r8_r8( R_AH, R_AH );
|
nkeynes@380 | 531 | JMP_TARGET(target1);
|
nkeynes@380 | 532 | JMP_TARGET(target2);
|
nkeynes@380 | 533 | JMP_TARGET(target3);
|
nkeynes@368 | 534 | SETE_t();
|
nkeynes@417 | 535 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@361 | 536 | :}
|
nkeynes@361 | 537 | DIV0S Rm, Rn {:
|
nkeynes@671 | 538 | COUNT_INST(I_DIV0S);
|
nkeynes@361 | 539 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 540 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 541 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 542 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 543 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 544 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 545 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 546 | SETNE_t();
|
nkeynes@417 | 547 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@361 | 548 | :}
|
nkeynes@361 | 549 | DIV0U {:
|
nkeynes@671 | 550 | COUNT_INST(I_DIV0U);
|
nkeynes@361 | 551 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 552 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 553 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 554 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 555 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@361 | 556 | :}
|
nkeynes@386 | 557 | DIV1 Rm, Rn {:
|
nkeynes@671 | 558 | COUNT_INST(I_DIV1);
|
nkeynes@386 | 559 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 560 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 561 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 562 | LDC_t();
|
nkeynes@417 | 563 | }
|
nkeynes@386 | 564 | RCL1_r32( R_EAX );
|
nkeynes@386 | 565 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 566 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@669 | 567 | JE_rel8(mqequal);
|
nkeynes@386 | 568 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@669 | 569 | JMP_rel8(end);
|
nkeynes@380 | 570 | JMP_TARGET(mqequal);
|
nkeynes@386 | 571 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 572 | JMP_TARGET(end);
|
nkeynes@386 | 573 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 574 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 575 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 576 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 577 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 578 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 579 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 580 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 581 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 582 | :}
|
nkeynes@361 | 583 | DMULS.L Rm, Rn {:
|
nkeynes@671 | 584 | COUNT_INST(I_DMULS);
|
nkeynes@361 | 585 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 586 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 587 | IMUL_r32(R_ECX);
|
nkeynes@361 | 588 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 589 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 590 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 591 | :}
|
nkeynes@361 | 592 | DMULU.L Rm, Rn {:
|
nkeynes@671 | 593 | COUNT_INST(I_DMULU);
|
nkeynes@361 | 594 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 595 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 596 | MUL_r32(R_ECX);
|
nkeynes@361 | 597 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 598 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 599 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 600 | :}
|
nkeynes@359 | 601 | DT Rn {:
|
nkeynes@671 | 602 | COUNT_INST(I_DT);
|
nkeynes@359 | 603 | load_reg( R_EAX, Rn );
|
nkeynes@382 | 604 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 605 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 606 | SETE_t();
|
nkeynes@417 | 607 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 608 | :}
|
nkeynes@359 | 609 | EXTS.B Rm, Rn {:
|
nkeynes@671 | 610 | COUNT_INST(I_EXTSB);
|
nkeynes@359 | 611 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 612 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 613 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 614 | :}
|
nkeynes@361 | 615 | EXTS.W Rm, Rn {:
|
nkeynes@671 | 616 | COUNT_INST(I_EXTSW);
|
nkeynes@361 | 617 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 618 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 619 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 620 | :}
|
nkeynes@361 | 621 | EXTU.B Rm, Rn {:
|
nkeynes@671 | 622 | COUNT_INST(I_EXTUB);
|
nkeynes@361 | 623 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 624 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 625 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 626 | :}
|
nkeynes@361 | 627 | EXTU.W Rm, Rn {:
|
nkeynes@671 | 628 | COUNT_INST(I_EXTUW);
|
nkeynes@361 | 629 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 630 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 631 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 632 | :}
|
nkeynes@586 | 633 | MAC.L @Rm+, @Rn+ {:
|
nkeynes@671 | 634 | COUNT_INST(I_MACL);
|
nkeynes@586 | 635 | if( Rm == Rn ) {
|
nkeynes@586 | 636 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 637 | check_ralign32( R_EAX );
|
nkeynes@586 | 638 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 639 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 640 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 641 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@596 | 642 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 643 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 644 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 645 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 646 | } else {
|
nkeynes@586 | 647 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 648 | check_ralign32( R_EAX );
|
nkeynes@586 | 649 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 650 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 651 | check_ralign32( R_ECX );
|
nkeynes@586 | 652 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 653 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 654 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 655 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 656 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 657 | }
|
nkeynes@586 | 658 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 659 | POP_r32( R_ECX );
|
nkeynes@586 | 660 | PUSH_r32( R_EAX );
|
nkeynes@386 | 661 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@547 | 662 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 663 |
|
nkeynes@386 | 664 | IMUL_r32( R_ECX );
|
nkeynes@386 | 665 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 666 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 667 |
|
nkeynes@386 | 668 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 669 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@669 | 670 | JE_rel8( nosat );
|
nkeynes@386 | 671 | call_func0( signsat48 );
|
nkeynes@386 | 672 | JMP_TARGET( nosat );
|
nkeynes@417 | 673 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 674 | :}
|
nkeynes@386 | 675 | MAC.W @Rm+, @Rn+ {:
|
nkeynes@671 | 676 | COUNT_INST(I_MACW);
|
nkeynes@586 | 677 | if( Rm == Rn ) {
|
nkeynes@586 | 678 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 679 | check_ralign16( R_EAX );
|
nkeynes@586 | 680 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 681 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 682 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 683 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@596 | 684 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 685 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 686 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 687 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 688 | } else {
|
nkeynes@586 | 689 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 690 | check_ralign16( R_EAX );
|
nkeynes@586 | 691 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 692 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 693 | check_ralign16( R_ECX );
|
nkeynes@586 | 694 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 695 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 696 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 697 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 698 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 699 | }
|
nkeynes@586 | 700 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 701 | POP_r32( R_ECX );
|
nkeynes@586 | 702 | PUSH_r32( R_EAX );
|
nkeynes@386 | 703 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@547 | 704 | POP_realigned_r32( R_ECX );
|
nkeynes@386 | 705 | IMUL_r32( R_ECX );
|
nkeynes@386 | 706 |
|
nkeynes@386 | 707 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 708 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@669 | 709 | JE_rel8( nosat );
|
nkeynes@386 | 710 |
|
nkeynes@386 | 711 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 712 | JNO_rel8( end ); // 2
|
nkeynes@386 | 713 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 714 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@669 | 715 | JS_rel8( positive ); // 2
|
nkeynes@386 | 716 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 717 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 718 | JMP_rel8(end2); // 2
|
nkeynes@386 | 719 |
|
nkeynes@386 | 720 | JMP_TARGET(positive);
|
nkeynes@386 | 721 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 722 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@669 | 723 | JMP_rel8(end3); // 2
|
nkeynes@386 | 724 |
|
nkeynes@386 | 725 | JMP_TARGET(nosat);
|
nkeynes@386 | 726 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 727 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 728 | JMP_TARGET(end);
|
nkeynes@386 | 729 | JMP_TARGET(end2);
|
nkeynes@386 | 730 | JMP_TARGET(end3);
|
nkeynes@417 | 731 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 732 | :}
|
nkeynes@359 | 733 | MOVT Rn {:
|
nkeynes@671 | 734 | COUNT_INST(I_MOVT);
|
nkeynes@359 | 735 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 736 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 737 | :}
|
nkeynes@361 | 738 | MUL.L Rm, Rn {:
|
nkeynes@671 | 739 | COUNT_INST(I_MULL);
|
nkeynes@361 | 740 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 741 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 742 | MUL_r32( R_ECX );
|
nkeynes@361 | 743 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 744 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 745 | :}
|
nkeynes@374 | 746 | MULS.W Rm, Rn {:
|
nkeynes@671 | 747 | COUNT_INST(I_MULSW);
|
nkeynes@374 | 748 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 749 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 750 | MUL_r32( R_ECX );
|
nkeynes@374 | 751 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 752 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 753 | :}
|
nkeynes@374 | 754 | MULU.W Rm, Rn {:
|
nkeynes@671 | 755 | COUNT_INST(I_MULUW);
|
nkeynes@374 | 756 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 757 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 758 | MUL_r32( R_ECX );
|
nkeynes@374 | 759 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 760 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 761 | :}
|
nkeynes@359 | 762 | NEG Rm, Rn {:
|
nkeynes@671 | 763 | COUNT_INST(I_NEG);
|
nkeynes@359 | 764 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 765 | NEG_r32( R_EAX );
|
nkeynes@359 | 766 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 767 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 768 | :}
|
nkeynes@359 | 769 | NEGC Rm, Rn {:
|
nkeynes@671 | 770 | COUNT_INST(I_NEGC);
|
nkeynes@359 | 771 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 772 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 773 | LDC_t();
|
nkeynes@359 | 774 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 775 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 776 | SETC_t();
|
nkeynes@417 | 777 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 778 | :}
|
nkeynes@359 | 779 | NOT Rm, Rn {:
|
nkeynes@671 | 780 | COUNT_INST(I_NOT);
|
nkeynes@359 | 781 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 782 | NOT_r32( R_EAX );
|
nkeynes@359 | 783 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 784 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 785 | :}
|
nkeynes@359 | 786 | OR Rm, Rn {:
|
nkeynes@671 | 787 | COUNT_INST(I_OR);
|
nkeynes@359 | 788 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 789 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 790 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 791 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 792 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 793 | :}
|
nkeynes@359 | 794 | OR #imm, R0 {:
|
nkeynes@671 | 795 | COUNT_INST(I_ORI);
|
nkeynes@359 | 796 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 797 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 798 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 799 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 800 | :}
|
nkeynes@374 | 801 | OR.B #imm, @(R0, GBR) {:
|
nkeynes@671 | 802 | COUNT_INST(I_ORB);
|
nkeynes@374 | 803 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 804 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 805 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 806 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 807 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 808 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 809 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 810 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 811 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 812 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 813 | :}
|
nkeynes@359 | 814 | ROTCL Rn {:
|
nkeynes@671 | 815 | COUNT_INST(I_ROTCL);
|
nkeynes@359 | 816 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 817 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 818 | LDC_t();
|
nkeynes@417 | 819 | }
|
nkeynes@359 | 820 | RCL1_r32( R_EAX );
|
nkeynes@359 | 821 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 822 | SETC_t();
|
nkeynes@417 | 823 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 824 | :}
|
nkeynes@359 | 825 | ROTCR Rn {:
|
nkeynes@671 | 826 | COUNT_INST(I_ROTCR);
|
nkeynes@359 | 827 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 828 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 829 | LDC_t();
|
nkeynes@417 | 830 | }
|
nkeynes@359 | 831 | RCR1_r32( R_EAX );
|
nkeynes@359 | 832 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 833 | SETC_t();
|
nkeynes@417 | 834 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 835 | :}
|
nkeynes@359 | 836 | ROTL Rn {:
|
nkeynes@671 | 837 | COUNT_INST(I_ROTL);
|
nkeynes@359 | 838 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 839 | ROL1_r32( R_EAX );
|
nkeynes@359 | 840 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 841 | SETC_t();
|
nkeynes@417 | 842 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 843 | :}
|
nkeynes@359 | 844 | ROTR Rn {:
|
nkeynes@671 | 845 | COUNT_INST(I_ROTR);
|
nkeynes@359 | 846 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 847 | ROR1_r32( R_EAX );
|
nkeynes@359 | 848 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 849 | SETC_t();
|
nkeynes@417 | 850 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 851 | :}
|
nkeynes@359 | 852 | SHAD Rm, Rn {:
|
nkeynes@671 | 853 | COUNT_INST(I_SHAD);
|
nkeynes@359 | 854 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 855 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 856 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 857 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@669 | 858 | JGE_rel8(doshl);
|
nkeynes@361 | 859 |
|
nkeynes@361 | 860 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 861 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@669 | 862 | JE_rel8(emptysar); // 2
|
nkeynes@361 | 863 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@669 | 864 | JMP_rel8(end); // 2
|
nkeynes@386 | 865 |
|
nkeynes@386 | 866 | JMP_TARGET(emptysar);
|
nkeynes@386 | 867 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@669 | 868 | JMP_rel8(end2);
|
nkeynes@382 | 869 |
|
nkeynes@380 | 870 | JMP_TARGET(doshl);
|
nkeynes@361 | 871 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 872 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 873 | JMP_TARGET(end);
|
nkeynes@386 | 874 | JMP_TARGET(end2);
|
nkeynes@361 | 875 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 876 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 877 | :}
|
nkeynes@359 | 878 | SHLD Rm, Rn {:
|
nkeynes@671 | 879 | COUNT_INST(I_SHLD);
|
nkeynes@368 | 880 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 881 | load_reg( R_ECX, Rm );
|
nkeynes@382 | 882 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@669 | 883 | JGE_rel8(doshl);
|
nkeynes@368 | 884 |
|
nkeynes@382 | 885 | NEG_r32( R_ECX ); // 2
|
nkeynes@382 | 886 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@669 | 887 | JE_rel8(emptyshr );
|
nkeynes@382 | 888 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@669 | 889 | JMP_rel8(end); // 2
|
nkeynes@386 | 890 |
|
nkeynes@386 | 891 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 892 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@669 | 893 | JMP_rel8(end2);
|
nkeynes@382 | 894 |
|
nkeynes@382 | 895 | JMP_TARGET(doshl);
|
nkeynes@382 | 896 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@382 | 897 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@382 | 898 | JMP_TARGET(end);
|
nkeynes@386 | 899 | JMP_TARGET(end2);
|
nkeynes@368 | 900 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 901 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 902 | :}
|
nkeynes@359 | 903 | SHAL Rn {:
|
nkeynes@671 | 904 | COUNT_INST(I_SHAL);
|
nkeynes@359 | 905 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 906 | SHL1_r32( R_EAX );
|
nkeynes@397 | 907 | SETC_t();
|
nkeynes@359 | 908 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 909 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 910 | :}
|
nkeynes@359 | 911 | SHAR Rn {:
|
nkeynes@671 | 912 | COUNT_INST(I_SHAR);
|
nkeynes@359 | 913 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 914 | SAR1_r32( R_EAX );
|
nkeynes@397 | 915 | SETC_t();
|
nkeynes@359 | 916 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 917 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 918 | :}
|
nkeynes@359 | 919 | SHLL Rn {:
|
nkeynes@671 | 920 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 921 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 922 | SHL1_r32( R_EAX );
|
nkeynes@397 | 923 | SETC_t();
|
nkeynes@359 | 924 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 925 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 926 | :}
|
nkeynes@359 | 927 | SHLL2 Rn {:
|
nkeynes@671 | 928 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 929 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 930 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 931 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 932 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 933 | :}
|
nkeynes@359 | 934 | SHLL8 Rn {:
|
nkeynes@671 | 935 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 936 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 937 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 938 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 939 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 940 | :}
|
nkeynes@359 | 941 | SHLL16 Rn {:
|
nkeynes@671 | 942 | COUNT_INST(I_SHLL);
|
nkeynes@359 | 943 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 944 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 945 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 946 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 947 | :}
|
nkeynes@359 | 948 | SHLR Rn {:
|
nkeynes@671 | 949 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 950 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 951 | SHR1_r32( R_EAX );
|
nkeynes@397 | 952 | SETC_t();
|
nkeynes@359 | 953 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 954 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 955 | :}
|
nkeynes@359 | 956 | SHLR2 Rn {:
|
nkeynes@671 | 957 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 958 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 959 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 960 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 961 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 962 | :}
|
nkeynes@359 | 963 | SHLR8 Rn {:
|
nkeynes@671 | 964 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 965 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 966 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 967 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 968 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 969 | :}
|
nkeynes@359 | 970 | SHLR16 Rn {:
|
nkeynes@671 | 971 | COUNT_INST(I_SHLR);
|
nkeynes@359 | 972 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 973 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 974 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 975 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 976 | :}
|
nkeynes@359 | 977 | SUB Rm, Rn {:
|
nkeynes@671 | 978 | COUNT_INST(I_SUB);
|
nkeynes@359 | 979 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 980 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 981 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 982 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 983 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 984 | :}
|
nkeynes@359 | 985 | SUBC Rm, Rn {:
|
nkeynes@671 | 986 | COUNT_INST(I_SUBC);
|
nkeynes@359 | 987 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 988 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 989 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 990 | LDC_t();
|
nkeynes@417 | 991 | }
|
nkeynes@359 | 992 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 993 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 994 | SETC_t();
|
nkeynes@417 | 995 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 996 | :}
|
nkeynes@359 | 997 | SUBV Rm, Rn {:
|
nkeynes@671 | 998 | COUNT_INST(I_SUBV);
|
nkeynes@359 | 999 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1000 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1001 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1002 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1003 | SETO_t();
|
nkeynes@417 | 1004 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1005 | :}
|
nkeynes@359 | 1006 | SWAP.B Rm, Rn {:
|
nkeynes@671 | 1007 | COUNT_INST(I_SWAPB);
|
nkeynes@359 | 1008 | load_reg( R_EAX, Rm );
|
nkeynes@601 | 1009 | XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
|
nkeynes@359 | 1010 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1011 | :}
|
nkeynes@359 | 1012 | SWAP.W Rm, Rn {:
|
nkeynes@671 | 1013 | COUNT_INST(I_SWAPB);
|
nkeynes@359 | 1014 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1015 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1016 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 1017 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1018 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1019 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1020 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1021 | :}
|
nkeynes@361 | 1022 | TAS.B @Rn {:
|
nkeynes@671 | 1023 | COUNT_INST(I_TASB);
|
nkeynes@586 | 1024 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1025 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1026 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 1027 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@361 | 1028 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1029 | SETE_t();
|
nkeynes@361 | 1030 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@586 | 1031 | POP_realigned_r32( R_ECX );
|
nkeynes@361 | 1032 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1033 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1034 | :}
|
nkeynes@361 | 1035 | TST Rm, Rn {:
|
nkeynes@671 | 1036 | COUNT_INST(I_TST);
|
nkeynes@361 | 1037 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1038 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1039 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1040 | SETE_t();
|
nkeynes@417 | 1041 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@361 | 1042 | :}
|
nkeynes@368 | 1043 | TST #imm, R0 {:
|
nkeynes@671 | 1044 | COUNT_INST(I_TSTI);
|
nkeynes@368 | 1045 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 1046 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 1047 | SETE_t();
|
nkeynes@417 | 1048 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@368 | 1049 | :}
|
nkeynes@368 | 1050 | TST.B #imm, @(R0, GBR) {:
|
nkeynes@671 | 1051 | COUNT_INST(I_TSTB);
|
nkeynes@368 | 1052 | load_reg( R_EAX, 0);
|
nkeynes@368 | 1053 | load_reg( R_ECX, R_GBR);
|
nkeynes@586 | 1054 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1055 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1056 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@394 | 1057 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 1058 | SETE_t();
|
nkeynes@417 | 1059 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@368 | 1060 | :}
|
nkeynes@359 | 1061 | XOR Rm, Rn {:
|
nkeynes@671 | 1062 | COUNT_INST(I_XOR);
|
nkeynes@359 | 1063 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1064 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1065 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1066 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1067 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1068 | :}
|
nkeynes@359 | 1069 | XOR #imm, R0 {:
|
nkeynes@671 | 1070 | COUNT_INST(I_XORI);
|
nkeynes@359 | 1071 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1072 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1073 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1074 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1075 | :}
|
nkeynes@359 | 1076 | XOR.B #imm, @(R0, GBR) {:
|
nkeynes@671 | 1077 | COUNT_INST(I_XORB);
|
nkeynes@359 | 1078 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1079 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 1080 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1081 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1082 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 1083 | MEM_READ_BYTE(R_EAX, R_EAX);
|
nkeynes@547 | 1084 | POP_realigned_r32(R_ECX);
|
nkeynes@359 | 1085 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1086 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1087 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1088 | :}
|
nkeynes@361 | 1089 | XTRCT Rm, Rn {:
|
nkeynes@671 | 1090 | COUNT_INST(I_XTRCT);
|
nkeynes@361 | 1091 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1092 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1093 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1094 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1095 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1096 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1097 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1098 | :}
|
nkeynes@359 | 1099 |
|
nkeynes@359 | 1100 | /* Data move instructions */
|
nkeynes@359 | 1101 | MOV Rm, Rn {:
|
nkeynes@671 | 1102 | COUNT_INST(I_MOV);
|
nkeynes@359 | 1103 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1104 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1105 | :}
|
nkeynes@359 | 1106 | MOV #imm, Rn {:
|
nkeynes@671 | 1107 | COUNT_INST(I_MOVI);
|
nkeynes@359 | 1108 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 1109 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1110 | :}
|
nkeynes@359 | 1111 | MOV.B Rm, @Rn {:
|
nkeynes@671 | 1112 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1113 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1114 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1115 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1116 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 1117 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1118 | :}
|
nkeynes@359 | 1119 | MOV.B Rm, @-Rn {:
|
nkeynes@671 | 1120 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1121 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1122 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@586 | 1123 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1124 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1125 | ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1126 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 1127 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1128 | :}
|
nkeynes@359 | 1129 | MOV.B Rm, @(R0, Rn) {:
|
nkeynes@671 | 1130 | COUNT_INST(I_MOVB);
|
nkeynes@359 | 1131 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1132 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 1133 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1134 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1135 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1136 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 1137 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1138 | :}
|
nkeynes@359 | 1139 | MOV.B R0, @(disp, GBR) {:
|
nkeynes@671 | 1140 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1141 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1142 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1143 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1144 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1145 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 1146 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1147 | :}
|
nkeynes@359 | 1148 | MOV.B R0, @(disp, Rn) {:
|
nkeynes@671 | 1149 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1150 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1151 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1152 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1153 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1154 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 1155 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1156 | :}
|
nkeynes@359 | 1157 | MOV.B @Rm, Rn {:
|
nkeynes@671 | 1158 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1159 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1160 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1161 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@386 | 1162 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1163 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1164 | :}
|
nkeynes@359 | 1165 | MOV.B @Rm+, Rn {:
|
nkeynes@671 | 1166 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1167 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1168 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1169 | ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1170 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 1171 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1172 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1173 | :}
|
nkeynes@359 | 1174 | MOV.B @(R0, Rm), Rn {:
|
nkeynes@671 | 1175 | COUNT_INST(I_MOVB);
|
nkeynes@359 | 1176 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1177 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 1178 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1179 | MMU_TRANSLATE_READ( R_EAX )
|
nkeynes@586 | 1180 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 1181 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1182 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1183 | :}
|
nkeynes@359 | 1184 | MOV.B @(disp, GBR), R0 {:
|
nkeynes@671 | 1185 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1186 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1187 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1188 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1189 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 1190 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1191 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1192 | :}
|
nkeynes@359 | 1193 | MOV.B @(disp, Rm), R0 {:
|
nkeynes@671 | 1194 | COUNT_INST(I_MOVB);
|
nkeynes@586 | 1195 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1196 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1197 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1198 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 1199 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1200 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1201 | :}
|
nkeynes@374 | 1202 | MOV.L Rm, @Rn {:
|
nkeynes@671 | 1203 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1204 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1205 | check_walign32(R_EAX);
|
nkeynes@586 | 1206 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1207 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1208 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1209 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1210 | :}
|
nkeynes@361 | 1211 | MOV.L Rm, @-Rn {:
|
nkeynes@671 | 1212 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1213 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1214 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1215 | check_walign32( R_EAX );
|
nkeynes@586 | 1216 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1217 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1218 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1219 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1220 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1221 | :}
|
nkeynes@361 | 1222 | MOV.L Rm, @(R0, Rn) {:
|
nkeynes@671 | 1223 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 1224 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1225 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 1226 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1227 | check_walign32( R_EAX );
|
nkeynes@586 | 1228 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1229 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1230 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1231 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1232 | :}
|
nkeynes@361 | 1233 | MOV.L R0, @(disp, GBR) {:
|
nkeynes@671 | 1234 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1235 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1236 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1237 | check_walign32( R_EAX );
|
nkeynes@586 | 1238 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1239 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1240 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1241 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1242 | :}
|
nkeynes@361 | 1243 | MOV.L Rm, @(disp, Rn) {:
|
nkeynes@671 | 1244 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1245 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1246 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1247 | check_walign32( R_EAX );
|
nkeynes@586 | 1248 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1249 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1250 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1251 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1252 | :}
|
nkeynes@361 | 1253 | MOV.L @Rm, Rn {:
|
nkeynes@671 | 1254 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1255 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1256 | check_ralign32( R_EAX );
|
nkeynes@586 | 1257 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1258 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 1259 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1260 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1261 | :}
|
nkeynes@361 | 1262 | MOV.L @Rm+, Rn {:
|
nkeynes@671 | 1263 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 1264 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1265 | check_ralign32( R_EAX );
|
nkeynes@586 | 1266 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1267 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1268 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 1269 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1270 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1271 | :}
|
nkeynes@361 | 1272 | MOV.L @(R0, Rm), Rn {:
|
nkeynes@671 | 1273 | COUNT_INST(I_MOVL);
|
nkeynes@361 | 1274 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1275 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 1276 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1277 | check_ralign32( R_EAX );
|
nkeynes@586 | 1278 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1279 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 1280 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1281 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1282 | :}
|
nkeynes@361 | 1283 | MOV.L @(disp, GBR), R0 {:
|
nkeynes@671 | 1284 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1285 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1286 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1287 | check_ralign32( R_EAX );
|
nkeynes@586 | 1288 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1289 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 1290 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1291 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1292 | :}
|
nkeynes@361 | 1293 | MOV.L @(disp, PC), Rn {:
|
nkeynes@671 | 1294 | COUNT_INST(I_MOVLPC);
|
nkeynes@374 | 1295 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1296 | SLOTILLEGAL();
|
nkeynes@374 | 1297 | } else {
|
nkeynes@388 | 1298 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@586 | 1299 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 1300 | // If the target address is in the same page as the code, it's
|
nkeynes@586 | 1301 | // pretty safe to just ref it directly and circumvent the whole
|
nkeynes@586 | 1302 | // memory subsystem. (this is a big performance win)
|
nkeynes@586 | 1303 |
|
nkeynes@586 | 1304 | // FIXME: There's a corner-case that's not handled here when
|
nkeynes@586 | 1305 | // the current code-page is in the ITLB but not in the UTLB.
|
nkeynes@586 | 1306 | // (should generate a TLB miss although need to test SH4
|
nkeynes@586 | 1307 | // behaviour to confirm) Unlikely to be anyone depending on this
|
nkeynes@586 | 1308 | // behaviour though.
|
nkeynes@586 | 1309 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@527 | 1310 | MOV_moff32_EAX( ptr );
|
nkeynes@388 | 1311 | } else {
|
nkeynes@586 | 1312 | // Note: we use sh4r.pc for the calc as we could be running at a
|
nkeynes@586 | 1313 | // different virtual address than the translation was done with,
|
nkeynes@586 | 1314 | // but we can safely assume that the low bits are the same.
|
nkeynes@586 | 1315 | load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 1316 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 1317 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1318 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 1319 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 1320 | }
|
nkeynes@382 | 1321 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1322 | }
|
nkeynes@361 | 1323 | :}
|
nkeynes@361 | 1324 | MOV.L @(disp, Rm), Rn {:
|
nkeynes@671 | 1325 | COUNT_INST(I_MOVL);
|
nkeynes@586 | 1326 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1327 | ADD_imm8s_r32( disp, R_EAX );
|
nkeynes@586 | 1328 | check_ralign32( R_EAX );
|
nkeynes@586 | 1329 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1330 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 1331 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1332 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1333 | :}
|
nkeynes@361 | 1334 | MOV.W Rm, @Rn {:
|
nkeynes@671 | 1335 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1336 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1337 | check_walign16( R_EAX );
|
nkeynes@586 | 1338 | MMU_TRANSLATE_WRITE( R_EAX )
|
nkeynes@586 | 1339 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1340 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1341 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1342 | :}
|
nkeynes@361 | 1343 | MOV.W Rm, @-Rn {:
|
nkeynes@671 | 1344 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1345 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1346 | ADD_imm8s_r32( -2, R_EAX );
|
nkeynes@586 | 1347 | check_walign16( R_EAX );
|
nkeynes@586 | 1348 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1349 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1350 | ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1351 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1352 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1353 | :}
|
nkeynes@361 | 1354 | MOV.W Rm, @(R0, Rn) {:
|
nkeynes@671 | 1355 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 1356 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1357 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 1358 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1359 | check_walign16( R_EAX );
|
nkeynes@586 | 1360 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1361 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 1362 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1363 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1364 | :}
|
nkeynes@361 | 1365 | MOV.W R0, @(disp, GBR) {:
|
nkeynes@671 | 1366 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1367 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1368 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1369 | check_walign16( R_EAX );
|
nkeynes@586 | 1370 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1371 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1372 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1373 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1374 | :}
|
nkeynes@361 | 1375 | MOV.W R0, @(disp, Rn) {:
|
nkeynes@671 | 1376 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1377 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1378 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1379 | check_walign16( R_EAX );
|
nkeynes@586 | 1380 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1381 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1382 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 1383 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1384 | :}
|
nkeynes@361 | 1385 | MOV.W @Rm, Rn {:
|
nkeynes@671 | 1386 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1387 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1388 | check_ralign16( R_EAX );
|
nkeynes@586 | 1389 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1390 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 1391 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1392 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1393 | :}
|
nkeynes@361 | 1394 | MOV.W @Rm+, Rn {:
|
nkeynes@671 | 1395 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 1396 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1397 | check_ralign16( R_EAX );
|
nkeynes@586 | 1398 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1399 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1400 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 1401 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1402 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1403 | :}
|
nkeynes@361 | 1404 | MOV.W @(R0, Rm), Rn {:
|
nkeynes@671 | 1405 | COUNT_INST(I_MOVW);
|
nkeynes@361 | 1406 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1407 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 1408 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 1409 | check_ralign16( R_EAX );
|
nkeynes@586 | 1410 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1411 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 1412 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1413 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1414 | :}
|
nkeynes@361 | 1415 | MOV.W @(disp, GBR), R0 {:
|
nkeynes@671 | 1416 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1417 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 1418 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1419 | check_ralign16( R_EAX );
|
nkeynes@586 | 1420 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1421 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 1422 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1423 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1424 | :}
|
nkeynes@361 | 1425 | MOV.W @(disp, PC), Rn {:
|
nkeynes@671 | 1426 | COUNT_INST(I_MOVW);
|
nkeynes@374 | 1427 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1428 | SLOTILLEGAL();
|
nkeynes@374 | 1429 | } else {
|
nkeynes@586 | 1430 | // See comments for MOV.L @(disp, PC), Rn
|
nkeynes@586 | 1431 | uint32_t target = pc + disp + 4;
|
nkeynes@586 | 1432 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 1433 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@586 | 1434 | MOV_moff32_EAX( ptr );
|
nkeynes@586 | 1435 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@586 | 1436 | } else {
|
nkeynes@586 | 1437 | load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
|
nkeynes@586 | 1438 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 1439 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1440 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 1441 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@586 | 1442 | }
|
nkeynes@374 | 1443 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1444 | }
|
nkeynes@361 | 1445 | :}
|
nkeynes@361 | 1446 | MOV.W @(disp, Rm), R0 {:
|
nkeynes@671 | 1447 | COUNT_INST(I_MOVW);
|
nkeynes@586 | 1448 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1449 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 1450 | check_ralign16( R_EAX );
|
nkeynes@586 | 1451 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1452 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 1453 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1454 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1455 | :}
|
nkeynes@361 | 1456 | MOVA @(disp, PC), R0 {:
|
nkeynes@671 | 1457 | COUNT_INST(I_MOVA);
|
nkeynes@374 | 1458 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1459 | SLOTILLEGAL();
|
nkeynes@374 | 1460 | } else {
|
nkeynes@586 | 1461 | load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 1462 | ADD_sh4r_r32( R_PC, R_ECX );
|
nkeynes@374 | 1463 | store_reg( R_ECX, 0 );
|
nkeynes@586 | 1464 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 1465 | }
|
nkeynes@361 | 1466 | :}
|
nkeynes@361 | 1467 | MOVCA.L R0, @Rn {:
|
nkeynes@671 | 1468 | COUNT_INST(I_MOVCA);
|
nkeynes@586 | 1469 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1470 | check_walign32( R_EAX );
|
nkeynes@586 | 1471 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1472 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 1473 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1474 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1475 | :}
|
nkeynes@359 | 1476 |
|
nkeynes@359 | 1477 | /* Control transfer instructions */
|
nkeynes@374 | 1478 | BF disp {:
|
nkeynes@671 | 1479 | COUNT_INST(I_BF);
|
nkeynes@374 | 1480 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1481 | SLOTILLEGAL();
|
nkeynes@374 | 1482 | } else {
|
nkeynes@586 | 1483 | sh4vma_t target = disp + pc + 4;
|
nkeynes@669 | 1484 | JT_rel8( nottaken );
|
nkeynes@586 | 1485 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 1486 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1487 | return 2;
|
nkeynes@374 | 1488 | }
|
nkeynes@374 | 1489 | :}
|
nkeynes@374 | 1490 | BF/S disp {:
|
nkeynes@671 | 1491 | COUNT_INST(I_BFS);
|
nkeynes@374 | 1492 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1493 | SLOTILLEGAL();
|
nkeynes@374 | 1494 | } else {
|
nkeynes@590 | 1495 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@601 | 1496 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1497 | load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
|
nkeynes@669 | 1498 | JT_rel8(nottaken);
|
nkeynes@601 | 1499 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 1500 | JMP_TARGET(nottaken);
|
nkeynes@601 | 1501 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@601 | 1502 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 1503 | exit_block_emu(pc+2);
|
nkeynes@601 | 1504 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1505 | return 2;
|
nkeynes@601 | 1506 | } else {
|
nkeynes@601 | 1507 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@601 | 1508 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@601 | 1509 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@601 | 1510 | }
|
nkeynes@601 | 1511 | sh4vma_t target = disp + pc + 4;
|
nkeynes@601 | 1512 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
|
nkeynes@601 | 1513 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1514 | exit_block_rel( target, pc+4 );
|
nkeynes@601 | 1515 |
|
nkeynes@601 | 1516 | // not taken
|
nkeynes@601 | 1517 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@601 | 1518 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1519 | return 4;
|
nkeynes@417 | 1520 | }
|
nkeynes@374 | 1521 | }
|
nkeynes@374 | 1522 | :}
|
nkeynes@374 | 1523 | BRA disp {:
|
nkeynes@671 | 1524 | COUNT_INST(I_BRA);
|
nkeynes@374 | 1525 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1526 | SLOTILLEGAL();
|
nkeynes@374 | 1527 | } else {
|
nkeynes@590 | 1528 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 1529 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1530 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1531 | load_spreg( R_EAX, R_PC );
|
nkeynes@601 | 1532 | ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@601 | 1533 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 1534 | exit_block_emu(pc+2);
|
nkeynes@601 | 1535 | return 2;
|
nkeynes@601 | 1536 | } else {
|
nkeynes@601 | 1537 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 1538 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 1539 | return 4;
|
nkeynes@601 | 1540 | }
|
nkeynes@374 | 1541 | }
|
nkeynes@374 | 1542 | :}
|
nkeynes@374 | 1543 | BRAF Rn {:
|
nkeynes@671 | 1544 | COUNT_INST(I_BRAF);
|
nkeynes@374 | 1545 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1546 | SLOTILLEGAL();
|
nkeynes@374 | 1547 | } else {
|
nkeynes@590 | 1548 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 1549 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@590 | 1550 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
|
nkeynes@590 | 1551 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 1552 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 1553 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 1554 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1555 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1556 | exit_block_emu(pc+2);
|
nkeynes@601 | 1557 | return 2;
|
nkeynes@601 | 1558 | } else {
|
nkeynes@601 | 1559 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 1560 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1561 | return 4;
|
nkeynes@601 | 1562 | }
|
nkeynes@374 | 1563 | }
|
nkeynes@374 | 1564 | :}
|
nkeynes@374 | 1565 | BSR disp {:
|
nkeynes@671 | 1566 | COUNT_INST(I_BSR);
|
nkeynes@374 | 1567 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1568 | SLOTILLEGAL();
|
nkeynes@374 | 1569 | } else {
|
nkeynes@590 | 1570 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 1571 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 1572 | store_spreg( R_EAX, R_PR );
|
nkeynes@590 | 1573 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 1574 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1575 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@601 | 1576 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1577 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 1578 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 1579 | exit_block_emu(pc+2);
|
nkeynes@601 | 1580 | return 2;
|
nkeynes@601 | 1581 | } else {
|
nkeynes@601 | 1582 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 1583 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 1584 | return 4;
|
nkeynes@601 | 1585 | }
|
nkeynes@374 | 1586 | }
|
nkeynes@374 | 1587 | :}
|
nkeynes@374 | 1588 | BSRF Rn {:
|
nkeynes@671 | 1589 | COUNT_INST(I_BSRF);
|
nkeynes@374 | 1590 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1591 | SLOTILLEGAL();
|
nkeynes@374 | 1592 | } else {
|
nkeynes@590 | 1593 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 1594 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@590 | 1595 | store_spreg( R_EAX, R_PR );
|
nkeynes@590 | 1596 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
|
nkeynes@590 | 1597 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 1598 |
|
nkeynes@601 | 1599 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 1600 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 1601 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1602 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1603 | exit_block_emu(pc+2);
|
nkeynes@601 | 1604 | return 2;
|
nkeynes@601 | 1605 | } else {
|
nkeynes@601 | 1606 | sh4_translate_instruction( pc + 2 );
|
nkeynes@601 | 1607 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1608 | return 4;
|
nkeynes@601 | 1609 | }
|
nkeynes@374 | 1610 | }
|
nkeynes@374 | 1611 | :}
|
nkeynes@374 | 1612 | BT disp {:
|
nkeynes@671 | 1613 | COUNT_INST(I_BT);
|
nkeynes@374 | 1614 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1615 | SLOTILLEGAL();
|
nkeynes@374 | 1616 | } else {
|
nkeynes@586 | 1617 | sh4vma_t target = disp + pc + 4;
|
nkeynes@669 | 1618 | JF_rel8( nottaken );
|
nkeynes@586 | 1619 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 1620 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1621 | return 2;
|
nkeynes@374 | 1622 | }
|
nkeynes@374 | 1623 | :}
|
nkeynes@374 | 1624 | BT/S disp {:
|
nkeynes@671 | 1625 | COUNT_INST(I_BTS);
|
nkeynes@374 | 1626 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1627 | SLOTILLEGAL();
|
nkeynes@374 | 1628 | } else {
|
nkeynes@590 | 1629 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@601 | 1630 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1631 | load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
|
nkeynes@669 | 1632 | JF_rel8(nottaken);
|
nkeynes@601 | 1633 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@601 | 1634 | JMP_TARGET(nottaken);
|
nkeynes@601 | 1635 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@601 | 1636 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@601 | 1637 | exit_block_emu(pc+2);
|
nkeynes@601 | 1638 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1639 | return 2;
|
nkeynes@601 | 1640 | } else {
|
nkeynes@601 | 1641 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@601 | 1642 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@601 | 1643 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@601 | 1644 | }
|
nkeynes@601 | 1645 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
|
nkeynes@601 | 1646 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1647 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@601 | 1648 | // not taken
|
nkeynes@601 | 1649 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@601 | 1650 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1651 | return 4;
|
nkeynes@417 | 1652 | }
|
nkeynes@374 | 1653 | }
|
nkeynes@374 | 1654 | :}
|
nkeynes@374 | 1655 | JMP @Rn {:
|
nkeynes@671 | 1656 | COUNT_INST(I_JMP);
|
nkeynes@374 | 1657 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1658 | SLOTILLEGAL();
|
nkeynes@374 | 1659 | } else {
|
nkeynes@408 | 1660 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 1661 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 1662 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 1663 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1664 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1665 | exit_block_emu(pc+2);
|
nkeynes@601 | 1666 | return 2;
|
nkeynes@601 | 1667 | } else {
|
nkeynes@601 | 1668 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1669 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1670 | return 4;
|
nkeynes@601 | 1671 | }
|
nkeynes@374 | 1672 | }
|
nkeynes@374 | 1673 | :}
|
nkeynes@374 | 1674 | JSR @Rn {:
|
nkeynes@671 | 1675 | COUNT_INST(I_JSR);
|
nkeynes@374 | 1676 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1677 | SLOTILLEGAL();
|
nkeynes@374 | 1678 | } else {
|
nkeynes@590 | 1679 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 1680 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 1681 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1682 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 1683 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@601 | 1684 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 1685 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1686 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@601 | 1687 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1688 | exit_block_emu(pc+2);
|
nkeynes@601 | 1689 | return 2;
|
nkeynes@601 | 1690 | } else {
|
nkeynes@601 | 1691 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1692 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1693 | return 4;
|
nkeynes@601 | 1694 | }
|
nkeynes@374 | 1695 | }
|
nkeynes@374 | 1696 | :}
|
nkeynes@374 | 1697 | RTE {:
|
nkeynes@671 | 1698 | COUNT_INST(I_RTE);
|
nkeynes@374 | 1699 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1700 | SLOTILLEGAL();
|
nkeynes@374 | 1701 | } else {
|
nkeynes@408 | 1702 | check_priv();
|
nkeynes@408 | 1703 | load_spreg( R_ECX, R_SPC );
|
nkeynes@590 | 1704 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@374 | 1705 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 1706 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@590 | 1707 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@377 | 1708 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 1709 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1710 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@409 | 1711 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1712 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1713 | exit_block_emu(pc+2);
|
nkeynes@601 | 1714 | return 2;
|
nkeynes@601 | 1715 | } else {
|
nkeynes@601 | 1716 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1717 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1718 | return 4;
|
nkeynes@601 | 1719 | }
|
nkeynes@374 | 1720 | }
|
nkeynes@374 | 1721 | :}
|
nkeynes@374 | 1722 | RTS {:
|
nkeynes@671 | 1723 | COUNT_INST(I_RTS);
|
nkeynes@374 | 1724 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1725 | SLOTILLEGAL();
|
nkeynes@374 | 1726 | } else {
|
nkeynes@408 | 1727 | load_spreg( R_ECX, R_PR );
|
nkeynes@590 | 1728 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 1729 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@409 | 1730 | sh4_x86.branch_taken = TRUE;
|
nkeynes@601 | 1731 | if( UNTRANSLATABLE(pc+2) ) {
|
nkeynes@601 | 1732 | exit_block_emu(pc+2);
|
nkeynes@601 | 1733 | return 2;
|
nkeynes@601 | 1734 | } else {
|
nkeynes@601 | 1735 | sh4_translate_instruction(pc+2);
|
nkeynes@601 | 1736 | exit_block_newpcset(pc+2);
|
nkeynes@601 | 1737 | return 4;
|
nkeynes@601 | 1738 | }
|
nkeynes@374 | 1739 | }
|
nkeynes@374 | 1740 | :}
|
nkeynes@374 | 1741 | TRAPA #imm {:
|
nkeynes@671 | 1742 | COUNT_INST(I_TRAPA);
|
nkeynes@374 | 1743 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1744 | SLOTILLEGAL();
|
nkeynes@374 | 1745 | } else {
|
nkeynes@590 | 1746 | load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5
|
nkeynes@590 | 1747 | ADD_r32_sh4r( R_ECX, R_PC );
|
nkeynes@527 | 1748 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 1749 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@417 | 1750 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 1751 | exit_block_pcset(pc);
|
nkeynes@409 | 1752 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1753 | return 2;
|
nkeynes@374 | 1754 | }
|
nkeynes@374 | 1755 | :}
|
nkeynes@374 | 1756 | UNDEF {:
|
nkeynes@671 | 1757 | COUNT_INST(I_UNDEF);
|
nkeynes@374 | 1758 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@382 | 1759 | SLOTILLEGAL();
|
nkeynes@374 | 1760 | } else {
|
nkeynes@586 | 1761 | JMP_exc(EXC_ILLEGAL);
|
nkeynes@408 | 1762 | return 2;
|
nkeynes@374 | 1763 | }
|
nkeynes@368 | 1764 | :}
|
nkeynes@374 | 1765 |
|
nkeynes@374 | 1766 | CLRMAC {:
|
nkeynes@671 | 1767 | COUNT_INST(I_CLRMAC);
|
nkeynes@374 | 1768 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 1769 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 1770 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1771 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@368 | 1772 | :}
|
nkeynes@374 | 1773 | CLRS {:
|
nkeynes@671 | 1774 | COUNT_INST(I_CLRS);
|
nkeynes@374 | 1775 | CLC();
|
nkeynes@374 | 1776 | SETC_sh4r(R_S);
|
nkeynes@417 | 1777 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@368 | 1778 | :}
|
nkeynes@374 | 1779 | CLRT {:
|
nkeynes@671 | 1780 | COUNT_INST(I_CLRT);
|
nkeynes@374 | 1781 | CLC();
|
nkeynes@374 | 1782 | SETC_t();
|
nkeynes@417 | 1783 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1784 | :}
|
nkeynes@374 | 1785 | SETS {:
|
nkeynes@671 | 1786 | COUNT_INST(I_SETS);
|
nkeynes@374 | 1787 | STC();
|
nkeynes@374 | 1788 | SETC_sh4r(R_S);
|
nkeynes@417 | 1789 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1790 | :}
|
nkeynes@374 | 1791 | SETT {:
|
nkeynes@671 | 1792 | COUNT_INST(I_SETT);
|
nkeynes@374 | 1793 | STC();
|
nkeynes@374 | 1794 | SETC_t();
|
nkeynes@417 | 1795 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@374 | 1796 | :}
|
nkeynes@359 | 1797 |
|
nkeynes@375 | 1798 | /* Floating point moves */
|
nkeynes@375 | 1799 | FMOV FRm, FRn {:
|
nkeynes@671 | 1800 | COUNT_INST(I_FMOV1);
|
nkeynes@375 | 1801 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 1802 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 1803 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 1804 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 1805 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 1806 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 1807 | */
|
nkeynes@377 | 1808 | check_fpuen();
|
nkeynes@375 | 1809 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1810 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@669 | 1811 | JNE_rel8(doublesize);
|
nkeynes@669 | 1812 | load_fr( R_EAX, FRm ); // PR=0 branch
|
nkeynes@669 | 1813 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 1814 | JMP_rel8(end);
|
nkeynes@669 | 1815 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1816 | load_dr0( R_EAX, FRm );
|
nkeynes@669 | 1817 | load_dr1( R_ECX, FRm );
|
nkeynes@669 | 1818 | store_dr0( R_EAX, FRn );
|
nkeynes@669 | 1819 | store_dr1( R_ECX, FRn );
|
nkeynes@669 | 1820 | JMP_TARGET(end);
|
nkeynes@417 | 1821 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1822 | :}
|
nkeynes@416 | 1823 | FMOV FRm, @Rn {:
|
nkeynes@671 | 1824 | COUNT_INST(I_FMOV2);
|
nkeynes@586 | 1825 | check_fpuen();
|
nkeynes@586 | 1826 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1827 | check_walign32( R_EAX );
|
nkeynes@586 | 1828 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 1829 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1830 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1831 | JNE_rel8(doublesize);
|
nkeynes@669 | 1832 |
|
nkeynes@669 | 1833 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 1834 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@669 | 1835 | JMP_rel8(end);
|
nkeynes@669 | 1836 |
|
nkeynes@669 | 1837 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1838 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 1839 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 1840 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 1841 | JMP_TARGET(end);
|
nkeynes@417 | 1842 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1843 | :}
|
nkeynes@375 | 1844 | FMOV @Rm, FRn {:
|
nkeynes@671 | 1845 | COUNT_INST(I_FMOV5);
|
nkeynes@586 | 1846 | check_fpuen();
|
nkeynes@586 | 1847 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1848 | check_ralign32( R_EAX );
|
nkeynes@586 | 1849 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 1850 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1851 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1852 | JNE_rel8(doublesize);
|
nkeynes@669 | 1853 |
|
nkeynes@586 | 1854 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 1855 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 1856 | JMP_rel8(end);
|
nkeynes@669 | 1857 |
|
nkeynes@669 | 1858 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1859 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 1860 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 1861 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 1862 | JMP_TARGET(end);
|
nkeynes@417 | 1863 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1864 | :}
|
nkeynes@377 | 1865 | FMOV FRm, @-Rn {:
|
nkeynes@671 | 1866 | COUNT_INST(I_FMOV3);
|
nkeynes@586 | 1867 | check_fpuen();
|
nkeynes@586 | 1868 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1869 | check_walign32( R_EAX );
|
nkeynes@416 | 1870 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1871 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1872 | JNE_rel8(doublesize);
|
nkeynes@669 | 1873 |
|
nkeynes@586 | 1874 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1875 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 1876 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 1877 | ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
|
nkeynes@669 | 1878 | MEM_WRITE_LONG( R_EAX, R_ECX );
|
nkeynes@669 | 1879 | JMP_rel8(end);
|
nkeynes@669 | 1880 |
|
nkeynes@669 | 1881 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1882 | ADD_imm8s_r32(-8,R_EAX);
|
nkeynes@669 | 1883 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@669 | 1884 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 1885 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 1886 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
|
nkeynes@669 | 1887 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 1888 | JMP_TARGET(end);
|
nkeynes@669 | 1889 |
|
nkeynes@417 | 1890 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1891 | :}
|
nkeynes@416 | 1892 | FMOV @Rm+, FRn {:
|
nkeynes@671 | 1893 | COUNT_INST(I_FMOV6);
|
nkeynes@586 | 1894 | check_fpuen();
|
nkeynes@586 | 1895 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1896 | check_ralign32( R_EAX );
|
nkeynes@586 | 1897 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 1898 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1899 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1900 | JNE_rel8(doublesize);
|
nkeynes@669 | 1901 |
|
nkeynes@586 | 1902 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1903 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 1904 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 1905 | JMP_rel8(end);
|
nkeynes@669 | 1906 |
|
nkeynes@669 | 1907 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1908 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
|
nkeynes@669 | 1909 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 1910 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 1911 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 1912 | JMP_TARGET(end);
|
nkeynes@669 | 1913 |
|
nkeynes@417 | 1914 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1915 | :}
|
nkeynes@377 | 1916 | FMOV FRm, @(R0, Rn) {:
|
nkeynes@671 | 1917 | COUNT_INST(I_FMOV4);
|
nkeynes@586 | 1918 | check_fpuen();
|
nkeynes@586 | 1919 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1920 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@586 | 1921 | check_walign32( R_EAX );
|
nkeynes@586 | 1922 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 1923 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1924 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1925 | JNE_rel8(doublesize);
|
nkeynes@669 | 1926 |
|
nkeynes@669 | 1927 | load_fr( R_ECX, FRm );
|
nkeynes@586 | 1928 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@669 | 1929 | JMP_rel8(end);
|
nkeynes@669 | 1930 |
|
nkeynes@669 | 1931 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1932 | load_dr0( R_ECX, FRm );
|
nkeynes@669 | 1933 | load_dr1( R_EDX, FRm );
|
nkeynes@669 | 1934 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@669 | 1935 | JMP_TARGET(end);
|
nkeynes@669 | 1936 |
|
nkeynes@417 | 1937 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1938 | :}
|
nkeynes@377 | 1939 | FMOV @(R0, Rm), FRn {:
|
nkeynes@671 | 1940 | COUNT_INST(I_FMOV7);
|
nkeynes@586 | 1941 | check_fpuen();
|
nkeynes@586 | 1942 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 1943 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@586 | 1944 | check_ralign32( R_EAX );
|
nkeynes@586 | 1945 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 1946 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1947 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@669 | 1948 | JNE_rel8(doublesize);
|
nkeynes@669 | 1949 |
|
nkeynes@586 | 1950 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 1951 | store_fr( R_EAX, FRn );
|
nkeynes@669 | 1952 | JMP_rel8(end);
|
nkeynes@669 | 1953 |
|
nkeynes@669 | 1954 | JMP_TARGET(doublesize);
|
nkeynes@669 | 1955 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@669 | 1956 | store_dr0( R_ECX, FRn );
|
nkeynes@669 | 1957 | store_dr1( R_EAX, FRn );
|
nkeynes@669 | 1958 | JMP_TARGET(end);
|
nkeynes@669 | 1959 |
|
nkeynes@417 | 1960 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1961 | :}
|
nkeynes@377 | 1962 | FLDI0 FRn {: /* IFF PR=0 */
|
nkeynes@671 | 1963 | COUNT_INST(I_FLDI0);
|
nkeynes@377 | 1964 | check_fpuen();
|
nkeynes@377 | 1965 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1966 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 1967 | JNE_rel8(end);
|
nkeynes@377 | 1968 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@669 | 1969 | store_fr( R_EAX, FRn );
|
nkeynes@380 | 1970 | JMP_TARGET(end);
|
nkeynes@417 | 1971 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1972 | :}
|
nkeynes@377 | 1973 | FLDI1 FRn {: /* IFF PR=0 */
|
nkeynes@671 | 1974 | COUNT_INST(I_FLDI1);
|
nkeynes@377 | 1975 | check_fpuen();
|
nkeynes@377 | 1976 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1977 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 1978 | JNE_rel8(end);
|
nkeynes@377 | 1979 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@669 | 1980 | store_fr( R_EAX, FRn );
|
nkeynes@380 | 1981 | JMP_TARGET(end);
|
nkeynes@417 | 1982 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1983 | :}
|
nkeynes@377 | 1984 |
|
nkeynes@377 | 1985 | FLOAT FPUL, FRn {:
|
nkeynes@671 | 1986 | COUNT_INST(I_FLOAT);
|
nkeynes@377 | 1987 | check_fpuen();
|
nkeynes@377 | 1988 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1989 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 1990 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 1991 | JNE_rel8(doubleprec);
|
nkeynes@669 | 1992 | pop_fr( FRn );
|
nkeynes@669 | 1993 | JMP_rel8(end);
|
nkeynes@380 | 1994 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 1995 | pop_dr( FRn );
|
nkeynes@380 | 1996 | JMP_TARGET(end);
|
nkeynes@417 | 1997 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1998 | :}
|
nkeynes@377 | 1999 | FTRC FRm, FPUL {:
|
nkeynes@671 | 2000 | COUNT_INST(I_FTRC);
|
nkeynes@377 | 2001 | check_fpuen();
|
nkeynes@388 | 2002 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2003 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2004 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2005 | push_fr( FRm );
|
nkeynes@669 | 2006 | JMP_rel8(doop);
|
nkeynes@388 | 2007 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2008 | push_dr( FRm );
|
nkeynes@388 | 2009 | JMP_TARGET( doop );
|
nkeynes@388 | 2010 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 2011 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 2012 | FCOMIP_st(1);
|
nkeynes@669 | 2013 | JNA_rel8( sat );
|
nkeynes@388 | 2014 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 2015 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 2016 | FCOMIP_st(1); // 2
|
nkeynes@669 | 2017 | JAE_rel8( sat2 ); // 2
|
nkeynes@394 | 2018 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 2019 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 2020 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 2021 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 2022 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 2023 | FLDCW_r32ind( R_EAX );
|
nkeynes@669 | 2024 | JMP_rel8(end); // 2
|
nkeynes@388 | 2025 |
|
nkeynes@388 | 2026 | JMP_TARGET(sat);
|
nkeynes@388 | 2027 | JMP_TARGET(sat2);
|
nkeynes@388 | 2028 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 2029 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 2030 | FPOP_st();
|
nkeynes@388 | 2031 | JMP_TARGET(end);
|
nkeynes@417 | 2032 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2033 | :}
|
nkeynes@377 | 2034 | FLDS FRm, FPUL {:
|
nkeynes@671 | 2035 | COUNT_INST(I_FLDS);
|
nkeynes@377 | 2036 | check_fpuen();
|
nkeynes@669 | 2037 | load_fr( R_EAX, FRm );
|
nkeynes@377 | 2038 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 2039 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2040 | :}
|
nkeynes@377 | 2041 | FSTS FPUL, FRn {:
|
nkeynes@671 | 2042 | COUNT_INST(I_FSTS);
|
nkeynes@377 | 2043 | check_fpuen();
|
nkeynes@377 | 2044 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@669 | 2045 | store_fr( R_EAX, FRn );
|
nkeynes@417 | 2046 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2047 | :}
|
nkeynes@377 | 2048 | FCNVDS FRm, FPUL {:
|
nkeynes@671 | 2049 | COUNT_INST(I_FCNVDS);
|
nkeynes@377 | 2050 | check_fpuen();
|
nkeynes@377 | 2051 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2052 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2053 | JE_rel8(end); // only when PR=1
|
nkeynes@669 | 2054 | push_dr( FRm );
|
nkeynes@377 | 2055 | pop_fpul();
|
nkeynes@380 | 2056 | JMP_TARGET(end);
|
nkeynes@417 | 2057 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2058 | :}
|
nkeynes@377 | 2059 | FCNVSD FPUL, FRn {:
|
nkeynes@671 | 2060 | COUNT_INST(I_FCNVSD);
|
nkeynes@377 | 2061 | check_fpuen();
|
nkeynes@377 | 2062 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2063 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2064 | JE_rel8(end); // only when PR=1
|
nkeynes@377 | 2065 | push_fpul();
|
nkeynes@669 | 2066 | pop_dr( FRn );
|
nkeynes@380 | 2067 | JMP_TARGET(end);
|
nkeynes@417 | 2068 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2069 | :}
|
nkeynes@375 | 2070 |
|
nkeynes@359 | 2071 | /* Floating point instructions */
|
nkeynes@374 | 2072 | FABS FRn {:
|
nkeynes@671 | 2073 | COUNT_INST(I_FABS);
|
nkeynes@377 | 2074 | check_fpuen();
|
nkeynes@374 | 2075 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@374 | 2076 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2077 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2078 | push_fr(FRn); // 6
|
nkeynes@374 | 2079 | FABS_st0(); // 2
|
nkeynes@669 | 2080 | pop_fr(FRn); //6
|
nkeynes@669 | 2081 | JMP_rel8(end); // 2
|
nkeynes@380 | 2082 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2083 | push_dr(FRn);
|
nkeynes@374 | 2084 | FABS_st0();
|
nkeynes@669 | 2085 | pop_dr(FRn);
|
nkeynes@380 | 2086 | JMP_TARGET(end);
|
nkeynes@417 | 2087 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2088 | :}
|
nkeynes@377 | 2089 | FADD FRm, FRn {:
|
nkeynes@671 | 2090 | COUNT_INST(I_FADD);
|
nkeynes@377 | 2091 | check_fpuen();
|
nkeynes@375 | 2092 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2093 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2094 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2095 | push_fr(FRm);
|
nkeynes@669 | 2096 | push_fr(FRn);
|
nkeynes@377 | 2097 | FADDP_st(1);
|
nkeynes@669 | 2098 | pop_fr(FRn);
|
nkeynes@669 | 2099 | JMP_rel8(end);
|
nkeynes@380 | 2100 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2101 | push_dr(FRm);
|
nkeynes@669 | 2102 | push_dr(FRn);
|
nkeynes@377 | 2103 | FADDP_st(1);
|
nkeynes@669 | 2104 | pop_dr(FRn);
|
nkeynes@380 | 2105 | JMP_TARGET(end);
|
nkeynes@417 | 2106 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2107 | :}
|
nkeynes@377 | 2108 | FDIV FRm, FRn {:
|
nkeynes@671 | 2109 | COUNT_INST(I_FDIV);
|
nkeynes@377 | 2110 | check_fpuen();
|
nkeynes@375 | 2111 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2112 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2113 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2114 | push_fr(FRn);
|
nkeynes@669 | 2115 | push_fr(FRm);
|
nkeynes@377 | 2116 | FDIVP_st(1);
|
nkeynes@669 | 2117 | pop_fr(FRn);
|
nkeynes@669 | 2118 | JMP_rel8(end);
|
nkeynes@380 | 2119 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2120 | push_dr(FRn);
|
nkeynes@669 | 2121 | push_dr(FRm);
|
nkeynes@377 | 2122 | FDIVP_st(1);
|
nkeynes@669 | 2123 | pop_dr(FRn);
|
nkeynes@380 | 2124 | JMP_TARGET(end);
|
nkeynes@417 | 2125 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2126 | :}
|
nkeynes@375 | 2127 | FMAC FR0, FRm, FRn {:
|
nkeynes@671 | 2128 | COUNT_INST(I_FMAC);
|
nkeynes@377 | 2129 | check_fpuen();
|
nkeynes@375 | 2130 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2131 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2132 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2133 | push_fr( 0 );
|
nkeynes@669 | 2134 | push_fr( FRm );
|
nkeynes@375 | 2135 | FMULP_st(1);
|
nkeynes@669 | 2136 | push_fr( FRn );
|
nkeynes@375 | 2137 | FADDP_st(1);
|
nkeynes@669 | 2138 | pop_fr( FRn );
|
nkeynes@669 | 2139 | JMP_rel8(end);
|
nkeynes@380 | 2140 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2141 | push_dr( 0 );
|
nkeynes@669 | 2142 | push_dr( FRm );
|
nkeynes@375 | 2143 | FMULP_st(1);
|
nkeynes@669 | 2144 | push_dr( FRn );
|
nkeynes@375 | 2145 | FADDP_st(1);
|
nkeynes@669 | 2146 | pop_dr( FRn );
|
nkeynes@380 | 2147 | JMP_TARGET(end);
|
nkeynes@417 | 2148 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2149 | :}
|
nkeynes@375 | 2150 |
|
nkeynes@377 | 2151 | FMUL FRm, FRn {:
|
nkeynes@671 | 2152 | COUNT_INST(I_FMUL);
|
nkeynes@377 | 2153 | check_fpuen();
|
nkeynes@377 | 2154 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2155 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2156 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2157 | push_fr(FRm);
|
nkeynes@669 | 2158 | push_fr(FRn);
|
nkeynes@377 | 2159 | FMULP_st(1);
|
nkeynes@669 | 2160 | pop_fr(FRn);
|
nkeynes@669 | 2161 | JMP_rel8(end);
|
nkeynes@380 | 2162 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2163 | push_dr(FRm);
|
nkeynes@669 | 2164 | push_dr(FRn);
|
nkeynes@377 | 2165 | FMULP_st(1);
|
nkeynes@669 | 2166 | pop_dr(FRn);
|
nkeynes@380 | 2167 | JMP_TARGET(end);
|
nkeynes@417 | 2168 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2169 | :}
|
nkeynes@377 | 2170 | FNEG FRn {:
|
nkeynes@671 | 2171 | COUNT_INST(I_FNEG);
|
nkeynes@377 | 2172 | check_fpuen();
|
nkeynes@377 | 2173 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2174 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2175 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2176 | push_fr(FRn);
|
nkeynes@377 | 2177 | FCHS_st0();
|
nkeynes@669 | 2178 | pop_fr(FRn);
|
nkeynes@669 | 2179 | JMP_rel8(end);
|
nkeynes@380 | 2180 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2181 | push_dr(FRn);
|
nkeynes@377 | 2182 | FCHS_st0();
|
nkeynes@669 | 2183 | pop_dr(FRn);
|
nkeynes@380 | 2184 | JMP_TARGET(end);
|
nkeynes@417 | 2185 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2186 | :}
|
nkeynes@377 | 2187 | FSRRA FRn {:
|
nkeynes@671 | 2188 | COUNT_INST(I_FSRRA);
|
nkeynes@377 | 2189 | check_fpuen();
|
nkeynes@377 | 2190 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2191 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2192 | JNE_rel8(end); // PR=0 only
|
nkeynes@377 | 2193 | FLD1_st0();
|
nkeynes@669 | 2194 | push_fr(FRn);
|
nkeynes@377 | 2195 | FSQRT_st0();
|
nkeynes@377 | 2196 | FDIVP_st(1);
|
nkeynes@669 | 2197 | pop_fr(FRn);
|
nkeynes@380 | 2198 | JMP_TARGET(end);
|
nkeynes@417 | 2199 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2200 | :}
|
nkeynes@377 | 2201 | FSQRT FRn {:
|
nkeynes@671 | 2202 | COUNT_INST(I_FSQRT);
|
nkeynes@377 | 2203 | check_fpuen();
|
nkeynes@377 | 2204 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2205 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2206 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2207 | push_fr(FRn);
|
nkeynes@377 | 2208 | FSQRT_st0();
|
nkeynes@669 | 2209 | pop_fr(FRn);
|
nkeynes@669 | 2210 | JMP_rel8(end);
|
nkeynes@380 | 2211 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2212 | push_dr(FRn);
|
nkeynes@377 | 2213 | FSQRT_st0();
|
nkeynes@669 | 2214 | pop_dr(FRn);
|
nkeynes@380 | 2215 | JMP_TARGET(end);
|
nkeynes@417 | 2216 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2217 | :}
|
nkeynes@377 | 2218 | FSUB FRm, FRn {:
|
nkeynes@671 | 2219 | COUNT_INST(I_FSUB);
|
nkeynes@377 | 2220 | check_fpuen();
|
nkeynes@377 | 2221 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2222 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2223 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2224 | push_fr(FRn);
|
nkeynes@669 | 2225 | push_fr(FRm);
|
nkeynes@388 | 2226 | FSUBP_st(1);
|
nkeynes@669 | 2227 | pop_fr(FRn);
|
nkeynes@669 | 2228 | JMP_rel8(end);
|
nkeynes@380 | 2229 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2230 | push_dr(FRn);
|
nkeynes@669 | 2231 | push_dr(FRm);
|
nkeynes@388 | 2232 | FSUBP_st(1);
|
nkeynes@669 | 2233 | pop_dr(FRn);
|
nkeynes@380 | 2234 | JMP_TARGET(end);
|
nkeynes@417 | 2235 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2236 | :}
|
nkeynes@377 | 2237 |
|
nkeynes@377 | 2238 | FCMP/EQ FRm, FRn {:
|
nkeynes@671 | 2239 | COUNT_INST(I_FCMPEQ);
|
nkeynes@377 | 2240 | check_fpuen();
|
nkeynes@377 | 2241 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2242 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2243 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2244 | push_fr(FRm);
|
nkeynes@669 | 2245 | push_fr(FRn);
|
nkeynes@669 | 2246 | JMP_rel8(end);
|
nkeynes@380 | 2247 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2248 | push_dr(FRm);
|
nkeynes@669 | 2249 | push_dr(FRn);
|
nkeynes@382 | 2250 | JMP_TARGET(end);
|
nkeynes@377 | 2251 | FCOMIP_st(1);
|
nkeynes@377 | 2252 | SETE_t();
|
nkeynes@377 | 2253 | FPOP_st();
|
nkeynes@417 | 2254 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2255 | :}
|
nkeynes@377 | 2256 | FCMP/GT FRm, FRn {:
|
nkeynes@671 | 2257 | COUNT_INST(I_FCMPGT);
|
nkeynes@377 | 2258 | check_fpuen();
|
nkeynes@377 | 2259 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2260 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2261 | JNE_rel8(doubleprec);
|
nkeynes@669 | 2262 | push_fr(FRm);
|
nkeynes@669 | 2263 | push_fr(FRn);
|
nkeynes@669 | 2264 | JMP_rel8(end);
|
nkeynes@380 | 2265 | JMP_TARGET(doubleprec);
|
nkeynes@669 | 2266 | push_dr(FRm);
|
nkeynes@669 | 2267 | push_dr(FRn);
|
nkeynes@380 | 2268 | JMP_TARGET(end);
|
nkeynes@377 | 2269 | FCOMIP_st(1);
|
nkeynes@377 | 2270 | SETA_t();
|
nkeynes@377 | 2271 | FPOP_st();
|
nkeynes@417 | 2272 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2273 | :}
|
nkeynes@377 | 2274 |
|
nkeynes@377 | 2275 | FSCA FPUL, FRn {:
|
nkeynes@671 | 2276 | COUNT_INST(I_FSCA);
|
nkeynes@377 | 2277 | check_fpuen();
|
nkeynes@388 | 2278 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2279 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2280 | JNE_rel8(doubleprec );
|
nkeynes@669 | 2281 | LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
|
nkeynes@388 | 2282 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 2283 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 2284 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2285 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2286 | :}
|
nkeynes@377 | 2287 | FIPR FVm, FVn {:
|
nkeynes@671 | 2288 | COUNT_INST(I_FIPR);
|
nkeynes@377 | 2289 | check_fpuen();
|
nkeynes@388 | 2290 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2291 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2292 | JNE_rel8( doubleprec);
|
nkeynes@388 | 2293 |
|
nkeynes@669 | 2294 | push_fr( FVm<<2 );
|
nkeynes@669 | 2295 | push_fr( FVn<<2 );
|
nkeynes@388 | 2296 | FMULP_st(1);
|
nkeynes@669 | 2297 | push_fr( (FVm<<2)+1);
|
nkeynes@669 | 2298 | push_fr( (FVn<<2)+1);
|
nkeynes@388 | 2299 | FMULP_st(1);
|
nkeynes@388 | 2300 | FADDP_st(1);
|
nkeynes@669 | 2301 | push_fr( (FVm<<2)+2);
|
nkeynes@669 | 2302 | push_fr( (FVn<<2)+2);
|
nkeynes@388 | 2303 | FMULP_st(1);
|
nkeynes@388 | 2304 | FADDP_st(1);
|
nkeynes@669 | 2305 | push_fr( (FVm<<2)+3);
|
nkeynes@669 | 2306 | push_fr( (FVn<<2)+3);
|
nkeynes@388 | 2307 | FMULP_st(1);
|
nkeynes@388 | 2308 | FADDP_st(1);
|
nkeynes@669 | 2309 | pop_fr( (FVn<<2)+3);
|
nkeynes@388 | 2310 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2311 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2312 | :}
|
nkeynes@377 | 2313 | FTRV XMTRX, FVn {:
|
nkeynes@671 | 2314 | COUNT_INST(I_FTRV);
|
nkeynes@377 | 2315 | check_fpuen();
|
nkeynes@388 | 2316 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2317 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@669 | 2318 | JNE_rel8( doubleprec );
|
nkeynes@669 | 2319 | LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
|
nkeynes@669 | 2320 | call_func1( sh4_ftrv, R_EDX ); // 12
|
nkeynes@388 | 2321 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2322 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2323 | :}
|
nkeynes@377 | 2324 |
|
nkeynes@377 | 2325 | FRCHG {:
|
nkeynes@671 | 2326 | COUNT_INST(I_FRCHG);
|
nkeynes@377 | 2327 | check_fpuen();
|
nkeynes@377 | 2328 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2329 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 2330 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@669 | 2331 | call_func0( sh4_switch_fr_banks );
|
nkeynes@417 | 2332 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2333 | :}
|
nkeynes@377 | 2334 | FSCHG {:
|
nkeynes@671 | 2335 | COUNT_INST(I_FSCHG);
|
nkeynes@377 | 2336 | check_fpuen();
|
nkeynes@377 | 2337 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2338 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 2339 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@417 | 2340 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2341 | :}
|
nkeynes@359 | 2342 |
|
nkeynes@359 | 2343 | /* Processor control instructions */
|
nkeynes@368 | 2344 | LDC Rm, SR {:
|
nkeynes@671 | 2345 | COUNT_INST(I_LDCSR);
|
nkeynes@386 | 2346 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2347 | SLOTILLEGAL();
|
nkeynes@386 | 2348 | } else {
|
nkeynes@386 | 2349 | check_priv();
|
nkeynes@386 | 2350 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2351 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2352 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2353 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2354 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2355 | }
|
nkeynes@368 | 2356 | :}
|
nkeynes@359 | 2357 | LDC Rm, GBR {:
|
nkeynes@671 | 2358 | COUNT_INST(I_LDC);
|
nkeynes@359 | 2359 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2360 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2361 | :}
|
nkeynes@359 | 2362 | LDC Rm, VBR {:
|
nkeynes@671 | 2363 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2364 | check_priv();
|
nkeynes@359 | 2365 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2366 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2367 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2368 | :}
|
nkeynes@359 | 2369 | LDC Rm, SSR {:
|
nkeynes@671 | 2370 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2371 | check_priv();
|
nkeynes@359 | 2372 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2373 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2374 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2375 | :}
|
nkeynes@359 | 2376 | LDC Rm, SGR {:
|
nkeynes@671 | 2377 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2378 | check_priv();
|
nkeynes@359 | 2379 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2380 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 2381 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2382 | :}
|
nkeynes@359 | 2383 | LDC Rm, SPC {:
|
nkeynes@671 | 2384 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2385 | check_priv();
|
nkeynes@359 | 2386 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2387 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2388 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2389 | :}
|
nkeynes@359 | 2390 | LDC Rm, DBR {:
|
nkeynes@671 | 2391 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2392 | check_priv();
|
nkeynes@359 | 2393 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2394 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 2395 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2396 | :}
|
nkeynes@374 | 2397 | LDC Rm, Rn_BANK {:
|
nkeynes@671 | 2398 | COUNT_INST(I_LDC);
|
nkeynes@386 | 2399 | check_priv();
|
nkeynes@374 | 2400 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2401 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2402 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2403 | :}
|
nkeynes@359 | 2404 | LDC.L @Rm+, GBR {:
|
nkeynes@671 | 2405 | COUNT_INST(I_LDCM);
|
nkeynes@359 | 2406 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2407 | check_ralign32( R_EAX );
|
nkeynes@586 | 2408 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2409 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2410 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2411 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 2412 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2413 | :}
|
nkeynes@368 | 2414 | LDC.L @Rm+, SR {:
|
nkeynes@671 | 2415 | COUNT_INST(I_LDCSRM);
|
nkeynes@386 | 2416 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2417 | SLOTILLEGAL();
|
nkeynes@386 | 2418 | } else {
|
nkeynes@586 | 2419 | check_priv();
|
nkeynes@386 | 2420 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2421 | check_ralign32( R_EAX );
|
nkeynes@586 | 2422 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2423 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2424 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@386 | 2425 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2426 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2427 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2428 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2429 | }
|
nkeynes@359 | 2430 | :}
|
nkeynes@359 | 2431 | LDC.L @Rm+, VBR {:
|
nkeynes@671 | 2432 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2433 | check_priv();
|
nkeynes@359 | 2434 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2435 | check_ralign32( R_EAX );
|
nkeynes@586 | 2436 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2437 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2438 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2439 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2440 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2441 | :}
|
nkeynes@359 | 2442 | LDC.L @Rm+, SSR {:
|
nkeynes@671 | 2443 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2444 | check_priv();
|
nkeynes@359 | 2445 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2446 | check_ralign32( R_EAX );
|
nkeynes@586 | 2447 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2448 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2449 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2450 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2451 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2452 | :}
|
nkeynes@359 | 2453 | LDC.L @Rm+, SGR {:
|
nkeynes@671 | 2454 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2455 | check_priv();
|
nkeynes@359 | 2456 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2457 | check_ralign32( R_EAX );
|
nkeynes@586 | 2458 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2459 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2460 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2461 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 2462 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2463 | :}
|
nkeynes@359 | 2464 | LDC.L @Rm+, SPC {:
|
nkeynes@671 | 2465 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2466 | check_priv();
|
nkeynes@359 | 2467 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2468 | check_ralign32( R_EAX );
|
nkeynes@586 | 2469 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2470 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2471 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2472 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2473 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2474 | :}
|
nkeynes@359 | 2475 | LDC.L @Rm+, DBR {:
|
nkeynes@671 | 2476 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2477 | check_priv();
|
nkeynes@359 | 2478 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2479 | check_ralign32( R_EAX );
|
nkeynes@586 | 2480 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2481 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2482 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2483 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 2484 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2485 | :}
|
nkeynes@359 | 2486 | LDC.L @Rm+, Rn_BANK {:
|
nkeynes@671 | 2487 | COUNT_INST(I_LDCM);
|
nkeynes@586 | 2488 | check_priv();
|
nkeynes@374 | 2489 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2490 | check_ralign32( R_EAX );
|
nkeynes@586 | 2491 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2492 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2493 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@374 | 2494 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2495 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2496 | :}
|
nkeynes@626 | 2497 | LDS Rm, FPSCR {:
|
nkeynes@671 | 2498 | COUNT_INST(I_LDS);
|
nkeynes@626 | 2499 | check_fpuen();
|
nkeynes@359 | 2500 | load_reg( R_EAX, Rm );
|
nkeynes@669 | 2501 | call_func1( sh4_write_fpscr, R_EAX );
|
nkeynes@417 | 2502 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2503 | :}
|
nkeynes@359 | 2504 | LDS.L @Rm+, FPSCR {:
|
nkeynes@671 | 2505 | COUNT_INST(I_LDS);
|
nkeynes@626 | 2506 | check_fpuen();
|
nkeynes@359 | 2507 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2508 | check_ralign32( R_EAX );
|
nkeynes@586 | 2509 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2510 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2511 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@669 | 2512 | call_func1( sh4_write_fpscr, R_EAX );
|
nkeynes@417 | 2513 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2514 | :}
|
nkeynes@359 | 2515 | LDS Rm, FPUL {:
|
nkeynes@671 | 2516 | COUNT_INST(I_LDS);
|
nkeynes@626 | 2517 | check_fpuen();
|
nkeynes@359 | 2518 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2519 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2520 | :}
|
nkeynes@359 | 2521 | LDS.L @Rm+, FPUL {:
|
nkeynes@671 | 2522 | COUNT_INST(I_LDSM);
|
nkeynes@626 | 2523 | check_fpuen();
|
nkeynes@359 | 2524 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2525 | check_ralign32( R_EAX );
|
nkeynes@586 | 2526 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2527 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2528 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2529 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 2530 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2531 | :}
|
nkeynes@359 | 2532 | LDS Rm, MACH {:
|
nkeynes@671 | 2533 | COUNT_INST(I_LDS);
|
nkeynes@359 | 2534 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2535 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2536 | :}
|
nkeynes@359 | 2537 | LDS.L @Rm+, MACH {:
|
nkeynes@671 | 2538 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 2539 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2540 | check_ralign32( R_EAX );
|
nkeynes@586 | 2541 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2542 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2543 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2544 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 2545 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2546 | :}
|
nkeynes@359 | 2547 | LDS Rm, MACL {:
|
nkeynes@671 | 2548 | COUNT_INST(I_LDS);
|
nkeynes@359 | 2549 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2550 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2551 | :}
|
nkeynes@359 | 2552 | LDS.L @Rm+, MACL {:
|
nkeynes@671 | 2553 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 2554 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2555 | check_ralign32( R_EAX );
|
nkeynes@586 | 2556 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2557 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2558 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2559 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 2560 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2561 | :}
|
nkeynes@359 | 2562 | LDS Rm, PR {:
|
nkeynes@671 | 2563 | COUNT_INST(I_LDS);
|
nkeynes@359 | 2564 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2565 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2566 | :}
|
nkeynes@359 | 2567 | LDS.L @Rm+, PR {:
|
nkeynes@671 | 2568 | COUNT_INST(I_LDSM);
|
nkeynes@359 | 2569 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2570 | check_ralign32( R_EAX );
|
nkeynes@586 | 2571 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2572 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2573 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 2574 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 2575 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2576 | :}
|
nkeynes@550 | 2577 | LDTLB {:
|
nkeynes@671 | 2578 | COUNT_INST(I_LDTLB);
|
nkeynes@553 | 2579 | call_func0( MMU_ldtlb );
|
nkeynes@550 | 2580 | :}
|
nkeynes@671 | 2581 | OCBI @Rn {:
|
nkeynes@671 | 2582 | COUNT_INST(I_OCBI);
|
nkeynes@671 | 2583 | :}
|
nkeynes@671 | 2584 | OCBP @Rn {:
|
nkeynes@671 | 2585 | COUNT_INST(I_OCBP);
|
nkeynes@671 | 2586 | :}
|
nkeynes@671 | 2587 | OCBWB @Rn {:
|
nkeynes@671 | 2588 | COUNT_INST(I_OCBWB);
|
nkeynes@671 | 2589 | :}
|
nkeynes@374 | 2590 | PREF @Rn {:
|
nkeynes@671 | 2591 | COUNT_INST(I_PREF);
|
nkeynes@374 | 2592 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 2593 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 2594 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 2595 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@669 | 2596 | JNE_rel8(end);
|
nkeynes@532 | 2597 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@586 | 2598 | TEST_r32_r32( R_EAX, R_EAX );
|
nkeynes@586 | 2599 | JE_exc(-1);
|
nkeynes@380 | 2600 | JMP_TARGET(end);
|
nkeynes@417 | 2601 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2602 | :}
|
nkeynes@388 | 2603 | SLEEP {:
|
nkeynes@671 | 2604 | COUNT_INST(I_SLEEP);
|
nkeynes@388 | 2605 | check_priv();
|
nkeynes@388 | 2606 | call_func0( sh4_sleep );
|
nkeynes@417 | 2607 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@590 | 2608 | sh4_x86.in_delay_slot = DELAY_NONE;
|
nkeynes@408 | 2609 | return 2;
|
nkeynes@388 | 2610 | :}
|
nkeynes@386 | 2611 | STC SR, Rn {:
|
nkeynes@671 | 2612 | COUNT_INST(I_STCSR);
|
nkeynes@386 | 2613 | check_priv();
|
nkeynes@386 | 2614 | call_func0(sh4_read_sr);
|
nkeynes@386 | 2615 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2616 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2617 | :}
|
nkeynes@359 | 2618 | STC GBR, Rn {:
|
nkeynes@671 | 2619 | COUNT_INST(I_STC);
|
nkeynes@359 | 2620 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2621 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2622 | :}
|
nkeynes@359 | 2623 | STC VBR, Rn {:
|
nkeynes@671 | 2624 | COUNT_INST(I_STC);
|
nkeynes@386 | 2625 | check_priv();
|
nkeynes@359 | 2626 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2627 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2628 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2629 | :}
|
nkeynes@359 | 2630 | STC SSR, Rn {:
|
nkeynes@671 | 2631 | COUNT_INST(I_STC);
|
nkeynes@386 | 2632 | check_priv();
|
nkeynes@359 | 2633 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2634 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2635 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2636 | :}
|
nkeynes@359 | 2637 | STC SPC, Rn {:
|
nkeynes@671 | 2638 | COUNT_INST(I_STC);
|
nkeynes@386 | 2639 | check_priv();
|
nkeynes@359 | 2640 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2641 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2642 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2643 | :}
|
nkeynes@359 | 2644 | STC SGR, Rn {:
|
nkeynes@671 | 2645 | COUNT_INST(I_STC);
|
nkeynes@386 | 2646 | check_priv();
|
nkeynes@359 | 2647 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2648 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2649 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2650 | :}
|
nkeynes@359 | 2651 | STC DBR, Rn {:
|
nkeynes@671 | 2652 | COUNT_INST(I_STC);
|
nkeynes@386 | 2653 | check_priv();
|
nkeynes@359 | 2654 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2655 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2656 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2657 | :}
|
nkeynes@374 | 2658 | STC Rm_BANK, Rn {:
|
nkeynes@671 | 2659 | COUNT_INST(I_STC);
|
nkeynes@386 | 2660 | check_priv();
|
nkeynes@374 | 2661 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2662 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2663 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2664 | :}
|
nkeynes@374 | 2665 | STC.L SR, @-Rn {:
|
nkeynes@671 | 2666 | COUNT_INST(I_STCSRM);
|
nkeynes@586 | 2667 | check_priv();
|
nkeynes@586 | 2668 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2669 | check_walign32( R_EAX );
|
nkeynes@586 | 2670 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2671 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2672 | PUSH_realigned_r32( R_EAX );
|
nkeynes@395 | 2673 | call_func0( sh4_read_sr );
|
nkeynes@586 | 2674 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 2675 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@368 | 2676 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 2677 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2678 | :}
|
nkeynes@359 | 2679 | STC.L VBR, @-Rn {:
|
nkeynes@671 | 2680 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2681 | check_priv();
|
nkeynes@586 | 2682 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2683 | check_walign32( R_EAX );
|
nkeynes@586 | 2684 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2685 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2686 | load_spreg( R_EDX, R_VBR );
|
nkeynes@586 | 2687 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2688 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2689 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2690 | :}
|
nkeynes@359 | 2691 | STC.L SSR, @-Rn {:
|
nkeynes@671 | 2692 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2693 | check_priv();
|
nkeynes@586 | 2694 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2695 | check_walign32( R_EAX );
|
nkeynes@586 | 2696 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2697 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2698 | load_spreg( R_EDX, R_SSR );
|
nkeynes@586 | 2699 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2700 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2701 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2702 | :}
|
nkeynes@416 | 2703 | STC.L SPC, @-Rn {:
|
nkeynes@671 | 2704 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2705 | check_priv();
|
nkeynes@586 | 2706 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2707 | check_walign32( R_EAX );
|
nkeynes@586 | 2708 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2709 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2710 | load_spreg( R_EDX, R_SPC );
|
nkeynes@586 | 2711 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2712 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2713 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2714 | :}
|
nkeynes@359 | 2715 | STC.L SGR, @-Rn {:
|
nkeynes@671 | 2716 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2717 | check_priv();
|
nkeynes@586 | 2718 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2719 | check_walign32( R_EAX );
|
nkeynes@586 | 2720 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2721 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2722 | load_spreg( R_EDX, R_SGR );
|
nkeynes@586 | 2723 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2724 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2725 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2726 | :}
|
nkeynes@359 | 2727 | STC.L DBR, @-Rn {:
|
nkeynes@671 | 2728 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2729 | check_priv();
|
nkeynes@586 | 2730 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2731 | check_walign32( R_EAX );
|
nkeynes@586 | 2732 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2733 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2734 | load_spreg( R_EDX, R_DBR );
|
nkeynes@586 | 2735 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2736 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2737 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2738 | :}
|
nkeynes@374 | 2739 | STC.L Rm_BANK, @-Rn {:
|
nkeynes@671 | 2740 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2741 | check_priv();
|
nkeynes@586 | 2742 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2743 | check_walign32( R_EAX );
|
nkeynes@586 | 2744 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2745 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2746 | load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@586 | 2747 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2748 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2749 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2750 | :}
|
nkeynes@359 | 2751 | STC.L GBR, @-Rn {:
|
nkeynes@671 | 2752 | COUNT_INST(I_STCM);
|
nkeynes@586 | 2753 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2754 | check_walign32( R_EAX );
|
nkeynes@586 | 2755 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 2756 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2757 | load_spreg( R_EDX, R_GBR );
|
nkeynes@586 | 2758 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2759 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2760 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2761 | :}
|
nkeynes@359 | 2762 | STS FPSCR, Rn {:
|
|