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lxdream.org :: lxdream/test/testspu.c
lxdream 0.9.1
released Jun 29
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filename test/testspu.c
changeset 278:a66aaa522d31
next812:8cc61d5ea1f8
author nkeynes
date Sun Jan 14 02:53:11 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Initial (non-working) spu dma test case
file annotate diff log raw
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#include <stdlib.h>
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#include "asic.h"
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#include "lib.h"
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#include "testdata.h"
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#define SPUBASE 0xA05F7800
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#define SPUBASERAM 0x00800000
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#define SPUWAIT  (SPUBASE+0x90)
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#define SPUMAGIC (SPUBASE+0xBC)
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#define SPUDMAEXT(x) (SPUBASE+(0x20*(x)))
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#define SPUDMAHOST(x) (SPUBASE+(0x20*(x))+0x04)
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#define SPUDMASIZE(x) (SPUBASE+(0x20*(x))+0x08)
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#define SPUDMADIR(x) (SPUBASE+(0x20*(x))+0x0C)
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#define SPUDMAMODE(x) (SPUBASE+(0x20*(x))+0x10)
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#define SPUDMACTL1(x) (SPUBASE+(0x20*(x))+0x14)
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#define SPUDMACTL2(x) (SPUBASE+(0x20*(x))+0x18)
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#define SPUDMASTOP(x) (SPUBASE+(0x20*(x))+0x1C)
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void dump_spu_regs()
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{
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    fwrite_dump( stderr, (char *)(0xA05F7800), 0x100 );
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}    
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int dma_to_spu( int chan, uint32_t target, char *data, uint32_t size )
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{
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    long_write( SPUWAIT, 0 );
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    long_write( SPUMAGIC, 0x4659404f );
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    long_write( SPUDMACTL1(chan), 0 );
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    long_write( SPUDMACTL2(chan), 0 );
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    long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
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    long_write( SPUDMASIZE(chan), size | 0x80000000 );
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    long_write( SPUDMAEXT(chan), target );
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    long_write( SPUDMADIR(chan), 0 );
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    long_write( SPUDMAMODE(chan), 0 );
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    long_write( SPUDMACTL1(chan), 1 );
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    long_write( SPUDMACTL2(chan), 1 );
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    if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
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	fprintf( stderr, "Timeout waiting for DMA event\n" );
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	dump_spu_regs();
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	return -1;
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    }
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    return 0;
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}
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int dma_from_spu( int chan, char *data, uint32_t src, uint32_t size )
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{
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    long_write( SPUWAIT, 0 );
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    long_write( SPUMAGIC, 0x4659404f );
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    long_write( SPUDMACTL1(chan), 0 );
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    long_write( SPUDMACTL2(chan), 0 );
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    long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
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    long_write( SPUDMASIZE(chan), size | 0x80000000 );
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    long_write( SPUDMAEXT(chan), src );
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    long_write( SPUDMADIR(chan), 1 );
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    long_write( SPUDMAMODE(chan), 5 );
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    long_write( SPUDMACTL1(chan), 1 );
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    long_write( SPUDMACTL2(chan), 1 );
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    if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
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	fprintf( stderr, "Timeout waiting for DMA event\n" );
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	dump_spu_regs();
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	return -1;
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    }
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    return 0;
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}
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#define SPUTARGETADDR (SPUBASERAM+0x10000)
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#define SPUTARGET ((char *)(SPUTARGETADDR))
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int test_spu_dma_channel( int chan )
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{
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    char sampledata1[256+32];
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    char sampledata2[256+32];
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    char resultdata[256+32];
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    int i;
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    char *p1 = DMA_ALIGN(sampledata1), *p2 = DMA_ALIGN(sampledata2);
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    char *r = DMA_ALIGN(resultdata);
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    for( i=0; i<256; i++ ) {
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	p1[i] = (char)(i*i);
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	p2[i] = 256 - i;
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    }
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    if( dma_to_spu( chan, SPUTARGETADDR, p1, 256 ) != 0 ) {
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	return -1;
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    }
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    if( memcmp( p1, SPUTARGET, 256 ) != 0 ) {
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	fprintf( stderr, "First data mismatch:\n" );
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	fwrite_diff( stderr, p1, 256, SPUTARGET, 256 );
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	return -1;
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    }
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    if( dma_to_spu( chan, SPUTARGETADDR, p2, 256 ) != 0 ) {
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	return -1;
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    }
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    if( memcmp( p2, SPUTARGET, 256 ) != 0 ) {
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	fprintf( stderr, "Second data mismatch:\n" );
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	fwrite_diff( stderr, p2, 256, SPUTARGET, 256 );
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	return -1;
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    }
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    memset( r, 0, 256 );
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    if( dma_from_spu( chan, r, SPUTARGETADDR, 256 ) != 0 ) {
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	return -1;
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    }
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    if( memcmp( p2, r, 256 ) != 0 ) {
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	fprintf( stderr, "Read data mismatch:\n" );
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	fwrite_diff( stderr, p2, 256, r, 256 );
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	return -1;
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    }
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}
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int test_spu_dma()
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{
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    int i; 
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    for( i=0; i<4; i++ ) {
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	if( test_spu_dma_channel(i) != 0 ) {
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	    return -1;
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	}
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    }
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}
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test_func_t tests[] = { test_spu_dma, NULL };
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int main()
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{
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    return run_tests(tests);
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}
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