| nkeynes@231 | 1 | .section .text
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| nkeynes@231 | 2 | .include "sh4/inc.s"
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| nkeynes@231 | 3 | !
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| nkeynes@231 | 4 | ! Test for all cases that raise a slot-illegal exception (according to the SH4
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| nkeynes@231 | 5 | ! manual). See Page 103 of the Hitachi manual
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| nkeynes@231 | 6 |
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| nkeynes@231 | 7 | .global _test_slot_illegal
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| nkeynes@231 | 8 | _test_slot_illegal:
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| nkeynes@231 | 9 | start_test
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| nkeynes@231 | 10 |
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| nkeynes@231 | 11 | ! First the easy ones - instructions not permitted in delay slots at any
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| nkeynes@231 | 12 | ! time:
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| nkeynes@231 | 13 | ! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
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| nkeynes@231 | 14 | ! LDC (to SR), MOV pcrel, MOVA
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| nkeynes@231 | 15 | !
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| nkeynes@231 | 16 | ! Note that the tests use BSR as the branch instruction, and assume it
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| nkeynes@231 | 17 | ! functions correctly.
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| nkeynes@231 | 18 |
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| nkeynes@231 | 19 | test_slot_1: !JMP
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| nkeynes@231 | 20 | add #1, r12
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| nkeynes@231 | 21 | expect_exc 0x000001A0
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| nkeynes@231 | 22 | test_slot_1_pc:
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| nkeynes@231 | 23 | bsr test_slot_fail
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| nkeynes@231 | 24 | jmp @r3
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| nkeynes@231 | 25 | assert_exc_caught test_slot_str_k1 test_slot_1_pc
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| nkeynes@231 | 26 |
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| nkeynes@231 | 27 | test_slot_2: ! JSR
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| nkeynes@231 | 28 | add #1, r12
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| nkeynes@231 | 29 | expect_exc 0x000001A0
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| nkeynes@231 | 30 | test_slot_2_pc:
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| nkeynes@231 | 31 | bsr test_slot_fail
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| nkeynes@231 | 32 | jsr @r3
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| nkeynes@231 | 33 | assert_exc_caught test_slot_str_k1 test_slot_2_pc
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| nkeynes@231 | 34 | bra test_slot_3
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| nkeynes@231 | 35 | nop
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| nkeynes@231 | 36 | test_slot_str_k1:
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| nkeynes@231 | 37 | .long test_slot_str
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| nkeynes@231 | 38 |
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| nkeynes@231 | 39 | test_slot_3: ! BRA
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| nkeynes@231 | 40 | add #1, r12
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| nkeynes@231 | 41 | expect_exc 0x000001A0
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| nkeynes@231 | 42 | test_slot_3_pc:
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| nkeynes@231 | 43 | bsr test_slot_fail
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| nkeynes@231 | 44 | bra test_slot_fail
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| nkeynes@231 | 45 | assert_exc_caught test_slot_str_k test_slot_3_pc
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| nkeynes@231 | 46 |
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| nkeynes@231 | 47 | test_slot_4: ! BRAF
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| nkeynes@231 | 48 | add #1, r12
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| nkeynes@231 | 49 | expect_exc 0x000001A0
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| nkeynes@231 | 50 | test_slot_4_pc:
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| nkeynes@231 | 51 | bsr test_slot_fail
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| nkeynes@231 | 52 | braf r3
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| nkeynes@231 | 53 | assert_exc_caught test_slot_str_k test_slot_4_pc
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| nkeynes@231 | 54 |
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| nkeynes@231 | 55 | test_slot_5: ! BSR
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| nkeynes@231 | 56 | add #1, r12
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| nkeynes@231 | 57 | expect_exc 0x000001A0
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| nkeynes@231 | 58 | test_slot_5_pc:
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| nkeynes@231 | 59 | bsr test_slot_fail
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| nkeynes@231 | 60 | bsr test_slot_fail
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| nkeynes@231 | 61 | assert_exc_caught test_slot_str_k test_slot_5_pc
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| nkeynes@231 | 62 |
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| nkeynes@231 | 63 | test_slot_6: ! BSRF
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| nkeynes@231 | 64 | add #1, r12
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| nkeynes@231 | 65 | expect_exc 0x000001A0
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| nkeynes@231 | 66 | test_slot_6_pc:
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| nkeynes@231 | 67 | bsr test_slot_fail
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| nkeynes@231 | 68 | bsrf r3
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| nkeynes@231 | 69 | assert_exc_caught test_slot_str_k test_slot_6_pc
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| nkeynes@231 | 70 |
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| nkeynes@231 | 71 | test_slot_7: ! BF
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| nkeynes@231 | 72 | add #1, r12
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| nkeynes@231 | 73 | expect_exc 0x000001A0
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| nkeynes@231 | 74 | test_slot_7_pc:
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| nkeynes@231 | 75 | bsr test_slot_fail
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| nkeynes@231 | 76 | bf test_slot_7_fail
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| nkeynes@231 | 77 | test_slot_7_fail:
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| nkeynes@231 | 78 | assert_exc_caught test_slot_str_k test_slot_7_pc
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| nkeynes@231 | 79 |
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| nkeynes@231 | 80 | test_slot_8: ! BT
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| nkeynes@231 | 81 | add #1, r12
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| nkeynes@231 | 82 | expect_exc 0x000001A0
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| nkeynes@231 | 83 | test_slot_8_pc:
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| nkeynes@231 | 84 | bsr test_slot_fail
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| nkeynes@231 | 85 | bt test_slot_8_fail
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| nkeynes@231 | 86 | test_slot_8_fail:
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| nkeynes@231 | 87 | assert_exc_caught test_slot_str_k test_slot_8_pc
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| nkeynes@231 | 88 |
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| nkeynes@231 | 89 | test_slot_9: ! BF/S
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| nkeynes@231 | 90 | add #1, r12
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| nkeynes@231 | 91 | expect_exc 0x000001A0
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| nkeynes@231 | 92 | test_slot_9_pc:
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| nkeynes@231 | 93 | bsr test_slot_fail
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| nkeynes@231 | 94 | bf/s test_slot_9_fail
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| nkeynes@231 | 95 | test_slot_9_fail:
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| nkeynes@231 | 96 | assert_exc_caught test_slot_str_k test_slot_9_pc
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| nkeynes@231 | 97 |
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| nkeynes@231 | 98 | test_slot_10: ! BT/S
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| nkeynes@231 | 99 | add #1, r12
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| nkeynes@231 | 100 | expect_exc 0x000001A0
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| nkeynes@231 | 101 | test_slot_10_pc:
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| nkeynes@231 | 102 | bsr test_slot_fail
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| nkeynes@231 | 103 | bt/s test_slot_10_fail
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| nkeynes@231 | 104 | test_slot_10_fail:
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| nkeynes@231 | 105 | assert_exc_caught test_slot_str_k test_slot_10_pc
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| nkeynes@231 | 106 |
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| nkeynes@231 | 107 | test_slot_11: ! TRAPA
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| nkeynes@231 | 108 | add #1, r12
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| nkeynes@231 | 109 | expect_exc 0x000001A0
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| nkeynes@231 | 110 | test_slot_11_pc:
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| nkeynes@231 | 111 | bsr test_slot_fail
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| nkeynes@231 | 112 | trapa #12
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| nkeynes@231 | 113 | assert_exc_caught test_slot_str_k test_slot_11_pc
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| nkeynes@231 | 114 |
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| nkeynes@231 | 115 | test_slot_12: ! LDC r0, sr
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| nkeynes@231 | 116 | add #1, r12
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| nkeynes@231 | 117 | expect_exc 0x000001A0
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| nkeynes@231 | 118 | stc sr, r0
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| nkeynes@231 | 119 | test_slot_12_pc:
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| nkeynes@231 | 120 | bsr test_slot_fail
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| nkeynes@231 | 121 | ldc r0, sr
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| nkeynes@231 | 122 | assert_exc_caught test_slot_str_k test_slot_12_pc
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| nkeynes@231 | 123 |
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| nkeynes@231 | 124 | test_slot_13: ! LDC @r0, sr
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| nkeynes@231 | 125 | add #1, r12
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| nkeynes@231 | 126 | expect_exc 0x000001A0
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| nkeynes@231 | 127 | stc sr, r1
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| nkeynes@231 | 128 | mova test_slot_13_temp, r0
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| nkeynes@231 | 129 | mov.l r1, @r0
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| nkeynes@231 | 130 | test_slot_13_pc:
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| nkeynes@231 | 131 | bsr test_slot_fail
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| nkeynes@231 | 132 | ldc.l @r0+, sr
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| nkeynes@231 | 133 | assert_exc_caught test_slot_str_k test_slot_13_pc
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| nkeynes@231 | 134 | bra test_slot_14
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| nkeynes@231 | 135 | nop
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| nkeynes@231 | 136 | test_slot_13_temp:
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| nkeynes@231 | 137 | .long 0
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| nkeynes@231 | 138 |
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| nkeynes@231 | 139 | test_slot_14: ! MOVA
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| nkeynes@231 | 140 | add #1, r12
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| nkeynes@231 | 141 | expect_exc 0x000001A0
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| nkeynes@231 | 142 | test_slot_14_pc:
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| nkeynes@231 | 143 | bsr test_slot_fail
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| nkeynes@231 | 144 | mova test_slot_15, r0
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| nkeynes@231 | 145 | assert_exc_caught test_slot_str_k test_slot_14_pc
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| nkeynes@231 | 146 |
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| nkeynes@231 | 147 | test_slot_15: ! MOV.W pcrel, Rn
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| nkeynes@231 | 148 | add #1, r12
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| nkeynes@231 | 149 | expect_exc 0x000001A0
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| nkeynes@231 | 150 | test_slot_15_pc:
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| nkeynes@231 | 151 | bsr test_slot_fail
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| nkeynes@231 | 152 | mov.w test_slot_16, r0
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| nkeynes@231 | 153 | assert_exc_caught test_slot_str_k test_slot_15_pc
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| nkeynes@231 | 154 |
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| nkeynes@231 | 155 | test_slot_16: ! MOV.L pcrel, Rn
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| nkeynes@231 | 156 | add #1, r12
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| nkeynes@231 | 157 | expect_exc 0x000001A0
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| nkeynes@231 | 158 | test_slot_16_pc:
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| nkeynes@231 | 159 | bsr test_slot_fail
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| nkeynes@231 | 160 | mov.l test_slot_str_k, r0
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| nkeynes@231 | 161 | assert_exc_caught test_slot_str_k test_slot_16_pc
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| nkeynes@231 | 162 |
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| nkeynes@231 | 163 | test_slot_17: ! "Undefined" 0xFFFD
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| nkeynes@231 | 164 | add #1, r12
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| nkeynes@231 | 165 | expect_exc 0x000001A0
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| nkeynes@231 | 166 | test_slot_17_pc:
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| nkeynes@231 | 167 | bsr test_slot_fail
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| nkeynes@231 | 168 | .word 0xFFFD
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| nkeynes@231 | 169 | assert_exc_caught test_slot_str_k test_slot_17_pc
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| nkeynes@231 | 170 |
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| nkeynes@231 | 171 | !
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| nkeynes@231 | 172 | ! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
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| nkeynes@231 | 173 | ! in a delay slot (otherwise it's GENERAL_ILLEGAL)
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| nkeynes@231 | 174 | ! TODO: need mode-switch code
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| nkeynes@231 | 175 |
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| nkeynes@231 | 176 | test_slot_end:
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| nkeynes@231 | 177 | end_test test_slot_str_k
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| nkeynes@231 | 178 |
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| nkeynes@231 | 179 | ! Returns after the delay slot, which should hit the "no exception" test
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| nkeynes@231 | 180 | test_slot_fail:
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| nkeynes@231 | 181 | rts
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| nkeynes@231 | 182 | nop
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| nkeynes@231 | 183 |
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| nkeynes@231 | 184 | test_slot_str_k:
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| nkeynes@231 | 185 | .long test_slot_str
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| nkeynes@231 | 186 | test_slot_str:
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| nkeynes@231 | 187 | .string "SLOT-ILLEGAL"
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| nkeynes@231 | 188 |
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| nkeynes@231 | 189 | |
lxdream 0.9.1