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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 381:aade6c9aca4d
prev380:2e8166bf6832
next382:fce3f4da92ab
author nkeynes
date Wed Sep 12 11:41:43 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix default block return value
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.8 2007-09-12 11:41:43 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2b);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2a);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() 
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{
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    PUSH_r32(R_EBP);
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    PUSH_r32(R_EDI);
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    PUSH_r32(R_ESI);
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    XOR_r32_r32(R_ESI, R_ESI);
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   355
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   356
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   357
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   358
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   359
}
nkeynes@359
   360
nkeynes@368
   361
/**
nkeynes@368
   362
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   363
 */
nkeynes@374
   364
void exit_block( )
nkeynes@368
   365
{
nkeynes@374
   366
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   367
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   368
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   369
    MUL_r32( R_ESI );
nkeynes@368
   370
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   371
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@381
   372
    load_imm32( R_EAX, 1 );
nkeynes@374
   373
    POP_r32(R_ESI);
nkeynes@374
   374
    POP_r32(R_EDI);
nkeynes@374
   375
    POP_r32(R_EBP);
nkeynes@368
   376
    RET();
nkeynes@359
   377
}
nkeynes@359
   378
nkeynes@359
   379
/**
nkeynes@359
   380
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   381
 */
nkeynes@359
   382
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   383
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   384
    // Normal termination - save PC, cycle count
nkeynes@374
   385
    exit_block( );
nkeynes@359
   386
nkeynes@368
   387
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   388
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   389
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@380
   390
    JMP_rel8( 33, target1 );
nkeynes@368
   391
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@380
   392
    JMP_rel8( 26, target2 );
nkeynes@368
   393
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@380
   394
    JMP_rel8( 19, target3 );
nkeynes@368
   395
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@380
   396
    JMP_rel8( 12, target4 );
nkeynes@368
   397
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@380
   398
    JMP_rel8( 5, target5 );
nkeynes@368
   399
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   400
    // target
nkeynes@380
   401
    JMP_TARGET(target1);
nkeynes@380
   402
    JMP_TARGET(target2);
nkeynes@380
   403
    JMP_TARGET(target3);
nkeynes@380
   404
    JMP_TARGET(target4);
nkeynes@380
   405
    JMP_TARGET(target5);
nkeynes@368
   406
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   407
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   408
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   409
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   410
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   411
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   412
    MUL_r32( R_ESI );
nkeynes@368
   413
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   414
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   415
nkeynes@368
   416
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   417
    CALL_r32( R_EAX ); // 2
nkeynes@368
   418
    POP_r32(R_EBP);
nkeynes@368
   419
    RET();
nkeynes@368
   420
nkeynes@368
   421
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   422
}
nkeynes@359
   423
nkeynes@359
   424
/**
nkeynes@359
   425
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   426
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   427
 * 
nkeynes@359
   428
 *
nkeynes@359
   429
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   430
 * (eg a branch or 
nkeynes@359
   431
 */
nkeynes@359
   432
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   433
{
nkeynes@361
   434
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   435
    
nkeynes@359
   436
%%
nkeynes@359
   437
/* ALU operations */
nkeynes@359
   438
ADD Rm, Rn {:
nkeynes@359
   439
    load_reg( R_EAX, Rm );
nkeynes@359
   440
    load_reg( R_ECX, Rn );
nkeynes@359
   441
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   442
    store_reg( R_ECX, Rn );
nkeynes@359
   443
:}
nkeynes@359
   444
ADD #imm, Rn {:  
nkeynes@359
   445
    load_reg( R_EAX, Rn );
nkeynes@359
   446
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   447
    store_reg( R_EAX, Rn );
nkeynes@359
   448
:}
nkeynes@359
   449
ADDC Rm, Rn {:
nkeynes@359
   450
    load_reg( R_EAX, Rm );
nkeynes@359
   451
    load_reg( R_ECX, Rn );
nkeynes@359
   452
    LDC_t();
nkeynes@359
   453
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   454
    store_reg( R_ECX, Rn );
nkeynes@359
   455
    SETC_t();
nkeynes@359
   456
:}
nkeynes@359
   457
ADDV Rm, Rn {:
nkeynes@359
   458
    load_reg( R_EAX, Rm );
nkeynes@359
   459
    load_reg( R_ECX, Rn );
nkeynes@359
   460
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   461
    store_reg( R_ECX, Rn );
nkeynes@359
   462
    SETO_t();
nkeynes@359
   463
:}
nkeynes@359
   464
AND Rm, Rn {:
nkeynes@359
   465
    load_reg( R_EAX, Rm );
nkeynes@359
   466
    load_reg( R_ECX, Rn );
nkeynes@359
   467
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   468
    store_reg( R_ECX, Rn );
nkeynes@359
   469
:}
nkeynes@359
   470
AND #imm, R0 {:  
nkeynes@359
   471
    load_reg( R_EAX, 0 );
nkeynes@359
   472
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   473
    store_reg( R_EAX, 0 );
nkeynes@359
   474
:}
nkeynes@359
   475
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   476
    load_reg( R_EAX, 0 );
nkeynes@359
   477
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   478
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   479
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   480
    AND_imm32_r32(imm, R_ECX );
nkeynes@359
   481
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   482
:}
nkeynes@359
   483
CMP/EQ Rm, Rn {:  
nkeynes@359
   484
    load_reg( R_EAX, Rm );
nkeynes@359
   485
    load_reg( R_ECX, Rn );
nkeynes@359
   486
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   487
    SETE_t();
nkeynes@359
   488
:}
nkeynes@359
   489
CMP/EQ #imm, R0 {:  
nkeynes@359
   490
    load_reg( R_EAX, 0 );
nkeynes@359
   491
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   492
    SETE_t();
nkeynes@359
   493
:}
nkeynes@359
   494
CMP/GE Rm, Rn {:  
nkeynes@359
   495
    load_reg( R_EAX, Rm );
nkeynes@359
   496
    load_reg( R_ECX, Rn );
nkeynes@359
   497
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   498
    SETGE_t();
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/GT Rm, Rn {: 
nkeynes@359
   501
    load_reg( R_EAX, Rm );
nkeynes@359
   502
    load_reg( R_ECX, Rn );
nkeynes@359
   503
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   504
    SETG_t();
nkeynes@359
   505
:}
nkeynes@359
   506
CMP/HI Rm, Rn {:  
nkeynes@359
   507
    load_reg( R_EAX, Rm );
nkeynes@359
   508
    load_reg( R_ECX, Rn );
nkeynes@359
   509
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   510
    SETA_t();
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/HS Rm, Rn {: 
nkeynes@359
   513
    load_reg( R_EAX, Rm );
nkeynes@359
   514
    load_reg( R_ECX, Rn );
nkeynes@359
   515
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   516
    SETAE_t();
nkeynes@359
   517
 :}
nkeynes@359
   518
CMP/PL Rn {: 
nkeynes@359
   519
    load_reg( R_EAX, Rn );
nkeynes@359
   520
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   521
    SETG_t();
nkeynes@359
   522
:}
nkeynes@359
   523
CMP/PZ Rn {:  
nkeynes@359
   524
    load_reg( R_EAX, Rn );
nkeynes@359
   525
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   526
    SETGE_t();
nkeynes@359
   527
:}
nkeynes@361
   528
CMP/STR Rm, Rn {:  
nkeynes@368
   529
    load_reg( R_EAX, Rm );
nkeynes@368
   530
    load_reg( R_ECX, Rn );
nkeynes@368
   531
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   532
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   533
    JE_rel8(13, target1);
nkeynes@368
   534
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   535
    JE_rel8(9, target2);
nkeynes@368
   536
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   537
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   538
    JE_rel8(2, target3);
nkeynes@368
   539
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   540
    JMP_TARGET(target1);
nkeynes@380
   541
    JMP_TARGET(target2);
nkeynes@380
   542
    JMP_TARGET(target3);
nkeynes@368
   543
    SETE_t();
nkeynes@361
   544
:}
nkeynes@361
   545
DIV0S Rm, Rn {:
nkeynes@361
   546
    load_reg( R_EAX, Rm );
nkeynes@361
   547
    load_reg( R_ECX, Rm );
nkeynes@361
   548
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   549
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   550
    store_spreg( R_EAX, R_M );
nkeynes@361
   551
    store_spreg( R_ECX, R_Q );
nkeynes@361
   552
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   553
    SETE_t();
nkeynes@361
   554
:}
nkeynes@361
   555
DIV0U {:  
nkeynes@361
   556
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   557
    store_spreg( R_EAX, R_Q );
nkeynes@361
   558
    store_spreg( R_EAX, R_M );
nkeynes@361
   559
    store_spreg( R_EAX, R_T );
nkeynes@361
   560
:}
nkeynes@374
   561
DIV1 Rm, Rn {:  
nkeynes@374
   562
    load_reg( R_ECX, Rn );
nkeynes@374
   563
    LDC_t();
nkeynes@374
   564
    RCL1_r32( R_ECX ); // OP2
nkeynes@374
   565
    SETC_r32( R_EDX ); // Q
nkeynes@374
   566
    load_spreg( R_EAX, R_Q );
nkeynes@374
   567
    CMP_sh4r_r32( R_M, R_EAX );
nkeynes@380
   568
    JE_rel8(8,mqequal);
nkeynes@374
   569
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@380
   570
    JMP_rel8(3, mqnotequal);
nkeynes@380
   571
    JMP_TARGET(mqequal);
nkeynes@374
   572
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@380
   573
    JMP_TARGET(mqnotequal);
nkeynes@374
   574
    // TODO
nkeynes@374
   575
:}
nkeynes@361
   576
DMULS.L Rm, Rn {:  
nkeynes@361
   577
    load_reg( R_EAX, Rm );
nkeynes@361
   578
    load_reg( R_ECX, Rn );
nkeynes@361
   579
    IMUL_r32(R_ECX);
nkeynes@361
   580
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   581
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   582
:}
nkeynes@361
   583
DMULU.L Rm, Rn {:  
nkeynes@361
   584
    load_reg( R_EAX, Rm );
nkeynes@361
   585
    load_reg( R_ECX, Rn );
nkeynes@361
   586
    MUL_r32(R_ECX);
nkeynes@361
   587
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   588
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   589
:}
nkeynes@359
   590
DT Rn {:  
nkeynes@359
   591
    load_reg( R_EAX, Rn );
nkeynes@359
   592
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   593
    store_reg( R_EAX, Rn );
nkeynes@359
   594
    SETE_t();
nkeynes@359
   595
:}
nkeynes@359
   596
EXTS.B Rm, Rn {:  
nkeynes@359
   597
    load_reg( R_EAX, Rm );
nkeynes@359
   598
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   599
    store_reg( R_EAX, Rn );
nkeynes@359
   600
:}
nkeynes@361
   601
EXTS.W Rm, Rn {:  
nkeynes@361
   602
    load_reg( R_EAX, Rm );
nkeynes@361
   603
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   604
    store_reg( R_EAX, Rn );
nkeynes@361
   605
:}
nkeynes@361
   606
EXTU.B Rm, Rn {:  
nkeynes@361
   607
    load_reg( R_EAX, Rm );
nkeynes@361
   608
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   609
    store_reg( R_EAX, Rn );
nkeynes@361
   610
:}
nkeynes@361
   611
EXTU.W Rm, Rn {:  
nkeynes@361
   612
    load_reg( R_EAX, Rm );
nkeynes@361
   613
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   614
    store_reg( R_EAX, Rn );
nkeynes@361
   615
:}
nkeynes@359
   616
MAC.L @Rm+, @Rn+ {:  :}
nkeynes@359
   617
MAC.W @Rm+, @Rn+ {:  :}
nkeynes@359
   618
MOVT Rn {:  
nkeynes@359
   619
    load_spreg( R_EAX, R_T );
nkeynes@359
   620
    store_reg( R_EAX, Rn );
nkeynes@359
   621
:}
nkeynes@361
   622
MUL.L Rm, Rn {:  
nkeynes@361
   623
    load_reg( R_EAX, Rm );
nkeynes@361
   624
    load_reg( R_ECX, Rn );
nkeynes@361
   625
    MUL_r32( R_ECX );
nkeynes@361
   626
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   627
:}
nkeynes@374
   628
MULS.W Rm, Rn {:
nkeynes@374
   629
    load_reg16s( R_EAX, Rm );
nkeynes@374
   630
    load_reg16s( R_ECX, Rn );
nkeynes@374
   631
    MUL_r32( R_ECX );
nkeynes@374
   632
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   633
:}
nkeynes@374
   634
MULU.W Rm, Rn {:  
nkeynes@374
   635
    load_reg16u( R_EAX, Rm );
nkeynes@374
   636
    load_reg16u( R_ECX, Rn );
nkeynes@374
   637
    MUL_r32( R_ECX );
nkeynes@374
   638
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   639
:}
nkeynes@359
   640
NEG Rm, Rn {:
nkeynes@359
   641
    load_reg( R_EAX, Rm );
nkeynes@359
   642
    NEG_r32( R_EAX );
nkeynes@359
   643
    store_reg( R_EAX, Rn );
nkeynes@359
   644
:}
nkeynes@359
   645
NEGC Rm, Rn {:  
nkeynes@359
   646
    load_reg( R_EAX, Rm );
nkeynes@359
   647
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   648
    LDC_t();
nkeynes@359
   649
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   650
    store_reg( R_ECX, Rn );
nkeynes@359
   651
    SETC_t();
nkeynes@359
   652
:}
nkeynes@359
   653
NOT Rm, Rn {:  
nkeynes@359
   654
    load_reg( R_EAX, Rm );
nkeynes@359
   655
    NOT_r32( R_EAX );
nkeynes@359
   656
    store_reg( R_EAX, Rn );
nkeynes@359
   657
:}
nkeynes@359
   658
OR Rm, Rn {:  
nkeynes@359
   659
    load_reg( R_EAX, Rm );
nkeynes@359
   660
    load_reg( R_ECX, Rn );
nkeynes@359
   661
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   662
    store_reg( R_ECX, Rn );
nkeynes@359
   663
:}
nkeynes@359
   664
OR #imm, R0 {:
nkeynes@359
   665
    load_reg( R_EAX, 0 );
nkeynes@359
   666
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   667
    store_reg( R_EAX, 0 );
nkeynes@359
   668
:}
nkeynes@374
   669
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   670
    load_reg( R_EAX, 0 );
nkeynes@374
   671
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   672
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   673
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
   674
    OR_imm32_r32(imm, R_ECX );
nkeynes@374
   675
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   676
:}
nkeynes@359
   677
ROTCL Rn {:
nkeynes@359
   678
    load_reg( R_EAX, Rn );
nkeynes@359
   679
    LDC_t();
nkeynes@359
   680
    RCL1_r32( R_EAX );
nkeynes@359
   681
    store_reg( R_EAX, Rn );
nkeynes@359
   682
    SETC_t();
nkeynes@359
   683
:}
nkeynes@359
   684
ROTCR Rn {:  
nkeynes@359
   685
    load_reg( R_EAX, Rn );
nkeynes@359
   686
    LDC_t();
nkeynes@359
   687
    RCR1_r32( R_EAX );
nkeynes@359
   688
    store_reg( R_EAX, Rn );
nkeynes@359
   689
    SETC_t();
nkeynes@359
   690
:}
nkeynes@359
   691
ROTL Rn {:  
nkeynes@359
   692
    load_reg( R_EAX, Rn );
nkeynes@359
   693
    ROL1_r32( R_EAX );
nkeynes@359
   694
    store_reg( R_EAX, Rn );
nkeynes@359
   695
    SETC_t();
nkeynes@359
   696
:}
nkeynes@359
   697
ROTR Rn {:  
nkeynes@359
   698
    load_reg( R_EAX, Rn );
nkeynes@359
   699
    ROR1_r32( R_EAX );
nkeynes@359
   700
    store_reg( R_EAX, Rn );
nkeynes@359
   701
    SETC_t();
nkeynes@359
   702
:}
nkeynes@359
   703
SHAD Rm, Rn {:
nkeynes@359
   704
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   705
    load_reg( R_EAX, Rn );
nkeynes@361
   706
    load_reg( R_ECX, Rm );
nkeynes@361
   707
    CMP_imm32_r32( 0, R_ECX );
nkeynes@380
   708
    JAE_rel8(9, doshl);
nkeynes@361
   709
                    
nkeynes@361
   710
    NEG_r32( R_ECX );      // 2
nkeynes@361
   711
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   712
    SAR_r32_CL( R_EAX );       // 2
nkeynes@380
   713
    JMP_rel8(5, end);          // 2
nkeynes@380
   714
    JMP_TARGET(doshl);
nkeynes@361
   715
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   716
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   717
    JMP_TARGET(end);
nkeynes@361
   718
    store_reg( R_EAX, Rn );
nkeynes@359
   719
:}
nkeynes@359
   720
SHLD Rm, Rn {:  
nkeynes@368
   721
    load_reg( R_EAX, Rn );
nkeynes@368
   722
    load_reg( R_ECX, Rm );
nkeynes@368
   723
nkeynes@368
   724
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
   725
    SHL_r32_CL( R_EAX );
nkeynes@368
   726
    NEG_r32( R_ECX );
nkeynes@368
   727
    SHR_r32_CL( R_EDX );
nkeynes@368
   728
    CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
   729
    CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
   730
    store_reg( R_EAX, Rn );
nkeynes@359
   731
:}
nkeynes@359
   732
SHAL Rn {: 
nkeynes@359
   733
    load_reg( R_EAX, Rn );
nkeynes@359
   734
    SHL1_r32( R_EAX );
nkeynes@359
   735
    store_reg( R_EAX, Rn );
nkeynes@359
   736
:}
nkeynes@359
   737
SHAR Rn {:  
nkeynes@359
   738
    load_reg( R_EAX, Rn );
nkeynes@359
   739
    SAR1_r32( R_EAX );
nkeynes@359
   740
    store_reg( R_EAX, Rn );
nkeynes@359
   741
:}
nkeynes@359
   742
SHLL Rn {:  
nkeynes@359
   743
    load_reg( R_EAX, Rn );
nkeynes@359
   744
    SHL1_r32( R_EAX );
nkeynes@359
   745
    store_reg( R_EAX, Rn );
nkeynes@359
   746
:}
nkeynes@359
   747
SHLL2 Rn {:
nkeynes@359
   748
    load_reg( R_EAX, Rn );
nkeynes@359
   749
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   750
    store_reg( R_EAX, Rn );
nkeynes@359
   751
:}
nkeynes@359
   752
SHLL8 Rn {:  
nkeynes@359
   753
    load_reg( R_EAX, Rn );
nkeynes@359
   754
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   755
    store_reg( R_EAX, Rn );
nkeynes@359
   756
:}
nkeynes@359
   757
SHLL16 Rn {:  
nkeynes@359
   758
    load_reg( R_EAX, Rn );
nkeynes@359
   759
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   760
    store_reg( R_EAX, Rn );
nkeynes@359
   761
:}
nkeynes@359
   762
SHLR Rn {:  
nkeynes@359
   763
    load_reg( R_EAX, Rn );
nkeynes@359
   764
    SHR1_r32( R_EAX );
nkeynes@359
   765
    store_reg( R_EAX, Rn );
nkeynes@359
   766
:}
nkeynes@359
   767
SHLR2 Rn {:  
nkeynes@359
   768
    load_reg( R_EAX, Rn );
nkeynes@359
   769
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   770
    store_reg( R_EAX, Rn );
nkeynes@359
   771
:}
nkeynes@359
   772
SHLR8 Rn {:  
nkeynes@359
   773
    load_reg( R_EAX, Rn );
nkeynes@359
   774
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   775
    store_reg( R_EAX, Rn );
nkeynes@359
   776
:}
nkeynes@359
   777
SHLR16 Rn {:  
nkeynes@359
   778
    load_reg( R_EAX, Rn );
nkeynes@359
   779
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   780
    store_reg( R_EAX, Rn );
nkeynes@359
   781
:}
nkeynes@359
   782
SUB Rm, Rn {:  
nkeynes@359
   783
    load_reg( R_EAX, Rm );
nkeynes@359
   784
    load_reg( R_ECX, Rn );
nkeynes@359
   785
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   786
    store_reg( R_ECX, Rn );
nkeynes@359
   787
:}
nkeynes@359
   788
SUBC Rm, Rn {:  
nkeynes@359
   789
    load_reg( R_EAX, Rm );
nkeynes@359
   790
    load_reg( R_ECX, Rn );
nkeynes@359
   791
    LDC_t();
nkeynes@359
   792
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   793
    store_reg( R_ECX, Rn );
nkeynes@359
   794
:}
nkeynes@359
   795
SUBV Rm, Rn {:  
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    load_reg( R_ECX, Rn );
nkeynes@359
   798
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   799
    store_reg( R_ECX, Rn );
nkeynes@359
   800
    SETO_t();
nkeynes@359
   801
:}
nkeynes@359
   802
SWAP.B Rm, Rn {:  
nkeynes@359
   803
    load_reg( R_EAX, Rm );
nkeynes@359
   804
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   805
    store_reg( R_EAX, Rn );
nkeynes@359
   806
:}
nkeynes@359
   807
SWAP.W Rm, Rn {:  
nkeynes@359
   808
    load_reg( R_EAX, Rm );
nkeynes@359
   809
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   810
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   811
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   812
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   813
    store_reg( R_ECX, Rn );
nkeynes@359
   814
:}
nkeynes@361
   815
TAS.B @Rn {:  
nkeynes@361
   816
    load_reg( R_ECX, Rn );
nkeynes@361
   817
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   818
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   819
    SETE_t();
nkeynes@361
   820
    OR_imm8_r8( 0x80, R_AL );
nkeynes@361
   821
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   822
:}
nkeynes@361
   823
TST Rm, Rn {:  
nkeynes@361
   824
    load_reg( R_EAX, Rm );
nkeynes@361
   825
    load_reg( R_ECX, Rn );
nkeynes@361
   826
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   827
    SETE_t();
nkeynes@361
   828
:}
nkeynes@368
   829
TST #imm, R0 {:  
nkeynes@368
   830
    load_reg( R_EAX, 0 );
nkeynes@368
   831
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   832
    SETE_t();
nkeynes@368
   833
:}
nkeynes@368
   834
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   835
    load_reg( R_EAX, 0);
nkeynes@368
   836
    load_reg( R_ECX, R_GBR);
nkeynes@368
   837
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   838
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
   839
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
   840
    SETE_t();
nkeynes@368
   841
:}
nkeynes@359
   842
XOR Rm, Rn {:  
nkeynes@359
   843
    load_reg( R_EAX, Rm );
nkeynes@359
   844
    load_reg( R_ECX, Rn );
nkeynes@359
   845
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   846
    store_reg( R_ECX, Rn );
nkeynes@359
   847
:}
nkeynes@359
   848
XOR #imm, R0 {:  
nkeynes@359
   849
    load_reg( R_EAX, 0 );
nkeynes@359
   850
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   851
    store_reg( R_EAX, 0 );
nkeynes@359
   852
:}
nkeynes@359
   853
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   854
    load_reg( R_EAX, 0 );
nkeynes@359
   855
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   856
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   857
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   858
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   859
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   860
:}
nkeynes@361
   861
XTRCT Rm, Rn {:
nkeynes@361
   862
    load_reg( R_EAX, Rm );
nkeynes@361
   863
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   864
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   865
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   866
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   867
    store_reg( R_ECX, Rn );
nkeynes@359
   868
:}
nkeynes@359
   869
nkeynes@359
   870
/* Data move instructions */
nkeynes@359
   871
MOV Rm, Rn {:  
nkeynes@359
   872
    load_reg( R_EAX, Rm );
nkeynes@359
   873
    store_reg( R_EAX, Rn );
nkeynes@359
   874
:}
nkeynes@359
   875
MOV #imm, Rn {:  
nkeynes@359
   876
    load_imm32( R_EAX, imm );
nkeynes@359
   877
    store_reg( R_EAX, Rn );
nkeynes@359
   878
:}
nkeynes@359
   879
MOV.B Rm, @Rn {:  
nkeynes@359
   880
    load_reg( R_EAX, Rm );
nkeynes@359
   881
    load_reg( R_ECX, Rn );
nkeynes@359
   882
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   883
:}
nkeynes@359
   884
MOV.B Rm, @-Rn {:  
nkeynes@359
   885
    load_reg( R_EAX, Rm );
nkeynes@359
   886
    load_reg( R_ECX, Rn );
nkeynes@359
   887
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   888
    store_reg( R_ECX, Rn );
nkeynes@359
   889
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   890
:}
nkeynes@359
   891
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   892
    load_reg( R_EAX, 0 );
nkeynes@359
   893
    load_reg( R_ECX, Rn );
nkeynes@359
   894
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   895
    load_reg( R_EAX, Rm );
nkeynes@359
   896
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   897
:}
nkeynes@359
   898
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   899
    load_reg( R_EAX, 0 );
nkeynes@359
   900
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   901
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   902
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   903
:}
nkeynes@359
   904
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   905
    load_reg( R_EAX, 0 );
nkeynes@359
   906
    load_reg( R_ECX, Rn );
nkeynes@359
   907
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   908
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   909
:}
nkeynes@359
   910
MOV.B @Rm, Rn {:  
nkeynes@359
   911
    load_reg( R_ECX, Rm );
nkeynes@359
   912
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   913
    store_reg( R_ECX, Rn );
nkeynes@359
   914
:}
nkeynes@359
   915
MOV.B @Rm+, Rn {:  
nkeynes@359
   916
    load_reg( R_ECX, Rm );
nkeynes@359
   917
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
   918
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
   919
    store_reg( R_EAX, Rm );
nkeynes@359
   920
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   921
    store_reg( R_EAX, Rn );
nkeynes@359
   922
:}
nkeynes@359
   923
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
   924
    load_reg( R_EAX, 0 );
nkeynes@359
   925
    load_reg( R_ECX, Rm );
nkeynes@359
   926
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   927
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   928
    store_reg( R_EAX, Rn );
nkeynes@359
   929
:}
nkeynes@359
   930
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
   931
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   932
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   933
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   934
    store_reg( R_EAX, 0 );
nkeynes@359
   935
:}
nkeynes@359
   936
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
   937
    load_reg( R_ECX, Rm );
nkeynes@359
   938
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   939
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   940
    store_reg( R_EAX, 0 );
nkeynes@359
   941
:}
nkeynes@374
   942
MOV.L Rm, @Rn {:
nkeynes@361
   943
    load_reg( R_EAX, Rm );
nkeynes@361
   944
    load_reg( R_ECX, Rn );
nkeynes@374
   945
    check_walign32(R_ECX);
nkeynes@361
   946
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   947
:}
nkeynes@361
   948
MOV.L Rm, @-Rn {:  
nkeynes@361
   949
    load_reg( R_EAX, Rm );
nkeynes@361
   950
    load_reg( R_ECX, Rn );
nkeynes@374
   951
    check_walign32( R_ECX );
nkeynes@361
   952
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   953
    store_reg( R_ECX, Rn );
nkeynes@361
   954
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   955
:}
nkeynes@361
   956
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
   957
    load_reg( R_EAX, 0 );
nkeynes@361
   958
    load_reg( R_ECX, Rn );
nkeynes@361
   959
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   960
    check_walign32( R_ECX );
nkeynes@361
   961
    load_reg( R_EAX, Rm );
nkeynes@361
   962
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   963
:}
nkeynes@361
   964
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
   965
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   966
    load_reg( R_EAX, 0 );
nkeynes@361
   967
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   968
    check_walign32( R_ECX );
nkeynes@361
   969
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   970
:}
nkeynes@361
   971
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
   972
    load_reg( R_ECX, Rn );
nkeynes@361
   973
    load_reg( R_EAX, Rm );
nkeynes@361
   974
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   975
    check_walign32( R_ECX );
nkeynes@361
   976
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   977
:}
nkeynes@361
   978
MOV.L @Rm, Rn {:  
nkeynes@361
   979
    load_reg( R_ECX, Rm );
nkeynes@374
   980
    check_ralign32( R_ECX );
nkeynes@361
   981
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   982
    store_reg( R_EAX, Rn );
nkeynes@361
   983
:}
nkeynes@361
   984
MOV.L @Rm+, Rn {:  
nkeynes@361
   985
    load_reg( R_EAX, Rm );
nkeynes@374
   986
    check_ralign32( R_ECX );
nkeynes@361
   987
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   988
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
   989
    store_reg( R_EAX, Rm );
nkeynes@361
   990
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   991
    store_reg( R_EAX, Rn );
nkeynes@361
   992
:}
nkeynes@361
   993
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
   994
    load_reg( R_EAX, 0 );
nkeynes@361
   995
    load_reg( R_ECX, Rm );
nkeynes@361
   996
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   997
    check_ralign32( R_ECX );
nkeynes@361
   998
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   999
    store_reg( R_EAX, Rn );
nkeynes@361
  1000
:}
nkeynes@361
  1001
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1002
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1003
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1004
    check_ralign32( R_ECX );
nkeynes@361
  1005
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1006
    store_reg( R_EAX, 0 );
nkeynes@361
  1007
:}
nkeynes@361
  1008
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1009
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1010
	SLOTILLEGAL();
nkeynes@374
  1011
    } else {
nkeynes@374
  1012
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1013
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1014
	store_reg( R_EAX, 0 );
nkeynes@374
  1015
    }
nkeynes@361
  1016
:}
nkeynes@361
  1017
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1018
    load_reg( R_ECX, Rm );
nkeynes@361
  1019
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1020
    check_ralign32( R_ECX );
nkeynes@361
  1021
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1022
    store_reg( R_EAX, Rn );
nkeynes@361
  1023
:}
nkeynes@361
  1024
MOV.W Rm, @Rn {:  
nkeynes@361
  1025
    load_reg( R_ECX, Rn );
nkeynes@374
  1026
    check_walign16( R_ECX );
nkeynes@361
  1027
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1028
    store_reg( R_EAX, Rn );
nkeynes@361
  1029
:}
nkeynes@361
  1030
MOV.W Rm, @-Rn {:  
nkeynes@361
  1031
    load_reg( R_ECX, Rn );
nkeynes@374
  1032
    check_walign16( R_ECX );
nkeynes@361
  1033
    load_reg( R_EAX, Rm );
nkeynes@361
  1034
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
  1035
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1036
:}
nkeynes@361
  1037
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1038
    load_reg( R_EAX, 0 );
nkeynes@361
  1039
    load_reg( R_ECX, Rn );
nkeynes@361
  1040
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1041
    check_walign16( R_ECX );
nkeynes@361
  1042
    load_reg( R_EAX, Rm );
nkeynes@361
  1043
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1044
:}
nkeynes@361
  1045
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1046
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1047
    load_reg( R_EAX, 0 );
nkeynes@361
  1048
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1049
    check_walign16( R_ECX );
nkeynes@361
  1050
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1051
:}
nkeynes@361
  1052
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1053
    load_reg( R_ECX, Rn );
nkeynes@361
  1054
    load_reg( R_EAX, 0 );
nkeynes@361
  1055
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1056
    check_walign16( R_ECX );
nkeynes@361
  1057
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1058
:}
nkeynes@361
  1059
MOV.W @Rm, Rn {:  
nkeynes@361
  1060
    load_reg( R_ECX, Rm );
nkeynes@374
  1061
    check_ralign16( R_ECX );
nkeynes@361
  1062
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1063
    store_reg( R_EAX, Rn );
nkeynes@361
  1064
:}
nkeynes@361
  1065
MOV.W @Rm+, Rn {:  
nkeynes@361
  1066
    load_reg( R_EAX, Rm );
nkeynes@374
  1067
    check_ralign16( R_EAX );
nkeynes@361
  1068
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1069
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1070
    store_reg( R_EAX, Rm );
nkeynes@361
  1071
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1072
    store_reg( R_EAX, Rn );
nkeynes@361
  1073
:}
nkeynes@361
  1074
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1075
    load_reg( R_EAX, 0 );
nkeynes@361
  1076
    load_reg( R_ECX, Rm );
nkeynes@361
  1077
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1078
    check_ralign16( R_ECX );
nkeynes@361
  1079
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1080
    store_reg( R_EAX, Rn );
nkeynes@361
  1081
:}
nkeynes@361
  1082
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1083
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1084
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1085
    check_ralign16( R_ECX );
nkeynes@361
  1086
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1087
    store_reg( R_EAX, 0 );
nkeynes@361
  1088
:}
nkeynes@361
  1089
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1090
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1091
	SLOTILLEGAL();
nkeynes@374
  1092
    } else {
nkeynes@374
  1093
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1094
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1095
	store_reg( R_EAX, Rn );
nkeynes@374
  1096
    }
nkeynes@361
  1097
:}
nkeynes@361
  1098
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1099
    load_reg( R_ECX, Rm );
nkeynes@361
  1100
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1101
    check_ralign16( R_ECX );
nkeynes@361
  1102
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1103
    store_reg( R_EAX, 0 );
nkeynes@361
  1104
:}
nkeynes@361
  1105
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1106
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1107
	SLOTILLEGAL();
nkeynes@374
  1108
    } else {
nkeynes@374
  1109
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1110
	store_reg( R_ECX, 0 );
nkeynes@374
  1111
    }
nkeynes@361
  1112
:}
nkeynes@361
  1113
MOVCA.L R0, @Rn {:  
nkeynes@361
  1114
    load_reg( R_EAX, 0 );
nkeynes@361
  1115
    load_reg( R_ECX, Rn );
nkeynes@374
  1116
    check_walign32( R_ECX );
nkeynes@361
  1117
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1118
:}
nkeynes@359
  1119
nkeynes@359
  1120
/* Control transfer instructions */
nkeynes@374
  1121
BF disp {:
nkeynes@374
  1122
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1123
	SLOTILLEGAL();
nkeynes@374
  1124
    } else {
nkeynes@374
  1125
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1126
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1127
	JNE_rel8( 5, nottaken );
nkeynes@374
  1128
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1129
	JMP_TARGET(nottaken);
nkeynes@374
  1130
	INC_r32(R_ESI);
nkeynes@374
  1131
	return 1;
nkeynes@374
  1132
    }
nkeynes@374
  1133
:}
nkeynes@374
  1134
BF/S disp {:
nkeynes@374
  1135
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1136
	SLOTILLEGAL();
nkeynes@374
  1137
    } else {
nkeynes@374
  1138
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1139
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1140
	JNE_rel8( 5, nottaken );
nkeynes@374
  1141
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1142
	JMP_TARGET(nottaken);
nkeynes@374
  1143
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1144
	INC_r32(R_ESI);
nkeynes@374
  1145
	return 0;
nkeynes@374
  1146
    }
nkeynes@374
  1147
:}
nkeynes@374
  1148
BRA disp {:  
nkeynes@374
  1149
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1150
	SLOTILLEGAL();
nkeynes@374
  1151
    } else {
nkeynes@374
  1152
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1153
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1154
	INC_r32(R_ESI);
nkeynes@374
  1155
	return 0;
nkeynes@374
  1156
    }
nkeynes@374
  1157
:}
nkeynes@374
  1158
BRAF Rn {:  
nkeynes@374
  1159
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1160
	SLOTILLEGAL();
nkeynes@374
  1161
    } else {
nkeynes@374
  1162
	load_reg( R_EDI, Rn );
nkeynes@374
  1163
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1164
	INC_r32(R_ESI);
nkeynes@374
  1165
	return 0;
nkeynes@374
  1166
    }
nkeynes@374
  1167
:}
nkeynes@374
  1168
BSR disp {:  
nkeynes@374
  1169
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1170
	SLOTILLEGAL();
nkeynes@374
  1171
    } else {
nkeynes@374
  1172
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1173
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1174
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1175
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1176
	INC_r32(R_ESI);
nkeynes@374
  1177
	return 0;
nkeynes@374
  1178
    }
nkeynes@374
  1179
:}
nkeynes@374
  1180
BSRF Rn {:  
nkeynes@374
  1181
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1182
	SLOTILLEGAL();
nkeynes@374
  1183
    } else {
nkeynes@374
  1184
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1185
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1186
	load_reg( R_EDI, Rn );
nkeynes@374
  1187
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1188
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1189
	INC_r32(R_ESI);
nkeynes@374
  1190
	return 0;
nkeynes@374
  1191
    }
nkeynes@374
  1192
:}
nkeynes@374
  1193
BT disp {:
nkeynes@374
  1194
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1195
	SLOTILLEGAL();
nkeynes@374
  1196
    } else {
nkeynes@374
  1197
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1198
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1199
	JE_rel8( 5, nottaken );
nkeynes@374
  1200
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1201
	JMP_TARGET(nottaken);
nkeynes@374
  1202
	INC_r32(R_ESI);
nkeynes@374
  1203
	return 1;
nkeynes@374
  1204
    }
nkeynes@374
  1205
:}
nkeynes@374
  1206
BT/S disp {:
nkeynes@374
  1207
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1208
	SLOTILLEGAL();
nkeynes@374
  1209
    } else {
nkeynes@374
  1210
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1211
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1212
	JE_rel8( 5, nottaken );
nkeynes@374
  1213
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1214
	JMP_TARGET(nottaken);
nkeynes@374
  1215
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1216
	INC_r32(R_ESI);
nkeynes@374
  1217
	return 0;
nkeynes@374
  1218
    }
nkeynes@374
  1219
:}
nkeynes@374
  1220
JMP @Rn {:  
nkeynes@374
  1221
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1222
	SLOTILLEGAL();
nkeynes@374
  1223
    } else {
nkeynes@374
  1224
	load_reg( R_EDI, Rn );
nkeynes@374
  1225
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1226
	INC_r32(R_ESI);
nkeynes@374
  1227
	return 0;
nkeynes@374
  1228
    }
nkeynes@374
  1229
:}
nkeynes@374
  1230
JSR @Rn {:  
nkeynes@374
  1231
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1232
	SLOTILLEGAL();
nkeynes@374
  1233
    } else {
nkeynes@374
  1234
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1235
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1236
	load_reg( R_EDI, Rn );
nkeynes@374
  1237
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1238
	INC_r32(R_ESI);
nkeynes@374
  1239
	return 0;
nkeynes@374
  1240
    }
nkeynes@374
  1241
:}
nkeynes@374
  1242
RTE {:  
nkeynes@374
  1243
    check_priv();
nkeynes@374
  1244
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1245
	SLOTILLEGAL();
nkeynes@374
  1246
    } else {
nkeynes@374
  1247
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1248
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1249
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1250
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1251
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1252
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1253
	INC_r32(R_ESI);
nkeynes@374
  1254
	return 0;
nkeynes@374
  1255
    }
nkeynes@374
  1256
:}
nkeynes@374
  1257
RTS {:  
nkeynes@374
  1258
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1259
	SLOTILLEGAL();
nkeynes@374
  1260
    } else {
nkeynes@374
  1261
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1262
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1263
	INC_r32(R_ESI);
nkeynes@374
  1264
	return 0;
nkeynes@374
  1265
    }
nkeynes@374
  1266
:}
nkeynes@374
  1267
TRAPA #imm {:  
nkeynes@374
  1268
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1269
	SLOTILLEGAL();
nkeynes@374
  1270
    } else {
nkeynes@374
  1271
	// TODO: Write TRA 
nkeynes@374
  1272
	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  1273
    }
nkeynes@374
  1274
:}
nkeynes@374
  1275
UNDEF {:  
nkeynes@374
  1276
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1277
	RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
nkeynes@374
  1278
    } else {
nkeynes@374
  1279
	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@374
  1280
    }
nkeynes@368
  1281
    return 1;
nkeynes@368
  1282
:}
nkeynes@374
  1283
nkeynes@374
  1284
CLRMAC {:  
nkeynes@374
  1285
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1286
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1287
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1288
:}
nkeynes@374
  1289
CLRS {:
nkeynes@374
  1290
    CLC();
nkeynes@374
  1291
    SETC_sh4r(R_S);
nkeynes@368
  1292
:}
nkeynes@374
  1293
CLRT {:  
nkeynes@374
  1294
    CLC();
nkeynes@374
  1295
    SETC_t();
nkeynes@359
  1296
:}
nkeynes@374
  1297
SETS {:  
nkeynes@374
  1298
    STC();
nkeynes@374
  1299
    SETC_sh4r(R_S);
nkeynes@359
  1300
:}
nkeynes@374
  1301
SETT {:  
nkeynes@374
  1302
    STC();
nkeynes@374
  1303
    SETC_t();
nkeynes@374
  1304
:}
nkeynes@359
  1305
nkeynes@375
  1306
/* Floating point moves */
nkeynes@375
  1307
FMOV FRm, FRn {:  
nkeynes@375
  1308
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1309
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1310
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1311
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1312
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1313
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1314
     */
nkeynes@377
  1315
    check_fpuen();
nkeynes@375
  1316
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1317
    load_fr_bank( R_EDX );
nkeynes@375
  1318
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1319
    JNE_rel8(8, doublesize);
nkeynes@375
  1320
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1321
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1322
    if( FRm&1 ) {
nkeynes@380
  1323
	JMP_rel8(22, end);
nkeynes@380
  1324
	JMP_TARGET(doublesize);
nkeynes@375
  1325
	load_xf_bank( R_ECX ); 
nkeynes@375
  1326
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1327
	if( FRn&1 ) {
nkeynes@375
  1328
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1329
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1330
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1331
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1332
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  1333
	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  1334
	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  1335
	}
nkeynes@380
  1336
	JMP_TARGET(end);
nkeynes@375
  1337
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1338
	if( FRn&1 ) {
nkeynes@380
  1339
	    JMP_rel8(22, end);
nkeynes@375
  1340
	    load_xf_bank( R_ECX );
nkeynes@375
  1341
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1342
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1343
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1344
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1345
	    JMP_TARGET(end);
nkeynes@375
  1346
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1347
	    JMP_rel8(12, end);
nkeynes@375
  1348
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1349
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1350
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1351
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1352
	    JMP_TARGET(end);
nkeynes@375
  1353
	}
nkeynes@375
  1354
    }
nkeynes@375
  1355
:}
nkeynes@375
  1356
FMOV FRm, @Rn {:  
nkeynes@377
  1357
    check_fpuen();
nkeynes@375
  1358
    load_reg( R_EDX, Rn );
nkeynes@375
  1359
    check_walign32( R_EDX );
nkeynes@375
  1360
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1361
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1362
    JNE_rel8(20, doublesize);
nkeynes@377
  1363
    load_fr_bank( R_ECX );
nkeynes@375
  1364
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1365
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1366
    if( FRm&1 ) {
nkeynes@380
  1367
	JMP_rel8( 46, end );
nkeynes@380
  1368
	JMP_TARGET(doublesize);
nkeynes@375
  1369
	load_xf_bank( R_ECX );
nkeynes@380
  1370
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1371
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1372
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1373
	JMP_TARGET(end);
nkeynes@375
  1374
    } else {
nkeynes@380
  1375
	JMP_rel8( 39, end );
nkeynes@380
  1376
	JMP_TARGET(doublesize);
nkeynes@377
  1377
	load_fr_bank( R_ECX );
nkeynes@380
  1378
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1379
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1380
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1381
	JMP_TARGET(end);
nkeynes@375
  1382
    }
nkeynes@375
  1383
:}
nkeynes@375
  1384
FMOV @Rm, FRn {:  
nkeynes@377
  1385
    check_fpuen();
nkeynes@375
  1386
    load_reg( R_EDX, Rm );
nkeynes@375
  1387
    check_ralign32( R_EDX );
nkeynes@375
  1388
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1389
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1390
    JNE_rel8(19, doublesize);
nkeynes@375
  1391
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1392
    load_fr_bank( R_ECX );
nkeynes@375
  1393
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1394
    if( FRn&1 ) {
nkeynes@380
  1395
	JMP_rel8(46, end);
nkeynes@380
  1396
	JMP_TARGET(doublesize);
nkeynes@375
  1397
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1398
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1399
	load_xf_bank( R_ECX );
nkeynes@380
  1400
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1401
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1402
	JMP_TARGET(end);
nkeynes@375
  1403
    } else {
nkeynes@380
  1404
	JMP_rel8(36, end);
nkeynes@380
  1405
	JMP_TARGET(doublesize);
nkeynes@375
  1406
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1407
	load_fr_bank( R_ECX );
nkeynes@380
  1408
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1409
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1410
	JMP_TARGET(end);
nkeynes@375
  1411
    }
nkeynes@375
  1412
:}
nkeynes@377
  1413
FMOV FRm, @-Rn {:  
nkeynes@377
  1414
    check_fpuen();
nkeynes@377
  1415
    load_reg( R_EDX, Rn );
nkeynes@377
  1416
    check_walign32( R_EDX );
nkeynes@377
  1417
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1418
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1419
    JNE_rel8(20, doublesize);
nkeynes@377
  1420
    load_fr_bank( R_ECX );
nkeynes@377
  1421
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1422
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1423
    store_reg( R_EDX, Rn );
nkeynes@377
  1424
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1425
    if( FRm&1 ) {
nkeynes@380
  1426
	JMP_rel8( 46, end );
nkeynes@380
  1427
	JMP_TARGET(doublesize);
nkeynes@377
  1428
	load_xf_bank( R_ECX );
nkeynes@380
  1429
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1430
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1431
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1432
	store_reg( R_EDX, Rn );
nkeynes@380
  1433
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1434
	JMP_TARGET(end);
nkeynes@377
  1435
    } else {
nkeynes@380
  1436
	JMP_rel8( 39, end );
nkeynes@380
  1437
	JMP_TARGET(doublesize);
nkeynes@377
  1438
	load_fr_bank( R_ECX );
nkeynes@380
  1439
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1440
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1441
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1442
	store_reg( R_EDX, Rn );
nkeynes@380
  1443
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1444
	JMP_TARGET(end);
nkeynes@377
  1445
    }
nkeynes@377
  1446
:}
nkeynes@377
  1447
FMOV @Rm+, FRn {:  
nkeynes@377
  1448
    check_fpuen();
nkeynes@377
  1449
    load_reg( R_EDX, Rm );
nkeynes@377
  1450
    check_ralign32( R_EDX );
nkeynes@377
  1451
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1452
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1453
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1454
    JNE_rel8(25, doublesize);
nkeynes@377
  1455
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1456
    store_reg( R_EAX, Rm );
nkeynes@377
  1457
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1458
    load_fr_bank( R_ECX );
nkeynes@377
  1459
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1460
    if( FRn&1 ) {
nkeynes@380
  1461
	JMP_rel8(52, end);
nkeynes@380
  1462
	JMP_TARGET(doublesize);
nkeynes@377
  1463
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1464
	store_reg(R_EAX, Rm);
nkeynes@377
  1465
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1466
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1467
	load_xf_bank( R_ECX );
nkeynes@380
  1468
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1469
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1470
	JMP_TARGET(end);
nkeynes@377
  1471
    } else {
nkeynes@380
  1472
	JMP_rel8(42, end);
nkeynes@377
  1473
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1474
	store_reg(R_EAX, Rm);
nkeynes@377
  1475
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1476
	load_fr_bank( R_ECX );
nkeynes@380
  1477
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1478
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1479
	JMP_TARGET(end);
nkeynes@377
  1480
    }
nkeynes@377
  1481
:}
nkeynes@377
  1482
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1483
    check_fpuen();
nkeynes@377
  1484
    load_reg( R_EDX, Rn );
nkeynes@377
  1485
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1486
    check_walign32( R_EDX );
nkeynes@377
  1487
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1488
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1489
    JNE_rel8(20, doublesize);
nkeynes@377
  1490
    load_fr_bank( R_ECX );
nkeynes@377
  1491
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1492
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1493
    if( FRm&1 ) {
nkeynes@380
  1494
	JMP_rel8( 46, end );
nkeynes@380
  1495
	JMP_TARGET(doublesize);
nkeynes@377
  1496
	load_xf_bank( R_ECX );
nkeynes@380
  1497
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1498
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1499
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1500
	JMP_TARGET(end);
nkeynes@377
  1501
    } else {
nkeynes@380
  1502
	JMP_rel8( 39, end );
nkeynes@380
  1503
	JMP_TARGET(doublesize);
nkeynes@377
  1504
	load_fr_bank( R_ECX );
nkeynes@380
  1505
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1506
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1507
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1508
	JMP_TARGET(end);
nkeynes@377
  1509
    }
nkeynes@377
  1510
:}
nkeynes@377
  1511
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1512
    check_fpuen();
nkeynes@377
  1513
    load_reg( R_EDX, Rm );
nkeynes@377
  1514
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1515
    check_ralign32( R_EDX );
nkeynes@377
  1516
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1517
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1518
    JNE_rel8(19, doublesize);
nkeynes@377
  1519
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1520
    load_fr_bank( R_ECX );
nkeynes@377
  1521
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1522
    if( FRn&1 ) {
nkeynes@380
  1523
	JMP_rel8(46, end);
nkeynes@380
  1524
	JMP_TARGET(doublesize);
nkeynes@377
  1525
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1526
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1527
	load_xf_bank( R_ECX );
nkeynes@380
  1528
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1529
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1530
	JMP_TARGET(end);
nkeynes@377
  1531
    } else {
nkeynes@380
  1532
	JMP_rel8(36, end);
nkeynes@380
  1533
	JMP_TARGET(doublesize);
nkeynes@377
  1534
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1535
	load_fr_bank( R_ECX );
nkeynes@380
  1536
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1537
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1538
	JMP_TARGET(end);
nkeynes@377
  1539
    }
nkeynes@377
  1540
:}
nkeynes@377
  1541
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1542
    check_fpuen();
nkeynes@377
  1543
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1544
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1545
    JNE_rel8(8, end);
nkeynes@377
  1546
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1547
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1548
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1549
    JMP_TARGET(end);
nkeynes@377
  1550
:}
nkeynes@377
  1551
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1552
    check_fpuen();
nkeynes@377
  1553
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1554
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1555
    JNE_rel8(11, end);
nkeynes@377
  1556
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1557
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1558
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1559
    JMP_TARGET(end);
nkeynes@377
  1560
:}
nkeynes@377
  1561
nkeynes@377
  1562
FLOAT FPUL, FRn {:  
nkeynes@377
  1563
    check_fpuen();
nkeynes@377
  1564
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1565
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1566
    FILD_sh4r(R_FPUL);
nkeynes@377
  1567
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1568
    JNE_rel8(5, doubleprec);
nkeynes@377
  1569
    pop_fr( R_EDX, FRn );
nkeynes@380
  1570
    JMP_rel8(3, end);
nkeynes@380
  1571
    JMP_TARGET(doubleprec);
nkeynes@377
  1572
    pop_dr( R_EDX, FRn );
nkeynes@380
  1573
    JMP_TARGET(end);
nkeynes@377
  1574
:}
nkeynes@377
  1575
FTRC FRm, FPUL {:  
nkeynes@377
  1576
    check_fpuen();
nkeynes@377
  1577
    // TODO
nkeynes@377
  1578
:}
nkeynes@377
  1579
FLDS FRm, FPUL {:  
nkeynes@377
  1580
    check_fpuen();
nkeynes@377
  1581
    load_fr_bank( R_ECX );
nkeynes@377
  1582
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1583
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1584
:}
nkeynes@377
  1585
FSTS FPUL, FRn {:  
nkeynes@377
  1586
    check_fpuen();
nkeynes@377
  1587
    load_fr_bank( R_ECX );
nkeynes@377
  1588
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1589
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1590
:}
nkeynes@377
  1591
FCNVDS FRm, FPUL {:  
nkeynes@377
  1592
    check_fpuen();
nkeynes@377
  1593
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1594
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1595
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1596
    load_fr_bank( R_ECX );
nkeynes@377
  1597
    push_dr( R_ECX, FRm );
nkeynes@377
  1598
    pop_fpul();
nkeynes@380
  1599
    JMP_TARGET(end);
nkeynes@377
  1600
:}
nkeynes@377
  1601
FCNVSD FPUL, FRn {:  
nkeynes@377
  1602
    check_fpuen();
nkeynes@377
  1603
    check_fpuen();
nkeynes@377
  1604
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1605
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1606
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1607
    load_fr_bank( R_ECX );
nkeynes@377
  1608
    push_fpul();
nkeynes@377
  1609
    pop_dr( R_ECX, FRn );
nkeynes@380
  1610
    JMP_TARGET(end);
nkeynes@377
  1611
:}
nkeynes@375
  1612
nkeynes@359
  1613
/* Floating point instructions */
nkeynes@374
  1614
FABS FRn {:  
nkeynes@377
  1615
    check_fpuen();
nkeynes@374
  1616
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1617
    load_fr_bank( R_EDX );
nkeynes@374
  1618
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1619
    JNE_rel8(10, doubleprec);
nkeynes@374
  1620
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1621
    FABS_st0(); // 2
nkeynes@374
  1622
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1623
    JMP_rel8(8,end); // 2
nkeynes@380
  1624
    JMP_TARGET(doubleprec);
nkeynes@374
  1625
    push_dr(R_EDX, FRn);
nkeynes@374
  1626
    FABS_st0();
nkeynes@374
  1627
    pop_dr(R_EDX, FRn);
nkeynes@380
  1628
    JMP_TARGET(end);
nkeynes@374
  1629
:}
nkeynes@377
  1630
FADD FRm, FRn {:  
nkeynes@377
  1631
    check_fpuen();
nkeynes@375
  1632
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1633
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1634
    load_fr_bank( R_EDX );
nkeynes@380
  1635
    JNE_rel8(13,doubleprec);
nkeynes@377
  1636
    push_fr(R_EDX, FRm);
nkeynes@377
  1637
    push_fr(R_EDX, FRn);
nkeynes@377
  1638
    FADDP_st(1);
nkeynes@377
  1639
    pop_fr(R_EDX, FRn);
nkeynes@380
  1640
    JMP_rel8(11,end);
nkeynes@380
  1641
    JMP_TARGET(doubleprec);
nkeynes@377
  1642
    push_dr(R_EDX, FRm);
nkeynes@377
  1643
    push_dr(R_EDX, FRn);
nkeynes@377
  1644
    FADDP_st(1);
nkeynes@377
  1645
    pop_dr(R_EDX, FRn);
nkeynes@380
  1646
    JMP_TARGET(end);
nkeynes@375
  1647
:}
nkeynes@377
  1648
FDIV FRm, FRn {:  
nkeynes@377
  1649
    check_fpuen();
nkeynes@375
  1650
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1651
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1652
    load_fr_bank( R_EDX );
nkeynes@380
  1653
    JNE_rel8(13, doubleprec);
nkeynes@377
  1654
    push_fr(R_EDX, FRn);
nkeynes@377
  1655
    push_fr(R_EDX, FRm);
nkeynes@377
  1656
    FDIVP_st(1);
nkeynes@377
  1657
    pop_fr(R_EDX, FRn);
nkeynes@380
  1658
    JMP_rel8(11, end);
nkeynes@380
  1659
    JMP_TARGET(doubleprec);
nkeynes@377
  1660
    push_dr(R_EDX, FRn);
nkeynes@377
  1661
    push_dr(R_EDX, FRm);
nkeynes@377
  1662
    FDIVP_st(1);
nkeynes@377
  1663
    pop_dr(R_EDX, FRn);
nkeynes@380
  1664
    JMP_TARGET(end);
nkeynes@375
  1665
:}
nkeynes@375
  1666
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1667
    check_fpuen();
nkeynes@375
  1668
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1669
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1670
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1671
    JNE_rel8(18, doubleprec);
nkeynes@375
  1672
    push_fr( R_EDX, 0 );
nkeynes@375
  1673
    push_fr( R_EDX, FRm );
nkeynes@375
  1674
    FMULP_st(1);
nkeynes@375
  1675
    push_fr( R_EDX, FRn );
nkeynes@375
  1676
    FADDP_st(1);
nkeynes@375
  1677
    pop_fr( R_EDX, FRn );
nkeynes@380
  1678
    JMP_rel8(16, end);
nkeynes@380
  1679
    JMP_TARGET(doubleprec);
nkeynes@375
  1680
    push_dr( R_EDX, 0 );
nkeynes@375
  1681
    push_dr( R_EDX, FRm );
nkeynes@375
  1682
    FMULP_st(1);
nkeynes@375
  1683
    push_dr( R_EDX, FRn );
nkeynes@375
  1684
    FADDP_st(1);
nkeynes@375
  1685
    pop_dr( R_EDX, FRn );
nkeynes@380
  1686
    JMP_TARGET(end);
nkeynes@375
  1687
:}
nkeynes@375
  1688
nkeynes@377
  1689
FMUL FRm, FRn {:  
nkeynes@377
  1690
    check_fpuen();
nkeynes@377
  1691
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1692
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1693
    load_fr_bank( R_EDX );
nkeynes@380
  1694
    JNE_rel8(13, doubleprec);
nkeynes@377
  1695
    push_fr(R_EDX, FRm);
nkeynes@377
  1696
    push_fr(R_EDX, FRn);
nkeynes@377
  1697
    FMULP_st(1);
nkeynes@377
  1698
    pop_fr(R_EDX, FRn);
nkeynes@380
  1699
    JMP_rel8(11, end);
nkeynes@380
  1700
    JMP_TARGET(doubleprec);
nkeynes@377
  1701
    push_dr(R_EDX, FRm);
nkeynes@377
  1702
    push_dr(R_EDX, FRn);
nkeynes@377
  1703
    FMULP_st(1);
nkeynes@377
  1704
    pop_dr(R_EDX, FRn);
nkeynes@380
  1705
    JMP_TARGET(end);
nkeynes@377
  1706
:}
nkeynes@377
  1707
FNEG FRn {:  
nkeynes@377
  1708
    check_fpuen();
nkeynes@377
  1709
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1710
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1711
    load_fr_bank( R_EDX );
nkeynes@380
  1712
    JNE_rel8(10, doubleprec);
nkeynes@377
  1713
    push_fr(R_EDX, FRn);
nkeynes@377
  1714
    FCHS_st0();
nkeynes@377
  1715
    pop_fr(R_EDX, FRn);
nkeynes@380
  1716
    JMP_rel8(8, end);
nkeynes@380
  1717
    JMP_TARGET(doubleprec);
nkeynes@377
  1718
    push_dr(R_EDX, FRn);
nkeynes@377
  1719
    FCHS_st0();
nkeynes@377
  1720
    pop_dr(R_EDX, FRn);
nkeynes@380
  1721
    JMP_TARGET(end);
nkeynes@377
  1722
:}
nkeynes@377
  1723
FSRRA FRn {:  
nkeynes@377
  1724
    check_fpuen();
nkeynes@377
  1725
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1726
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1727
    load_fr_bank( R_EDX );
nkeynes@380
  1728
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1729
    FLD1_st0();
nkeynes@377
  1730
    push_fr(R_EDX, FRn);
nkeynes@377
  1731
    FSQRT_st0();
nkeynes@377
  1732
    FDIVP_st(1);
nkeynes@377
  1733
    pop_fr(R_EDX, FRn);
nkeynes@380
  1734
    JMP_TARGET(end);
nkeynes@377
  1735
:}
nkeynes@377
  1736
FSQRT FRn {:  
nkeynes@377
  1737
    check_fpuen();
nkeynes@377
  1738
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1739
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1740
    load_fr_bank( R_EDX );
nkeynes@380
  1741
    JNE_rel8(10, doubleprec);
nkeynes@377
  1742
    push_fr(R_EDX, FRn);
nkeynes@377
  1743
    FSQRT_st0();
nkeynes@377
  1744
    pop_fr(R_EDX, FRn);
nkeynes@380
  1745
    JMP_rel8(8, end);
nkeynes@380
  1746
    JMP_TARGET(doubleprec);
nkeynes@377
  1747
    push_dr(R_EDX, FRn);
nkeynes@377
  1748
    FSQRT_st0();
nkeynes@377
  1749
    pop_dr(R_EDX, FRn);
nkeynes@380
  1750
    JMP_TARGET(end);
nkeynes@377
  1751
:}
nkeynes@377
  1752
FSUB FRm, FRn {:  
nkeynes@377
  1753
    check_fpuen();
nkeynes@377
  1754
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1755
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1756
    load_fr_bank( R_EDX );
nkeynes@380
  1757
    JNE_rel8(13, doubleprec);
nkeynes@377
  1758
    push_fr(R_EDX, FRn);
nkeynes@377
  1759
    push_fr(R_EDX, FRm);
nkeynes@377
  1760
    FMULP_st(1);
nkeynes@377
  1761
    pop_fr(R_EDX, FRn);
nkeynes@380
  1762
    JMP_rel8(11, end);
nkeynes@380
  1763
    JMP_TARGET(doubleprec);
nkeynes@377
  1764
    push_dr(R_EDX, FRn);
nkeynes@377
  1765
    push_dr(R_EDX, FRm);
nkeynes@377
  1766
    FMULP_st(1);
nkeynes@377
  1767
    pop_dr(R_EDX, FRn);
nkeynes@380
  1768
    JMP_TARGET(end);
nkeynes@377
  1769
:}
nkeynes@377
  1770
nkeynes@377
  1771
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1772
    check_fpuen();
nkeynes@377
  1773
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1774
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1775
    load_fr_bank( R_EDX );
nkeynes@380
  1776
    JNE_rel8(8, doubleprec);
nkeynes@377
  1777
    push_fr(R_EDX, FRm);
nkeynes@377
  1778
    push_fr(R_EDX, FRn);
nkeynes@380
  1779
    JMP_rel8(6, end);
nkeynes@380
  1780
    JMP_TARGET(doubleprec);
nkeynes@377
  1781
    push_dr(R_EDX, FRm);
nkeynes@377
  1782
    push_dr(R_EDX, FRn);
nkeynes@377
  1783
    FCOMIP_st(1);
nkeynes@377
  1784
    SETE_t();
nkeynes@377
  1785
    FPOP_st();
nkeynes@380
  1786
    JMP_TARGET(end);
nkeynes@377
  1787
:}
nkeynes@377
  1788
FCMP/GT FRm, FRn {:  
nkeynes@377
  1789
    check_fpuen();
nkeynes@377
  1790
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1791
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1792
    load_fr_bank( R_EDX );
nkeynes@380
  1793
    JNE_rel8(8, doubleprec);
nkeynes@377
  1794
    push_fr(R_EDX, FRm);
nkeynes@377
  1795
    push_fr(R_EDX, FRn);
nkeynes@380
  1796
    JMP_rel8(6, end);
nkeynes@380
  1797
    JMP_TARGET(doubleprec);
nkeynes@377
  1798
    push_dr(R_EDX, FRm);
nkeynes@377
  1799
    push_dr(R_EDX, FRn);
nkeynes@380
  1800
    JMP_TARGET(end);
nkeynes@377
  1801
    FCOMIP_st(1);
nkeynes@377
  1802
    SETA_t();
nkeynes@377
  1803
    FPOP_st();
nkeynes@377
  1804
:}
nkeynes@377
  1805
nkeynes@377
  1806
FSCA FPUL, FRn {:  
nkeynes@377
  1807
    check_fpuen();
nkeynes@377
  1808
:}
nkeynes@377
  1809
FIPR FVm, FVn {:  
nkeynes@377
  1810
    check_fpuen();
nkeynes@377
  1811
:}
nkeynes@377
  1812
FTRV XMTRX, FVn {:  
nkeynes@377
  1813
    check_fpuen();
nkeynes@377
  1814
:}
nkeynes@377
  1815
nkeynes@377
  1816
FRCHG {:  
nkeynes@377
  1817
    check_fpuen();
nkeynes@377
  1818
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1819
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  1820
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1821
    
nkeynes@377
  1822
:}
nkeynes@377
  1823
FSCHG {:  
nkeynes@377
  1824
    check_fpuen();
nkeynes@377
  1825
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1826
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1827
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1828
:}
nkeynes@359
  1829
nkeynes@359
  1830
/* Processor control instructions */
nkeynes@368
  1831
LDC Rm, SR {:
nkeynes@368
  1832
    load_reg( R_EAX, Rm );
nkeynes@374
  1833
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1834
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1835
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
  1836
:}
nkeynes@359
  1837
LDC Rm, GBR {: 
nkeynes@359
  1838
    load_reg( R_EAX, Rm );
nkeynes@359
  1839
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1840
:}
nkeynes@359
  1841
LDC Rm, VBR {:  
nkeynes@359
  1842
    load_reg( R_EAX, Rm );
nkeynes@359
  1843
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1844
:}
nkeynes@359
  1845
LDC Rm, SSR {:  
nkeynes@359
  1846
    load_reg( R_EAX, Rm );
nkeynes@359
  1847
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1848
:}
nkeynes@359
  1849
LDC Rm, SGR {:  
nkeynes@359
  1850
    load_reg( R_EAX, Rm );
nkeynes@359
  1851
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1852
:}
nkeynes@359
  1853
LDC Rm, SPC {:  
nkeynes@359
  1854
    load_reg( R_EAX, Rm );
nkeynes@359
  1855
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1856
:}
nkeynes@359
  1857
LDC Rm, DBR {:  
nkeynes@359
  1858
    load_reg( R_EAX, Rm );
nkeynes@359
  1859
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1860
:}
nkeynes@374
  1861
LDC Rm, Rn_BANK {:  
nkeynes@374
  1862
    load_reg( R_EAX, Rm );
nkeynes@374
  1863
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  1864
:}
nkeynes@359
  1865
LDC.L @Rm+, GBR {:  
nkeynes@359
  1866
    load_reg( R_EAX, Rm );
nkeynes@359
  1867
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1868
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1869
    store_reg( R_EAX, Rm );
nkeynes@359
  1870
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1871
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1872
:}
nkeynes@368
  1873
LDC.L @Rm+, SR {:
nkeynes@368
  1874
    load_reg( R_EAX, Rm );
nkeynes@368
  1875
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1876
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1877
    store_reg( R_EAX, Rm );
nkeynes@368
  1878
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1879
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1880
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1881
    sh4_x86.fpuen_checked = FALSE;
nkeynes@359
  1882
:}
nkeynes@359
  1883
LDC.L @Rm+, VBR {:  
nkeynes@359
  1884
    load_reg( R_EAX, Rm );
nkeynes@359
  1885
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1886
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1887
    store_reg( R_EAX, Rm );
nkeynes@359
  1888
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1889
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1890
:}
nkeynes@359
  1891
LDC.L @Rm+, SSR {:
nkeynes@359
  1892
    load_reg( R_EAX, Rm );
nkeynes@359
  1893
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1894
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1895
    store_reg( R_EAX, Rm );
nkeynes@359
  1896
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1897
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1898
:}
nkeynes@359
  1899
LDC.L @Rm+, SGR {:  
nkeynes@359
  1900
    load_reg( R_EAX, Rm );
nkeynes@359
  1901
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1902
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1903
    store_reg( R_EAX, Rm );
nkeynes@359
  1904
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1905
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1906
:}
nkeynes@359
  1907
LDC.L @Rm+, SPC {:  
nkeynes@359
  1908
    load_reg( R_EAX, Rm );
nkeynes@359
  1909
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1910
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1911
    store_reg( R_EAX, Rm );
nkeynes@359
  1912
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1913
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1914
:}
nkeynes@359
  1915
LDC.L @Rm+, DBR {:  
nkeynes@359
  1916
    load_reg( R_EAX, Rm );
nkeynes@359
  1917
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1918
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1919
    store_reg( R_EAX, Rm );
nkeynes@359
  1920
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1921
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1922
:}
nkeynes@359
  1923
LDC.L @Rm+, Rn_BANK {:  
nkeynes@374
  1924
    load_reg( R_EAX, Rm );
nkeynes@374
  1925
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1926
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1927
    store_reg( R_EAX, Rm );
nkeynes@374
  1928
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1929
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1930
:}
nkeynes@359
  1931
LDS Rm, FPSCR {:  
nkeynes@359
  1932
    load_reg( R_EAX, Rm );
nkeynes@359
  1933
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1934
:}
nkeynes@359
  1935
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  1936
    load_reg( R_EAX, Rm );
nkeynes@359
  1937
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1938
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1939
    store_reg( R_EAX, Rm );
nkeynes@359
  1940
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1941
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1942
:}
nkeynes@359
  1943
LDS Rm, FPUL {:  
nkeynes@359
  1944
    load_reg( R_EAX, Rm );
nkeynes@359
  1945
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1946
:}
nkeynes@359
  1947
LDS.L @Rm+, FPUL {:  
nkeynes@359
  1948
    load_reg( R_EAX, Rm );
nkeynes@359
  1949
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1950
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1951
    store_reg( R_EAX, Rm );
nkeynes@359
  1952
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1953
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1954
:}
nkeynes@359
  1955
LDS Rm, MACH {: 
nkeynes@359
  1956
    load_reg( R_EAX, Rm );
nkeynes@359
  1957
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1958
:}
nkeynes@359
  1959
LDS.L @Rm+, MACH {:  
nkeynes@359
  1960
    load_reg( R_EAX, Rm );
nkeynes@359
  1961
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1962
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1963
    store_reg( R_EAX, Rm );
nkeynes@359
  1964
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1965
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1966
:}
nkeynes@359
  1967
LDS Rm, MACL {:  
nkeynes@359
  1968
    load_reg( R_EAX, Rm );
nkeynes@359
  1969
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1970
:}
nkeynes@359
  1971
LDS.L @Rm+, MACL {:  
nkeynes@359
  1972
    load_reg( R_EAX, Rm );
nkeynes@359
  1973
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1974
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1975
    store_reg( R_EAX, Rm );
nkeynes@359
  1976
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1977
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1978
:}
nkeynes@359
  1979
LDS Rm, PR {:  
nkeynes@359
  1980
    load_reg( R_EAX, Rm );
nkeynes@359
  1981
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1982
:}
nkeynes@359
  1983
LDS.L @Rm+, PR {:  
nkeynes@359
  1984
    load_reg( R_EAX, Rm );
nkeynes@359
  1985
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1986
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1987
    store_reg( R_EAX, Rm );
nkeynes@359
  1988
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1989
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1990
:}
nkeynes@359
  1991
LDTLB {:  :}
nkeynes@359
  1992
OCBI @Rn {:  :}
nkeynes@359
  1993
OCBP @Rn {:  :}
nkeynes@359
  1994
OCBWB @Rn {:  :}
nkeynes@374
  1995
PREF @Rn {:
nkeynes@374
  1996
    load_reg( R_EAX, Rn );
nkeynes@374
  1997
    PUSH_r32( R_EAX );
nkeynes@374
  1998
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  1999
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2000
    JNE_rel8(7, end);
nkeynes@374
  2001
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2002
    JMP_TARGET(end);
nkeynes@377
  2003
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2004
:}
nkeynes@374
  2005
 SLEEP {: /* TODO */ :}
nkeynes@368
  2006
 STC SR, Rn {:
nkeynes@374
  2007
     call_func0(sh4_read_sr);
nkeynes@368
  2008
     store_reg( R_EAX, Rn );
nkeynes@359
  2009
:}
nkeynes@359
  2010
STC GBR, Rn {:  
nkeynes@359
  2011
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2012
    store_reg( R_EAX, Rn );
nkeynes@359
  2013
:}
nkeynes@359
  2014
STC VBR, Rn {:  
nkeynes@359
  2015
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2016
    store_reg( R_EAX, Rn );
nkeynes@359
  2017
:}
nkeynes@359
  2018
STC SSR, Rn {:  
nkeynes@359
  2019
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2020
    store_reg( R_EAX, Rn );
nkeynes@359
  2021
:}
nkeynes@359
  2022
STC SPC, Rn {:  
nkeynes@359
  2023
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2024
    store_reg( R_EAX, Rn );
nkeynes@359
  2025
:}
nkeynes@359
  2026
STC SGR, Rn {:  
nkeynes@359
  2027
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2028
    store_reg( R_EAX, Rn );
nkeynes@359
  2029
:}
nkeynes@359
  2030
STC DBR, Rn {:  
nkeynes@359
  2031
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2032
    store_reg( R_EAX, Rn );
nkeynes@359
  2033
:}
nkeynes@374
  2034
STC Rm_BANK, Rn {:
nkeynes@374
  2035
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2036
    store_reg( R_EAX, Rn );
nkeynes@359
  2037
:}
nkeynes@374
  2038
STC.L SR, @-Rn {:
nkeynes@368
  2039
    load_reg( R_ECX, Rn );
nkeynes@368
  2040
    ADD_imm8s_r32( -4, Rn );
nkeynes@368
  2041
    store_reg( R_ECX, Rn );
nkeynes@374
  2042
    call_func0( sh4_read_sr );
nkeynes@368
  2043
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2044
:}
nkeynes@359
  2045
STC.L VBR, @-Rn {:  
nkeynes@359
  2046
    load_reg( R_ECX, Rn );
nkeynes@359
  2047
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2048
    store_reg( R_ECX, Rn );
nkeynes@359
  2049
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2050
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2051
:}
nkeynes@359
  2052
STC.L SSR, @-Rn {:  
nkeynes@359
  2053
    load_reg( R_ECX, Rn );
nkeynes@359
  2054
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2055
    store_reg( R_ECX, Rn );
nkeynes@359
  2056
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2057
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2058
:}
nkeynes@359
  2059
STC.L SPC, @-Rn {:  
nkeynes@359
  2060
    load_reg( R_ECX, Rn );
nkeynes@359
  2061
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2062
    store_reg( R_ECX, Rn );
nkeynes@359
  2063
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2064
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2065
:}
nkeynes@359
  2066
STC.L SGR, @-Rn {:  
nkeynes@359
  2067
    load_reg( R_ECX, Rn );
nkeynes@359
  2068
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2069
    store_reg( R_ECX, Rn );
nkeynes@359
  2070
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2071
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2072
:}
nkeynes@359
  2073
STC.L DBR, @-Rn {:  
nkeynes@359
  2074
    load_reg( R_ECX, Rn );
nkeynes@359
  2075
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2076
    store_reg( R_ECX, Rn );
nkeynes@359
  2077
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2078
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2079
:}
nkeynes@374
  2080
STC.L Rm_BANK, @-Rn {:  
nkeynes@374
  2081
    load_reg( R_ECX, Rn );
nkeynes@374
  2082
    ADD_imm8s_r32( -4, Rn );
nkeynes@374
  2083
    store_reg( R_ECX, Rn );
nkeynes@374
  2084
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2085
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2086
:}
nkeynes@359
  2087
STC.L GBR, @-Rn {:  
nkeynes@359
  2088
    load_reg( R_ECX, Rn );
nkeynes@359
  2089
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2090
    store_reg( R_ECX, Rn );
nkeynes@359
  2091
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2092
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2093
:}
nkeynes@359
  2094
STS FPSCR, Rn {:  
nkeynes@359
  2095
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2096
    store_reg( R_EAX, Rn );
nkeynes@359
  2097
:}
nkeynes@359
  2098
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2099
    load_reg( R_ECX, Rn );
nkeynes@359
  2100
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2101
    store_reg( R_ECX, Rn );
nkeynes@359
  2102
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2103
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2104
:}
nkeynes@359
  2105
STS FPUL, Rn {:  
nkeynes@359
  2106
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2107
    store_reg( R_EAX, Rn );
nkeynes@359
  2108
:}
nkeynes@359
  2109
STS.L FPUL, @-Rn {:  
nkeynes@359
  2110
    load_reg( R_ECX, Rn );
nkeynes@359
  2111
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2112
    store_reg( R_ECX, Rn );
nkeynes@359
  2113
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2114
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2115
:}
nkeynes@359
  2116
STS MACH, Rn {:  
nkeynes@359
  2117
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2118
    store_reg( R_EAX, Rn );
nkeynes@359
  2119
:}
nkeynes@359
  2120
STS.L MACH, @-Rn {:  
nkeynes@359
  2121
    load_reg( R_ECX, Rn );
nkeynes@359
  2122
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2123
    store_reg( R_ECX, Rn );
nkeynes@359
  2124
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2125
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2126
:}
nkeynes@359
  2127
STS MACL, Rn {:  
nkeynes@359
  2128
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2129
    store_reg( R_EAX, Rn );
nkeynes@359
  2130
:}
nkeynes@359
  2131
STS.L MACL, @-Rn {:  
nkeynes@359
  2132
    load_reg( R_ECX, Rn );
nkeynes@359
  2133
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2134
    store_reg( R_ECX, Rn );
nkeynes@359
  2135
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2136
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2137
:}
nkeynes@359
  2138
STS PR, Rn {:  
nkeynes@359
  2139
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2140
    store_reg( R_EAX, Rn );
nkeynes@359
  2141
:}
nkeynes@359
  2142
STS.L PR, @-Rn {:  
nkeynes@359
  2143
    load_reg( R_ECX, Rn );
nkeynes@359
  2144
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2145
    store_reg( R_ECX, Rn );
nkeynes@359
  2146
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2147
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2148
:}
nkeynes@359
  2149
nkeynes@359
  2150
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2151
%%
nkeynes@368
  2152
    INC_r32(R_ESI);
nkeynes@374
  2153
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2154
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2155
	return 1;
nkeynes@374
  2156
    }
nkeynes@359
  2157
    return 0;
nkeynes@359
  2158
}
.