filename | src/sh4/sh4.c |
changeset | 669:ab344e42bca9 |
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author | nkeynes |
date | Mon May 12 10:00:13 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Cleanup most of the -Wall warnings (getting a bit sloppy...) Convert FP code to use fixed banks rather than indirect pointer (3-4% faster this way now) |
file | annotate | diff | log | raw |
nkeynes@378 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@378 | 3 | * |
nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral |
nkeynes@378 | 5 | * modules. |
nkeynes@378 | 6 | * |
nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@378 | 8 | * |
nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@378 | 12 | * (at your option) any later version. |
nkeynes@378 | 13 | * |
nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@378 | 17 | * GNU General Public License for more details. |
nkeynes@378 | 18 | */ |
nkeynes@378 | 19 | |
nkeynes@378 | 20 | #define MODULE sh4_module |
nkeynes@378 | 21 | #include <math.h> |
nkeynes@617 | 22 | #include <assert.h> |
nkeynes@378 | 23 | #include "dream.h" |
nkeynes@422 | 24 | #include "dreamcast.h" |
nkeynes@669 | 25 | #include "mem.h" |
nkeynes@669 | 26 | #include "clock.h" |
nkeynes@669 | 27 | #include "eventq.h" |
nkeynes@669 | 28 | #include "syscall.h" |
nkeynes@669 | 29 | #include "sh4/intc.h" |
nkeynes@378 | 30 | #include "sh4/sh4core.h" |
nkeynes@378 | 31 | #include "sh4/sh4mmio.h" |
nkeynes@422 | 32 | #include "sh4/sh4stat.h" |
nkeynes@617 | 33 | #include "sh4/sh4trans.h" |
nkeynes@669 | 34 | #include "sh4/xltcache.h" |
nkeynes@378 | 35 | |
nkeynes@378 | 36 | void sh4_init( void ); |
nkeynes@526 | 37 | void sh4_xlat_init( void ); |
nkeynes@378 | 38 | void sh4_reset( void ); |
nkeynes@378 | 39 | void sh4_start( void ); |
nkeynes@378 | 40 | void sh4_stop( void ); |
nkeynes@378 | 41 | void sh4_save_state( FILE *f ); |
nkeynes@378 | 42 | int sh4_load_state( FILE *f ); |
nkeynes@378 | 43 | |
nkeynes@378 | 44 | uint32_t sh4_run_slice( uint32_t ); |
nkeynes@378 | 45 | uint32_t sh4_xlat_run_slice( uint32_t ); |
nkeynes@378 | 46 | |
nkeynes@378 | 47 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, |
nkeynes@591 | 48 | sh4_start, sh4_run_slice, sh4_stop, |
nkeynes@378 | 49 | sh4_save_state, sh4_load_state }; |
nkeynes@378 | 50 | |
nkeynes@378 | 51 | struct sh4_registers sh4r; |
nkeynes@378 | 52 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@378 | 53 | int sh4_breakpoint_count = 0; |
nkeynes@586 | 54 | sh4ptr_t sh4_main_ram; |
nkeynes@591 | 55 | gboolean sh4_starting = FALSE; |
nkeynes@526 | 56 | static gboolean sh4_use_translator = FALSE; |
nkeynes@586 | 57 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 }; |
nkeynes@378 | 58 | |
nkeynes@378 | 59 | void sh4_set_use_xlat( gboolean use ) |
nkeynes@378 | 60 | { |
nkeynes@526 | 61 | // No-op if the translator was not built |
nkeynes@526 | 62 | #ifdef SH4_TRANSLATOR |
nkeynes@378 | 63 | if( use ) { |
nkeynes@378 | 64 | xlat_cache_init(); |
nkeynes@669 | 65 | sh4_translate_init(); |
nkeynes@378 | 66 | sh4_module.run_time_slice = sh4_xlat_run_slice; |
nkeynes@378 | 67 | } else { |
nkeynes@378 | 68 | sh4_module.run_time_slice = sh4_run_slice; |
nkeynes@378 | 69 | } |
nkeynes@526 | 70 | sh4_use_translator = use; |
nkeynes@526 | 71 | #endif |
nkeynes@378 | 72 | } |
nkeynes@378 | 73 | |
nkeynes@586 | 74 | gboolean sh4_is_using_xlat() |
nkeynes@586 | 75 | { |
nkeynes@586 | 76 | return sh4_use_translator; |
nkeynes@586 | 77 | } |
nkeynes@586 | 78 | |
nkeynes@378 | 79 | void sh4_init(void) |
nkeynes@378 | 80 | { |
nkeynes@378 | 81 | register_io_regions( mmio_list_sh4mmio ); |
nkeynes@418 | 82 | sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN); |
nkeynes@378 | 83 | MMU_init(); |
nkeynes@619 | 84 | TMU_init(); |
nkeynes@378 | 85 | sh4_reset(); |
nkeynes@378 | 86 | } |
nkeynes@378 | 87 | |
nkeynes@591 | 88 | void sh4_start(void) |
nkeynes@591 | 89 | { |
nkeynes@591 | 90 | sh4_starting = TRUE; |
nkeynes@591 | 91 | } |
nkeynes@591 | 92 | |
nkeynes@378 | 93 | void sh4_reset(void) |
nkeynes@378 | 94 | { |
nkeynes@526 | 95 | if( sh4_use_translator ) { |
nkeynes@472 | 96 | xlat_flush_cache(); |
nkeynes@472 | 97 | } |
nkeynes@472 | 98 | |
nkeynes@378 | 99 | /* zero everything out, for the sake of having a consistent state. */ |
nkeynes@378 | 100 | memset( &sh4r, 0, sizeof(sh4r) ); |
nkeynes@378 | 101 | |
nkeynes@378 | 102 | /* Resume running if we were halted */ |
nkeynes@378 | 103 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@378 | 104 | |
nkeynes@378 | 105 | sh4r.pc = 0xA0000000; |
nkeynes@378 | 106 | sh4r.new_pc= 0xA0000002; |
nkeynes@378 | 107 | sh4r.vbr = 0x00000000; |
nkeynes@378 | 108 | sh4r.fpscr = 0x00040001; |
nkeynes@378 | 109 | sh4r.sr = 0x700000F0; |
nkeynes@378 | 110 | |
nkeynes@378 | 111 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */ |
nkeynes@378 | 112 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); |
nkeynes@378 | 113 | |
nkeynes@378 | 114 | /* Peripheral modules */ |
nkeynes@378 | 115 | CPG_reset(); |
nkeynes@378 | 116 | INTC_reset(); |
nkeynes@378 | 117 | MMU_reset(); |
nkeynes@378 | 118 | TMU_reset(); |
nkeynes@378 | 119 | SCIF_reset(); |
nkeynes@401 | 120 | sh4_stats_reset(); |
nkeynes@378 | 121 | } |
nkeynes@378 | 122 | |
nkeynes@378 | 123 | void sh4_stop(void) |
nkeynes@378 | 124 | { |
nkeynes@526 | 125 | if( sh4_use_translator ) { |
nkeynes@502 | 126 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@502 | 127 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@502 | 128 | sh4r.in_delay_slot = FALSE; |
nkeynes@502 | 129 | } |
nkeynes@378 | 130 | |
nkeynes@378 | 131 | } |
nkeynes@378 | 132 | |
nkeynes@378 | 133 | void sh4_save_state( FILE *f ) |
nkeynes@378 | 134 | { |
nkeynes@526 | 135 | if( sh4_use_translator ) { |
nkeynes@401 | 136 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@401 | 137 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@401 | 138 | sh4r.in_delay_slot = FALSE; |
nkeynes@401 | 139 | } |
nkeynes@401 | 140 | |
nkeynes@378 | 141 | fwrite( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@378 | 142 | MMU_save_state( f ); |
nkeynes@378 | 143 | INTC_save_state( f ); |
nkeynes@378 | 144 | TMU_save_state( f ); |
nkeynes@378 | 145 | SCIF_save_state( f ); |
nkeynes@378 | 146 | } |
nkeynes@378 | 147 | |
nkeynes@378 | 148 | int sh4_load_state( FILE * f ) |
nkeynes@378 | 149 | { |
nkeynes@526 | 150 | if( sh4_use_translator ) { |
nkeynes@472 | 151 | xlat_flush_cache(); |
nkeynes@472 | 152 | } |
nkeynes@378 | 153 | fread( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@378 | 154 | MMU_load_state( f ); |
nkeynes@378 | 155 | INTC_load_state( f ); |
nkeynes@378 | 156 | TMU_load_state( f ); |
nkeynes@378 | 157 | return SCIF_load_state( f ); |
nkeynes@378 | 158 | } |
nkeynes@378 | 159 | |
nkeynes@378 | 160 | |
nkeynes@586 | 161 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 162 | { |
nkeynes@378 | 163 | sh4_breakpoints[sh4_breakpoint_count].address = pc; |
nkeynes@378 | 164 | sh4_breakpoints[sh4_breakpoint_count].type = type; |
nkeynes@586 | 165 | if( sh4_use_translator ) { |
nkeynes@586 | 166 | xlat_invalidate_word( pc ); |
nkeynes@586 | 167 | } |
nkeynes@378 | 168 | sh4_breakpoint_count++; |
nkeynes@378 | 169 | } |
nkeynes@378 | 170 | |
nkeynes@586 | 171 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 172 | { |
nkeynes@378 | 173 | int i; |
nkeynes@378 | 174 | |
nkeynes@378 | 175 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@378 | 176 | if( sh4_breakpoints[i].address == pc && |
nkeynes@378 | 177 | sh4_breakpoints[i].type == type ) { |
nkeynes@378 | 178 | while( ++i < sh4_breakpoint_count ) { |
nkeynes@378 | 179 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address; |
nkeynes@378 | 180 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type; |
nkeynes@378 | 181 | } |
nkeynes@586 | 182 | if( sh4_use_translator ) { |
nkeynes@586 | 183 | xlat_invalidate_word( pc ); |
nkeynes@586 | 184 | } |
nkeynes@378 | 185 | sh4_breakpoint_count--; |
nkeynes@378 | 186 | return TRUE; |
nkeynes@378 | 187 | } |
nkeynes@378 | 188 | } |
nkeynes@378 | 189 | return FALSE; |
nkeynes@378 | 190 | } |
nkeynes@378 | 191 | |
nkeynes@378 | 192 | int sh4_get_breakpoint( uint32_t pc ) |
nkeynes@378 | 193 | { |
nkeynes@378 | 194 | int i; |
nkeynes@378 | 195 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@378 | 196 | if( sh4_breakpoints[i].address == pc ) |
nkeynes@378 | 197 | return sh4_breakpoints[i].type; |
nkeynes@378 | 198 | } |
nkeynes@378 | 199 | return 0; |
nkeynes@378 | 200 | } |
nkeynes@378 | 201 | |
nkeynes@401 | 202 | void sh4_set_pc( int pc ) |
nkeynes@401 | 203 | { |
nkeynes@401 | 204 | sh4r.pc = pc; |
nkeynes@401 | 205 | sh4r.new_pc = pc+2; |
nkeynes@401 | 206 | } |
nkeynes@401 | 207 | |
nkeynes@401 | 208 | |
nkeynes@401 | 209 | /******************************* Support methods ***************************/ |
nkeynes@401 | 210 | |
nkeynes@401 | 211 | static void sh4_switch_banks( ) |
nkeynes@401 | 212 | { |
nkeynes@401 | 213 | uint32_t tmp[8]; |
nkeynes@401 | 214 | |
nkeynes@401 | 215 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); |
nkeynes@401 | 216 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); |
nkeynes@401 | 217 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); |
nkeynes@401 | 218 | } |
nkeynes@401 | 219 | |
nkeynes@669 | 220 | void sh4_switch_fr_banks() |
nkeynes@669 | 221 | { |
nkeynes@669 | 222 | int i; |
nkeynes@669 | 223 | for( i=0; i<16; i++ ) { |
nkeynes@669 | 224 | float tmp = sh4r.fr[0][i]; |
nkeynes@669 | 225 | sh4r.fr[0][i] = sh4r.fr[1][i]; |
nkeynes@669 | 226 | sh4r.fr[1][i] = tmp; |
nkeynes@669 | 227 | } |
nkeynes@669 | 228 | } |
nkeynes@669 | 229 | |
nkeynes@401 | 230 | void sh4_write_sr( uint32_t newval ) |
nkeynes@401 | 231 | { |
nkeynes@586 | 232 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 233 | int newbank = (newval&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 234 | if( oldbank != newbank ) |
nkeynes@401 | 235 | sh4_switch_banks(); |
nkeynes@401 | 236 | sh4r.sr = newval; |
nkeynes@401 | 237 | sh4r.t = (newval&SR_T) ? 1 : 0; |
nkeynes@401 | 238 | sh4r.s = (newval&SR_S) ? 1 : 0; |
nkeynes@401 | 239 | sh4r.m = (newval&SR_M) ? 1 : 0; |
nkeynes@401 | 240 | sh4r.q = (newval&SR_Q) ? 1 : 0; |
nkeynes@401 | 241 | intc_mask_changed(); |
nkeynes@401 | 242 | } |
nkeynes@401 | 243 | |
nkeynes@669 | 244 | void sh4_write_fpscr( uint32_t newval ) |
nkeynes@669 | 245 | { |
nkeynes@669 | 246 | if( (sh4r.fpscr ^ newval) & FPSCR_FR ) { |
nkeynes@669 | 247 | sh4_switch_fr_banks(); |
nkeynes@669 | 248 | } |
nkeynes@669 | 249 | sh4r.fpscr = newval; |
nkeynes@669 | 250 | } |
nkeynes@669 | 251 | |
nkeynes@401 | 252 | uint32_t sh4_read_sr( void ) |
nkeynes@401 | 253 | { |
nkeynes@401 | 254 | /* synchronize sh4r.sr with the various bitflags */ |
nkeynes@401 | 255 | sh4r.sr &= SR_MQSTMASK; |
nkeynes@401 | 256 | if( sh4r.t ) sh4r.sr |= SR_T; |
nkeynes@401 | 257 | if( sh4r.s ) sh4r.sr |= SR_S; |
nkeynes@401 | 258 | if( sh4r.m ) sh4r.sr |= SR_M; |
nkeynes@401 | 259 | if( sh4r.q ) sh4r.sr |= SR_Q; |
nkeynes@401 | 260 | return sh4r.sr; |
nkeynes@401 | 261 | } |
nkeynes@401 | 262 | |
nkeynes@401 | 263 | |
nkeynes@401 | 264 | |
nkeynes@401 | 265 | #define RAISE( x, v ) do{ \ |
nkeynes@401 | 266 | if( sh4r.vbr == 0 ) { \ |
nkeynes@401 | 267 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \ |
nkeynes@401 | 268 | dreamcast_stop(); return FALSE; \ |
nkeynes@401 | 269 | } else { \ |
nkeynes@401 | 270 | sh4r.spc = sh4r.pc; \ |
nkeynes@401 | 271 | sh4r.ssr = sh4_read_sr(); \ |
nkeynes@401 | 272 | sh4r.sgr = sh4r.r[15]; \ |
nkeynes@401 | 273 | MMIO_WRITE(MMU,EXPEVT,x); \ |
nkeynes@401 | 274 | sh4r.pc = sh4r.vbr + v; \ |
nkeynes@401 | 275 | sh4r.new_pc = sh4r.pc + 2; \ |
nkeynes@401 | 276 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \ |
nkeynes@401 | 277 | if( sh4r.in_delay_slot ) { \ |
nkeynes@401 | 278 | sh4r.in_delay_slot = 0; \ |
nkeynes@401 | 279 | sh4r.spc -= 2; \ |
nkeynes@401 | 280 | } \ |
nkeynes@401 | 281 | } \ |
nkeynes@401 | 282 | return TRUE; } while(0) |
nkeynes@401 | 283 | |
nkeynes@401 | 284 | /** |
nkeynes@401 | 285 | * Raise a general CPU exception for the specified exception code. |
nkeynes@401 | 286 | * (NOT for TRAPA or TLB exceptions) |
nkeynes@401 | 287 | */ |
nkeynes@401 | 288 | gboolean sh4_raise_exception( int code ) |
nkeynes@401 | 289 | { |
nkeynes@401 | 290 | RAISE( code, EXV_EXCEPTION ); |
nkeynes@401 | 291 | } |
nkeynes@401 | 292 | |
nkeynes@586 | 293 | /** |
nkeynes@586 | 294 | * Raise a CPU reset exception with the specified exception code. |
nkeynes@586 | 295 | */ |
nkeynes@586 | 296 | gboolean sh4_raise_reset( int code ) |
nkeynes@586 | 297 | { |
nkeynes@586 | 298 | // FIXME: reset modules as per "manual reset" |
nkeynes@586 | 299 | sh4_reset(); |
nkeynes@586 | 300 | MMIO_WRITE(MMU,EXPEVT,code); |
nkeynes@586 | 301 | sh4r.vbr = 0; |
nkeynes@586 | 302 | sh4r.pc = 0xA0000000; |
nkeynes@586 | 303 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@586 | 304 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK) |
nkeynes@586 | 305 | &(~SR_FD) ); |
nkeynes@669 | 306 | return TRUE; |
nkeynes@586 | 307 | } |
nkeynes@586 | 308 | |
nkeynes@401 | 309 | gboolean sh4_raise_trap( int trap ) |
nkeynes@401 | 310 | { |
nkeynes@401 | 311 | MMIO_WRITE( MMU, TRA, trap<<2 ); |
nkeynes@586 | 312 | RAISE( EXC_TRAP, EXV_EXCEPTION ); |
nkeynes@401 | 313 | } |
nkeynes@401 | 314 | |
nkeynes@401 | 315 | gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) { |
nkeynes@401 | 316 | if( sh4r.in_delay_slot ) { |
nkeynes@401 | 317 | return sh4_raise_exception(slot_code); |
nkeynes@401 | 318 | } else { |
nkeynes@401 | 319 | return sh4_raise_exception(normal_code); |
nkeynes@401 | 320 | } |
nkeynes@401 | 321 | } |
nkeynes@401 | 322 | |
nkeynes@401 | 323 | gboolean sh4_raise_tlb_exception( int code ) |
nkeynes@401 | 324 | { |
nkeynes@401 | 325 | RAISE( code, EXV_TLBMISS ); |
nkeynes@401 | 326 | } |
nkeynes@401 | 327 | |
nkeynes@401 | 328 | void sh4_accept_interrupt( void ) |
nkeynes@401 | 329 | { |
nkeynes@401 | 330 | uint32_t code = intc_accept_interrupt(); |
nkeynes@401 | 331 | sh4r.ssr = sh4_read_sr(); |
nkeynes@401 | 332 | sh4r.spc = sh4r.pc; |
nkeynes@401 | 333 | sh4r.sgr = sh4r.r[15]; |
nkeynes@401 | 334 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); |
nkeynes@401 | 335 | MMIO_WRITE( MMU, INTEVT, code ); |
nkeynes@401 | 336 | sh4r.pc = sh4r.vbr + 0x600; |
nkeynes@401 | 337 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@401 | 338 | // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc ); |
nkeynes@401 | 339 | } |
nkeynes@401 | 340 | |
nkeynes@401 | 341 | void signsat48( void ) |
nkeynes@401 | 342 | { |
nkeynes@401 | 343 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL ) |
nkeynes@401 | 344 | sh4r.mac = 0xFFFF800000000000LL; |
nkeynes@401 | 345 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL ) |
nkeynes@401 | 346 | sh4r.mac = 0x00007FFFFFFFFFFFLL; |
nkeynes@401 | 347 | } |
nkeynes@401 | 348 | |
nkeynes@401 | 349 | void sh4_fsca( uint32_t anglei, float *fr ) |
nkeynes@401 | 350 | { |
nkeynes@401 | 351 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI; |
nkeynes@401 | 352 | *fr++ = cosf(angle); |
nkeynes@401 | 353 | *fr = sinf(angle); |
nkeynes@401 | 354 | } |
nkeynes@401 | 355 | |
nkeynes@617 | 356 | /** |
nkeynes@617 | 357 | * Enter sleep mode (eg by executing a SLEEP instruction). |
nkeynes@617 | 358 | * Sets sh4_state appropriately and ensures any stopping peripheral modules |
nkeynes@617 | 359 | * are up to date. |
nkeynes@617 | 360 | */ |
nkeynes@401 | 361 | void sh4_sleep(void) |
nkeynes@401 | 362 | { |
nkeynes@401 | 363 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) { |
nkeynes@401 | 364 | sh4r.sh4_state = SH4_STATE_STANDBY; |
nkeynes@617 | 365 | /* Bring all running peripheral modules up to date, and then halt them. */ |
nkeynes@617 | 366 | TMU_run_slice( sh4r.slice_cycle ); |
nkeynes@617 | 367 | SCIF_run_slice( sh4r.slice_cycle ); |
nkeynes@401 | 368 | } else { |
nkeynes@617 | 369 | if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) { |
nkeynes@617 | 370 | sh4r.sh4_state = SH4_STATE_DEEP_SLEEP; |
nkeynes@617 | 371 | /* Halt DMAC but other peripherals still running */ |
nkeynes@617 | 372 | |
nkeynes@617 | 373 | } else { |
nkeynes@617 | 374 | sh4r.sh4_state = SH4_STATE_SLEEP; |
nkeynes@617 | 375 | } |
nkeynes@617 | 376 | } |
nkeynes@617 | 377 | if( sh4_xlat_is_running() ) { |
nkeynes@617 | 378 | sh4_translate_exit( XLAT_EXIT_SLEEP ); |
nkeynes@401 | 379 | } |
nkeynes@401 | 380 | } |
nkeynes@401 | 381 | |
nkeynes@401 | 382 | /** |
nkeynes@617 | 383 | * Wakeup following sleep mode (IRQ or reset). Sets state back to running, |
nkeynes@617 | 384 | * and restarts any peripheral devices that were stopped. |
nkeynes@617 | 385 | */ |
nkeynes@617 | 386 | void sh4_wakeup(void) |
nkeynes@617 | 387 | { |
nkeynes@617 | 388 | switch( sh4r.sh4_state ) { |
nkeynes@617 | 389 | case SH4_STATE_STANDBY: |
nkeynes@617 | 390 | break; |
nkeynes@617 | 391 | case SH4_STATE_DEEP_SLEEP: |
nkeynes@617 | 392 | break; |
nkeynes@617 | 393 | case SH4_STATE_SLEEP: |
nkeynes@617 | 394 | break; |
nkeynes@617 | 395 | } |
nkeynes@617 | 396 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@617 | 397 | } |
nkeynes@617 | 398 | |
nkeynes@617 | 399 | /** |
nkeynes@617 | 400 | * Run a time slice (or portion of a timeslice) while the SH4 is sleeping. |
nkeynes@617 | 401 | * Returns when either the SH4 wakes up (interrupt received) or the end of |
nkeynes@617 | 402 | * the slice is reached. Updates sh4.slice_cycle with the exit time and |
nkeynes@617 | 403 | * returns the same value. |
nkeynes@617 | 404 | */ |
nkeynes@617 | 405 | uint32_t sh4_sleep_run_slice( uint32_t nanosecs ) |
nkeynes@617 | 406 | { |
nkeynes@617 | 407 | int sleep_state = sh4r.sh4_state; |
nkeynes@617 | 408 | assert( sleep_state != SH4_STATE_RUNNING ); |
nkeynes@638 | 409 | |
nkeynes@617 | 410 | while( sh4r.event_pending < nanosecs ) { |
nkeynes@617 | 411 | sh4r.slice_cycle = sh4r.event_pending; |
nkeynes@617 | 412 | if( sh4r.event_types & PENDING_EVENT ) { |
nkeynes@617 | 413 | event_execute(); |
nkeynes@617 | 414 | } |
nkeynes@617 | 415 | if( sh4r.event_types & PENDING_IRQ ) { |
nkeynes@617 | 416 | sh4_wakeup(); |
nkeynes@638 | 417 | return sh4r.slice_cycle; |
nkeynes@617 | 418 | } |
nkeynes@617 | 419 | } |
nkeynes@617 | 420 | sh4r.slice_cycle = nanosecs; |
nkeynes@617 | 421 | return sh4r.slice_cycle; |
nkeynes@617 | 422 | } |
nkeynes@617 | 423 | |
nkeynes@617 | 424 | |
nkeynes@617 | 425 | /** |
nkeynes@401 | 426 | * Compute the matrix tranform of fv given the matrix xf. |
nkeynes@401 | 427 | * Both fv and xf are word-swapped as per the sh4r.fr banks |
nkeynes@401 | 428 | */ |
nkeynes@669 | 429 | void sh4_ftrv( float *target ) |
nkeynes@401 | 430 | { |
nkeynes@401 | 431 | float fv[4] = { target[1], target[0], target[3], target[2] }; |
nkeynes@669 | 432 | target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] + |
nkeynes@669 | 433 | sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3]; |
nkeynes@669 | 434 | target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] + |
nkeynes@669 | 435 | sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3]; |
nkeynes@669 | 436 | target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] + |
nkeynes@669 | 437 | sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3]; |
nkeynes@669 | 438 | target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] + |
nkeynes@669 | 439 | sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3]; |
nkeynes@401 | 440 | } |
nkeynes@401 | 441 | |
nkeynes@597 | 442 | gboolean sh4_has_page( sh4vma_t vma ) |
nkeynes@597 | 443 | { |
nkeynes@597 | 444 | sh4addr_t addr = mmu_vma_to_phys_disasm(vma); |
nkeynes@597 | 445 | return addr != MMU_VMA_ERROR && mem_has_page(addr); |
nkeynes@597 | 446 | } |
.