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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 669:ab344e42bca9
prev626:a010e30a30e9
next671:a530ea88eebd
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SH4_TRANSLATOR == TARGET_X86_64
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#include "sh4/ia64abi.h"
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#else /* SH4_TRANSLATOR == TARGET_X86 */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
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#endif
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uint32_t sh4_translate_end_block_size()
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{
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    if( sh4_x86.backpatch_posn <= 3 ) {
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	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
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    } else {
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	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
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    }
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}
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/**
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 * Embed a breakpoint into the generated code
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   311
 */
nkeynes@586
   312
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   313
{
nkeynes@591
   314
    load_imm32( R_EAX, pc );
nkeynes@591
   315
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   316
}
nkeynes@590
   317
nkeynes@601
   318
nkeynes@601
   319
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   320
nkeynes@590
   321
/**
nkeynes@590
   322
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   323
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   324
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   325
 *
nkeynes@601
   326
 * Performs:
nkeynes@601
   327
 *   Set PC = endpc
nkeynes@601
   328
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   329
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   330
 *   Call sh4_execute_instruction
nkeynes@601
   331
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   332
 */
nkeynes@601
   333
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   334
{
nkeynes@590
   335
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   336
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   337
    
nkeynes@601
   338
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   339
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   340
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   341
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   342
nkeynes@590
   343
    call_func0( sh4_execute_instruction );    
nkeynes@601
   344
    load_spreg( R_EAX, R_PC );
nkeynes@590
   345
    if( sh4_x86.tlb_on ) {
nkeynes@590
   346
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   347
    } else {
nkeynes@590
   348
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   349
    }
nkeynes@601
   350
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   351
    POP_r32(R_EBP);
nkeynes@590
   352
    RET();
nkeynes@590
   353
} 
nkeynes@539
   354
nkeynes@359
   355
/**
nkeynes@359
   356
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   357
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   358
 * 
nkeynes@586
   359
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   360
 *
nkeynes@359
   361
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   362
 * (eg a branch or 
nkeynes@359
   363
 */
nkeynes@590
   364
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   365
{
nkeynes@388
   366
    uint32_t ir;
nkeynes@586
   367
    /* Read instruction from icache */
nkeynes@586
   368
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   369
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   370
    
nkeynes@586
   371
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   372
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   373
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   374
	 * almost certainly in a delay slot.
nkeynes@586
   375
	 *
nkeynes@586
   376
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   377
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   378
	 * small repairs to cope with the different environment).
nkeynes@586
   379
	 */
nkeynes@586
   380
nkeynes@586
   381
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   382
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   383
    }
nkeynes@359
   384
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   385
            case 0x0:
nkeynes@359
   386
                switch( ir&0xF ) {
nkeynes@359
   387
                    case 0x2:
nkeynes@359
   388
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   389
                            case 0x0:
nkeynes@359
   390
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   391
                                    case 0x0:
nkeynes@359
   392
                                        { /* STC SR, Rn */
nkeynes@359
   393
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   394
                                        check_priv();
nkeynes@374
   395
                                        call_func0(sh4_read_sr);
nkeynes@368
   396
                                        store_reg( R_EAX, Rn );
nkeynes@417
   397
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   398
                                        }
nkeynes@359
   399
                                        break;
nkeynes@359
   400
                                    case 0x1:
nkeynes@359
   401
                                        { /* STC GBR, Rn */
nkeynes@359
   402
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   403
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   404
                                        store_reg( R_EAX, Rn );
nkeynes@359
   405
                                        }
nkeynes@359
   406
                                        break;
nkeynes@359
   407
                                    case 0x2:
nkeynes@359
   408
                                        { /* STC VBR, Rn */
nkeynes@359
   409
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   410
                                        check_priv();
nkeynes@359
   411
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   412
                                        store_reg( R_EAX, Rn );
nkeynes@417
   413
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   414
                                        }
nkeynes@359
   415
                                        break;
nkeynes@359
   416
                                    case 0x3:
nkeynes@359
   417
                                        { /* STC SSR, Rn */
nkeynes@359
   418
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   419
                                        check_priv();
nkeynes@359
   420
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   421
                                        store_reg( R_EAX, Rn );
nkeynes@417
   422
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   423
                                        }
nkeynes@359
   424
                                        break;
nkeynes@359
   425
                                    case 0x4:
nkeynes@359
   426
                                        { /* STC SPC, Rn */
nkeynes@359
   427
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   428
                                        check_priv();
nkeynes@359
   429
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   430
                                        store_reg( R_EAX, Rn );
nkeynes@417
   431
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   432
                                        }
nkeynes@359
   433
                                        break;
nkeynes@359
   434
                                    default:
nkeynes@359
   435
                                        UNDEF();
nkeynes@359
   436
                                        break;
nkeynes@359
   437
                                }
nkeynes@359
   438
                                break;
nkeynes@359
   439
                            case 0x1:
nkeynes@359
   440
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   441
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   442
                                check_priv();
nkeynes@374
   443
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   444
                                store_reg( R_EAX, Rn );
nkeynes@417
   445
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   446
                                }
nkeynes@359
   447
                                break;
nkeynes@359
   448
                        }
nkeynes@359
   449
                        break;
nkeynes@359
   450
                    case 0x3:
nkeynes@359
   451
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   452
                            case 0x0:
nkeynes@359
   453
                                { /* BSRF Rn */
nkeynes@359
   454
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   455
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   456
                            	SLOTILLEGAL();
nkeynes@374
   457
                                } else {
nkeynes@590
   458
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   459
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   460
                            	store_spreg( R_EAX, R_PR );
nkeynes@590
   461
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   462
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   463
                            
nkeynes@601
   464
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   465
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   466
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   467
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   468
                            	    exit_block_emu(pc+2);
nkeynes@601
   469
                            	    return 2;
nkeynes@601
   470
                            	} else {
nkeynes@601
   471
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   472
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   473
                            	    return 4;
nkeynes@601
   474
                            	}
nkeynes@374
   475
                                }
nkeynes@359
   476
                                }
nkeynes@359
   477
                                break;
nkeynes@359
   478
                            case 0x2:
nkeynes@359
   479
                                { /* BRAF Rn */
nkeynes@359
   480
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   481
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   482
                            	SLOTILLEGAL();
nkeynes@374
   483
                                } else {
nkeynes@590
   484
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   485
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   486
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   487
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   488
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   489
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   490
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   491
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   492
                            	    exit_block_emu(pc+2);
nkeynes@601
   493
                            	    return 2;
nkeynes@601
   494
                            	} else {
nkeynes@601
   495
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   496
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   497
                            	    return 4;
nkeynes@601
   498
                            	}
nkeynes@374
   499
                                }
nkeynes@359
   500
                                }
nkeynes@359
   501
                                break;
nkeynes@359
   502
                            case 0x8:
nkeynes@359
   503
                                { /* PREF @Rn */
nkeynes@359
   504
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   505
                                load_reg( R_EAX, Rn );
nkeynes@532
   506
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   507
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   508
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
   509
                                JNE_rel8(end);
nkeynes@532
   510
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
   511
                                TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
   512
                                JE_exc(-1);
nkeynes@380
   513
                                JMP_TARGET(end);
nkeynes@417
   514
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   515
                                }
nkeynes@359
   516
                                break;
nkeynes@359
   517
                            case 0x9:
nkeynes@359
   518
                                { /* OCBI @Rn */
nkeynes@359
   519
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   520
                                }
nkeynes@359
   521
                                break;
nkeynes@359
   522
                            case 0xA:
nkeynes@359
   523
                                { /* OCBP @Rn */
nkeynes@359
   524
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   525
                                }
nkeynes@359
   526
                                break;
nkeynes@359
   527
                            case 0xB:
nkeynes@359
   528
                                { /* OCBWB @Rn */
nkeynes@359
   529
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   530
                                }
nkeynes@359
   531
                                break;
nkeynes@359
   532
                            case 0xC:
nkeynes@359
   533
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   534
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
   535
                                load_reg( R_EAX, Rn );
nkeynes@586
   536
                                check_walign32( R_EAX );
nkeynes@586
   537
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   538
                                load_reg( R_EDX, 0 );
nkeynes@586
   539
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   540
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   541
                                }
nkeynes@359
   542
                                break;
nkeynes@359
   543
                            default:
nkeynes@359
   544
                                UNDEF();
nkeynes@359
   545
                                break;
nkeynes@359
   546
                        }
nkeynes@359
   547
                        break;
nkeynes@359
   548
                    case 0x4:
nkeynes@359
   549
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   550
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   551
                        load_reg( R_EAX, 0 );
nkeynes@359
   552
                        load_reg( R_ECX, Rn );
nkeynes@586
   553
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   554
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   555
                        load_reg( R_EDX, Rm );
nkeynes@586
   556
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   557
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   558
                        }
nkeynes@359
   559
                        break;
nkeynes@359
   560
                    case 0x5:
nkeynes@359
   561
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   562
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   563
                        load_reg( R_EAX, 0 );
nkeynes@361
   564
                        load_reg( R_ECX, Rn );
nkeynes@586
   565
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   566
                        check_walign16( R_EAX );
nkeynes@586
   567
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   568
                        load_reg( R_EDX, Rm );
nkeynes@586
   569
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   570
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   571
                        }
nkeynes@359
   572
                        break;
nkeynes@359
   573
                    case 0x6:
nkeynes@359
   574
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   575
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   576
                        load_reg( R_EAX, 0 );
nkeynes@361
   577
                        load_reg( R_ECX, Rn );
nkeynes@586
   578
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   579
                        check_walign32( R_EAX );
nkeynes@586
   580
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   581
                        load_reg( R_EDX, Rm );
nkeynes@586
   582
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   583
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   584
                        }
nkeynes@359
   585
                        break;
nkeynes@359
   586
                    case 0x7:
nkeynes@359
   587
                        { /* MUL.L Rm, Rn */
nkeynes@359
   588
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   589
                        load_reg( R_EAX, Rm );
nkeynes@361
   590
                        load_reg( R_ECX, Rn );
nkeynes@361
   591
                        MUL_r32( R_ECX );
nkeynes@361
   592
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   593
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   594
                        }
nkeynes@359
   595
                        break;
nkeynes@359
   596
                    case 0x8:
nkeynes@359
   597
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   598
                            case 0x0:
nkeynes@359
   599
                                { /* CLRT */
nkeynes@374
   600
                                CLC();
nkeynes@374
   601
                                SETC_t();
nkeynes@417
   602
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   603
                                }
nkeynes@359
   604
                                break;
nkeynes@359
   605
                            case 0x1:
nkeynes@359
   606
                                { /* SETT */
nkeynes@374
   607
                                STC();
nkeynes@374
   608
                                SETC_t();
nkeynes@417
   609
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   610
                                }
nkeynes@359
   611
                                break;
nkeynes@359
   612
                            case 0x2:
nkeynes@359
   613
                                { /* CLRMAC */
nkeynes@374
   614
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   615
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   616
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   617
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   618
                                }
nkeynes@359
   619
                                break;
nkeynes@359
   620
                            case 0x3:
nkeynes@359
   621
                                { /* LDTLB */
nkeynes@553
   622
                                call_func0( MMU_ldtlb );
nkeynes@359
   623
                                }
nkeynes@359
   624
                                break;
nkeynes@359
   625
                            case 0x4:
nkeynes@359
   626
                                { /* CLRS */
nkeynes@374
   627
                                CLC();
nkeynes@374
   628
                                SETC_sh4r(R_S);
nkeynes@417
   629
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   630
                                }
nkeynes@359
   631
                                break;
nkeynes@359
   632
                            case 0x5:
nkeynes@359
   633
                                { /* SETS */
nkeynes@374
   634
                                STC();
nkeynes@374
   635
                                SETC_sh4r(R_S);
nkeynes@417
   636
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   637
                                }
nkeynes@359
   638
                                break;
nkeynes@359
   639
                            default:
nkeynes@359
   640
                                UNDEF();
nkeynes@359
   641
                                break;
nkeynes@359
   642
                        }
nkeynes@359
   643
                        break;
nkeynes@359
   644
                    case 0x9:
nkeynes@359
   645
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   646
                            case 0x0:
nkeynes@359
   647
                                { /* NOP */
nkeynes@359
   648
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   649
                                }
nkeynes@359
   650
                                break;
nkeynes@359
   651
                            case 0x1:
nkeynes@359
   652
                                { /* DIV0U */
nkeynes@361
   653
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   654
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   655
                                store_spreg( R_EAX, R_M );
nkeynes@361
   656
                                store_spreg( R_EAX, R_T );
nkeynes@417
   657
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   658
                                }
nkeynes@359
   659
                                break;
nkeynes@359
   660
                            case 0x2:
nkeynes@359
   661
                                { /* MOVT Rn */
nkeynes@359
   662
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   663
                                load_spreg( R_EAX, R_T );
nkeynes@359
   664
                                store_reg( R_EAX, Rn );
nkeynes@359
   665
                                }
nkeynes@359
   666
                                break;
nkeynes@359
   667
                            default:
nkeynes@359
   668
                                UNDEF();
nkeynes@359
   669
                                break;
nkeynes@359
   670
                        }
nkeynes@359
   671
                        break;
nkeynes@359
   672
                    case 0xA:
nkeynes@359
   673
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   674
                            case 0x0:
nkeynes@359
   675
                                { /* STS MACH, Rn */
nkeynes@359
   676
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   677
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   678
                                store_reg( R_EAX, Rn );
nkeynes@359
   679
                                }
nkeynes@359
   680
                                break;
nkeynes@359
   681
                            case 0x1:
nkeynes@359
   682
                                { /* STS MACL, Rn */
nkeynes@359
   683
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   684
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   685
                                store_reg( R_EAX, Rn );
nkeynes@359
   686
                                }
nkeynes@359
   687
                                break;
nkeynes@359
   688
                            case 0x2:
nkeynes@359
   689
                                { /* STS PR, Rn */
nkeynes@359
   690
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   691
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   692
                                store_reg( R_EAX, Rn );
nkeynes@359
   693
                                }
nkeynes@359
   694
                                break;
nkeynes@359
   695
                            case 0x3:
nkeynes@359
   696
                                { /* STC SGR, Rn */
nkeynes@359
   697
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   698
                                check_priv();
nkeynes@359
   699
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   700
                                store_reg( R_EAX, Rn );
nkeynes@417
   701
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   702
                                }
nkeynes@359
   703
                                break;
nkeynes@359
   704
                            case 0x5:
nkeynes@359
   705
                                { /* STS FPUL, Rn */
nkeynes@359
   706
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@626
   707
                                check_fpuen();
nkeynes@359
   708
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   709
                                store_reg( R_EAX, Rn );
nkeynes@359
   710
                                }
nkeynes@359
   711
                                break;
nkeynes@359
   712
                            case 0x6:
nkeynes@359
   713
                                { /* STS FPSCR, Rn */
nkeynes@359
   714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@626
   715
                                check_fpuen();
nkeynes@359
   716
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   717
                                store_reg( R_EAX, Rn );
nkeynes@359
   718
                                }
nkeynes@359
   719
                                break;
nkeynes@359
   720
                            case 0xF:
nkeynes@359
   721
                                { /* STC DBR, Rn */
nkeynes@359
   722
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   723
                                check_priv();
nkeynes@359
   724
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   725
                                store_reg( R_EAX, Rn );
nkeynes@417
   726
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   727
                                }
nkeynes@359
   728
                                break;
nkeynes@359
   729
                            default:
nkeynes@359
   730
                                UNDEF();
nkeynes@359
   731
                                break;
nkeynes@359
   732
                        }
nkeynes@359
   733
                        break;
nkeynes@359
   734
                    case 0xB:
nkeynes@359
   735
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   736
                            case 0x0:
nkeynes@359
   737
                                { /* RTS */
nkeynes@374
   738
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   739
                            	SLOTILLEGAL();
nkeynes@374
   740
                                } else {
nkeynes@408
   741
                            	load_spreg( R_ECX, R_PR );
nkeynes@590
   742
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
   743
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
   744
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   745
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   746
                            	    exit_block_emu(pc+2);
nkeynes@601
   747
                            	    return 2;
nkeynes@601
   748
                            	} else {
nkeynes@601
   749
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   750
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   751
                            	    return 4;
nkeynes@601
   752
                            	}
nkeynes@374
   753
                                }
nkeynes@359
   754
                                }
nkeynes@359
   755
                                break;
nkeynes@359
   756
                            case 0x1:
nkeynes@359
   757
                                { /* SLEEP */
nkeynes@388
   758
                                check_priv();
nkeynes@388
   759
                                call_func0( sh4_sleep );
nkeynes@417
   760
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
   761
                                sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
   762
                                return 2;
nkeynes@359
   763
                                }
nkeynes@359
   764
                                break;
nkeynes@359
   765
                            case 0x2:
nkeynes@359
   766
                                { /* RTE */
nkeynes@374
   767
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   768
                            	SLOTILLEGAL();
nkeynes@374
   769
                                } else {
nkeynes@408
   770
                            	check_priv();
nkeynes@408
   771
                            	load_spreg( R_ECX, R_SPC );
nkeynes@590
   772
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
   773
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   774
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
   775
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
   776
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   777
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   778
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   779
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   780
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   781
                            	    exit_block_emu(pc+2);
nkeynes@601
   782
                            	    return 2;
nkeynes@601
   783
                            	} else {
nkeynes@601
   784
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   785
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   786
                            	    return 4;
nkeynes@601
   787
                            	}
nkeynes@374
   788
                                }
nkeynes@359
   789
                                }
nkeynes@359
   790
                                break;
nkeynes@359
   791
                            default:
nkeynes@359
   792
                                UNDEF();
nkeynes@359
   793
                                break;
nkeynes@359
   794
                        }
nkeynes@359
   795
                        break;
nkeynes@359
   796
                    case 0xC:
nkeynes@359
   797
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   798
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   799
                        load_reg( R_EAX, 0 );
nkeynes@359
   800
                        load_reg( R_ECX, Rm );
nkeynes@586
   801
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   802
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
   803
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   804
                        store_reg( R_EAX, Rn );
nkeynes@417
   805
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   806
                        }
nkeynes@359
   807
                        break;
nkeynes@359
   808
                    case 0xD:
nkeynes@359
   809
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   810
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   811
                        load_reg( R_EAX, 0 );
nkeynes@361
   812
                        load_reg( R_ECX, Rm );
nkeynes@586
   813
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   814
                        check_ralign16( R_EAX );
nkeynes@586
   815
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   816
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   817
                        store_reg( R_EAX, Rn );
nkeynes@417
   818
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   819
                        }
nkeynes@359
   820
                        break;
nkeynes@359
   821
                    case 0xE:
nkeynes@359
   822
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   823
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   824
                        load_reg( R_EAX, 0 );
nkeynes@361
   825
                        load_reg( R_ECX, Rm );
nkeynes@586
   826
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   827
                        check_ralign32( R_EAX );
nkeynes@586
   828
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   829
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   830
                        store_reg( R_EAX, Rn );
nkeynes@417
   831
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   832
                        }
nkeynes@359
   833
                        break;
nkeynes@359
   834
                    case 0xF:
nkeynes@359
   835
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   836
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   837
                        if( Rm == Rn ) {
nkeynes@586
   838
                    	load_reg( R_EAX, Rm );
nkeynes@586
   839
                    	check_ralign32( R_EAX );
nkeynes@586
   840
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   841
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   842
                    	load_reg( R_EAX, Rn );
nkeynes@586
   843
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   844
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   845
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   846
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   847
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
   848
                        } else {
nkeynes@586
   849
                    	load_reg( R_EAX, Rm );
nkeynes@586
   850
                    	check_ralign32( R_EAX );
nkeynes@586
   851
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   852
                    	load_reg( R_ECX, Rn );
nkeynes@596
   853
                    	check_ralign32( R_ECX );
nkeynes@586
   854
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
   855
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   856
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   857
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   858
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   859
                        }
nkeynes@586
   860
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   861
                        POP_r32( R_ECX );
nkeynes@586
   862
                        PUSH_r32( R_EAX );
nkeynes@386
   863
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   864
                        POP_realigned_r32( R_ECX );
nkeynes@586
   865
                    
nkeynes@386
   866
                        IMUL_r32( R_ECX );
nkeynes@386
   867
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   868
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   869
                    
nkeynes@386
   870
                        load_spreg( R_ECX, R_S );
nkeynes@386
   871
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   872
                        JE_rel8( nosat );
nkeynes@386
   873
                        call_func0( signsat48 );
nkeynes@386
   874
                        JMP_TARGET( nosat );
nkeynes@417
   875
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   876
                        }
nkeynes@359
   877
                        break;
nkeynes@359
   878
                    default:
nkeynes@359
   879
                        UNDEF();
nkeynes@359
   880
                        break;
nkeynes@359
   881
                }
nkeynes@359
   882
                break;
nkeynes@359
   883
            case 0x1:
nkeynes@359
   884
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   885
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
   886
                load_reg( R_EAX, Rn );
nkeynes@586
   887
                ADD_imm32_r32( disp, R_EAX );
nkeynes@586
   888
                check_walign32( R_EAX );
nkeynes@586
   889
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   890
                load_reg( R_EDX, Rm );
nkeynes@586
   891
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   892
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   893
                }
nkeynes@359
   894
                break;
nkeynes@359
   895
            case 0x2:
nkeynes@359
   896
                switch( ir&0xF ) {
nkeynes@359
   897
                    case 0x0:
nkeynes@359
   898
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   899
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   900
                        load_reg( R_EAX, Rn );
nkeynes@586
   901
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   902
                        load_reg( R_EDX, Rm );
nkeynes@586
   903
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   904
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   905
                        }
nkeynes@359
   906
                        break;
nkeynes@359
   907
                    case 0x1:
nkeynes@359
   908
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   909
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   910
                        load_reg( R_EAX, Rn );
nkeynes@586
   911
                        check_walign16( R_EAX );
nkeynes@586
   912
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
   913
                        load_reg( R_EDX, Rm );
nkeynes@586
   914
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   915
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   916
                        }
nkeynes@359
   917
                        break;
nkeynes@359
   918
                    case 0x2:
nkeynes@359
   919
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   920
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   921
                        load_reg( R_EAX, Rn );
nkeynes@586
   922
                        check_walign32(R_EAX);
nkeynes@586
   923
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   924
                        load_reg( R_EDX, Rm );
nkeynes@586
   925
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   926
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   927
                        }
nkeynes@359
   928
                        break;
nkeynes@359
   929
                    case 0x4:
nkeynes@359
   930
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   931
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   932
                        load_reg( R_EAX, Rn );
nkeynes@586
   933
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
   934
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   935
                        load_reg( R_EDX, Rm );
nkeynes@586
   936
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
   937
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   938
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   939
                        }
nkeynes@359
   940
                        break;
nkeynes@359
   941
                    case 0x5:
nkeynes@359
   942
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   943
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   944
                        load_reg( R_EAX, Rn );
nkeynes@586
   945
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
   946
                        check_walign16( R_EAX );
nkeynes@586
   947
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   948
                        load_reg( R_EDX, Rm );
nkeynes@586
   949
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
   950
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   951
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   952
                        }
nkeynes@359
   953
                        break;
nkeynes@359
   954
                    case 0x6:
nkeynes@359
   955
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   956
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   957
                        load_reg( R_EAX, Rn );
nkeynes@586
   958
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
   959
                        check_walign32( R_EAX );
nkeynes@586
   960
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   961
                        load_reg( R_EDX, Rm );
nkeynes@586
   962
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
   963
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   964
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
                        }
nkeynes@359
   966
                        break;
nkeynes@359
   967
                    case 0x7:
nkeynes@359
   968
                        { /* DIV0S Rm, Rn */
nkeynes@359
   969
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   970
                        load_reg( R_EAX, Rm );
nkeynes@386
   971
                        load_reg( R_ECX, Rn );
nkeynes@361
   972
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   973
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   974
                        store_spreg( R_EAX, R_M );
nkeynes@361
   975
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   976
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   977
                        SETNE_t();
nkeynes@417
   978
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   979
                        }
nkeynes@359
   980
                        break;
nkeynes@359
   981
                    case 0x8:
nkeynes@359
   982
                        { /* TST Rm, Rn */
nkeynes@359
   983
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   984
                        load_reg( R_EAX, Rm );
nkeynes@361
   985
                        load_reg( R_ECX, Rn );
nkeynes@361
   986
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   987
                        SETE_t();
nkeynes@417
   988
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   989
                        }
nkeynes@359
   990
                        break;
nkeynes@359
   991
                    case 0x9:
nkeynes@359
   992
                        { /* AND Rm, Rn */
nkeynes@359
   993
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   994
                        load_reg( R_EAX, Rm );
nkeynes@359
   995
                        load_reg( R_ECX, Rn );
nkeynes@359
   996
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   997
                        store_reg( R_ECX, Rn );
nkeynes@417
   998
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   999
                        }
nkeynes@359
  1000
                        break;
nkeynes@359
  1001
                    case 0xA:
nkeynes@359
  1002
                        { /* XOR Rm, Rn */
nkeynes@359
  1003
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1004
                        load_reg( R_EAX, Rm );
nkeynes@359
  1005
                        load_reg( R_ECX, Rn );
nkeynes@359
  1006
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1007
                        store_reg( R_ECX, Rn );
nkeynes@417
  1008
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1009
                        }
nkeynes@359
  1010
                        break;
nkeynes@359
  1011
                    case 0xB:
nkeynes@359
  1012
                        { /* OR Rm, Rn */
nkeynes@359
  1013
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1014
                        load_reg( R_EAX, Rm );
nkeynes@359
  1015
                        load_reg( R_ECX, Rn );
nkeynes@359
  1016
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1017
                        store_reg( R_ECX, Rn );
nkeynes@417
  1018
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1019
                        }
nkeynes@359
  1020
                        break;
nkeynes@359
  1021
                    case 0xC:
nkeynes@359
  1022
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1023
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1024
                        load_reg( R_EAX, Rm );
nkeynes@368
  1025
                        load_reg( R_ECX, Rn );
nkeynes@368
  1026
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1027
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@669
  1028
                        JE_rel8(target1);
nkeynes@669
  1029
                        TEST_r8_r8( R_AH, R_AH );
nkeynes@669
  1030
                        JE_rel8(target2);
nkeynes@669
  1031
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@669
  1032
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@669
  1033
                        JE_rel8(target3);
nkeynes@669
  1034
                        TEST_r8_r8( R_AH, R_AH );
nkeynes@380
  1035
                        JMP_TARGET(target1);
nkeynes@380
  1036
                        JMP_TARGET(target2);
nkeynes@380
  1037
                        JMP_TARGET(target3);
nkeynes@368
  1038
                        SETE_t();
nkeynes@417
  1039
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1040
                        }
nkeynes@359
  1041
                        break;
nkeynes@359
  1042
                    case 0xD:
nkeynes@359
  1043
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1044
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1045
                        load_reg( R_EAX, Rm );
nkeynes@394
  1046
                        load_reg( R_ECX, Rn );
nkeynes@394
  1047
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1048
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1049
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1050
                        store_reg( R_ECX, Rn );
nkeynes@417
  1051
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1052
                        }
nkeynes@359
  1053
                        break;
nkeynes@359
  1054
                    case 0xE:
nkeynes@359
  1055
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1056
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1057
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1058
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1059
                        MUL_r32( R_ECX );
nkeynes@374
  1060
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1061
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1062
                        }
nkeynes@359
  1063
                        break;
nkeynes@359
  1064
                    case 0xF:
nkeynes@359
  1065
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1066
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1067
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1068
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1069
                        MUL_r32( R_ECX );
nkeynes@374
  1070
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1071
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1072
                        }
nkeynes@359
  1073
                        break;
nkeynes@359
  1074
                    default:
nkeynes@359
  1075
                        UNDEF();
nkeynes@359
  1076
                        break;
nkeynes@359
  1077
                }
nkeynes@359
  1078
                break;
nkeynes@359
  1079
            case 0x3:
nkeynes@359
  1080
                switch( ir&0xF ) {
nkeynes@359
  1081
                    case 0x0:
nkeynes@359
  1082
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1083
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1084
                        load_reg( R_EAX, Rm );
nkeynes@359
  1085
                        load_reg( R_ECX, Rn );
nkeynes@359
  1086
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1087
                        SETE_t();
nkeynes@417
  1088
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1089
                        }
nkeynes@359
  1090
                        break;
nkeynes@359
  1091
                    case 0x2:
nkeynes@359
  1092
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1093
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1094
                        load_reg( R_EAX, Rm );
nkeynes@359
  1095
                        load_reg( R_ECX, Rn );
nkeynes@359
  1096
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1097
                        SETAE_t();
nkeynes@417
  1098
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1099
                        }
nkeynes@359
  1100
                        break;
nkeynes@359
  1101
                    case 0x3:
nkeynes@359
  1102
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1103
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1104
                        load_reg( R_EAX, Rm );
nkeynes@359
  1105
                        load_reg( R_ECX, Rn );
nkeynes@359
  1106
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1107
                        SETGE_t();
nkeynes@417
  1108
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1109
                        }
nkeynes@359
  1110
                        break;
nkeynes@359
  1111
                    case 0x4:
nkeynes@359
  1112
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1113
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1114
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1115
                        load_reg( R_EAX, Rn );
nkeynes@417
  1116
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1117
                    	LDC_t();
nkeynes@417
  1118
                        }
nkeynes@386
  1119
                        RCL1_r32( R_EAX );
nkeynes@386
  1120
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1121
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
  1122
                        JE_rel8(mqequal);
nkeynes@386
  1123
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
  1124
                        JMP_rel8(end);
nkeynes@380
  1125
                        JMP_TARGET(mqequal);
nkeynes@386
  1126
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1127
                        JMP_TARGET(end);
nkeynes@386
  1128
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1129
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1130
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1131
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1132
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1133
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1134
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1135
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1136
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1137
                        }
nkeynes@359
  1138
                        break;
nkeynes@359
  1139
                    case 0x5:
nkeynes@359
  1140
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1141
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1142
                        load_reg( R_EAX, Rm );
nkeynes@361
  1143
                        load_reg( R_ECX, Rn );
nkeynes@361
  1144
                        MUL_r32(R_ECX);
nkeynes@361
  1145
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1146
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1147
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1148
                        }
nkeynes@359
  1149
                        break;
nkeynes@359
  1150
                    case 0x6:
nkeynes@359
  1151
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1152
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1153
                        load_reg( R_EAX, Rm );
nkeynes@359
  1154
                        load_reg( R_ECX, Rn );
nkeynes@359
  1155
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1156
                        SETA_t();
nkeynes@417
  1157
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1158
                        }
nkeynes@359
  1159
                        break;
nkeynes@359
  1160
                    case 0x7:
nkeynes@359
  1161
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1162
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1163
                        load_reg( R_EAX, Rm );
nkeynes@359
  1164
                        load_reg( R_ECX, Rn );
nkeynes@359
  1165
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1166
                        SETG_t();
nkeynes@417
  1167
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1168
                        }
nkeynes@359
  1169
                        break;
nkeynes@359
  1170
                    case 0x8:
nkeynes@359
  1171
                        { /* SUB Rm, Rn */
nkeynes@359
  1172
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1173
                        load_reg( R_EAX, Rm );
nkeynes@359
  1174
                        load_reg( R_ECX, Rn );
nkeynes@359
  1175
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1176
                        store_reg( R_ECX, Rn );
nkeynes@417
  1177
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1178
                        }
nkeynes@359
  1179
                        break;
nkeynes@359
  1180
                    case 0xA:
nkeynes@359
  1181
                        { /* SUBC Rm, Rn */
nkeynes@359
  1182
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1183
                        load_reg( R_EAX, Rm );
nkeynes@359
  1184
                        load_reg( R_ECX, Rn );
nkeynes@417
  1185
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1186
                    	LDC_t();
nkeynes@417
  1187
                        }
nkeynes@359
  1188
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1189
                        store_reg( R_ECX, Rn );
nkeynes@394
  1190
                        SETC_t();
nkeynes@417
  1191
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1192
                        }
nkeynes@359
  1193
                        break;
nkeynes@359
  1194
                    case 0xB:
nkeynes@359
  1195
                        { /* SUBV Rm, Rn */
nkeynes@359
  1196
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1197
                        load_reg( R_EAX, Rm );
nkeynes@359
  1198
                        load_reg( R_ECX, Rn );
nkeynes@359
  1199
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1200
                        store_reg( R_ECX, Rn );
nkeynes@359
  1201
                        SETO_t();
nkeynes@417
  1202
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1203
                        }
nkeynes@359
  1204
                        break;
nkeynes@359
  1205
                    case 0xC:
nkeynes@359
  1206
                        { /* ADD Rm, Rn */
nkeynes@359
  1207
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1208
                        load_reg( R_EAX, Rm );
nkeynes@359
  1209
                        load_reg( R_ECX, Rn );
nkeynes@359
  1210
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1211
                        store_reg( R_ECX, Rn );
nkeynes@417
  1212
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1213
                        }
nkeynes@359
  1214
                        break;
nkeynes@359
  1215
                    case 0xD:
nkeynes@359
  1216
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1217
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1218
                        load_reg( R_EAX, Rm );
nkeynes@361
  1219
                        load_reg( R_ECX, Rn );
nkeynes@361
  1220
                        IMUL_r32(R_ECX);
nkeynes@361
  1221
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1222
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1223
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1224
                        }
nkeynes@359
  1225
                        break;
nkeynes@359
  1226
                    case 0xE:
nkeynes@359
  1227
                        { /* ADDC Rm, Rn */
nkeynes@359
  1228
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1229
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1230
                    	LDC_t();
nkeynes@417
  1231
                        }
nkeynes@359
  1232
                        load_reg( R_EAX, Rm );
nkeynes@359
  1233
                        load_reg( R_ECX, Rn );
nkeynes@359
  1234
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1235
                        store_reg( R_ECX, Rn );
nkeynes@359
  1236
                        SETC_t();
nkeynes@417
  1237
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1238
                        }
nkeynes@359
  1239
                        break;
nkeynes@359
  1240
                    case 0xF:
nkeynes@359
  1241
                        { /* ADDV Rm, Rn */
nkeynes@359
  1242
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1243
                        load_reg( R_EAX, Rm );
nkeynes@359
  1244
                        load_reg( R_ECX, Rn );
nkeynes@359
  1245
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1246
                        store_reg( R_ECX, Rn );
nkeynes@359
  1247
                        SETO_t();
nkeynes@417
  1248
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1249
                        }
nkeynes@359
  1250
                        break;
nkeynes@359
  1251
                    default:
nkeynes@359
  1252
                        UNDEF();
nkeynes@359
  1253
                        break;
nkeynes@359
  1254
                }
nkeynes@359
  1255
                break;
nkeynes@359
  1256
            case 0x4:
nkeynes@359
  1257
                switch( ir&0xF ) {
nkeynes@359
  1258
                    case 0x0:
nkeynes@359
  1259
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1260
                            case 0x0:
nkeynes@359
  1261
                                { /* SHLL Rn */
nkeynes@359
  1262
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1263
                                load_reg( R_EAX, Rn );
nkeynes@359
  1264
                                SHL1_r32( R_EAX );
nkeynes@397
  1265
                                SETC_t();
nkeynes@359
  1266
                                store_reg( R_EAX, Rn );
nkeynes@417
  1267
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1268
                                }
nkeynes@359
  1269
                                break;
nkeynes@359
  1270
                            case 0x1:
nkeynes@359
  1271
                                { /* DT Rn */
nkeynes@359
  1272
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1273
                                load_reg( R_EAX, Rn );
nkeynes@386
  1274
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1275
                                store_reg( R_EAX, Rn );
nkeynes@359
  1276
                                SETE_t();
nkeynes@417
  1277
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1278
                                }
nkeynes@359
  1279
                                break;
nkeynes@359
  1280
                            case 0x2:
nkeynes@359
  1281
                                { /* SHAL Rn */
nkeynes@359
  1282
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1283
                                load_reg( R_EAX, Rn );
nkeynes@359
  1284
                                SHL1_r32( R_EAX );
nkeynes@397
  1285
                                SETC_t();
nkeynes@359
  1286
                                store_reg( R_EAX, Rn );
nkeynes@417
  1287
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1288
                                }
nkeynes@359
  1289
                                break;
nkeynes@359
  1290
                            default:
nkeynes@359
  1291
                                UNDEF();
nkeynes@359
  1292
                                break;
nkeynes@359
  1293
                        }
nkeynes@359
  1294
                        break;
nkeynes@359
  1295
                    case 0x1:
nkeynes@359
  1296
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1297
                            case 0x0:
nkeynes@359
  1298
                                { /* SHLR Rn */
nkeynes@359
  1299
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1300
                                load_reg( R_EAX, Rn );
nkeynes@359
  1301
                                SHR1_r32( R_EAX );
nkeynes@397
  1302
                                SETC_t();
nkeynes@359
  1303
                                store_reg( R_EAX, Rn );
nkeynes@417
  1304
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1305
                                }
nkeynes@359
  1306
                                break;
nkeynes@359
  1307
                            case 0x1:
nkeynes@359
  1308
                                { /* CMP/PZ Rn */
nkeynes@359
  1309
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1310
                                load_reg( R_EAX, Rn );
nkeynes@359
  1311
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1312
                                SETGE_t();
nkeynes@417
  1313
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1314
                                }
nkeynes@359
  1315
                                break;
nkeynes@359
  1316
                            case 0x2:
nkeynes@359
  1317
                                { /* SHAR Rn */
nkeynes@359
  1318
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1319
                                load_reg( R_EAX, Rn );
nkeynes@359
  1320
                                SAR1_r32( R_EAX );
nkeynes@397
  1321
                                SETC_t();
nkeynes@359
  1322
                                store_reg( R_EAX, Rn );
nkeynes@417
  1323
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1324
                                }
nkeynes@359
  1325
                                break;
nkeynes@359
  1326
                            default:
nkeynes@359
  1327
                                UNDEF();
nkeynes@359
  1328
                                break;
nkeynes@359
  1329
                        }
nkeynes@359
  1330
                        break;
nkeynes@359
  1331
                    case 0x2:
nkeynes@359
  1332
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1333
                            case 0x0:
nkeynes@359
  1334
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1335
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1336
                                load_reg( R_EAX, Rn );
nkeynes@586
  1337
                                check_walign32( R_EAX );
nkeynes@586
  1338
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1339
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1340
                                load_spreg( R_EDX, R_MACH );
nkeynes@586
  1341
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1342
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1343
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1344
                                }
nkeynes@359
  1345
                                break;
nkeynes@359
  1346
                            case 0x1:
nkeynes@359
  1347
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1348
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1349
                                load_reg( R_EAX, Rn );
nkeynes@586
  1350
                                check_walign32( R_EAX );
nkeynes@586
  1351
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1352
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1353
                                load_spreg( R_EDX, R_MACL );
nkeynes@586
  1354
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1355
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1356
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1357
                                }
nkeynes@359
  1358
                                break;
nkeynes@359
  1359
                            case 0x2:
nkeynes@359
  1360
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1361
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1362
                                load_reg( R_EAX, Rn );
nkeynes@586
  1363
                                check_walign32( R_EAX );
nkeynes@586
  1364
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1365
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1366
                                load_spreg( R_EDX, R_PR );
nkeynes@586
  1367
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1368
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1369
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1370
                                }
nkeynes@359
  1371
                                break;
nkeynes@359
  1372
                            case 0x3:
nkeynes@359
  1373
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1374
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1375
                                check_priv();
nkeynes@586
  1376
                                load_reg( R_EAX, Rn );
nkeynes@586
  1377
                                check_walign32( R_EAX );
nkeynes@586
  1378
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1379
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1380
                                load_spreg( R_EDX, R_SGR );
nkeynes@586
  1381
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1382
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1383
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1384
                                }
nkeynes@359
  1385
                                break;
nkeynes@359
  1386
                            case 0x5:
nkeynes@359
  1387
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1388
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@626
  1389
                                check_fpuen();
nkeynes@586
  1390
                                load_reg( R_EAX, Rn );
nkeynes@586
  1391
                                check_walign32( R_EAX );
nkeynes@586
  1392
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1393
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1394
                                load_spreg( R_EDX, R_FPUL );
nkeynes@586
  1395
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1396
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1397
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1398
                                }
nkeynes@359
  1399
                                break;
nkeynes@359
  1400
                            case 0x6:
nkeynes@359
  1401
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1402
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@626
  1403
                                check_fpuen();
nkeynes@586
  1404
                                load_reg( R_EAX, Rn );
nkeynes@586
  1405
                                check_walign32( R_EAX );
nkeynes@586
  1406
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1407
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1408
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  1409
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1410
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1411
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1412
                                }
nkeynes@359
  1413
                                break;
nkeynes@359
  1414
                            case 0xF:
nkeynes@359
  1415
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1416
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1417
                                check_priv();
nkeynes@586
  1418
                                load_reg( R_EAX, Rn );
nkeynes@586
  1419
                                check_walign32( R_EAX );
nkeynes@586
  1420
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1421
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1422
                                load_spreg( R_EDX, R_DBR );
nkeynes@586
  1423
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1424
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1425
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1426
                                }
nkeynes@359
  1427
                                break;
nkeynes@359
  1428
                            default:
nkeynes@359
  1429
                                UNDEF();
nkeynes@359
  1430
                                break;
nkeynes@359
  1431
                        }
nkeynes@359
  1432
                        break;
nkeynes@359
  1433
                    case 0x3:
nkeynes@359
  1434
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1435
                            case 0x0:
nkeynes@359
  1436
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1437
                                    case 0x0:
nkeynes@359
  1438
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1439
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1440
                                        check_priv();
nkeynes@586
  1441
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1442
                                        check_walign32( R_EAX );
nkeynes@586
  1443
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1444
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1445
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1446
                                        call_func0( sh4_read_sr );
nkeynes@586
  1447
                                        POP_realigned_r32( R_ECX );
nkeynes@586
  1448
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1449
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1450
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1451
                                        }
nkeynes@359
  1452
                                        break;
nkeynes@359
  1453
                                    case 0x1:
nkeynes@359
  1454
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1455
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1456
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1457
                                        check_walign32( R_EAX );
nkeynes@586
  1458
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1459
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1460
                                        load_spreg( R_EDX, R_GBR );
nkeynes@586
  1461
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1462
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1463
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1464
                                        }
nkeynes@359
  1465
                                        break;
nkeynes@359
  1466
                                    case 0x2:
nkeynes@359
  1467
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1468
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1469
                                        check_priv();
nkeynes@586
  1470
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1471
                                        check_walign32( R_EAX );
nkeynes@586
  1472
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1473
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1474
                                        load_spreg( R_EDX, R_VBR );
nkeynes@586
  1475
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1476
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1477
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1478
                                        }
nkeynes@359
  1479
                                        break;
nkeynes@359
  1480
                                    case 0x3:
nkeynes@359
  1481
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1482
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1483
                                        check_priv();
nkeynes@586
  1484
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1485
                                        check_walign32( R_EAX );
nkeynes@586
  1486
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1487
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1488
                                        load_spreg( R_EDX, R_SSR );
nkeynes@586
  1489
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1490
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1491
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1492
                                        }
nkeynes@359
  1493
                                        break;
nkeynes@359
  1494
                                    case 0x4:
nkeynes@359
  1495
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1496
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1497
                                        check_priv();
nkeynes@586
  1498
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1499
                                        check_walign32( R_EAX );
nkeynes@586
  1500
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1501
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1502
                                        load_spreg( R_EDX, R_SPC );
nkeynes@586
  1503
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1504
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1505
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1506
                                        }
nkeynes@359
  1507
                                        break;
nkeynes@359
  1508
                                    default:
nkeynes@359
  1509
                                        UNDEF();
nkeynes@359
  1510
                                        break;
nkeynes@359
  1511
                                }
nkeynes@359
  1512
                                break;
nkeynes@359
  1513
                            case 0x1:
nkeynes@359
  1514
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1515
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1516
                                check_priv();
nkeynes@586
  1517
                                load_reg( R_EAX, Rn );
nkeynes@586
  1518
                                check_walign32( R_EAX );
nkeynes@586
  1519
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1520
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1521
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  1522
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1523
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1524
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1525
                                }
nkeynes@359
  1526
                                break;
nkeynes@359
  1527
                        }
nkeynes@359
  1528
                        break;
nkeynes@359
  1529
                    case 0x4:
nkeynes@359
  1530
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1531
                            case 0x0:
nkeynes@359
  1532
                                { /* ROTL Rn */
nkeynes@359
  1533
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1534
                                load_reg( R_EAX, Rn );
nkeynes@359
  1535
                                ROL1_r32( R_EAX );
nkeynes@359
  1536
                                store_reg( R_EAX, Rn );
nkeynes@359
  1537
                                SETC_t();
nkeynes@417
  1538
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1539
                                }
nkeynes@359
  1540
                                break;
nkeynes@359
  1541
                            case 0x2:
nkeynes@359
  1542
                                { /* ROTCL Rn */
nkeynes@359
  1543
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1544
                                load_reg( R_EAX, Rn );
nkeynes@417
  1545
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1546
                            	LDC_t();
nkeynes@417
  1547
                                }
nkeynes@359
  1548
                                RCL1_r32( R_EAX );
nkeynes@359
  1549
                                store_reg( R_EAX, Rn );
nkeynes@359
  1550
                                SETC_t();
nkeynes@417
  1551
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1552
                                }
nkeynes@359
  1553
                                break;
nkeynes@359
  1554
                            default:
nkeynes@359
  1555
                                UNDEF();
nkeynes@359
  1556
                                break;
nkeynes@359
  1557
                        }
nkeynes@359
  1558
                        break;
nkeynes@359
  1559
                    case 0x5:
nkeynes@359
  1560
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1561
                            case 0x0:
nkeynes@359
  1562
                                { /* ROTR Rn */
nkeynes@359
  1563
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1564
                                load_reg( R_EAX, Rn );
nkeynes@359
  1565
                                ROR1_r32( R_EAX );
nkeynes@359
  1566
                                store_reg( R_EAX, Rn );
nkeynes@359
  1567
                                SETC_t();
nkeynes@417
  1568
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1569
                                }
nkeynes@359
  1570
                                break;
nkeynes@359
  1571
                            case 0x1:
nkeynes@359
  1572
                                { /* CMP/PL Rn */
nkeynes@359
  1573
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1574
                                load_reg( R_EAX, Rn );
nkeynes@359
  1575
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1576
                                SETG_t();
nkeynes@417
  1577
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1578
                                }
nkeynes@359
  1579
                                break;
nkeynes@359
  1580
                            case 0x2:
nkeynes@359
  1581
                                { /* ROTCR Rn */
nkeynes@359
  1582
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1583
                                load_reg( R_EAX, Rn );
nkeynes@417
  1584
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1585
                            	LDC_t();
nkeynes@417
  1586
                                }
nkeynes@359
  1587
                                RCR1_r32( R_EAX );
nkeynes@359
  1588
                                store_reg( R_EAX, Rn );
nkeynes@359
  1589
                                SETC_t();
nkeynes@417
  1590
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1591
                                }
nkeynes@359
  1592
                                break;
nkeynes@359
  1593
                            default:
nkeynes@359
  1594
                                UNDEF();
nkeynes@359
  1595
                                break;
nkeynes@359
  1596
                        }
nkeynes@359
  1597
                        break;
nkeynes@359
  1598
                    case 0x6:
nkeynes@359
  1599
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1600
                            case 0x0:
nkeynes@359
  1601
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1602
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1603
                                load_reg( R_EAX, Rm );
nkeynes@395
  1604
                                check_ralign32( R_EAX );
nkeynes@586
  1605
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1606
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1607
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1608
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1609
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1610
                                }
nkeynes@359
  1611
                                break;
nkeynes@359
  1612
                            case 0x1:
nkeynes@359
  1613
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1614
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1615
                                load_reg( R_EAX, Rm );
nkeynes@395
  1616
                                check_ralign32( R_EAX );
nkeynes@586
  1617
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1618
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1619
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1620
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1621
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1622
                                }
nkeynes@359
  1623
                                break;
nkeynes@359
  1624
                            case 0x2:
nkeynes@359
  1625
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1626
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1627
                                load_reg( R_EAX, Rm );
nkeynes@395
  1628
                                check_ralign32( R_EAX );
nkeynes@586
  1629
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1630
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1631
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1632
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1633
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1634
                                }
nkeynes@359
  1635
                                break;
nkeynes@359
  1636
                            case 0x3:
nkeynes@359
  1637
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1638
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1639
                                check_priv();
nkeynes@359
  1640
                                load_reg( R_EAX, Rm );
nkeynes@395
  1641
                                check_ralign32( R_EAX );
nkeynes@586
  1642
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1643
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1644
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1645
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1646
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1647
                                }
nkeynes@359
  1648
                                break;
nkeynes@359
  1649
                            case 0x5:
nkeynes@359
  1650
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1651
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@626
  1652
                                check_fpuen();
nkeynes@359
  1653
                                load_reg( R_EAX, Rm );
nkeynes@395
  1654
                                check_ralign32( R_EAX );
nkeynes@586
  1655
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1656
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1657
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1658
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1659
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1660
                                }
nkeynes@359
  1661
                                break;
nkeynes@359
  1662
                            case 0x6:
nkeynes@359
  1663
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1664
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@626
  1665
                                check_fpuen();
nkeynes@359
  1666
                                load_reg( R_EAX, Rm );
nkeynes@395
  1667
                                check_ralign32( R_EAX );
nkeynes@586
  1668
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1669
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1670
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1671
                                call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  1672
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1673
                                }
nkeynes@359
  1674
                                break;
nkeynes@359
  1675
                            case 0xF:
nkeynes@359
  1676
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1677
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1678
                                check_priv();
nkeynes@359
  1679
                                load_reg( R_EAX, Rm );
nkeynes@395
  1680
                                check_ralign32( R_EAX );
nkeynes@586
  1681
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1682
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1683
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1684
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1685
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1686
                                }
nkeynes@359
  1687
                                break;
nkeynes@359
  1688
                            default:
nkeynes@359
  1689
                                UNDEF();
nkeynes@359
  1690
                                break;
nkeynes@359
  1691
                        }
nkeynes@359
  1692
                        break;
nkeynes@359
  1693
                    case 0x7:
nkeynes@359
  1694
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1695
                            case 0x0:
nkeynes@359
  1696
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1697
                                    case 0x0:
nkeynes@359
  1698
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1699
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1700
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1701
                                    	SLOTILLEGAL();
nkeynes@386
  1702
                                        } else {
nkeynes@586
  1703
                                    	check_priv();
nkeynes@386
  1704
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1705
                                    	check_ralign32( R_EAX );
nkeynes@586
  1706
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1707
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1708
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1709
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1710
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1711
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1712
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1713
                                        }
nkeynes@359
  1714
                                        }
nkeynes@359
  1715
                                        break;
nkeynes@359
  1716
                                    case 0x1:
nkeynes@359
  1717
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1718
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1719
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1720
                                        check_ralign32( R_EAX );
nkeynes@586
  1721
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1722
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1723
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1724
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1725
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1726
                                        }
nkeynes@359
  1727
                                        break;
nkeynes@359
  1728
                                    case 0x2:
nkeynes@359
  1729
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1730
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1731
                                        check_priv();
nkeynes@359
  1732
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1733
                                        check_ralign32( R_EAX );
nkeynes@586
  1734
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1735
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1736
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1737
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1738
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1739
                                        }
nkeynes@359
  1740
                                        break;
nkeynes@359
  1741
                                    case 0x3:
nkeynes@359
  1742
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1743
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1744
                                        check_priv();
nkeynes@359
  1745
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1746
                                        check_ralign32( R_EAX );
nkeynes@586
  1747
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1748
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1749
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1750
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1751
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1752
                                        }
nkeynes@359
  1753
                                        break;
nkeynes@359
  1754
                                    case 0x4:
nkeynes@359
  1755
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1756
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1757
                                        check_priv();
nkeynes@359
  1758
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1759
                                        check_ralign32( R_EAX );
nkeynes@586
  1760
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1761
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1762
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1763
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1764
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1765
                                        }
nkeynes@359
  1766
                                        break;
nkeynes@359
  1767
                                    default:
nkeynes@359
  1768
                                        UNDEF();
nkeynes@359
  1769
                                        break;
nkeynes@359
  1770
                                }
nkeynes@359
  1771
                                break;
nkeynes@359
  1772
                            case 0x1:
nkeynes@359
  1773
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1774
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1775
                                check_priv();
nkeynes@374
  1776
                                load_reg( R_EAX, Rm );
nkeynes@395
  1777
                                check_ralign32( R_EAX );
nkeynes@586
  1778
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1779
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1780
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1781
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1782
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1783
                                }
nkeynes@359
  1784
                                break;
nkeynes@359
  1785
                        }
nkeynes@359
  1786
                        break;
nkeynes@359
  1787
                    case 0x8:
nkeynes@359
  1788
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1789
                            case 0x0:
nkeynes@359
  1790
                                { /* SHLL2 Rn */
nkeynes@359
  1791
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1792
                                load_reg( R_EAX, Rn );
nkeynes@359
  1793
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1794
                                store_reg( R_EAX, Rn );
nkeynes@417
  1795
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1796
                                }
nkeynes@359
  1797
                                break;
nkeynes@359
  1798
                            case 0x1:
nkeynes@359
  1799
                                { /* SHLL8 Rn */
nkeynes@359
  1800
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1801
                                load_reg( R_EAX, Rn );
nkeynes@359
  1802
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1803
                                store_reg( R_EAX, Rn );
nkeynes@417
  1804
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1805
                                }
nkeynes@359
  1806
                                break;
nkeynes@359
  1807
                            case 0x2:
nkeynes@359
  1808
                                { /* SHLL16 Rn */
nkeynes@359
  1809
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1810
                                load_reg( R_EAX, Rn );
nkeynes@359
  1811
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1812
                                store_reg( R_EAX, Rn );
nkeynes@417
  1813
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1814
                                }
nkeynes@359
  1815
                                break;
nkeynes@359
  1816
                            default:
nkeynes@359
  1817
                                UNDEF();
nkeynes@359
  1818
                                break;
nkeynes@359
  1819
                        }
nkeynes@359
  1820
                        break;
nkeynes@359
  1821
                    case 0x9:
nkeynes@359
  1822
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1823
                            case 0x0:
nkeynes@359
  1824
                                { /* SHLR2 Rn */
nkeynes@359
  1825
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1826
                                load_reg( R_EAX, Rn );
nkeynes@359
  1827
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1828
                                store_reg( R_EAX, Rn );
nkeynes@417
  1829
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1830
                                }
nkeynes@359
  1831
                                break;
nkeynes@359
  1832
                            case 0x1:
nkeynes@359
  1833
                                { /* SHLR8 Rn */
nkeynes@359
  1834
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1835
                                load_reg( R_EAX, Rn );
nkeynes@359
  1836
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1837
                                store_reg( R_EAX, Rn );
nkeynes@417
  1838
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1839
                                }
nkeynes@359
  1840
                                break;
nkeynes@359
  1841
                            case 0x2:
nkeynes@359
  1842
                                { /* SHLR16 Rn */
nkeynes@359
  1843
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1844
                                load_reg( R_EAX, Rn );
nkeynes@359
  1845
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1846
                                store_reg( R_EAX, Rn );
nkeynes@417
  1847
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1848
                                }
nkeynes@359
  1849
                                break;
nkeynes@359
  1850
                            default:
nkeynes@359
  1851
                                UNDEF();
nkeynes@359
  1852
                                break;
nkeynes@359
  1853
                        }
nkeynes@359
  1854
                        break;
nkeynes@359
  1855
                    case 0xA:
nkeynes@359
  1856
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1857
                            case 0x0:
nkeynes@359
  1858
                                { /* LDS Rm, MACH */
nkeynes@359
  1859
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1860
                                load_reg( R_EAX, Rm );
nkeynes@359
  1861
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1862
                                }
nkeynes@359
  1863
                                break;
nkeynes@359
  1864
                            case 0x1:
nkeynes@359
  1865
                                { /* LDS Rm, MACL */
nkeynes@359
  1866
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1867
                                load_reg( R_EAX, Rm );
nkeynes@359
  1868
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1869
                                }
nkeynes@359
  1870
                                break;
nkeynes@359
  1871
                            case 0x2:
nkeynes@359
  1872
                                { /* LDS Rm, PR */
nkeynes@359
  1873
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1874
                                load_reg( R_EAX, Rm );
nkeynes@359
  1875
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1876
                                }
nkeynes@359
  1877
                                break;
nkeynes@359
  1878
                            case 0x3:
nkeynes@359
  1879
                                { /* LDC Rm, SGR */
nkeynes@359
  1880
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1881
                                check_priv();
nkeynes@359
  1882
                                load_reg( R_EAX, Rm );
nkeynes@359
  1883
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1884
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1885
                                }
nkeynes@359
  1886
                                break;
nkeynes@359
  1887
                            case 0x5:
nkeynes@359
  1888
                                { /* LDS Rm, FPUL */
nkeynes@359
  1889
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@626
  1890
                                check_fpuen();
nkeynes@359
  1891
                                load_reg( R_EAX, Rm );
nkeynes@359
  1892
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1893
                                }
nkeynes@359
  1894
                                break;
nkeynes@359
  1895
                            case 0x6:
nkeynes@359
  1896
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1897
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@626
  1898
                                check_fpuen();
nkeynes@359
  1899
                                load_reg( R_EAX, Rm );
nkeynes@669
  1900
                                call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  1901
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1902
                                }
nkeynes@359
  1903
                                break;
nkeynes@359
  1904
                            case 0xF:
nkeynes@359
  1905
                                { /* LDC Rm, DBR */
nkeynes@359
  1906
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1907
                                check_priv();
nkeynes@359
  1908
                                load_reg( R_EAX, Rm );
nkeynes@359
  1909
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1910
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1911
                                }
nkeynes@359
  1912
                                break;
nkeynes@359
  1913
                            default:
nkeynes@359
  1914
                                UNDEF();
nkeynes@359
  1915
                                break;
nkeynes@359
  1916
                        }
nkeynes@359
  1917
                        break;
nkeynes@359
  1918
                    case 0xB:
nkeynes@359
  1919
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1920
                            case 0x0:
nkeynes@359
  1921
                                { /* JSR @Rn */
nkeynes@359
  1922
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1923
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1924
                            	SLOTILLEGAL();
nkeynes@374
  1925
                                } else {
nkeynes@590
  1926
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
  1927
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1928
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1929
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1930
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1931
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1932
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1933
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1934
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1935
                            	    exit_block_emu(pc+2);
nkeynes@601
  1936
                            	    return 2;
nkeynes@601
  1937
                            	} else {
nkeynes@601
  1938
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  1939
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  1940
                            	    return 4;
nkeynes@601
  1941
                            	}
nkeynes@374
  1942
                                }
nkeynes@359
  1943
                                }
nkeynes@359
  1944
                                break;
nkeynes@359
  1945
                            case 0x1:
nkeynes@359
  1946
                                { /* TAS.B @Rn */
nkeynes@359
  1947
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1948
                                load_reg( R_EAX, Rn );
nkeynes@586
  1949
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1950
                                PUSH_realigned_r32( R_EAX );
nkeynes@586
  1951
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1952
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1953
                                SETE_t();
nkeynes@361
  1954
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1955
                                POP_realigned_r32( R_ECX );
nkeynes@361
  1956
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1957
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1958
                                }
nkeynes@359
  1959
                                break;
nkeynes@359
  1960
                            case 0x2:
nkeynes@359
  1961
                                { /* JMP @Rn */
nkeynes@359
  1962
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1963
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1964
                            	SLOTILLEGAL();
nkeynes@374
  1965
                                } else {
nkeynes@408
  1966
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1967
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1968
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1969
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1970
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1971
                            	    exit_block_emu(pc+2);
nkeynes@601
  1972
                            	    return 2;
nkeynes@601
  1973
                            	} else {
nkeynes@601
  1974
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  1975
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  1976
                            	    return 4;
nkeynes@601
  1977
                            	}
nkeynes@374
  1978
                                }
nkeynes@359
  1979
                                }
nkeynes@359
  1980
                                break;
nkeynes@359
  1981
                            default:
nkeynes@359
  1982
                                UNDEF();
nkeynes@359
  1983
                                break;
nkeynes@359
  1984
                        }
nkeynes@359
  1985
                        break;
nkeynes@359
  1986
                    case 0xC:
nkeynes@359
  1987
                        { /* SHAD Rm, Rn */
nkeynes@359
  1988
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1989
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1990
                        load_reg( R_EAX, Rn );
nkeynes@361
  1991
                        load_reg( R_ECX, Rm );
nkeynes@361
  1992
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@669
  1993
                        JGE_rel8(doshl);
nkeynes@361
  1994
                                        
nkeynes@361
  1995
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1996
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
  1997
                        JE_rel8(emptysar);     // 2
nkeynes@361
  1998
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@669
  1999
                        JMP_rel8(end);          // 2
nkeynes@386
  2000
                    
nkeynes@386
  2001
                        JMP_TARGET(emptysar);
nkeynes@386
  2002
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
  2003
                        JMP_rel8(end2);
nkeynes@386
  2004
                    
nkeynes@380
  2005
                        JMP_TARGET(doshl);
nkeynes@361
  2006
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2007
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2008
                        JMP_TARGET(end);
nkeynes@386
  2009
                        JMP_TARGET(end2);
nkeynes@361
  2010
                        store_reg( R_EAX, Rn );
nkeynes@417
  2011
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2012
                        }
nkeynes@359
  2013
                        break;
nkeynes@359
  2014
                    case 0xD:
nkeynes@359
  2015
                        { /* SHLD Rm, Rn */
nkeynes@359
  2016
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2017
                        load_reg( R_EAX, Rn );
nkeynes@368
  2018
                        load_reg( R_ECX, Rm );
nkeynes@386
  2019
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@669
  2020
                        JGE_rel8(doshl);
nkeynes@368
  2021
                    
nkeynes@386
  2022
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2023
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
  2024
                        JE_rel8(emptyshr );
nkeynes@386
  2025
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@669
  2026
                        JMP_rel8(end);          // 2
nkeynes@386
  2027
                    
nkeynes@386
  2028
                        JMP_TARGET(emptyshr);
nkeynes@386
  2029
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  2030
                        JMP_rel8(end2);
nkeynes@386
  2031
                    
nkeynes@386
  2032
                        JMP_TARGET(doshl);
nkeynes@386
  2033
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2034
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2035
                        JMP_TARGET(end);
nkeynes@386
  2036
                        JMP_TARGET(end2);
nkeynes@368
  2037
                        store_reg( R_EAX, Rn );
nkeynes@417
  2038
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2039
                        }
nkeynes@359
  2040
                        break;
nkeynes@359
  2041
                    case 0xE:
nkeynes@359
  2042
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2043
                            case 0x0:
nkeynes@359
  2044
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2045
                                    case 0x0:
nkeynes@359
  2046
                                        { /* LDC Rm, SR */
nkeynes@359
  2047
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2048
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2049
                                    	SLOTILLEGAL();
nkeynes@386
  2050
                                        } else {
nkeynes@386
  2051
                                    	check_priv();
nkeynes@386
  2052
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2053
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2054
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2055
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2056
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2057
                                        }
nkeynes@359
  2058
                                        }
nkeynes@359
  2059
                                        break;
nkeynes@359
  2060
                                    case 0x1:
nkeynes@359
  2061
                                        { /* LDC Rm, GBR */
nkeynes@359
  2062
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2063
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2064
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2065
                                        }
nkeynes@359
  2066
                                        break;
nkeynes@359
  2067
                                    case 0x2:
nkeynes@359
  2068
                                        { /* LDC Rm, VBR */
nkeynes@359
  2069
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2070
                                        check_priv();
nkeynes@359
  2071
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2072
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2073
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2074
                                        }
nkeynes@359
  2075
                                        break;
nkeynes@359
  2076
                                    case 0x3:
nkeynes@359
  2077
                                        { /* LDC Rm, SSR */
nkeynes@359
  2078
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2079
                                        check_priv();
nkeynes@359
  2080
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2081
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2082
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2083
                                        }
nkeynes@359
  2084
                                        break;
nkeynes@359
  2085
                                    case 0x4:
nkeynes@359
  2086
                                        { /* LDC Rm, SPC */
nkeynes@359
  2087
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2088
                                        check_priv();
nkeynes@359
  2089
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2090
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2091
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2092
                                        }
nkeynes@359
  2093
                                        break;
nkeynes@359
  2094
                                    default:
nkeynes@359
  2095
                                        UNDEF();
nkeynes@359
  2096
                                        break;
nkeynes@359
  2097
                                }
nkeynes@359
  2098
                                break;
nkeynes@359
  2099
                            case 0x1:
nkeynes@359
  2100
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2101
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2102
                                check_priv();
nkeynes@374
  2103
                                load_reg( R_EAX, Rm );
nkeynes@374
  2104
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2105
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2106
                                }
nkeynes@359
  2107
                                break;
nkeynes@359
  2108
                        }
nkeynes@359
  2109
                        break;
nkeynes@359
  2110
                    case 0xF:
nkeynes@359
  2111
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2112
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2113
                        if( Rm == Rn ) {
nkeynes@586
  2114
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2115
                    	check_ralign16( R_EAX );
nkeynes@586
  2116
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2117
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2118
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2119
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
  2120
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
  2121
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2122
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  2123
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
  2124
                        } else {
nkeynes@586
  2125
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2126
                    	check_ralign16( R_EAX );
nkeynes@586
  2127
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
  2128
                    	load_reg( R_ECX, Rn );
nkeynes@596
  2129
                    	check_ralign16( R_ECX );
nkeynes@586
  2130
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
  2131
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
  2132
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2133
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
  2134
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2135
                        }
nkeynes@586
  2136
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2137
                        POP_r32( R_ECX );
nkeynes@586
  2138
                        PUSH_r32( R_EAX );
nkeynes@386
  2139
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2140
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2141
                        IMUL_r32( R_ECX );
nkeynes@386
  2142
                    
nkeynes@386
  2143
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2144
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
  2145
                        JE_rel8( nosat );
nkeynes@386
  2146
                    
nkeynes@386
  2147
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
  2148
                        JNO_rel8( end );            // 2
nkeynes@386
  2149
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2150
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
  2151
                        JS_rel8( positive );        // 2
nkeynes@386
  2152
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2153
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
  2154
                        JMP_rel8(end2);           // 2
nkeynes@386
  2155
                    
nkeynes@386
  2156
                        JMP_TARGET(positive);
nkeynes@386
  2157
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2158
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
  2159
                        JMP_rel8(end3);            // 2
nkeynes@386
  2160
                    
nkeynes@386
  2161
                        JMP_TARGET(nosat);
nkeynes@386
  2162
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2163
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2164
                        JMP_TARGET(end);
nkeynes@386
  2165
                        JMP_TARGET(end2);
nkeynes@386
  2166
                        JMP_TARGET(end3);
nkeynes@417
  2167
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2168
                        }
nkeynes@359
  2169
                        break;
nkeynes@359
  2170
                }
nkeynes@359
  2171
                break;
nkeynes@359
  2172
            case 0x5:
nkeynes@359
  2173
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2174
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
  2175
                load_reg( R_EAX, Rm );
nkeynes@586
  2176
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  2177
                check_ralign32( R_EAX );
nkeynes@586
  2178
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2179
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2180
                store_reg( R_EAX, Rn );
nkeynes@417
  2181
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2182
                }
nkeynes@359
  2183
                break;
nkeynes@359
  2184
            case 0x6:
nkeynes@359
  2185
                switch( ir&0xF ) {
nkeynes@359
  2186
                    case 0x0:
nkeynes@359
  2187
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2188
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2189
                        load_reg( R_EAX, Rm );
nkeynes@586
  2190
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2191
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2192
                        store_reg( R_EAX, Rn );
nkeynes@417
  2193
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2194
                        }
nkeynes@359
  2195
                        break;
nkeynes@359
  2196
                    case 0x1:
nkeynes@359
  2197
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2198
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2199
                        load_reg( R_EAX, Rm );
nkeynes@586
  2200
                        check_ralign16( R_EAX );
nkeynes@586
  2201
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2202
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2203
                        store_reg( R_EAX, Rn );
nkeynes@417
  2204
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2205
                        }
nkeynes@359
  2206
                        break;
nkeynes@359
  2207
                    case 0x2:
nkeynes@359
  2208
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2209
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2210
                        load_reg( R_EAX, Rm );
nkeynes@586
  2211
                        check_ralign32( R_EAX );
nkeynes@586
  2212
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2213
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2214
                        store_reg( R_EAX, Rn );
nkeynes@417
  2215
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2216
                        }
nkeynes@359
  2217
                        break;
nkeynes@359
  2218
                    case 0x3:
nkeynes@359
  2219
                        { /* MOV Rm, Rn */
nkeynes@359
  2220
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2221
                        load_reg( R_EAX, Rm );
nkeynes@359
  2222
                        store_reg( R_EAX, Rn );
nkeynes@359
  2223
                        }
nkeynes@359
  2224
                        break;
nkeynes@359
  2225
                    case 0x4:
nkeynes@359
  2226
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2227
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2228
                        load_reg( R_EAX, Rm );
nkeynes@586
  2229
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2230
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  2231
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2232
                        store_reg( R_EAX, Rn );
nkeynes@417
  2233
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2234
                        }
nkeynes@359
  2235
                        break;
nkeynes@359
  2236
                    case 0x5:
nkeynes@359
  2237
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2238
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2239
                        load_reg( R_EAX, Rm );
nkeynes@374
  2240
                        check_ralign16( R_EAX );
nkeynes@586
  2241
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2242
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2243
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2244
                        store_reg( R_EAX, Rn );
nkeynes@417
  2245
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2246
                        }
nkeynes@359
  2247
                        break;
nkeynes@359
  2248
                    case 0x6:
nkeynes@359
  2249
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2250
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2251
                        load_reg( R_EAX, Rm );
nkeynes@386
  2252
                        check_ralign32( R_EAX );
nkeynes@586
  2253
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2254
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2255
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2256
                        store_reg( R_EAX, Rn );
nkeynes@417
  2257
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2258
                        }
nkeynes@359
  2259
                        break;
nkeynes@359
  2260
                    case 0x7:
nkeynes@359
  2261
                        { /* NOT Rm, Rn */
nkeynes@359
  2262
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2263
                        load_reg( R_EAX, Rm );
nkeynes@359
  2264
                        NOT_r32( R_EAX );
nkeynes@359
  2265
                        store_reg( R_EAX, Rn );
nkeynes@417
  2266
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2267
                        }
nkeynes@359
  2268
                        break;
nkeynes@359
  2269
                    case 0x8:
nkeynes@359
  2270
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2271
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2272
                        load_reg( R_EAX, Rm );
nkeynes@601
  2273
                        XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  2274
                        store_reg( R_EAX, Rn );
nkeynes@359
  2275
                        }
nkeynes@359
  2276
                        break;
nkeynes@359
  2277
                    case 0x9:
nkeynes@359
  2278
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2279
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2280
                        load_reg( R_EAX, Rm );
nkeynes@359
  2281
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2282
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2283
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2284
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2285
                        store_reg( R_ECX, Rn );
nkeynes@417
  2286
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2287
                        }
nkeynes@359
  2288
                        break;
nkeynes@359
  2289
                    case 0xA:
nkeynes@359
  2290
                        { /* NEGC Rm, Rn */
nkeynes@359
  2291
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2292
                        load_reg( R_EAX, Rm );
nkeynes@359
  2293
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2294
                        LDC_t();
nkeynes@359
  2295
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2296
                        store_reg( R_ECX, Rn );
nkeynes@359
  2297
                        SETC_t();
nkeynes@417
  2298
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2299
                        }
nkeynes@359
  2300
                        break;
nkeynes@359
  2301
                    case 0xB:
nkeynes@359
  2302
                        { /* NEG Rm, Rn */
nkeynes@359
  2303
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2304
                        load_reg( R_EAX, Rm );
nkeynes@359
  2305
                        NEG_r32( R_EAX );
nkeynes@359
  2306
                        store_reg( R_EAX, Rn );
nkeynes@417
  2307
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
                        }
nkeynes@359
  2309
                        break;
nkeynes@359
  2310
                    case 0xC:
nkeynes@359
  2311
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2312
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2313
                        load_reg( R_EAX, Rm );
nkeynes@361
  2314
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2315
                        store_reg( R_EAX, Rn );
nkeynes@359
  2316
                        }
nkeynes@359
  2317
                        break;
nkeynes@359
  2318
                    case 0xD:
nkeynes@359
  2319
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2320
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2321
                        load_reg( R_EAX, Rm );
nkeynes@361
  2322
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2323
                        store_reg( R_EAX, Rn );
nkeynes@359
  2324
                        }
nkeynes@359
  2325
                        break;
nkeynes@359
  2326
                    case 0xE:
nkeynes@359
  2327
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2328
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2329
                        load_reg( R_EAX, Rm );
nkeynes@359
  2330
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2331
                        store_reg( R_EAX, Rn );
nkeynes@359
  2332
                        }
nkeynes@359
  2333
                        break;
nkeynes@359
  2334
                    case 0xF:
nkeynes@359
  2335
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2336
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2337
                        load_reg( R_EAX, Rm );
nkeynes@361
  2338
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2339
                        store_reg( R_EAX, Rn );
nkeynes@359
  2340
                        }
nkeynes@359
  2341
                        break;
nkeynes@359
  2342
                }
nkeynes@359
  2343
                break;
nkeynes@359
  2344
            case 0x7:
nkeynes@359
  2345
                { /* ADD #imm, Rn */
nkeynes@359
  2346
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2347
                load_reg( R_EAX, Rn );
nkeynes@359
  2348
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2349
                store_reg( R_EAX, Rn );
nkeynes@417
  2350
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2351
                }
nkeynes@359
  2352
                break;
nkeynes@359
  2353
            case 0x8:
nkeynes@359
  2354
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2355
                    case 0x0:
nkeynes@359
  2356
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2357
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2358
                        load_reg( R_EAX, Rn );
nkeynes@586
  2359
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2360
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2361
                        load_reg( R_EDX, 0 );
nkeynes@586
  2362
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2363
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2364
                        }
nkeynes@359
  2365
                        break;
nkeynes@359
  2366
                    case 0x1:
nkeynes@359
  2367
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2368
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2369
                        load_reg( R_EAX, Rn );
nkeynes@586
  2370
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2371
                        check_walign16( R_EAX );
nkeynes@586
  2372
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2373
                        load_reg( R_EDX, 0 );
nkeynes@586
  2374
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2375
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2376
                        }
nkeynes@359
  2377
                        break;
nkeynes@359
  2378
                    case 0x4:
nkeynes@359
  2379
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2380
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2381
                        load_reg( R_EAX, Rm );
nkeynes@586
  2382
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2383
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2384
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2385
                        store_reg( R_EAX, 0 );
nkeynes@417
  2386
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
                        }
nkeynes@359
  2388
                        break;
nkeynes@359
  2389
                    case 0x5:
nkeynes@359
  2390
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2391
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2392
                        load_reg( R_EAX, Rm );
nkeynes@586
  2393
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2394
                        check_ralign16( R_EAX );
nkeynes@586
  2395
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2396
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2397
                        store_reg( R_EAX, 0 );
nkeynes@417
  2398
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2399
                        }
nkeynes@359
  2400
                        break;
nkeynes@359
  2401
                    case 0x8:
nkeynes@359
  2402
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2403
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2404
                        load_reg( R_EAX, 0 );
nkeynes@359
  2405
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2406
                        SETE_t();
nkeynes@417
  2407
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2408
                        }
nkeynes@359
  2409
                        break;
nkeynes@359
  2410
                    case 0x9:
nkeynes@359
  2411
                        { /* BT disp */
nkeynes@359
  2412
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2413
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2414
                    	SLOTILLEGAL();
nkeynes@374
  2415
                        } else {
nkeynes@586
  2416
                    	sh4vma_t target = disp + pc + 4;
nkeynes@669
  2417
                    	JF_rel8( nottaken );
nkeynes@586
  2418
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2419
                    	JMP_TARGET(nottaken);
nkeynes@408
  2420
                    	return 2;
nkeynes@374
  2421
                        }
nkeynes@359
  2422
                        }
nkeynes@359
  2423
                        break;
nkeynes@359
  2424
                    case 0xB:
nkeynes@359
  2425
                        { /* BF disp */
nkeynes@359
  2426
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2427
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2428
                    	SLOTILLEGAL();
nkeynes@374
  2429
                        } else {
nkeynes@586
  2430
                    	sh4vma_t target = disp + pc + 4;
nkeynes@669
  2431
                    	JT_rel8( nottaken );
nkeynes@586
  2432
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2433
                    	JMP_TARGET(nottaken);
nkeynes@408
  2434
                    	return 2;
nkeynes@374
  2435
                        }
nkeynes@359
  2436
                        }
nkeynes@359
  2437
                        break;
nkeynes@359
  2438
                    case 0xD:
nkeynes@359
  2439
                        { /* BT/S disp */
nkeynes@359
  2440
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2441
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2442
                    	SLOTILLEGAL();
nkeynes@374
  2443
                        } else {
nkeynes@590
  2444
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2445
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2446
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  2447
                    	    JF_rel8(nottaken);
nkeynes@601
  2448
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2449
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2450
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2451
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2452
                    	    exit_block_emu(pc+2);
nkeynes@601
  2453
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2454
                    	    return 2;
nkeynes@601
  2455
                    	} else {
nkeynes@601
  2456
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2457
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2458
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2459
                    	    }
nkeynes@601
  2460
                    	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  2461
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2462
                    	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2463
                    	    // not taken
nkeynes@601
  2464
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2465
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2466
                    	    return 4;
nkeynes@417
  2467
                    	}
nkeynes@374
  2468
                        }
nkeynes@359
  2469
                        }
nkeynes@359
  2470
                        break;
nkeynes@359
  2471
                    case 0xF:
nkeynes@359
  2472
                        { /* BF/S disp */
nkeynes@359
  2473
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2474
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2475
                    	SLOTILLEGAL();
nkeynes@374
  2476
                        } else {
nkeynes@590
  2477
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2478
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2479
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  2480
                    	    JT_rel8(nottaken);
nkeynes@601
  2481
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2482
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2483
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2484
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2485
                    	    exit_block_emu(pc+2);
nkeynes@601
  2486
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2487
                    	    return 2;
nkeynes@601
  2488
                    	} else {
nkeynes@601
  2489
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2490
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2491
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2492
                    	    }
nkeynes@601
  2493
                    	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  2494
                    	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  2495
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2496
                    	    exit_block_rel( target, pc+4 );
nkeynes@601
  2497
                    	    
nkeynes@601
  2498
                    	    // not taken
nkeynes@601
  2499
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2500
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2501
                    	    return 4;
nkeynes@417
  2502
                    	}
nkeynes@374
  2503
                        }
nkeynes@359
  2504
                        }
nkeynes@359
  2505
                        break;
nkeynes@359
  2506
                    default:
nkeynes@359
  2507
                        UNDEF();
nkeynes@359
  2508
                        break;
nkeynes@359
  2509
                }
nkeynes@359
  2510
                break;
nkeynes@359
  2511
            case 0x9:
nkeynes@359
  2512
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2513
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2514
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2515
            	SLOTILLEGAL();
nkeynes@374
  2516
                } else {
nkeynes@586
  2517
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  2518
            	uint32_t target = pc + disp + 4;
nkeynes@586
  2519
            	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  2520
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  2521
            	    MOV_moff32_EAX( ptr );
nkeynes@586
  2522
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  2523
            	} else {
nkeynes@586
  2524
            	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  2525
            	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  2526
            	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2527
            	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2528
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  2529
            	}
nkeynes@374
  2530
            	store_reg( R_EAX, Rn );
nkeynes@374
  2531
                }
nkeynes@359
  2532
                }
nkeynes@359
  2533
                break;
nkeynes@359
  2534
            case 0xA:
nkeynes@359
  2535
                { /* BRA disp */
nkeynes@359
  2536
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2537
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2538
            	SLOTILLEGAL();
nkeynes@374
  2539
                } else {
nkeynes@590
  2540
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2541
            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2542
            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2543
            	    load_spreg( R_EAX, R_PC );
nkeynes@601
  2544
            	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  2545
            	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2546
            	    exit_block_emu(pc+2);
nkeynes@601
  2547
            	    return 2;
nkeynes@601
  2548
            	} else {
nkeynes@601
  2549
            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2550
            	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2551
            	    return 4;
nkeynes@601
  2552
            	}
nkeynes@374
  2553
                }
nkeynes@359
  2554
                }
nkeynes@359
  2555
                break;
nkeynes@359
  2556
            case 0xB:
nkeynes@359
  2557
                { /* BSR disp */
nkeynes@359
  2558
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2559
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2560
            	SLOTILLEGAL();
nkeynes@374
  2561
                } else {
nkeynes@590
  2562
            	load_spreg( R_EAX, R_PC );
nkeynes@590
  2563
            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  2564
            	store_spreg( R_EAX, R_PR );
nkeynes@590
  2565
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2566
            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2567
            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2568
            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2569
            	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2570
            	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2571
            	    exit_block_emu(pc+2);
nkeynes@601
  2572
            	    return 2;
nkeynes@601
  2573
            	} else {
nkeynes@601
  2574
            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2575
            	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2576
            	    return 4;
nkeynes@601
  2577
            	}
nkeynes@374
  2578
                }
nkeynes@359
  2579
                }
nkeynes@359
  2580
                break;
nkeynes@359
  2581
            case 0xC:
nkeynes@359
  2582
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2583
                    case 0x0:
nkeynes@359
  2584
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2585
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2586
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2587
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2588
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2589
                        load_reg( R_EDX, 0 );
nkeynes@586
  2590
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2591
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2592
                        }
nkeynes@359
  2593
                        break;
nkeynes@359
  2594
                    case 0x1:
nkeynes@359
  2595
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2596
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2597
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2598
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2599
                        check_walign16( R_EAX );
nkeynes@586
  2600
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2601
                        load_reg( R_EDX, 0 );
nkeynes@586
  2602
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2603
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2604
                        }
nkeynes@359
  2605
                        break;
nkeynes@359
  2606
                    case 0x2:
nkeynes@359
  2607
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2608
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2609
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2610
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2611
                        check_walign32( R_EAX );
nkeynes@586
  2612
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2613
                        load_reg( R_EDX, 0 );
nkeynes@586
  2614
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2615
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
                        }
nkeynes@359
  2617
                        break;
nkeynes@359
  2618
                    case 0x3:
nkeynes@359
  2619
                        { /* TRAPA #imm */
nkeynes@359
  2620
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2621
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2622
                    	SLOTILLEGAL();
nkeynes@374
  2623
                        } else {
nkeynes@590
  2624
                    	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  2625
                    	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  2626
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2627
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2628
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2629
                    	exit_block_pcset(pc);
nkeynes@409
  2630
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2631
                    	return 2;
nkeynes@374
  2632
                        }
nkeynes@359
  2633
                        }
nkeynes@359
  2634
                        break;
nkeynes@359
  2635
                    case 0x4:
nkeynes@359
  2636
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2637
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2638
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2639
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2640
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2641
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2642
                        store_reg( R_EAX, 0 );
nkeynes@417
  2643
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2644
                        }
nkeynes@359
  2645
                        break;
nkeynes@359
  2646
                    case 0x5:
nkeynes@359
  2647
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2648
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2649
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2650
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2651
                        check_ralign16( R_EAX );
nkeynes@586
  2652
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2653
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2654
                        store_reg( R_EAX, 0 );
nkeynes@417
  2655
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2656
                        }
nkeynes@359
  2657
                        break;
nkeynes@359
  2658
                    case 0x6:
nkeynes@359
  2659
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2660
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2661
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2662
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2663
                        check_ralign32( R_EAX );
nkeynes@586
  2664
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2665
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2666
                        store_reg( R_EAX, 0 );
nkeynes@417
  2667
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2668
                        }
nkeynes@359
  2669
                        break;
nkeynes@359
  2670
                    case 0x7:
nkeynes@359
  2671
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2672
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2673
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2674
                    	SLOTILLEGAL();
nkeynes@374
  2675
                        } else {
nkeynes@586
  2676
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  2677
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2678
                    	store_reg( R_ECX, 0 );
nkeynes@586
  2679
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2680
                        }
nkeynes@359
  2681
                        }
nkeynes@359
  2682
                        break;
nkeynes@359
  2683
                    case 0x8:
nkeynes@359
  2684
                        { /* TST #imm, R0 */
nkeynes@359
  2685
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2686
                        load_reg( R_EAX, 0 );
nkeynes@368
  2687
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2688
                        SETE_t();
nkeynes@417
  2689
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2690
                        }
nkeynes@359
  2691
                        break;
nkeynes@359
  2692
                    case 0x9:
nkeynes@359
  2693
                        { /* AND #imm, R0 */
nkeynes@359
  2694
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2695
                        load_reg( R_EAX, 0 );
nkeynes@359
  2696
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2697
                        store_reg( R_EAX, 0 );
nkeynes@417
  2698
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2699
                        }
nkeynes@359
  2700
                        break;
nkeynes@359
  2701
                    case 0xA:
nkeynes@359
  2702
                        { /* XOR #imm, R0 */
nkeynes@359
  2703
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2704
                        load_reg( R_EAX, 0 );
nkeynes@359
  2705
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2706
                        store_reg( R_EAX, 0 );
nkeynes@417
  2707
                        sh4_x86.tstate = TSTATE_NONE;