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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 669:ab344e42bca9
prev626:a010e30a30e9
next671:a530ea88eebd
author nkeynes
date Mon May 12 10:00:13 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SH4_TRANSLATOR == TARGET_X86_64
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#include "sh4/ia64abi.h"
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#else /* SH4_TRANSLATOR == TARGET_X86 */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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#else
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#include "sh4/ia32abi.h"
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#endif
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#endif
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uint32_t sh4_translate_end_block_size()
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{
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    if( sh4_x86.backpatch_posn <= 3 ) {
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	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
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    } else {
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	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
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    }
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}
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/**
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 * Embed a breakpoint into the generated code
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   311
 */
nkeynes@586
   312
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   313
{
nkeynes@591
   314
    load_imm32( R_EAX, pc );
nkeynes@591
   315
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   316
}
nkeynes@590
   317
nkeynes@601
   318
nkeynes@601
   319
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   320
nkeynes@590
   321
/**
nkeynes@590
   322
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   323
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   324
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   325
 *
nkeynes@601
   326
 * Performs:
nkeynes@601
   327
 *   Set PC = endpc
nkeynes@601
   328
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   329
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   330
 *   Call sh4_execute_instruction
nkeynes@601
   331
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   332
 */
nkeynes@601
   333
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   334
{
nkeynes@590
   335
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   336
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   337
    
nkeynes@601
   338
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   339
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   340
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   341
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   342
nkeynes@590
   343
    call_func0( sh4_execute_instruction );    
nkeynes@601
   344
    load_spreg( R_EAX, R_PC );
nkeynes@590
   345
    if( sh4_x86.tlb_on ) {
nkeynes@590
   346
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   347
    } else {
nkeynes@590
   348
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   349
    }
nkeynes@601
   350
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   351
    POP_r32(R_EBP);
nkeynes@590
   352
    RET();
nkeynes@590
   353
} 
nkeynes@539
   354
nkeynes@359
   355
/**
nkeynes@359
   356
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   357
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   358
 * 
nkeynes@586
   359
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   360
 *
nkeynes@359
   361
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   362
 * (eg a branch or 
nkeynes@359
   363
 */
nkeynes@590
   364
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   365
{
nkeynes@388
   366
    uint32_t ir;
nkeynes@586
   367
    /* Read instruction from icache */
nkeynes@586
   368
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   369
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   370
    
nkeynes@586
   371
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   372
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   373
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   374
	 * almost certainly in a delay slot.
nkeynes@586
   375
	 *
nkeynes@586
   376
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   377
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   378
	 * small repairs to cope with the different environment).
nkeynes@586
   379
	 */
nkeynes@586
   380
nkeynes@586
   381
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   382
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   383
    }
nkeynes@359
   384
%%
nkeynes@359
   385
/* ALU operations */
nkeynes@359
   386
ADD Rm, Rn {:
nkeynes@359
   387
    load_reg( R_EAX, Rm );
nkeynes@359
   388
    load_reg( R_ECX, Rn );
nkeynes@359
   389
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   390
    store_reg( R_ECX, Rn );
nkeynes@417
   391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   392
:}
nkeynes@359
   393
ADD #imm, Rn {:  
nkeynes@359
   394
    load_reg( R_EAX, Rn );
nkeynes@359
   395
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   396
    store_reg( R_EAX, Rn );
nkeynes@417
   397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   398
:}
nkeynes@359
   399
ADDC Rm, Rn {:
nkeynes@417
   400
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   401
	LDC_t();
nkeynes@417
   402
    }
nkeynes@359
   403
    load_reg( R_EAX, Rm );
nkeynes@359
   404
    load_reg( R_ECX, Rn );
nkeynes@359
   405
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   406
    store_reg( R_ECX, Rn );
nkeynes@359
   407
    SETC_t();
nkeynes@417
   408
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   409
:}
nkeynes@359
   410
ADDV Rm, Rn {:
nkeynes@359
   411
    load_reg( R_EAX, Rm );
nkeynes@359
   412
    load_reg( R_ECX, Rn );
nkeynes@359
   413
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   414
    store_reg( R_ECX, Rn );
nkeynes@359
   415
    SETO_t();
nkeynes@417
   416
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   417
:}
nkeynes@359
   418
AND Rm, Rn {:
nkeynes@359
   419
    load_reg( R_EAX, Rm );
nkeynes@359
   420
    load_reg( R_ECX, Rn );
nkeynes@359
   421
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   422
    store_reg( R_ECX, Rn );
nkeynes@417
   423
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   424
:}
nkeynes@359
   425
AND #imm, R0 {:  
nkeynes@359
   426
    load_reg( R_EAX, 0 );
nkeynes@359
   427
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   428
    store_reg( R_EAX, 0 );
nkeynes@417
   429
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   430
:}
nkeynes@359
   431
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   432
    load_reg( R_EAX, 0 );
nkeynes@359
   433
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   434
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   435
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   436
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   437
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   438
    POP_realigned_r32(R_ECX);
nkeynes@386
   439
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   440
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   442
:}
nkeynes@359
   443
CMP/EQ Rm, Rn {:  
nkeynes@359
   444
    load_reg( R_EAX, Rm );
nkeynes@359
   445
    load_reg( R_ECX, Rn );
nkeynes@359
   446
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   447
    SETE_t();
nkeynes@417
   448
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   449
:}
nkeynes@359
   450
CMP/EQ #imm, R0 {:  
nkeynes@359
   451
    load_reg( R_EAX, 0 );
nkeynes@359
   452
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   453
    SETE_t();
nkeynes@417
   454
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   455
:}
nkeynes@359
   456
CMP/GE Rm, Rn {:  
nkeynes@359
   457
    load_reg( R_EAX, Rm );
nkeynes@359
   458
    load_reg( R_ECX, Rn );
nkeynes@359
   459
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   460
    SETGE_t();
nkeynes@417
   461
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   462
:}
nkeynes@359
   463
CMP/GT Rm, Rn {: 
nkeynes@359
   464
    load_reg( R_EAX, Rm );
nkeynes@359
   465
    load_reg( R_ECX, Rn );
nkeynes@359
   466
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   467
    SETG_t();
nkeynes@417
   468
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   469
:}
nkeynes@359
   470
CMP/HI Rm, Rn {:  
nkeynes@359
   471
    load_reg( R_EAX, Rm );
nkeynes@359
   472
    load_reg( R_ECX, Rn );
nkeynes@359
   473
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   474
    SETA_t();
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   476
:}
nkeynes@359
   477
CMP/HS Rm, Rn {: 
nkeynes@359
   478
    load_reg( R_EAX, Rm );
nkeynes@359
   479
    load_reg( R_ECX, Rn );
nkeynes@359
   480
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   481
    SETAE_t();
nkeynes@417
   482
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   483
 :}
nkeynes@359
   484
CMP/PL Rn {: 
nkeynes@359
   485
    load_reg( R_EAX, Rn );
nkeynes@359
   486
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   487
    SETG_t();
nkeynes@417
   488
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   489
:}
nkeynes@359
   490
CMP/PZ Rn {:  
nkeynes@359
   491
    load_reg( R_EAX, Rn );
nkeynes@359
   492
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   493
    SETGE_t();
nkeynes@417
   494
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   495
:}
nkeynes@361
   496
CMP/STR Rm, Rn {:  
nkeynes@368
   497
    load_reg( R_EAX, Rm );
nkeynes@368
   498
    load_reg( R_ECX, Rn );
nkeynes@368
   499
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   500
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   501
    JE_rel8(target1);
nkeynes@669
   502
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   503
    JE_rel8(target2);
nkeynes@669
   504
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   505
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   506
    JE_rel8(target3);
nkeynes@669
   507
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   508
    JMP_TARGET(target1);
nkeynes@380
   509
    JMP_TARGET(target2);
nkeynes@380
   510
    JMP_TARGET(target3);
nkeynes@368
   511
    SETE_t();
nkeynes@417
   512
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   513
:}
nkeynes@361
   514
DIV0S Rm, Rn {:
nkeynes@361
   515
    load_reg( R_EAX, Rm );
nkeynes@386
   516
    load_reg( R_ECX, Rn );
nkeynes@361
   517
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   518
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   519
    store_spreg( R_EAX, R_M );
nkeynes@361
   520
    store_spreg( R_ECX, R_Q );
nkeynes@361
   521
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   522
    SETNE_t();
nkeynes@417
   523
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   524
:}
nkeynes@361
   525
DIV0U {:  
nkeynes@361
   526
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   527
    store_spreg( R_EAX, R_Q );
nkeynes@361
   528
    store_spreg( R_EAX, R_M );
nkeynes@361
   529
    store_spreg( R_EAX, R_T );
nkeynes@417
   530
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   531
:}
nkeynes@386
   532
DIV1 Rm, Rn {:
nkeynes@386
   533
    load_spreg( R_ECX, R_M );
nkeynes@386
   534
    load_reg( R_EAX, Rn );
nkeynes@417
   535
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   536
	LDC_t();
nkeynes@417
   537
    }
nkeynes@386
   538
    RCL1_r32( R_EAX );
nkeynes@386
   539
    SETC_r8( R_DL ); // Q'
nkeynes@386
   540
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   541
    JE_rel8(mqequal);
nkeynes@386
   542
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   543
    JMP_rel8(end);
nkeynes@380
   544
    JMP_TARGET(mqequal);
nkeynes@386
   545
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   546
    JMP_TARGET(end);
nkeynes@386
   547
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   548
    SETC_r8(R_AL); // tmp1
nkeynes@386
   549
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   550
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   551
    store_spreg( R_ECX, R_Q );
nkeynes@386
   552
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   553
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   554
    store_spreg( R_EAX, R_T );
nkeynes@417
   555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   556
:}
nkeynes@361
   557
DMULS.L Rm, Rn {:  
nkeynes@361
   558
    load_reg( R_EAX, Rm );
nkeynes@361
   559
    load_reg( R_ECX, Rn );
nkeynes@361
   560
    IMUL_r32(R_ECX);
nkeynes@361
   561
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   562
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   563
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   564
:}
nkeynes@361
   565
DMULU.L Rm, Rn {:  
nkeynes@361
   566
    load_reg( R_EAX, Rm );
nkeynes@361
   567
    load_reg( R_ECX, Rn );
nkeynes@361
   568
    MUL_r32(R_ECX);
nkeynes@361
   569
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   570
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   571
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   572
:}
nkeynes@359
   573
DT Rn {:  
nkeynes@359
   574
    load_reg( R_EAX, Rn );
nkeynes@382
   575
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   576
    store_reg( R_EAX, Rn );
nkeynes@359
   577
    SETE_t();
nkeynes@417
   578
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   579
:}
nkeynes@359
   580
EXTS.B Rm, Rn {:  
nkeynes@359
   581
    load_reg( R_EAX, Rm );
nkeynes@359
   582
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   583
    store_reg( R_EAX, Rn );
nkeynes@359
   584
:}
nkeynes@361
   585
EXTS.W Rm, Rn {:  
nkeynes@361
   586
    load_reg( R_EAX, Rm );
nkeynes@361
   587
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   588
    store_reg( R_EAX, Rn );
nkeynes@361
   589
:}
nkeynes@361
   590
EXTU.B Rm, Rn {:  
nkeynes@361
   591
    load_reg( R_EAX, Rm );
nkeynes@361
   592
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   593
    store_reg( R_EAX, Rn );
nkeynes@361
   594
:}
nkeynes@361
   595
EXTU.W Rm, Rn {:  
nkeynes@361
   596
    load_reg( R_EAX, Rm );
nkeynes@361
   597
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   598
    store_reg( R_EAX, Rn );
nkeynes@361
   599
:}
nkeynes@586
   600
MAC.L @Rm+, @Rn+ {:
nkeynes@586
   601
    if( Rm == Rn ) {
nkeynes@586
   602
	load_reg( R_EAX, Rm );
nkeynes@586
   603
	check_ralign32( R_EAX );
nkeynes@586
   604
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   605
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   606
	load_reg( R_EAX, Rn );
nkeynes@586
   607
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   608
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   609
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   610
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   611
	// adding a page-boundary check to skip the second translation
nkeynes@586
   612
    } else {
nkeynes@586
   613
	load_reg( R_EAX, Rm );
nkeynes@586
   614
	check_ralign32( R_EAX );
nkeynes@586
   615
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   616
	load_reg( R_ECX, Rn );
nkeynes@596
   617
	check_ralign32( R_ECX );
nkeynes@586
   618
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   619
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   620
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   621
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   622
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   623
    }
nkeynes@586
   624
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   625
    POP_r32( R_ECX );
nkeynes@586
   626
    PUSH_r32( R_EAX );
nkeynes@386
   627
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   628
    POP_realigned_r32( R_ECX );
nkeynes@586
   629
nkeynes@386
   630
    IMUL_r32( R_ECX );
nkeynes@386
   631
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   632
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   633
nkeynes@386
   634
    load_spreg( R_ECX, R_S );
nkeynes@386
   635
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   636
    JE_rel8( nosat );
nkeynes@386
   637
    call_func0( signsat48 );
nkeynes@386
   638
    JMP_TARGET( nosat );
nkeynes@417
   639
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   640
:}
nkeynes@386
   641
MAC.W @Rm+, @Rn+ {:  
nkeynes@586
   642
    if( Rm == Rn ) {
nkeynes@586
   643
	load_reg( R_EAX, Rm );
nkeynes@586
   644
	check_ralign16( R_EAX );
nkeynes@586
   645
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   646
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   647
	load_reg( R_EAX, Rn );
nkeynes@586
   648
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   649
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   650
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   651
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   652
	// adding a page-boundary check to skip the second translation
nkeynes@586
   653
    } else {
nkeynes@586
   654
	load_reg( R_EAX, Rm );
nkeynes@586
   655
	check_ralign16( R_EAX );
nkeynes@586
   656
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   657
	load_reg( R_ECX, Rn );
nkeynes@596
   658
	check_ralign16( R_ECX );
nkeynes@586
   659
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   660
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   661
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   662
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   663
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   664
    }
nkeynes@586
   665
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   666
    POP_r32( R_ECX );
nkeynes@586
   667
    PUSH_r32( R_EAX );
nkeynes@386
   668
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   669
    POP_realigned_r32( R_ECX );
nkeynes@386
   670
    IMUL_r32( R_ECX );
nkeynes@386
   671
nkeynes@386
   672
    load_spreg( R_ECX, R_S );
nkeynes@386
   673
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   674
    JE_rel8( nosat );
nkeynes@386
   675
nkeynes@386
   676
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   677
    JNO_rel8( end );            // 2
nkeynes@386
   678
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   679
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   680
    JS_rel8( positive );        // 2
nkeynes@386
   681
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   682
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   683
    JMP_rel8(end2);           // 2
nkeynes@386
   684
nkeynes@386
   685
    JMP_TARGET(positive);
nkeynes@386
   686
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   687
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   688
    JMP_rel8(end3);            // 2
nkeynes@386
   689
nkeynes@386
   690
    JMP_TARGET(nosat);
nkeynes@386
   691
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   692
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   693
    JMP_TARGET(end);
nkeynes@386
   694
    JMP_TARGET(end2);
nkeynes@386
   695
    JMP_TARGET(end3);
nkeynes@417
   696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   697
:}
nkeynes@359
   698
MOVT Rn {:  
nkeynes@359
   699
    load_spreg( R_EAX, R_T );
nkeynes@359
   700
    store_reg( R_EAX, Rn );
nkeynes@359
   701
:}
nkeynes@361
   702
MUL.L Rm, Rn {:  
nkeynes@361
   703
    load_reg( R_EAX, Rm );
nkeynes@361
   704
    load_reg( R_ECX, Rn );
nkeynes@361
   705
    MUL_r32( R_ECX );
nkeynes@361
   706
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   707
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   708
:}
nkeynes@374
   709
MULS.W Rm, Rn {:
nkeynes@374
   710
    load_reg16s( R_EAX, Rm );
nkeynes@374
   711
    load_reg16s( R_ECX, Rn );
nkeynes@374
   712
    MUL_r32( R_ECX );
nkeynes@374
   713
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   714
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   715
:}
nkeynes@374
   716
MULU.W Rm, Rn {:  
nkeynes@374
   717
    load_reg16u( R_EAX, Rm );
nkeynes@374
   718
    load_reg16u( R_ECX, Rn );
nkeynes@374
   719
    MUL_r32( R_ECX );
nkeynes@374
   720
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   721
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   722
:}
nkeynes@359
   723
NEG Rm, Rn {:
nkeynes@359
   724
    load_reg( R_EAX, Rm );
nkeynes@359
   725
    NEG_r32( R_EAX );
nkeynes@359
   726
    store_reg( R_EAX, Rn );
nkeynes@417
   727
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   728
:}
nkeynes@359
   729
NEGC Rm, Rn {:  
nkeynes@359
   730
    load_reg( R_EAX, Rm );
nkeynes@359
   731
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   732
    LDC_t();
nkeynes@359
   733
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   734
    store_reg( R_ECX, Rn );
nkeynes@359
   735
    SETC_t();
nkeynes@417
   736
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   737
:}
nkeynes@359
   738
NOT Rm, Rn {:  
nkeynes@359
   739
    load_reg( R_EAX, Rm );
nkeynes@359
   740
    NOT_r32( R_EAX );
nkeynes@359
   741
    store_reg( R_EAX, Rn );
nkeynes@417
   742
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   743
:}
nkeynes@359
   744
OR Rm, Rn {:  
nkeynes@359
   745
    load_reg( R_EAX, Rm );
nkeynes@359
   746
    load_reg( R_ECX, Rn );
nkeynes@359
   747
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   748
    store_reg( R_ECX, Rn );
nkeynes@417
   749
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   750
:}
nkeynes@359
   751
OR #imm, R0 {:
nkeynes@359
   752
    load_reg( R_EAX, 0 );
nkeynes@359
   753
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   754
    store_reg( R_EAX, 0 );
nkeynes@417
   755
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   756
:}
nkeynes@374
   757
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   758
    load_reg( R_EAX, 0 );
nkeynes@374
   759
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   760
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   761
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   762
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   763
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   764
    POP_realigned_r32(R_ECX);
nkeynes@386
   765
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   766
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   767
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   768
:}
nkeynes@359
   769
ROTCL Rn {:
nkeynes@359
   770
    load_reg( R_EAX, Rn );
nkeynes@417
   771
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   772
	LDC_t();
nkeynes@417
   773
    }
nkeynes@359
   774
    RCL1_r32( R_EAX );
nkeynes@359
   775
    store_reg( R_EAX, Rn );
nkeynes@359
   776
    SETC_t();
nkeynes@417
   777
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   778
:}
nkeynes@359
   779
ROTCR Rn {:  
nkeynes@359
   780
    load_reg( R_EAX, Rn );
nkeynes@417
   781
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   782
	LDC_t();
nkeynes@417
   783
    }
nkeynes@359
   784
    RCR1_r32( R_EAX );
nkeynes@359
   785
    store_reg( R_EAX, Rn );
nkeynes@359
   786
    SETC_t();
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   788
:}
nkeynes@359
   789
ROTL Rn {:  
nkeynes@359
   790
    load_reg( R_EAX, Rn );
nkeynes@359
   791
    ROL1_r32( R_EAX );
nkeynes@359
   792
    store_reg( R_EAX, Rn );
nkeynes@359
   793
    SETC_t();
nkeynes@417
   794
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   795
:}
nkeynes@359
   796
ROTR Rn {:  
nkeynes@359
   797
    load_reg( R_EAX, Rn );
nkeynes@359
   798
    ROR1_r32( R_EAX );
nkeynes@359
   799
    store_reg( R_EAX, Rn );
nkeynes@359
   800
    SETC_t();
nkeynes@417
   801
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   802
:}
nkeynes@359
   803
SHAD Rm, Rn {:
nkeynes@359
   804
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   805
    load_reg( R_EAX, Rn );
nkeynes@361
   806
    load_reg( R_ECX, Rm );
nkeynes@361
   807
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   808
    JGE_rel8(doshl);
nkeynes@361
   809
                    
nkeynes@361
   810
    NEG_r32( R_ECX );      // 2
nkeynes@361
   811
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   812
    JE_rel8(emptysar);     // 2
nkeynes@361
   813
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   814
    JMP_rel8(end);          // 2
nkeynes@386
   815
nkeynes@386
   816
    JMP_TARGET(emptysar);
nkeynes@386
   817
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   818
    JMP_rel8(end2);
nkeynes@382
   819
nkeynes@380
   820
    JMP_TARGET(doshl);
nkeynes@361
   821
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   822
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   823
    JMP_TARGET(end);
nkeynes@386
   824
    JMP_TARGET(end2);
nkeynes@361
   825
    store_reg( R_EAX, Rn );
nkeynes@417
   826
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   827
:}
nkeynes@359
   828
SHLD Rm, Rn {:  
nkeynes@368
   829
    load_reg( R_EAX, Rn );
nkeynes@368
   830
    load_reg( R_ECX, Rm );
nkeynes@382
   831
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   832
    JGE_rel8(doshl);
nkeynes@368
   833
nkeynes@382
   834
    NEG_r32( R_ECX );      // 2
nkeynes@382
   835
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   836
    JE_rel8(emptyshr );
nkeynes@382
   837
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   838
    JMP_rel8(end);          // 2
nkeynes@386
   839
nkeynes@386
   840
    JMP_TARGET(emptyshr);
nkeynes@386
   841
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   842
    JMP_rel8(end2);
nkeynes@382
   843
nkeynes@382
   844
    JMP_TARGET(doshl);
nkeynes@382
   845
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   846
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   847
    JMP_TARGET(end);
nkeynes@386
   848
    JMP_TARGET(end2);
nkeynes@368
   849
    store_reg( R_EAX, Rn );
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   851
:}
nkeynes@359
   852
SHAL Rn {: 
nkeynes@359
   853
    load_reg( R_EAX, Rn );
nkeynes@359
   854
    SHL1_r32( R_EAX );
nkeynes@397
   855
    SETC_t();
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   858
:}
nkeynes@359
   859
SHAR Rn {:  
nkeynes@359
   860
    load_reg( R_EAX, Rn );
nkeynes@359
   861
    SAR1_r32( R_EAX );
nkeynes@397
   862
    SETC_t();
nkeynes@359
   863
    store_reg( R_EAX, Rn );
nkeynes@417
   864
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   865
:}
nkeynes@359
   866
SHLL Rn {:  
nkeynes@359
   867
    load_reg( R_EAX, Rn );
nkeynes@359
   868
    SHL1_r32( R_EAX );
nkeynes@397
   869
    SETC_t();
nkeynes@359
   870
    store_reg( R_EAX, Rn );
nkeynes@417
   871
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   872
:}
nkeynes@359
   873
SHLL2 Rn {:
nkeynes@359
   874
    load_reg( R_EAX, Rn );
nkeynes@359
   875
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   876
    store_reg( R_EAX, Rn );
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   878
:}
nkeynes@359
   879
SHLL8 Rn {:  
nkeynes@359
   880
    load_reg( R_EAX, Rn );
nkeynes@359
   881
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   882
    store_reg( R_EAX, Rn );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@359
   885
SHLL16 Rn {:  
nkeynes@359
   886
    load_reg( R_EAX, Rn );
nkeynes@359
   887
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   888
    store_reg( R_EAX, Rn );
nkeynes@417
   889
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   890
:}
nkeynes@359
   891
SHLR Rn {:  
nkeynes@359
   892
    load_reg( R_EAX, Rn );
nkeynes@359
   893
    SHR1_r32( R_EAX );
nkeynes@397
   894
    SETC_t();
nkeynes@359
   895
    store_reg( R_EAX, Rn );
nkeynes@417
   896
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   897
:}
nkeynes@359
   898
SHLR2 Rn {:  
nkeynes@359
   899
    load_reg( R_EAX, Rn );
nkeynes@359
   900
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   901
    store_reg( R_EAX, Rn );
nkeynes@417
   902
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   903
:}
nkeynes@359
   904
SHLR8 Rn {:  
nkeynes@359
   905
    load_reg( R_EAX, Rn );
nkeynes@359
   906
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   907
    store_reg( R_EAX, Rn );
nkeynes@417
   908
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   909
:}
nkeynes@359
   910
SHLR16 Rn {:  
nkeynes@359
   911
    load_reg( R_EAX, Rn );
nkeynes@359
   912
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   913
    store_reg( R_EAX, Rn );
nkeynes@417
   914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   915
:}
nkeynes@359
   916
SUB Rm, Rn {:  
nkeynes@359
   917
    load_reg( R_EAX, Rm );
nkeynes@359
   918
    load_reg( R_ECX, Rn );
nkeynes@359
   919
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   920
    store_reg( R_ECX, Rn );
nkeynes@417
   921
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   922
:}
nkeynes@359
   923
SUBC Rm, Rn {:  
nkeynes@359
   924
    load_reg( R_EAX, Rm );
nkeynes@359
   925
    load_reg( R_ECX, Rn );
nkeynes@417
   926
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   927
	LDC_t();
nkeynes@417
   928
    }
nkeynes@359
   929
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   930
    store_reg( R_ECX, Rn );
nkeynes@394
   931
    SETC_t();
nkeynes@417
   932
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   933
:}
nkeynes@359
   934
SUBV Rm, Rn {:  
nkeynes@359
   935
    load_reg( R_EAX, Rm );
nkeynes@359
   936
    load_reg( R_ECX, Rn );
nkeynes@359
   937
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   938
    store_reg( R_ECX, Rn );
nkeynes@359
   939
    SETO_t();
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   941
:}
nkeynes@359
   942
SWAP.B Rm, Rn {:  
nkeynes@359
   943
    load_reg( R_EAX, Rm );
nkeynes@601
   944
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
   945
    store_reg( R_EAX, Rn );
nkeynes@359
   946
:}
nkeynes@359
   947
SWAP.W Rm, Rn {:  
nkeynes@359
   948
    load_reg( R_EAX, Rm );
nkeynes@359
   949
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   950
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   951
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   952
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   953
    store_reg( R_ECX, Rn );
nkeynes@417
   954
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   955
:}
nkeynes@361
   956
TAS.B @Rn {:  
nkeynes@586
   957
    load_reg( R_EAX, Rn );
nkeynes@586
   958
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   959
    PUSH_realigned_r32( R_EAX );
nkeynes@586
   960
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
   961
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   962
    SETE_t();
nkeynes@361
   963
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
   964
    POP_realigned_r32( R_ECX );
nkeynes@361
   965
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   967
:}
nkeynes@361
   968
TST Rm, Rn {:  
nkeynes@361
   969
    load_reg( R_EAX, Rm );
nkeynes@361
   970
    load_reg( R_ECX, Rn );
nkeynes@361
   971
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   972
    SETE_t();
nkeynes@417
   973
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   974
:}
nkeynes@368
   975
TST #imm, R0 {:  
nkeynes@368
   976
    load_reg( R_EAX, 0 );
nkeynes@368
   977
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   978
    SETE_t();
nkeynes@417
   979
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   980
:}
nkeynes@368
   981
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   982
    load_reg( R_EAX, 0);
nkeynes@368
   983
    load_reg( R_ECX, R_GBR);
nkeynes@586
   984
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   985
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   986
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
   987
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   988
    SETE_t();
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   990
:}
nkeynes@359
   991
XOR Rm, Rn {:  
nkeynes@359
   992
    load_reg( R_EAX, Rm );
nkeynes@359
   993
    load_reg( R_ECX, Rn );
nkeynes@359
   994
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   995
    store_reg( R_ECX, Rn );
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   997
:}
nkeynes@359
   998
XOR #imm, R0 {:  
nkeynes@359
   999
    load_reg( R_EAX, 0 );
nkeynes@359
  1000
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1001
    store_reg( R_EAX, 0 );
nkeynes@417
  1002
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1003
:}
nkeynes@359
  1004
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1005
    load_reg( R_EAX, 0 );
nkeynes@359
  1006
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1007
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1008
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1009
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1010
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1011
    POP_realigned_r32(R_ECX);
nkeynes@359
  1012
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1013
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1014
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1015
:}
nkeynes@361
  1016
XTRCT Rm, Rn {:
nkeynes@361
  1017
    load_reg( R_EAX, Rm );
nkeynes@394
  1018
    load_reg( R_ECX, Rn );
nkeynes@394
  1019
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1020
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1021
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1022
    store_reg( R_ECX, Rn );
nkeynes@417
  1023
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1024
:}
nkeynes@359
  1025
nkeynes@359
  1026
/* Data move instructions */
nkeynes@359
  1027
MOV Rm, Rn {:  
nkeynes@359
  1028
    load_reg( R_EAX, Rm );
nkeynes@359
  1029
    store_reg( R_EAX, Rn );
nkeynes@359
  1030
:}
nkeynes@359
  1031
MOV #imm, Rn {:  
nkeynes@359
  1032
    load_imm32( R_EAX, imm );
nkeynes@359
  1033
    store_reg( R_EAX, Rn );
nkeynes@359
  1034
:}
nkeynes@359
  1035
MOV.B Rm, @Rn {:  
nkeynes@586
  1036
    load_reg( R_EAX, Rn );
nkeynes@586
  1037
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1038
    load_reg( R_EDX, Rm );
nkeynes@586
  1039
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1040
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1041
:}
nkeynes@359
  1042
MOV.B Rm, @-Rn {:  
nkeynes@586
  1043
    load_reg( R_EAX, Rn );
nkeynes@586
  1044
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1045
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1046
    load_reg( R_EDX, Rm );
nkeynes@586
  1047
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1048
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1049
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1050
:}
nkeynes@359
  1051
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1052
    load_reg( R_EAX, 0 );
nkeynes@359
  1053
    load_reg( R_ECX, Rn );
nkeynes@586
  1054
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1055
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1056
    load_reg( R_EDX, Rm );
nkeynes@586
  1057
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1058
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1059
:}
nkeynes@359
  1060
MOV.B R0, @(disp, GBR) {:  
nkeynes@586
  1061
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1062
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1063
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1064
    load_reg( R_EDX, 0 );
nkeynes@586
  1065
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1067
:}
nkeynes@359
  1068
MOV.B R0, @(disp, Rn) {:  
nkeynes@586
  1069
    load_reg( R_EAX, Rn );
nkeynes@586
  1070
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1071
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1072
    load_reg( R_EDX, 0 );
nkeynes@586
  1073
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1075
:}
nkeynes@359
  1076
MOV.B @Rm, Rn {:  
nkeynes@586
  1077
    load_reg( R_EAX, Rm );
nkeynes@586
  1078
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1079
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1080
    store_reg( R_EAX, Rn );
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1082
:}
nkeynes@359
  1083
MOV.B @Rm+, Rn {:  
nkeynes@586
  1084
    load_reg( R_EAX, Rm );
nkeynes@586
  1085
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1086
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1087
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1088
    store_reg( R_EAX, Rn );
nkeynes@417
  1089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1090
:}
nkeynes@359
  1091
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1092
    load_reg( R_EAX, 0 );
nkeynes@359
  1093
    load_reg( R_ECX, Rm );
nkeynes@586
  1094
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1095
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1096
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1097
    store_reg( R_EAX, Rn );
nkeynes@417
  1098
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1099
:}
nkeynes@359
  1100
MOV.B @(disp, GBR), R0 {:  
nkeynes@586
  1101
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1102
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1103
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1104
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1105
    store_reg( R_EAX, 0 );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV.B @(disp, Rm), R0 {:  
nkeynes@586
  1109
    load_reg( R_EAX, Rm );
nkeynes@586
  1110
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1111
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1112
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1113
    store_reg( R_EAX, 0 );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
:}
nkeynes@374
  1116
MOV.L Rm, @Rn {:
nkeynes@586
  1117
    load_reg( R_EAX, Rn );
nkeynes@586
  1118
    check_walign32(R_EAX);
nkeynes@586
  1119
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1120
    load_reg( R_EDX, Rm );
nkeynes@586
  1121
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1123
:}
nkeynes@361
  1124
MOV.L Rm, @-Rn {:  
nkeynes@586
  1125
    load_reg( R_EAX, Rn );
nkeynes@586
  1126
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1127
    check_walign32( R_EAX );
nkeynes@586
  1128
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1129
    load_reg( R_EDX, Rm );
nkeynes@586
  1130
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1131
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1132
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1133
:}
nkeynes@361
  1134
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1135
    load_reg( R_EAX, 0 );
nkeynes@361
  1136
    load_reg( R_ECX, Rn );
nkeynes@586
  1137
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1138
    check_walign32( R_EAX );
nkeynes@586
  1139
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1140
    load_reg( R_EDX, Rm );
nkeynes@586
  1141
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1142
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1143
:}
nkeynes@361
  1144
MOV.L R0, @(disp, GBR) {:  
nkeynes@586
  1145
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1146
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1147
    check_walign32( R_EAX );
nkeynes@586
  1148
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1149
    load_reg( R_EDX, 0 );
nkeynes@586
  1150
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1151
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1152
:}
nkeynes@361
  1153
MOV.L Rm, @(disp, Rn) {:  
nkeynes@586
  1154
    load_reg( R_EAX, Rn );
nkeynes@586
  1155
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1156
    check_walign32( R_EAX );
nkeynes@586
  1157
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1158
    load_reg( R_EDX, Rm );
nkeynes@586
  1159
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1160
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1161
:}
nkeynes@361
  1162
MOV.L @Rm, Rn {:  
nkeynes@586
  1163
    load_reg( R_EAX, Rm );
nkeynes@586
  1164
    check_ralign32( R_EAX );
nkeynes@586
  1165
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1166
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1167
    store_reg( R_EAX, Rn );
nkeynes@417
  1168
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1169
:}
nkeynes@361
  1170
MOV.L @Rm+, Rn {:  
nkeynes@361
  1171
    load_reg( R_EAX, Rm );
nkeynes@382
  1172
    check_ralign32( R_EAX );
nkeynes@586
  1173
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1174
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1175
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1176
    store_reg( R_EAX, Rn );
nkeynes@417
  1177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1178
:}
nkeynes@361
  1179
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1180
    load_reg( R_EAX, 0 );
nkeynes@361
  1181
    load_reg( R_ECX, Rm );
nkeynes@586
  1182
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1183
    check_ralign32( R_EAX );
nkeynes@586
  1184
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1185
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1186
    store_reg( R_EAX, Rn );
nkeynes@417
  1187
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1188
:}
nkeynes@361
  1189
MOV.L @(disp, GBR), R0 {:
nkeynes@586
  1190
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1191
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1192
    check_ralign32( R_EAX );
nkeynes@586
  1193
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1194
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1195
    store_reg( R_EAX, 0 );
nkeynes@417
  1196
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1197
:}
nkeynes@361
  1198
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1199
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1200
	SLOTILLEGAL();
nkeynes@374
  1201
    } else {
nkeynes@388
  1202
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1203
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1204
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1205
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1206
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1207
nkeynes@586
  1208
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1209
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1210
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1211
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1212
	    // behaviour though.
nkeynes@586
  1213
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1214
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1215
	} else {
nkeynes@586
  1216
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1217
	    // different virtual address than the translation was done with,
nkeynes@586
  1218
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1219
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1220
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1221
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1222
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1223
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1224
	}
nkeynes@382
  1225
	store_reg( R_EAX, Rn );
nkeynes@374
  1226
    }
nkeynes@361
  1227
:}
nkeynes@361
  1228
MOV.L @(disp, Rm), Rn {:  
nkeynes@586
  1229
    load_reg( R_EAX, Rm );
nkeynes@586
  1230
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1231
    check_ralign32( R_EAX );
nkeynes@586
  1232
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1233
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1234
    store_reg( R_EAX, Rn );
nkeynes@417
  1235
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1236
:}
nkeynes@361
  1237
MOV.W Rm, @Rn {:  
nkeynes@586
  1238
    load_reg( R_EAX, Rn );
nkeynes@586
  1239
    check_walign16( R_EAX );
nkeynes@586
  1240
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1241
    load_reg( R_EDX, Rm );
nkeynes@586
  1242
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.W Rm, @-Rn {:  
nkeynes@586
  1246
    load_reg( R_EAX, Rn );
nkeynes@586
  1247
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1248
    check_walign16( R_EAX );
nkeynes@586
  1249
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1250
    load_reg( R_EDX, Rm );
nkeynes@586
  1251
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1252
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1256
    load_reg( R_EAX, 0 );
nkeynes@361
  1257
    load_reg( R_ECX, Rn );
nkeynes@586
  1258
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1259
    check_walign16( R_EAX );
nkeynes@586
  1260
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1261
    load_reg( R_EDX, Rm );
nkeynes@586
  1262
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1263
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1264
:}
nkeynes@361
  1265
MOV.W R0, @(disp, GBR) {:  
nkeynes@586
  1266
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1267
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1268
    check_walign16( R_EAX );
nkeynes@586
  1269
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1270
    load_reg( R_EDX, 0 );
nkeynes@586
  1271
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1272
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1273
:}
nkeynes@361
  1274
MOV.W R0, @(disp, Rn) {:  
nkeynes@586
  1275
    load_reg( R_EAX, Rn );
nkeynes@586
  1276
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1277
    check_walign16( R_EAX );
nkeynes@586
  1278
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1279
    load_reg( R_EDX, 0 );
nkeynes@586
  1280
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1281
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1282
:}
nkeynes@361
  1283
MOV.W @Rm, Rn {:  
nkeynes@586
  1284
    load_reg( R_EAX, Rm );
nkeynes@586
  1285
    check_ralign16( R_EAX );
nkeynes@586
  1286
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1287
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1288
    store_reg( R_EAX, Rn );
nkeynes@417
  1289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1290
:}
nkeynes@361
  1291
MOV.W @Rm+, Rn {:  
nkeynes@361
  1292
    load_reg( R_EAX, Rm );
nkeynes@374
  1293
    check_ralign16( R_EAX );
nkeynes@586
  1294
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1295
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1296
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1297
    store_reg( R_EAX, Rn );
nkeynes@417
  1298
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1299
:}
nkeynes@361
  1300
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1301
    load_reg( R_EAX, 0 );
nkeynes@361
  1302
    load_reg( R_ECX, Rm );
nkeynes@586
  1303
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1304
    check_ralign16( R_EAX );
nkeynes@586
  1305
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1306
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1307
    store_reg( R_EAX, Rn );
nkeynes@417
  1308
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1309
:}
nkeynes@361
  1310
MOV.W @(disp, GBR), R0 {:  
nkeynes@586
  1311
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1312
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1313
    check_ralign16( R_EAX );
nkeynes@586
  1314
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1315
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1316
    store_reg( R_EAX, 0 );
nkeynes@417
  1317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1318
:}
nkeynes@361
  1319
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1320
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1321
	SLOTILLEGAL();
nkeynes@374
  1322
    } else {
nkeynes@586
  1323
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1324
	uint32_t target = pc + disp + 4;
nkeynes@586
  1325
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1326
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1327
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1328
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1329
	} else {
nkeynes@586
  1330
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1331
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1332
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1333
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1334
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1335
	}
nkeynes@374
  1336
	store_reg( R_EAX, Rn );
nkeynes@374
  1337
    }
nkeynes@361
  1338
:}
nkeynes@361
  1339
MOV.W @(disp, Rm), R0 {:  
nkeynes@586
  1340
    load_reg( R_EAX, Rm );
nkeynes@586
  1341
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1342
    check_ralign16( R_EAX );
nkeynes@586
  1343
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1344
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1345
    store_reg( R_EAX, 0 );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1347
:}
nkeynes@361
  1348
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1349
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1350
	SLOTILLEGAL();
nkeynes@374
  1351
    } else {
nkeynes@586
  1352
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1353
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1354
	store_reg( R_ECX, 0 );
nkeynes@586
  1355
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1356
    }
nkeynes@361
  1357
:}
nkeynes@361
  1358
MOVCA.L R0, @Rn {:  
nkeynes@586
  1359
    load_reg( R_EAX, Rn );
nkeynes@586
  1360
    check_walign32( R_EAX );
nkeynes@586
  1361
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1362
    load_reg( R_EDX, 0 );
nkeynes@586
  1363
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1365
:}
nkeynes@359
  1366
nkeynes@359
  1367
/* Control transfer instructions */
nkeynes@374
  1368
BF disp {:
nkeynes@374
  1369
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1370
	SLOTILLEGAL();
nkeynes@374
  1371
    } else {
nkeynes@586
  1372
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1373
	JT_rel8( nottaken );
nkeynes@586
  1374
	exit_block_rel(target, pc+2 );
nkeynes@380
  1375
	JMP_TARGET(nottaken);
nkeynes@408
  1376
	return 2;
nkeynes@374
  1377
    }
nkeynes@374
  1378
:}
nkeynes@374
  1379
BF/S disp {:
nkeynes@374
  1380
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1381
	SLOTILLEGAL();
nkeynes@374
  1382
    } else {
nkeynes@590
  1383
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1384
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1385
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1386
	    JT_rel8(nottaken);
nkeynes@601
  1387
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1388
	    JMP_TARGET(nottaken);
nkeynes@601
  1389
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1390
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1391
	    exit_block_emu(pc+2);
nkeynes@601
  1392
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1393
	    return 2;
nkeynes@601
  1394
	} else {
nkeynes@601
  1395
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1396
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1397
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1398
	    }
nkeynes@601
  1399
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1400
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1401
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1402
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1403
	    
nkeynes@601
  1404
	    // not taken
nkeynes@601
  1405
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1406
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1407
	    return 4;
nkeynes@417
  1408
	}
nkeynes@374
  1409
    }
nkeynes@374
  1410
:}
nkeynes@374
  1411
BRA disp {:  
nkeynes@374
  1412
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1413
	SLOTILLEGAL();
nkeynes@374
  1414
    } else {
nkeynes@590
  1415
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1416
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1417
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1418
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1419
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1420
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1421
	    exit_block_emu(pc+2);
nkeynes@601
  1422
	    return 2;
nkeynes@601
  1423
	} else {
nkeynes@601
  1424
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1425
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1426
	    return 4;
nkeynes@601
  1427
	}
nkeynes@374
  1428
    }
nkeynes@374
  1429
:}
nkeynes@374
  1430
BRAF Rn {:  
nkeynes@374
  1431
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1432
	SLOTILLEGAL();
nkeynes@374
  1433
    } else {
nkeynes@590
  1434
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1435
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1436
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1437
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1438
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1439
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1440
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1441
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1442
	    exit_block_emu(pc+2);
nkeynes@601
  1443
	    return 2;
nkeynes@601
  1444
	} else {
nkeynes@601
  1445
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1446
	    exit_block_newpcset(pc+2);
nkeynes@601
  1447
	    return 4;
nkeynes@601
  1448
	}
nkeynes@374
  1449
    }
nkeynes@374
  1450
:}
nkeynes@374
  1451
BSR disp {:  
nkeynes@374
  1452
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1453
	SLOTILLEGAL();
nkeynes@374
  1454
    } else {
nkeynes@590
  1455
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1456
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1457
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1458
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1459
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1460
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1461
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1462
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1463
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1464
	    exit_block_emu(pc+2);
nkeynes@601
  1465
	    return 2;
nkeynes@601
  1466
	} else {
nkeynes@601
  1467
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1468
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1469
	    return 4;
nkeynes@601
  1470
	}
nkeynes@374
  1471
    }
nkeynes@374
  1472
:}
nkeynes@374
  1473
BSRF Rn {:  
nkeynes@374
  1474
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1475
	SLOTILLEGAL();
nkeynes@374
  1476
    } else {
nkeynes@590
  1477
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1478
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1479
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1480
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1481
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1482
nkeynes@601
  1483
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1484
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1485
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1486
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1487
	    exit_block_emu(pc+2);
nkeynes@601
  1488
	    return 2;
nkeynes@601
  1489
	} else {
nkeynes@601
  1490
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1491
	    exit_block_newpcset(pc+2);
nkeynes@601
  1492
	    return 4;
nkeynes@601
  1493
	}
nkeynes@374
  1494
    }
nkeynes@374
  1495
:}
nkeynes@374
  1496
BT disp {:
nkeynes@374
  1497
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1498
	SLOTILLEGAL();
nkeynes@374
  1499
    } else {
nkeynes@586
  1500
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1501
	JF_rel8( nottaken );
nkeynes@586
  1502
	exit_block_rel(target, pc+2 );
nkeynes@380
  1503
	JMP_TARGET(nottaken);
nkeynes@408
  1504
	return 2;
nkeynes@374
  1505
    }
nkeynes@374
  1506
:}
nkeynes@374
  1507
BT/S disp {:
nkeynes@374
  1508
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1509
	SLOTILLEGAL();
nkeynes@374
  1510
    } else {
nkeynes@590
  1511
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1512
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1513
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1514
	    JF_rel8(nottaken);
nkeynes@601
  1515
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1516
	    JMP_TARGET(nottaken);
nkeynes@601
  1517
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1518
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1519
	    exit_block_emu(pc+2);
nkeynes@601
  1520
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1521
	    return 2;
nkeynes@601
  1522
	} else {
nkeynes@601
  1523
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1524
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1525
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1526
	    }
nkeynes@601
  1527
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1528
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1529
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1530
	    // not taken
nkeynes@601
  1531
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1532
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1533
	    return 4;
nkeynes@417
  1534
	}
nkeynes@374
  1535
    }
nkeynes@374
  1536
:}
nkeynes@374
  1537
JMP @Rn {:  
nkeynes@374
  1538
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1539
	SLOTILLEGAL();
nkeynes@374
  1540
    } else {
nkeynes@408
  1541
	load_reg( R_ECX, Rn );
nkeynes@590
  1542
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1543
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1544
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1545
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1546
	    exit_block_emu(pc+2);
nkeynes@601
  1547
	    return 2;
nkeynes@601
  1548
	} else {
nkeynes@601
  1549
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1550
	    exit_block_newpcset(pc+2);
nkeynes@601
  1551
	    return 4;
nkeynes@601
  1552
	}
nkeynes@374
  1553
    }
nkeynes@374
  1554
:}
nkeynes@374
  1555
JSR @Rn {:  
nkeynes@374
  1556
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1557
	SLOTILLEGAL();
nkeynes@374
  1558
    } else {
nkeynes@590
  1559
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1560
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1561
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1562
	load_reg( R_ECX, Rn );
nkeynes@590
  1563
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1564
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1565
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1566
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1567
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1568
	    exit_block_emu(pc+2);
nkeynes@601
  1569
	    return 2;
nkeynes@601
  1570
	} else {
nkeynes@601
  1571
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1572
	    exit_block_newpcset(pc+2);
nkeynes@601
  1573
	    return 4;
nkeynes@601
  1574
	}
nkeynes@374
  1575
    }
nkeynes@374
  1576
:}
nkeynes@374
  1577
RTE {:  
nkeynes@374
  1578
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1579
	SLOTILLEGAL();
nkeynes@374
  1580
    } else {
nkeynes@408
  1581
	check_priv();
nkeynes@408
  1582
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1583
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1584
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1585
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1586
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1587
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1588
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1589
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1590
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1591
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1592
	    exit_block_emu(pc+2);
nkeynes@601
  1593
	    return 2;
nkeynes@601
  1594
	} else {
nkeynes@601
  1595
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1596
	    exit_block_newpcset(pc+2);
nkeynes@601
  1597
	    return 4;
nkeynes@601
  1598
	}
nkeynes@374
  1599
    }
nkeynes@374
  1600
:}
nkeynes@374
  1601
RTS {:  
nkeynes@374
  1602
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1603
	SLOTILLEGAL();
nkeynes@374
  1604
    } else {
nkeynes@408
  1605
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1606
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1607
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1608
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1609
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1610
	    exit_block_emu(pc+2);
nkeynes@601
  1611
	    return 2;
nkeynes@601
  1612
	} else {
nkeynes@601
  1613
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1614
	    exit_block_newpcset(pc+2);
nkeynes@601
  1615
	    return 4;
nkeynes@601
  1616
	}
nkeynes@374
  1617
    }
nkeynes@374
  1618
:}
nkeynes@374
  1619
TRAPA #imm {:  
nkeynes@374
  1620
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1621
	SLOTILLEGAL();
nkeynes@374
  1622
    } else {
nkeynes@590
  1623
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1624
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1625
	load_imm32( R_EAX, imm );
nkeynes@527
  1626
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1627
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1628
	exit_block_pcset(pc);
nkeynes@409
  1629
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1630
	return 2;
nkeynes@374
  1631
    }
nkeynes@374
  1632
:}
nkeynes@374
  1633
UNDEF {:  
nkeynes@374
  1634
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1635
	SLOTILLEGAL();
nkeynes@374
  1636
    } else {
nkeynes@586
  1637
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1638
	return 2;
nkeynes@374
  1639
    }
nkeynes@368
  1640
:}
nkeynes@374
  1641
nkeynes@374
  1642
CLRMAC {:  
nkeynes@374
  1643
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1644
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1645
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1646
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1647
:}
nkeynes@374
  1648
CLRS {:
nkeynes@374
  1649
    CLC();
nkeynes@374
  1650
    SETC_sh4r(R_S);
nkeynes@417
  1651
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1652
:}
nkeynes@374
  1653
CLRT {:  
nkeynes@374
  1654
    CLC();
nkeynes@374
  1655
    SETC_t();
nkeynes@417
  1656
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1657
:}
nkeynes@374
  1658
SETS {:  
nkeynes@374
  1659
    STC();
nkeynes@374
  1660
    SETC_sh4r(R_S);
nkeynes@417
  1661
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1662
:}
nkeynes@374
  1663
SETT {:  
nkeynes@374
  1664
    STC();
nkeynes@374
  1665
    SETC_t();
nkeynes@417
  1666
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1667
:}
nkeynes@359
  1668
nkeynes@375
  1669
/* Floating point moves */
nkeynes@375
  1670
FMOV FRm, FRn {:  
nkeynes@375
  1671
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1672
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1673
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1674
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1675
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1676
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1677
     */
nkeynes@377
  1678
    check_fpuen();
nkeynes@375
  1679
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1680
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@669
  1681
    JNE_rel8(doublesize);
nkeynes@669
  1682
    load_fr( R_EAX, FRm ); // PR=0 branch
nkeynes@669
  1683
    store_fr( R_EAX, FRn );
nkeynes@669
  1684
    JMP_rel8(end);
nkeynes@669
  1685
    JMP_TARGET(doublesize);
nkeynes@669
  1686
    load_dr0( R_EAX, FRm );
nkeynes@669
  1687
    load_dr1( R_ECX, FRm );
nkeynes@669
  1688
    store_dr0( R_EAX, FRn );
nkeynes@669
  1689
    store_dr1( R_ECX, FRn );
nkeynes@669
  1690
    JMP_TARGET(end);
nkeynes@417
  1691
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1692
:}
nkeynes@416
  1693
FMOV FRm, @Rn {: 
nkeynes@586
  1694
    check_fpuen();
nkeynes@586
  1695
    load_reg( R_EAX, Rn );
nkeynes@586
  1696
    check_walign32( R_EAX );
nkeynes@586
  1697
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1698
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1699
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1700
    JNE_rel8(doublesize);
nkeynes@669
  1701
nkeynes@669
  1702
    load_fr( R_ECX, FRm );
nkeynes@586
  1703
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1704
    JMP_rel8(end);
nkeynes@669
  1705
nkeynes@669
  1706
    JMP_TARGET(doublesize);
nkeynes@669
  1707
    load_dr0( R_ECX, FRm );
nkeynes@669
  1708
    load_dr1( R_EDX, FRm );
nkeynes@669
  1709
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1710
    JMP_TARGET(end);
nkeynes@417
  1711
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1712
:}
nkeynes@375
  1713
FMOV @Rm, FRn {:  
nkeynes@586
  1714
    check_fpuen();
nkeynes@586
  1715
    load_reg( R_EAX, Rm );
nkeynes@586
  1716
    check_ralign32( R_EAX );
nkeynes@586
  1717
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1718
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1719
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1720
    JNE_rel8(doublesize);
nkeynes@669
  1721
nkeynes@586
  1722
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1723
    store_fr( R_EAX, FRn );
nkeynes@669
  1724
    JMP_rel8(end);
nkeynes@669
  1725
nkeynes@669
  1726
    JMP_TARGET(doublesize);
nkeynes@669
  1727
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1728
    store_dr0( R_ECX, FRn );
nkeynes@669
  1729
    store_dr1( R_EAX, FRn );
nkeynes@669
  1730
    JMP_TARGET(end);
nkeynes@417
  1731
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1732
:}
nkeynes@377
  1733
FMOV FRm, @-Rn {:  
nkeynes@586
  1734
    check_fpuen();
nkeynes@586
  1735
    load_reg( R_EAX, Rn );
nkeynes@586
  1736
    check_walign32( R_EAX );
nkeynes@416
  1737
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1738
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1739
    JNE_rel8(doublesize);
nkeynes@669
  1740
nkeynes@586
  1741
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1742
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1743
    load_fr( R_ECX, FRm );
nkeynes@586
  1744
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@669
  1745
    MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@669
  1746
    JMP_rel8(end);
nkeynes@669
  1747
nkeynes@669
  1748
    JMP_TARGET(doublesize);
nkeynes@669
  1749
    ADD_imm8s_r32(-8,R_EAX);
nkeynes@669
  1750
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1751
    load_dr0( R_ECX, FRm );
nkeynes@669
  1752
    load_dr1( R_EDX, FRm );
nkeynes@669
  1753
    ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@669
  1754
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1755
    JMP_TARGET(end);
nkeynes@669
  1756
nkeynes@417
  1757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1758
:}
nkeynes@416
  1759
FMOV @Rm+, FRn {:
nkeynes@586
  1760
    check_fpuen();
nkeynes@586
  1761
    load_reg( R_EAX, Rm );
nkeynes@586
  1762
    check_ralign32( R_EAX );
nkeynes@586
  1763
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1764
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1765
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1766
    JNE_rel8(doublesize);
nkeynes@669
  1767
nkeynes@586
  1768
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1769
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1770
    store_fr( R_EAX, FRn );
nkeynes@669
  1771
    JMP_rel8(end);
nkeynes@669
  1772
nkeynes@669
  1773
    JMP_TARGET(doublesize);
nkeynes@669
  1774
    ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@669
  1775
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1776
    store_dr0( R_ECX, FRn );
nkeynes@669
  1777
    store_dr1( R_EAX, FRn );
nkeynes@669
  1778
    JMP_TARGET(end);
nkeynes@669
  1779
nkeynes@417
  1780
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1781
:}
nkeynes@377
  1782
FMOV FRm, @(R0, Rn) {:  
nkeynes@586
  1783
    check_fpuen();
nkeynes@586
  1784
    load_reg( R_EAX, Rn );
nkeynes@586
  1785
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1786
    check_walign32( R_EAX );
nkeynes@586
  1787
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1788
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1789
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1790
    JNE_rel8(doublesize);
nkeynes@669
  1791
nkeynes@669
  1792
    load_fr( R_ECX, FRm );
nkeynes@586
  1793
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1794
    JMP_rel8(end);
nkeynes@669
  1795
nkeynes@669
  1796
    JMP_TARGET(doublesize);
nkeynes@669
  1797
    load_dr0( R_ECX, FRm );
nkeynes@669
  1798
    load_dr1( R_EDX, FRm );
nkeynes@669
  1799
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1800
    JMP_TARGET(end);
nkeynes@669
  1801
nkeynes@417
  1802
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1803
:}
nkeynes@377
  1804
FMOV @(R0, Rm), FRn {:  
nkeynes@586
  1805
    check_fpuen();
nkeynes@586
  1806
    load_reg( R_EAX, Rm );
nkeynes@586
  1807
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1808
    check_ralign32( R_EAX );
nkeynes@586
  1809
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1810
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1811
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1812
    JNE_rel8(doublesize);
nkeynes@669
  1813
nkeynes@586
  1814
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1815
    store_fr( R_EAX, FRn );
nkeynes@669
  1816
    JMP_rel8(end);
nkeynes@669
  1817
nkeynes@669
  1818
    JMP_TARGET(doublesize);
nkeynes@669
  1819
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1820
    store_dr0( R_ECX, FRn );
nkeynes@669
  1821
    store_dr1( R_EAX, FRn );
nkeynes@669
  1822
    JMP_TARGET(end);
nkeynes@669
  1823
nkeynes@417
  1824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1825
:}
nkeynes@377
  1826
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1827
    check_fpuen();
nkeynes@377
  1828
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1829
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1830
    JNE_rel8(end);
nkeynes@377
  1831
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  1832
    store_fr( R_EAX, FRn );
nkeynes@380
  1833
    JMP_TARGET(end);
nkeynes@417
  1834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1835
:}
nkeynes@377
  1836
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1837
    check_fpuen();
nkeynes@377
  1838
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1839
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1840
    JNE_rel8(end);
nkeynes@377
  1841
    load_imm32(R_EAX, 0x3F800000);
nkeynes@669
  1842
    store_fr( R_EAX, FRn );
nkeynes@380
  1843
    JMP_TARGET(end);
nkeynes@417
  1844
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1845
:}
nkeynes@377
  1846
nkeynes@377
  1847
FLOAT FPUL, FRn {:  
nkeynes@377
  1848
    check_fpuen();
nkeynes@377
  1849
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1850
    FILD_sh4r(R_FPUL);
nkeynes@377
  1851
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1852
    JNE_rel8(doubleprec);
nkeynes@669
  1853
    pop_fr( FRn );
nkeynes@669
  1854
    JMP_rel8(end);
nkeynes@380
  1855
    JMP_TARGET(doubleprec);
nkeynes@669
  1856
    pop_dr( FRn );
nkeynes@380
  1857
    JMP_TARGET(end);
nkeynes@417
  1858
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1859
:}
nkeynes@377
  1860
FTRC FRm, FPUL {:  
nkeynes@377
  1861
    check_fpuen();
nkeynes@388
  1862
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1863
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1864
    JNE_rel8(doubleprec);
nkeynes@669
  1865
    push_fr( FRm );
nkeynes@669
  1866
    JMP_rel8(doop);
nkeynes@388
  1867
    JMP_TARGET(doubleprec);
nkeynes@669
  1868
    push_dr( FRm );
nkeynes@388
  1869
    JMP_TARGET( doop );
nkeynes@388
  1870
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1871
    FILD_r32ind( R_ECX );
nkeynes@388
  1872
    FCOMIP_st(1);
nkeynes@669
  1873
    JNA_rel8( sat );
nkeynes@388
  1874
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1875
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1876
    FCOMIP_st(1);                   // 2
nkeynes@669
  1877
    JAE_rel8( sat2 );            // 2
nkeynes@394
  1878
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1879
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1880
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1881
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1882
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1883
    FLDCW_r32ind( R_EAX );
nkeynes@669
  1884
    JMP_rel8(end);             // 2
nkeynes@388
  1885
nkeynes@388
  1886
    JMP_TARGET(sat);
nkeynes@388
  1887
    JMP_TARGET(sat2);
nkeynes@388
  1888
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1889
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1890
    FPOP_st();
nkeynes@388
  1891
    JMP_TARGET(end);
nkeynes@417
  1892
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1893
:}
nkeynes@377
  1894
FLDS FRm, FPUL {:  
nkeynes@377
  1895
    check_fpuen();
nkeynes@669
  1896
    load_fr( R_EAX, FRm );
nkeynes@377
  1897
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1898
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1899
:}
nkeynes@377
  1900
FSTS FPUL, FRn {:  
nkeynes@377
  1901
    check_fpuen();
nkeynes@377
  1902
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  1903
    store_fr( R_EAX, FRn );
nkeynes@417
  1904
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1905
:}
nkeynes@377
  1906
FCNVDS FRm, FPUL {:  
nkeynes@377
  1907
    check_fpuen();
nkeynes@377
  1908
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1909
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1910
    JE_rel8(end); // only when PR=1
nkeynes@669
  1911
    push_dr( FRm );
nkeynes@377
  1912
    pop_fpul();
nkeynes@380
  1913
    JMP_TARGET(end);
nkeynes@417
  1914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1915
:}
nkeynes@377
  1916
FCNVSD FPUL, FRn {:  
nkeynes@377
  1917
    check_fpuen();
nkeynes@377
  1918
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1919
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1920
    JE_rel8(end); // only when PR=1
nkeynes@377
  1921
    push_fpul();
nkeynes@669
  1922
    pop_dr( FRn );
nkeynes@380
  1923
    JMP_TARGET(end);
nkeynes@417
  1924
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1925
:}
nkeynes@375
  1926
nkeynes@359
  1927
/* Floating point instructions */
nkeynes@374
  1928
FABS FRn {:  
nkeynes@377
  1929
    check_fpuen();
nkeynes@374
  1930
    load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  1931
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1932
    JNE_rel8(doubleprec);
nkeynes@669
  1933
    push_fr(FRn); // 6
nkeynes@374
  1934
    FABS_st0(); // 2
nkeynes@669
  1935
    pop_fr(FRn); //6
nkeynes@669
  1936
    JMP_rel8(end); // 2
nkeynes@380
  1937
    JMP_TARGET(doubleprec);
nkeynes@669
  1938
    push_dr(FRn);
nkeynes@374
  1939
    FABS_st0();
nkeynes@669
  1940
    pop_dr(FRn);
nkeynes@380
  1941
    JMP_TARGET(end);
nkeynes@417
  1942
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1943
:}
nkeynes@377
  1944
FADD FRm, FRn {:  
nkeynes@377
  1945
    check_fpuen();
nkeynes@375
  1946
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1947
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1948
    JNE_rel8(doubleprec);
nkeynes@669
  1949
    push_fr(FRm);
nkeynes@669
  1950
    push_fr(FRn);
nkeynes@377
  1951
    FADDP_st(1);
nkeynes@669
  1952
    pop_fr(FRn);
nkeynes@669
  1953
    JMP_rel8(end);
nkeynes@380
  1954
    JMP_TARGET(doubleprec);
nkeynes@669
  1955
    push_dr(FRm);
nkeynes@669
  1956
    push_dr(FRn);
nkeynes@377
  1957
    FADDP_st(1);
nkeynes@669
  1958
    pop_dr(FRn);
nkeynes@380
  1959
    JMP_TARGET(end);
nkeynes@417
  1960
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1961
:}
nkeynes@377
  1962
FDIV FRm, FRn {:  
nkeynes@377
  1963
    check_fpuen();
nkeynes@375
  1964
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1965
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1966
    JNE_rel8(doubleprec);
nkeynes@669
  1967
    push_fr(FRn);
nkeynes@669
  1968
    push_fr(FRm);
nkeynes@377
  1969
    FDIVP_st(1);
nkeynes@669
  1970
    pop_fr(FRn);
nkeynes@669
  1971
    JMP_rel8(end);
nkeynes@380
  1972
    JMP_TARGET(doubleprec);
nkeynes@669
  1973
    push_dr(FRn);
nkeynes@669
  1974
    push_dr(FRm);
nkeynes@377
  1975
    FDIVP_st(1);
nkeynes@669
  1976
    pop_dr(FRn);
nkeynes@380
  1977
    JMP_TARGET(end);
nkeynes@417
  1978
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1979
:}
nkeynes@375
  1980
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1981
    check_fpuen();
nkeynes@375
  1982
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1983
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1984
    JNE_rel8(doubleprec);
nkeynes@669
  1985
    push_fr( 0 );
nkeynes@669
  1986
    push_fr( FRm );
nkeynes@375
  1987
    FMULP_st(1);
nkeynes@669
  1988
    push_fr( FRn );
nkeynes@375
  1989
    FADDP_st(1);
nkeynes@669
  1990
    pop_fr( FRn );
nkeynes@669
  1991
    JMP_rel8(end);
nkeynes@380
  1992
    JMP_TARGET(doubleprec);
nkeynes@669
  1993
    push_dr( 0 );
nkeynes@669
  1994
    push_dr( FRm );
nkeynes@375
  1995
    FMULP_st(1);
nkeynes@669
  1996
    push_dr( FRn );
nkeynes@375
  1997
    FADDP_st(1);
nkeynes@669
  1998
    pop_dr( FRn );
nkeynes@380
  1999
    JMP_TARGET(end);
nkeynes@417
  2000
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2001
:}
nkeynes@375
  2002
nkeynes@377
  2003
FMUL FRm, FRn {:  
nkeynes@377
  2004
    check_fpuen();
nkeynes@377
  2005
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2006
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2007
    JNE_rel8(doubleprec);
nkeynes@669
  2008
    push_fr(FRm);
nkeynes@669
  2009
    push_fr(FRn);
nkeynes@377
  2010
    FMULP_st(1);
nkeynes@669
  2011
    pop_fr(FRn);
nkeynes@669
  2012
    JMP_rel8(end);
nkeynes@380
  2013
    JMP_TARGET(doubleprec);
nkeynes@669
  2014
    push_dr(FRm);
nkeynes@669
  2015
    push_dr(FRn);
nkeynes@377
  2016
    FMULP_st(1);
nkeynes@669
  2017
    pop_dr(FRn);
nkeynes@380
  2018
    JMP_TARGET(end);
nkeynes@417
  2019
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2020
:}
nkeynes@377
  2021
FNEG FRn {:  
nkeynes@377
  2022
    check_fpuen();
nkeynes@377
  2023
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2024
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2025
    JNE_rel8(doubleprec);
nkeynes@669
  2026
    push_fr(FRn);
nkeynes@377
  2027
    FCHS_st0();
nkeynes@669
  2028
    pop_fr(FRn);
nkeynes@669
  2029
    JMP_rel8(end);
nkeynes@380
  2030
    JMP_TARGET(doubleprec);
nkeynes@669
  2031
    push_dr(FRn);
nkeynes@377
  2032
    FCHS_st0();
nkeynes@669
  2033
    pop_dr(FRn);
nkeynes@380
  2034
    JMP_TARGET(end);
nkeynes@417
  2035
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2036
:}
nkeynes@377
  2037
FSRRA FRn {:  
nkeynes@377
  2038
    check_fpuen();
nkeynes@377
  2039
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2040
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2041
    JNE_rel8(end); // PR=0 only
nkeynes@377
  2042
    FLD1_st0();
nkeynes@669
  2043
    push_fr(FRn);
nkeynes@377
  2044
    FSQRT_st0();
nkeynes@377
  2045
    FDIVP_st(1);
nkeynes@669
  2046
    pop_fr(FRn);
nkeynes@380
  2047
    JMP_TARGET(end);
nkeynes@417
  2048
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2049
:}
nkeynes@377
  2050
FSQRT FRn {:  
nkeynes@377
  2051
    check_fpuen();
nkeynes@377
  2052
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2053
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2054
    JNE_rel8(doubleprec);
nkeynes@669
  2055
    push_fr(FRn);
nkeynes@377
  2056
    FSQRT_st0();
nkeynes@669
  2057
    pop_fr(FRn);
nkeynes@669
  2058
    JMP_rel8(end);
nkeynes@380
  2059
    JMP_TARGET(doubleprec);
nkeynes@669
  2060
    push_dr(FRn);
nkeynes@377
  2061
    FSQRT_st0();
nkeynes@669
  2062
    pop_dr(FRn);
nkeynes@380
  2063
    JMP_TARGET(end);
nkeynes@417
  2064
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2065
:}
nkeynes@377
  2066
FSUB FRm, FRn {:  
nkeynes@377
  2067
    check_fpuen();
nkeynes@377
  2068
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2069
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2070
    JNE_rel8(doubleprec);
nkeynes@669
  2071
    push_fr(FRn);
nkeynes@669
  2072
    push_fr(FRm);
nkeynes@388
  2073
    FSUBP_st(1);
nkeynes@669
  2074
    pop_fr(FRn);
nkeynes@669
  2075
    JMP_rel8(end);
nkeynes@380
  2076
    JMP_TARGET(doubleprec);
nkeynes@669
  2077
    push_dr(FRn);
nkeynes@669
  2078
    push_dr(FRm);
nkeynes@388
  2079
    FSUBP_st(1);
nkeynes@669
  2080
    pop_dr(FRn);
nkeynes@380
  2081
    JMP_TARGET(end);
nkeynes@417
  2082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2083
:}
nkeynes@377
  2084
nkeynes@377
  2085
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2086
    check_fpuen();
nkeynes@377
  2087
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2088
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2089
    JNE_rel8(doubleprec);
nkeynes@669
  2090
    push_fr(FRm);
nkeynes@669
  2091
    push_fr(FRn);
nkeynes@669
  2092
    JMP_rel8(end);
nkeynes@380
  2093
    JMP_TARGET(doubleprec);
nkeynes@669
  2094
    push_dr(FRm);
nkeynes@669
  2095
    push_dr(FRn);
nkeynes@382
  2096
    JMP_TARGET(end);
nkeynes@377
  2097
    FCOMIP_st(1);
nkeynes@377
  2098
    SETE_t();
nkeynes@377
  2099
    FPOP_st();
nkeynes@417
  2100
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2101
:}
nkeynes@377
  2102
FCMP/GT FRm, FRn {:  
nkeynes@377
  2103
    check_fpuen();
nkeynes@377
  2104
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2105
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2106
    JNE_rel8(doubleprec);
nkeynes@669
  2107
    push_fr(FRm);
nkeynes@669
  2108
    push_fr(FRn);
nkeynes@669
  2109
    JMP_rel8(end);
nkeynes@380
  2110
    JMP_TARGET(doubleprec);
nkeynes@669
  2111
    push_dr(FRm);
nkeynes@669
  2112
    push_dr(FRn);
nkeynes@380
  2113
    JMP_TARGET(end);
nkeynes@377
  2114
    FCOMIP_st(1);
nkeynes@377
  2115
    SETA_t();
nkeynes@377
  2116
    FPOP_st();
nkeynes@417
  2117
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2118
:}
nkeynes@377
  2119
nkeynes@377
  2120
FSCA FPUL, FRn {:  
nkeynes@377
  2121
    check_fpuen();
nkeynes@388
  2122
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2123
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2124
    JNE_rel8(doubleprec );
nkeynes@669
  2125
    LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@388
  2126
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2127
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2128
    JMP_TARGET(doubleprec);
nkeynes@417
  2129
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2130
:}
nkeynes@377
  2131
FIPR FVm, FVn {:  
nkeynes@377
  2132
    check_fpuen();
nkeynes@388
  2133
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2134
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2135
    JNE_rel8( doubleprec);
nkeynes@388
  2136
    
nkeynes@669
  2137
    push_fr( FVm<<2 );
nkeynes@669
  2138
    push_fr( FVn<<2 );
nkeynes@388
  2139
    FMULP_st(1);
nkeynes@669
  2140
    push_fr( (FVm<<2)+1);
nkeynes@669
  2141
    push_fr( (FVn<<2)+1);
nkeynes@388
  2142
    FMULP_st(1);
nkeynes@388
  2143
    FADDP_st(1);
nkeynes@669
  2144
    push_fr( (FVm<<2)+2);
nkeynes@669
  2145
    push_fr( (FVn<<2)+2);
nkeynes@388
  2146
    FMULP_st(1);
nkeynes@388
  2147
    FADDP_st(1);
nkeynes@669
  2148
    push_fr( (FVm<<2)+3);
nkeynes@669
  2149
    push_fr( (FVn<<2)+3);
nkeynes@388
  2150
    FMULP_st(1);
nkeynes@388
  2151
    FADDP_st(1);
nkeynes@669
  2152
    pop_fr( (FVn<<2)+3);
nkeynes@388
  2153
    JMP_TARGET(doubleprec);
nkeynes@417
  2154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2155
:}
nkeynes@377
  2156
FTRV XMTRX, FVn {:  
nkeynes@377
  2157
    check_fpuen();
nkeynes@388
  2158
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2159
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2160
    JNE_rel8( doubleprec );
nkeynes@669
  2161
    LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
nkeynes@669
  2162
    call_func1( sh4_ftrv, R_EDX );  // 12
nkeynes@388
  2163
    JMP_TARGET(doubleprec);
nkeynes@417
  2164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2165
:}
nkeynes@377
  2166
nkeynes@377
  2167
FRCHG {:  
nkeynes@377
  2168
    check_fpuen();
nkeynes@377
  2169
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2170
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2171
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2172
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2174
:}
nkeynes@377
  2175
FSCHG {:  
nkeynes@377
  2176
    check_fpuen();
nkeynes@377
  2177
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2178
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2179
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2181
:}
nkeynes@359
  2182
nkeynes@359
  2183
/* Processor control instructions */
nkeynes@368
  2184
LDC Rm, SR {:
nkeynes@386
  2185
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2186
	SLOTILLEGAL();
nkeynes@386
  2187
    } else {
nkeynes@386
  2188
	check_priv();
nkeynes@386
  2189
	load_reg( R_EAX, Rm );
nkeynes@386
  2190
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2191
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2192
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2193
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2194
    }
nkeynes@368
  2195
:}
nkeynes@359
  2196
LDC Rm, GBR {: 
nkeynes@359
  2197
    load_reg( R_EAX, Rm );
nkeynes@359
  2198
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2199
:}
nkeynes@359
  2200
LDC Rm, VBR {:  
nkeynes@386
  2201
    check_priv();
nkeynes@359
  2202
    load_reg( R_EAX, Rm );
nkeynes@359
  2203
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2204
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2205
:}
nkeynes@359
  2206
LDC Rm, SSR {:  
nkeynes@386
  2207
    check_priv();
nkeynes@359
  2208
    load_reg( R_EAX, Rm );
nkeynes@359
  2209
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2210
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2211
:}
nkeynes@359
  2212
LDC Rm, SGR {:  
nkeynes@386
  2213
    check_priv();
nkeynes@359
  2214
    load_reg( R_EAX, Rm );
nkeynes@359
  2215
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2216
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2217
:}
nkeynes@359
  2218
LDC Rm, SPC {:  
nkeynes@386
  2219
    check_priv();
nkeynes@359
  2220
    load_reg( R_EAX, Rm );
nkeynes@359
  2221
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2223
:}
nkeynes@359
  2224
LDC Rm, DBR {:  
nkeynes@386
  2225
    check_priv();
nkeynes@359
  2226
    load_reg( R_EAX, Rm );
nkeynes@359
  2227
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2229
:}
nkeynes@374
  2230
LDC Rm, Rn_BANK {:  
nkeynes@386
  2231
    check_priv();
nkeynes@374
  2232
    load_reg( R_EAX, Rm );
nkeynes@374
  2233
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2235
:}
nkeynes@359
  2236
LDC.L @Rm+, GBR {:  
nkeynes@359
  2237
    load_reg( R_EAX, Rm );
nkeynes@395
  2238
    check_ralign32( R_EAX );
nkeynes@586
  2239
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2240
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2241
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2242
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2244
:}
nkeynes@368
  2245
LDC.L @Rm+, SR {:
nkeynes@386
  2246
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2247
	SLOTILLEGAL();
nkeynes@386
  2248
    } else {
nkeynes@586
  2249
	check_priv();
nkeynes@386
  2250
	load_reg( R_EAX, Rm );
nkeynes@395
  2251
	check_ralign32( R_EAX );
nkeynes@586
  2252
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2253
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2254
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2255
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2256
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2257
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2258
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2259
    }
nkeynes@359
  2260
:}
nkeynes@359
  2261
LDC.L @Rm+, VBR {:  
nkeynes@586
  2262
    check_priv();
nkeynes@359
  2263
    load_reg( R_EAX, Rm );
nkeynes@395
  2264
    check_ralign32( R_EAX );
nkeynes@586
  2265
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2266
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2267
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2268
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2269
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2270
:}
nkeynes@359
  2271
LDC.L @Rm+, SSR {:
nkeynes@586
  2272
    check_priv();
nkeynes@359
  2273
    load_reg( R_EAX, Rm );
nkeynes@416
  2274
    check_ralign32( R_EAX );
nkeynes@586
  2275
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2276
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2277
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2278
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2279
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2280
:}
nkeynes@359
  2281
LDC.L @Rm+, SGR {:  
nkeynes@586
  2282
    check_priv();
nkeynes@359
  2283
    load_reg( R_EAX, Rm );
nkeynes@395
  2284
    check_ralign32( R_EAX );
nkeynes@586
  2285
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2286
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2287
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2288
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC.L @Rm+, SPC {:  
nkeynes@586
  2292
    check_priv();
nkeynes@359
  2293
    load_reg( R_EAX, Rm );
nkeynes@395
  2294
    check_ralign32( R_EAX );
nkeynes@586
  2295
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2296
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2297
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2298
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2299
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2300
:}
nkeynes@359
  2301
LDC.L @Rm+, DBR {:  
nkeynes@586
  2302
    check_priv();
nkeynes@359
  2303
    load_reg( R_EAX, Rm );
nkeynes@395
  2304
    check_ralign32( R_EAX );
nkeynes@586
  2305
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2306
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2307
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2308
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2309
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2310
:}
nkeynes@359
  2311
LDC.L @Rm+, Rn_BANK {:  
nkeynes@586
  2312
    check_priv();
nkeynes@374
  2313
    load_reg( R_EAX, Rm );
nkeynes@395
  2314
    check_ralign32( R_EAX );
nkeynes@586
  2315
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2316
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2317
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2318
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2320
:}
nkeynes@626
  2321
LDS Rm, FPSCR {:
nkeynes@626
  2322
    check_fpuen();
nkeynes@359
  2323
    load_reg( R_EAX, Rm );
nkeynes@669
  2324
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2325
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2326
:}
nkeynes@359
  2327
LDS.L @Rm+, FPSCR {:  
nkeynes@626
  2328
    check_fpuen();
nkeynes@359
  2329
    load_reg( R_EAX, Rm );
nkeynes@395
  2330
    check_ralign32( R_EAX );
nkeynes@586
  2331
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2332
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2333
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2334
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2336
:}
nkeynes@359
  2337
LDS Rm, FPUL {:  
nkeynes@626
  2338
    check_fpuen();
nkeynes@359
  2339
    load_reg( R_EAX, Rm );
nkeynes@359
  2340
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2341
:}
nkeynes@359
  2342
LDS.L @Rm+, FPUL {:  
nkeynes@626
  2343
    check_fpuen();
nkeynes@359
  2344
    load_reg( R_EAX, Rm );
nkeynes@395
  2345
    check_ralign32( R_EAX );
nkeynes@586
  2346
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2347
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2348
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2349
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2351
:}
nkeynes@359
  2352
LDS Rm, MACH {: 
nkeynes@359
  2353
    load_reg( R_EAX, Rm );
nkeynes@359
  2354
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2355
:}
nkeynes@359
  2356
LDS.L @Rm+, MACH {:  
nkeynes@359
  2357
    load_reg( R_EAX, Rm );
nkeynes@395
  2358
    check_ralign32( R_EAX );
nkeynes@586
  2359
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2360
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2361
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2362
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2364
:}
nkeynes@359
  2365
LDS Rm, MACL {:  
nkeynes@359
  2366
    load_reg( R_EAX, Rm );
nkeynes@359
  2367
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2368
:}
nkeynes@359
  2369
LDS.L @Rm+, MACL {:  
nkeynes@359
  2370
    load_reg( R_EAX, Rm );
nkeynes@395
  2371
    check_ralign32( R_EAX );
nkeynes@586
  2372
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2373
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2374
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2375
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2377
:}
nkeynes@359
  2378
LDS Rm, PR {:  
nkeynes@359
  2379
    load_reg( R_EAX, Rm );
nkeynes@359
  2380
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2381
:}
nkeynes@359
  2382
LDS.L @Rm+, PR {:  
nkeynes@359
  2383
    load_reg( R_EAX, Rm );
nkeynes@395
  2384
    check_ralign32( R_EAX );
nkeynes@586
  2385
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2386
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2387
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2388
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2390
:}
nkeynes@550
  2391
LDTLB {:  
nkeynes@553
  2392
    call_func0( MMU_ldtlb );
nkeynes@550
  2393
:}
nkeynes@359
  2394
OCBI @Rn {:  :}
nkeynes@359
  2395
OCBP @Rn {:  :}
nkeynes@359
  2396
OCBWB @Rn {:  :}
nkeynes@374
  2397
PREF @Rn {:
nkeynes@374
  2398
    load_reg( R_EAX, Rn );
nkeynes@532
  2399
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2400
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2401
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2402
    JNE_rel8(end);
nkeynes@532
  2403
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2404
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2405
    JE_exc(-1);
nkeynes@380
  2406
    JMP_TARGET(end);
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2408
:}
nkeynes@388
  2409
SLEEP {: 
nkeynes@388
  2410
    check_priv();
nkeynes@388
  2411
    call_func0( sh4_sleep );
nkeynes@417
  2412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2413
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2414
    return 2;
nkeynes@388
  2415
:}
nkeynes@386
  2416
STC SR, Rn {:
nkeynes@386
  2417
    check_priv();
nkeynes@386
  2418
    call_func0(sh4_read_sr);
nkeynes@386
  2419
    store_reg( R_EAX, Rn );
nkeynes@417
  2420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2421
:}
nkeynes@359
  2422
STC GBR, Rn {:  
nkeynes@359
  2423
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2424
    store_reg( R_EAX, Rn );
nkeynes@359
  2425
:}
nkeynes@359
  2426
STC VBR, Rn {:  
nkeynes@386
  2427
    check_priv();
nkeynes@359
  2428
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2429
    store_reg( R_EAX, Rn );
nkeynes@417
  2430
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2431
:}
nkeynes@359
  2432
STC SSR, Rn {:  
nkeynes@386
  2433
    check_priv();
nkeynes@359
  2434
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2435
    store_reg( R_EAX, Rn );
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2437
:}
nkeynes@359
  2438
STC SPC, Rn {:  
nkeynes@386
  2439
    check_priv();
nkeynes@359
  2440
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2441
    store_reg( R_EAX, Rn );
nkeynes@417
  2442
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2443
:}
nkeynes@359
  2444
STC SGR, Rn {:  
nkeynes@386
  2445
    check_priv();
nkeynes@359
  2446
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2447
    store_reg( R_EAX, Rn );
nkeynes@417
  2448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2449
:}
nkeynes@359
  2450
STC DBR, Rn {:  
nkeynes@386
  2451
    check_priv();
nkeynes@359
  2452
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2453
    store_reg( R_EAX, Rn );
nkeynes@417
  2454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2455
:}
nkeynes@374
  2456
STC Rm_BANK, Rn {:
nkeynes@386
  2457
    check_priv();
nkeynes@374
  2458
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2459
    store_reg( R_EAX, Rn );
nkeynes@417
  2460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2461
:}
nkeynes@374
  2462
STC.L SR, @-Rn {:
nkeynes@586
  2463
    check_priv();
nkeynes@586
  2464
    load_reg( R_EAX, Rn );
nkeynes@586
  2465
    check_walign32( R_EAX );
nkeynes@586
  2466
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2467
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2468
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2469
    call_func0( sh4_read_sr );
nkeynes@586
  2470
    POP_realigned_r32( R_ECX );
nkeynes@586
  2471
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2472
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2473
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2474
:}
nkeynes@359
  2475
STC.L VBR, @-Rn {:  
nkeynes@586
  2476
    check_priv();
nkeynes@586
  2477
    load_reg( R_EAX, Rn );
nkeynes@586
  2478
    check_walign32( R_EAX );
nkeynes@586
  2479
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2480
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2481
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2482
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2483
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2484
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2485
:}
nkeynes@359
  2486
STC.L SSR, @-Rn {:  
nkeynes@586
  2487
    check_priv();
nkeynes@586
  2488
    load_reg( R_EAX, Rn );
nkeynes@586
  2489
    check_walign32( R_EAX );
nkeynes@586
  2490
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2491
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2492
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2493
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2494
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2496
:}
nkeynes@416
  2497
STC.L SPC, @-Rn {:
nkeynes@586
  2498
    check_priv();
nkeynes@586
  2499
    load_reg( R_EAX, Rn );
nkeynes@586
  2500
    check_walign32( R_EAX );
nkeynes@586
  2501
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2502
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2503
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2504
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2505
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2507
:}
nkeynes@359
  2508
STC.L SGR, @-Rn {:  
nkeynes@586
  2509
    check_priv();
nkeynes@586
  2510
    load_reg( R_EAX, Rn );
nkeynes@586
  2511
    check_walign32( R_EAX );
nkeynes@586
  2512
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2513
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2514
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2515
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2516
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2518
:}
nkeynes@359
  2519
STC.L DBR, @-Rn {:  
nkeynes@586
  2520
    check_priv();
nkeynes@586
  2521
    load_reg( R_EAX, Rn );
nkeynes@586
  2522
    check_walign32( R_EAX );
nkeynes@586
  2523
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2524
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2525
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2526
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2527
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2528
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2529
:}
nkeynes@374
  2530
STC.L Rm_BANK, @-Rn {:  
nkeynes@586
  2531
    check_priv();
nkeynes@586
  2532
    load_reg( R_EAX, Rn );
nkeynes@586
  2533
    check_walign32( R_EAX );
nkeynes@586
  2534
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2535
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2536
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2537
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2538
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2539
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2540
:}
nkeynes@359
  2541
STC.L GBR, @-Rn {:  
nkeynes@586
  2542
    load_reg( R_EAX, Rn );
nkeynes@586
  2543
    check_walign32( R_EAX );
nkeynes@586
  2544
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2545
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2546
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2547
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2548
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2549
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2550
:}
nkeynes@359
  2551
STS FPSCR, Rn {:  
nkeynes@626
  2552
    check_fpuen();
nkeynes@359
  2553
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2554
    store_reg( R_EAX, Rn );
nkeynes@359
  2555
:}
nkeynes@359
  2556
STS.L FPSCR, @-Rn {:  
nkeynes@626
  2557
    check_fpuen();
nkeynes@586
  2558
    load_reg( R_EAX, Rn );
nkeynes@586
  2559
    check_walign32( R_EAX );
nkeynes@586
  2560
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2561
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2562
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2563
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2564
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2565
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2566
:}
nkeynes@359
  2567
STS FPUL, Rn {:  
nkeynes@626
  2568
    check_fpuen();
nkeynes@359
  2569
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2570
    store_reg( R_EAX, Rn );
nkeynes@359
  2571
:}
nkeynes@359
  2572
STS.L FPUL, @-Rn {:  
nkeynes@626
  2573
    check_fpuen();
nkeynes@586
  2574
    load_reg( R_EAX, Rn );
nkeynes@586
  2575
    check_walign32( R_EAX );
nkeynes@586
  2576
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2577
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2578
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2579
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2580
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2582
:}
nkeynes@359
  2583
STS MACH, Rn {:  
nkeynes@359
  2584
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2585
    store_reg( R_EAX, Rn );
nkeynes@359
  2586
:}
nkeynes@359
  2587
STS.L MACH, @-Rn {:  
nkeynes@586
  2588
    load_reg( R_EAX, Rn );
nkeynes@586
  2589
    check_walign32( R_EAX );
nkeynes@586
  2590
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2591
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2592
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2593
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2594
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2595
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2596
:}
nkeynes@359
  2597
STS MACL, Rn {:  
nkeynes@359
  2598
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2599
    store_reg( R_EAX, Rn );
nkeynes@359
  2600
:}
nkeynes@359
  2601
STS.L MACL, @-Rn {:  
nkeynes@586
  2602
    load_reg( R_EAX, Rn );
nkeynes@586
  2603
    check_walign32( R_EAX );
nkeynes@586
  2604
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2605
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2606
    load_spreg( R_EDX, R_MACL );
nkeynes@586
  2607
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2608
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2609
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2610
:}
nkeynes@359
  2611
STS PR, Rn {:  
nkeynes@359
  2612
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2613
    store_reg( R_EAX, Rn );
nkeynes@359
  2614
:}
nkeynes@359
  2615
STS.L PR, @-Rn {:  
nkeynes@586
  2616
    load_reg( R_EAX, Rn );
nkeynes@586
  2617
    check_walign32( R_EAX );
nkeynes@586
  2618
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2619
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2620
    load_spreg( R_EDX, R_PR );
nkeynes@586
  2621
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2622
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2623
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2624
:}
nkeynes@359
  2625
nkeynes@359
  2626
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2627
%%
nkeynes@590
  2628
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359
  2629
    return 0;
nkeynes@359
  2630
}
.