nkeynes@31 | 1 | /**
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nkeynes@493 | 2 | * $Id: ide.h,v 1.14 2007-11-06 08:35:33 nkeynes Exp $
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nkeynes@2 | 3 | *
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nkeynes@31 | 4 | * This file defines the interface and structures of the dreamcast's IDE
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nkeynes@31 | 5 | * port. Note that the register definitions are in asic.h, as the registers
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nkeynes@31 | 6 | * fall into the general ASIC ranges (and I don't want to use smaller pages
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nkeynes@31 | 7 | * at this stage). The registers here are exactly as per the ATA
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nkeynes@31 | 8 | * specifications, which makes things a little easier.
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nkeynes@2 | 9 | *
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nkeynes@31 | 10 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 11 | *
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nkeynes@31 | 12 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 13 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 14 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 15 | * (at your option) any later version.
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nkeynes@31 | 16 | *
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nkeynes@31 | 17 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 20 | * GNU General Public License for more details.
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nkeynes@2 | 21 | */
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nkeynes@31 | 22 |
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nkeynes@2 | 23 | #ifndef dream_ide_H
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nkeynes@2 | 24 | #define dream_ide_H 1
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nkeynes@2 | 25 |
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nkeynes@2 | 26 | #include "dream.h"
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nkeynes@2 | 27 |
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nkeynes@493 | 28 | #define GDROM_SENSE_LENGTH 10
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nkeynes@493 | 29 | #define GDROM_MODE_LENGTH 32
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nkeynes@493 | 30 |
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nkeynes@2 | 31 | struct ide_registers {
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nkeynes@152 | 32 | /* IDE interface registers */
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nkeynes@2 | 33 | uint8_t status; /* A05F709C + A05F7018 Read-only */
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nkeynes@2 | 34 | uint8_t control; /* A05F7018 Write-only 01110 */
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nkeynes@2 | 35 | uint8_t error; /* A05F7084 Read-only 10001 */
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nkeynes@2 | 36 | uint8_t feature; /* A05F7084 Write-only 10001 */
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nkeynes@2 | 37 | uint8_t count; /* A05F7088 Read/Write 10010 */
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nkeynes@2 | 38 | uint8_t disc; /* A05F708C Read-only 10011 */
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nkeynes@2 | 39 | uint8_t lba0; /* A05F708C Write-only 10011 (NB: Presumed, TBV */
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nkeynes@2 | 40 | uint8_t lba1; /* A05F7090 Read/Write 10100 */
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nkeynes@2 | 41 | uint8_t lba2; /* A05F7094 Read/Write 10101 */
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nkeynes@2 | 42 | uint8_t device; /* A05F7098 Read/Write 10110 */
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nkeynes@2 | 43 | uint8_t command; /* A05F709C Write-only 10111 */
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nkeynes@152 | 44 |
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nkeynes@152 | 45 | /* Internal IDE state */
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nkeynes@138 | 46 | uint8_t intrq_pending; /* Flag to indicate if the INTRQ line is active */
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nkeynes@245 | 47 | gboolean interface_enabled;
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nkeynes@254 | 48 | gboolean was_reset; /* Flag indicating that the device has just been reset */
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nkeynes@493 | 49 | uint32_t state;
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nkeynes@493 | 50 | uint32_t last_packet_command; /* Identifies the command executing during a r/w cycle */
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nkeynes@138 | 51 |
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nkeynes@152 | 52 | /* Sense response for the last executed packet command */
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nkeynes@493 | 53 | unsigned char gdrom_sense[GDROM_SENSE_LENGTH];
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nkeynes@493 | 54 | unsigned char gdrom_mode[GDROM_MODE_LENGTH];
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nkeynes@152 | 55 |
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nkeynes@152 | 56 | /* offset in the buffer of the next word to read/write, or -1
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nkeynes@152 | 57 | * if inactive.
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nkeynes@152 | 58 | */
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nkeynes@493 | 59 | int32_t data_offset;
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nkeynes@493 | 60 | int32_t data_length;
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nkeynes@152 | 61 |
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nkeynes@245 | 62 | /* Status reporting information */
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nkeynes@245 | 63 | uint8_t last_read_track;
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nkeynes@493 | 64 | uint32_t current_lba;
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nkeynes@493 | 65 | uint32_t current_mode;
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nkeynes@342 | 66 | uint32_t sectors_left; /* sectors left after current read */
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nkeynes@2 | 67 | };
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nkeynes@2 | 68 |
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nkeynes@152 | 69 | #define IDE_STATE_IDLE 0
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nkeynes@152 | 70 | #define IDE_STATE_CMD_WRITE 1
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nkeynes@152 | 71 | #define IDE_STATE_PIO_READ 2
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nkeynes@152 | 72 | #define IDE_STATE_PIO_WRITE 3
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nkeynes@152 | 73 | #define IDE_STATE_DMA_READ 4
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nkeynes@152 | 74 | #define IDE_STATE_DMA_WRITE 5
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nkeynes@152 | 75 | #define IDE_STATE_BUSY 6
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nkeynes@152 | 76 |
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nkeynes@152 | 77 | /* Flag bits */
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nkeynes@152 | 78 | #define IDE_STATUS_BSY 0x80 /* Busy */
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nkeynes@152 | 79 | #define IDE_STATUS_DRDY 0x40 /* Device ready */
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nkeynes@152 | 80 | #define IDE_STATUS_DMRD 0x20 /* DMA Request */
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nkeynes@152 | 81 | #define IDE_STATUS_SERV 0x10
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nkeynes@152 | 82 | #define IDE_STATUS_DRQ 0x08
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nkeynes@152 | 83 | #define IDE_STATUS_CHK 0x01 /* Check condition (ie error) */
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nkeynes@2 | 84 |
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nkeynes@149 | 85 | #define IDE_FEAT_DMA 0x01
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nkeynes@149 | 86 | #define IDE_FEAT_OVL 0x02
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nkeynes@149 | 87 |
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nkeynes@152 | 88 | #define IDE_COUNT_CD 0x01 /* Command (1)/Data (0) */
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nkeynes@257 | 89 | #define IDE_COUNT_IO 0x02 /* Input (1)/Output (0) */
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nkeynes@152 | 90 | #define IDE_COUNT_REL 0x04 /* Release device */
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nkeynes@149 | 91 |
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nkeynes@149 | 92 |
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nkeynes@2 | 93 | #define IDE_CTL_RESET 0x04
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nkeynes@2 | 94 | #define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
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nkeynes@2 | 95 |
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nkeynes@240 | 96 | #define IDE_CMD_NOP 0x00
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nkeynes@2 | 97 | #define IDE_CMD_RESET_DEVICE 0x08
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nkeynes@2 | 98 | #define IDE_CMD_PACKET 0xA0
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nkeynes@2 | 99 | #define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
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nkeynes@2 | 100 | #define IDE_CMD_SERVICE 0xA2
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nkeynes@2 | 101 | #define IDE_CMD_SET_FEATURE 0xEF
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nkeynes@2 | 102 |
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nkeynes@47 | 103 | #define IDE_FEAT_SET_TRANSFER_MODE 0x03
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nkeynes@47 | 104 | #define IDE_XFER_PIO 0x00
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nkeynes@47 | 105 | #define IDE_XFER_PIO_FLOW 0x08
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nkeynes@47 | 106 | #define IDE_XFER_MULTI_DMA 0x20
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nkeynes@47 | 107 | #define IDE_XFER_ULTRA_DMA 0x40
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nkeynes@47 | 108 |
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nkeynes@2 | 109 | extern struct ide_registers idereg;
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nkeynes@2 | 110 |
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nkeynes@2 | 111 | /* Note: control can be written at any time - all other registers are writable
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nkeynes@2 | 112 | * only when ide_can_write_regs() is true
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nkeynes@2 | 113 | */
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nkeynes@254 | 114 | #define ide_can_write_regs() ((idereg.status&0x80)==0)
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nkeynes@125 | 115 | #define IS_IDE_IRQ_ENABLED() ((idereg.control&0x02)==0)
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nkeynes@2 | 116 |
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nkeynes@2 | 117 |
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nkeynes@2 | 118 | uint16_t ide_read_data_pio(void);
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nkeynes@152 | 119 | void ide_write_data_pio( uint16_t value );
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nkeynes@152 | 120 | uint32_t ide_read_data_dma( uint32_t addr, uint32_t length );
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nkeynes@125 | 121 | uint8_t ide_read_status(void);
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nkeynes@342 | 122 | uint8_t ide_get_drive_status(void);
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nkeynes@493 | 123 | void ide_write_buffer( unsigned char *data, uint32_t length );
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nkeynes@2 | 124 |
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nkeynes@2 | 125 | void ide_write_command( uint8_t command );
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nkeynes@2 | 126 | void ide_write_control( uint8_t value );
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nkeynes@152 | 127 |
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nkeynes@152 | 128 | void ide_dma_read_req( uint32_t addr, uint32_t length );
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nkeynes@2 | 129 | #endif
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