nkeynes@359 | 1 | /**
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nkeynes@408 | 2 | * $Id: sh4x86.c,v 1.15 2007-09-28 07:27:20 nkeynes Exp $
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@368 | 28 | #include "sh4/sh4core.h"
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nkeynes@368 | 29 | #include "sh4/sh4trans.h"
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nkeynes@388 | 30 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 31 | #include "sh4/x86op.h"
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nkeynes@368 | 32 | #include "clock.h"
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nkeynes@368 | 33 |
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nkeynes@368 | 34 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 35 |
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nkeynes@368 | 36 | /**
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nkeynes@368 | 37 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 38 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 39 | * sh4_translate_end_block()
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nkeynes@368 | 40 | */
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nkeynes@368 | 41 | struct sh4_x86_state {
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nkeynes@368 | 42 | gboolean in_delay_slot;
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nkeynes@368 | 43 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 44 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@408 | 45 | uint32_t block_start_pc;
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nkeynes@368 | 46 |
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nkeynes@368 | 47 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@368 | 48 | uint32_t **backpatch_list;
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nkeynes@368 | 49 | uint32_t backpatch_posn;
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nkeynes@368 | 50 | uint32_t backpatch_size;
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nkeynes@368 | 51 | };
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nkeynes@368 | 52 |
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nkeynes@368 | 53 | #define EXIT_DATA_ADDR_READ 0
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nkeynes@368 | 54 | #define EXIT_DATA_ADDR_WRITE 7
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nkeynes@368 | 55 | #define EXIT_ILLEGAL 14
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nkeynes@368 | 56 | #define EXIT_SLOT_ILLEGAL 21
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nkeynes@368 | 57 | #define EXIT_FPU_DISABLED 28
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nkeynes@368 | 58 | #define EXIT_SLOT_FPU_DISABLED 35
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nkeynes@368 | 59 |
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nkeynes@368 | 60 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 61 |
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nkeynes@388 | 62 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 63 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 64 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 65 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 66 |
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nkeynes@368 | 67 | void sh4_x86_init()
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nkeynes@368 | 68 | {
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nkeynes@368 | 69 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@368 | 70 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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nkeynes@368 | 71 | }
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nkeynes@368 | 72 |
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nkeynes@368 | 73 |
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nkeynes@368 | 74 | static void sh4_x86_add_backpatch( uint8_t *ptr )
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nkeynes@368 | 75 | {
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nkeynes@368 | 76 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 77 | sh4_x86.backpatch_size <<= 1;
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nkeynes@368 | 78 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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nkeynes@368 | 79 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 80 | }
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nkeynes@368 | 81 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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nkeynes@368 | 82 | }
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nkeynes@368 | 83 |
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nkeynes@368 | 84 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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nkeynes@368 | 85 | {
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nkeynes@368 | 86 | unsigned int i;
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nkeynes@368 | 87 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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nkeynes@374 | 88 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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nkeynes@368 | 89 | }
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nkeynes@368 | 90 | }
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nkeynes@368 | 91 |
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nkeynes@359 | 92 | /**
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nkeynes@359 | 93 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 94 | */
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nkeynes@359 | 95 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 96 | {
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nkeynes@359 | 97 | /* mov [bp+n], reg */
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nkeynes@361 | 98 | OP(0x8B);
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nkeynes@361 | 99 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 100 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 101 | }
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nkeynes@359 | 102 |
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nkeynes@374 | 103 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 104 | {
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nkeynes@374 | 105 | OP(0x0F);
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nkeynes@374 | 106 | OP(0xBF);
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nkeynes@374 | 107 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 108 | }
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nkeynes@368 | 109 |
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nkeynes@374 | 110 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 111 | {
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nkeynes@374 | 112 | OP(0x0F);
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nkeynes@374 | 113 | OP(0xB7);
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nkeynes@374 | 114 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 115 |
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nkeynes@368 | 116 | }
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nkeynes@368 | 117 |
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nkeynes@380 | 118 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 119 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 120 | /**
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nkeynes@359 | 121 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 122 | */
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nkeynes@359 | 123 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 124 | /* mov #value, reg */
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nkeynes@359 | 125 | OP(0xB8 + x86reg);
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nkeynes@359 | 126 | OP32(value);
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nkeynes@359 | 127 | }
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nkeynes@359 | 128 |
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nkeynes@359 | 129 | /**
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nkeynes@359 | 130 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 131 | */
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nkeynes@359 | 132 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 133 | /* mov reg, [bp+n] */
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nkeynes@361 | 134 | OP(0x89);
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nkeynes@361 | 135 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 136 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 137 | }
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nkeynes@374 | 138 |
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nkeynes@374 | 139 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 140 |
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nkeynes@375 | 141 | /**
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nkeynes@375 | 142 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 143 | * register (eg for register-to-register moves)
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nkeynes@375 | 144 | */
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nkeynes@375 | 145 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 146 | {
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nkeynes@375 | 147 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 148 | }
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nkeynes@375 | 149 |
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nkeynes@375 | 150 | /**
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nkeynes@375 | 151 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 152 | * register (eg for register-to-register moves)
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nkeynes@375 | 153 | */
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nkeynes@375 | 154 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 155 | {
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nkeynes@375 | 156 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 157 | }
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nkeynes@375 | 158 |
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nkeynes@375 | 159 |
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nkeynes@375 | 160 | /**
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nkeynes@375 | 161 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 162 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 163 | * NB: 12 bytes
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nkeynes@375 | 164 | */
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nkeynes@374 | 165 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 166 | {
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nkeynes@386 | 167 | NOT_r32( bankreg );
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nkeynes@374 | 168 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 169 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 170 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 171 | }
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nkeynes@374 | 172 |
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nkeynes@375 | 173 | /**
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nkeynes@386 | 174 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 175 | */
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nkeynes@386 | 176 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 177 | {
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nkeynes@386 | 178 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 179 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 180 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 181 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 182 | }
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nkeynes@386 | 183 | /**
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nkeynes@377 | 184 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 185 | */
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nkeynes@377 | 186 | static inline void push_fpul( )
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nkeynes@377 | 187 | {
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nkeynes@377 | 188 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 189 | }
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nkeynes@377 | 190 |
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nkeynes@377 | 191 | /**
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nkeynes@377 | 192 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 193 | */
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nkeynes@377 | 194 | static inline void pop_fpul( )
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nkeynes@377 | 195 | {
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nkeynes@377 | 196 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 197 | }
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nkeynes@377 | 198 |
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nkeynes@377 | 199 | /**
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nkeynes@375 | 200 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 201 | * with the location of the current fp bank.
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nkeynes@375 | 202 | */
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nkeynes@374 | 203 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 204 | {
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nkeynes@374 | 205 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 206 | }
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nkeynes@374 | 207 |
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nkeynes@375 | 208 | /**
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nkeynes@375 | 209 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 210 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 211 | */
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nkeynes@374 | 212 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 213 | {
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nkeynes@374 | 214 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 215 | }
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nkeynes@374 | 216 |
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nkeynes@375 | 217 | /**
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nkeynes@375 | 218 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 219 | * with the location of the current fp bank.
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nkeynes@375 | 220 | */
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nkeynes@374 | 221 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 222 | {
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nkeynes@377 | 223 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 224 | }
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nkeynes@374 | 225 |
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nkeynes@374 | 226 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 227 | {
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nkeynes@377 | 228 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 229 | }
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nkeynes@374 | 230 |
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nkeynes@361 | 231 | /**
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nkeynes@361 | 232 | * Note: clobbers EAX to make the indirect call - this isn't usually
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nkeynes@361 | 233 | * a problem since the callee will usually clobber it anyway.
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nkeynes@361 | 234 | */
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nkeynes@361 | 235 | static inline void call_func0( void *ptr )
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nkeynes@361 | 236 | {
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nkeynes@361 | 237 | load_imm32(R_EAX, (uint32_t)ptr);
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nkeynes@368 | 238 | CALL_r32(R_EAX);
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nkeynes@361 | 239 | }
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nkeynes@361 | 240 |
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nkeynes@361 | 241 | static inline void call_func1( void *ptr, int arg1 )
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nkeynes@361 | 242 | {
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nkeynes@361 | 243 | PUSH_r32(arg1);
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nkeynes@361 | 244 | call_func0(ptr);
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nkeynes@377 | 245 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@361 | 246 | }
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nkeynes@361 | 247 |
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nkeynes@361 | 248 | static inline void call_func2( void *ptr, int arg1, int arg2 )
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nkeynes@361 | 249 | {
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nkeynes@361 | 250 | PUSH_r32(arg2);
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nkeynes@361 | 251 | PUSH_r32(arg1);
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nkeynes@361 | 252 | call_func0(ptr);
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nkeynes@377 | 253 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 254 | }
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nkeynes@375 | 255 |
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nkeynes@375 | 256 | /**
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nkeynes@375 | 257 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
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nkeynes@375 | 258 | * the second in arg2b
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nkeynes@375 | 259 | * NB: 30 bytes
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nkeynes@375 | 260 | */
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nkeynes@375 | 261 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 262 | {
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nkeynes@375 | 263 | ADD_imm8s_r32( 4, addr );
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nkeynes@386 | 264 | PUSH_r32(arg2b);
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nkeynes@375 | 265 | PUSH_r32(addr);
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nkeynes@375 | 266 | ADD_imm8s_r32( -4, addr );
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nkeynes@386 | 267 | PUSH_r32(arg2a);
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nkeynes@375 | 268 | PUSH_r32(addr);
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nkeynes@375 | 269 | call_func0(sh4_write_long);
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nkeynes@377 | 270 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 271 | call_func0(sh4_write_long);
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nkeynes@377 | 272 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 273 | }
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nkeynes@375 | 274 |
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nkeynes@375 | 275 | /**
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nkeynes@375 | 276 | * Read a double (64-bit) value from memory, writing the first word into arg2a
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nkeynes@375 | 277 | * and the second into arg2b. The addr must not be in EAX
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nkeynes@375 | 278 | * NB: 27 bytes
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nkeynes@375 | 279 | */
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nkeynes@375 | 280 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 281 | {
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nkeynes@375 | 282 | PUSH_r32(addr);
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nkeynes@375 | 283 | call_func0(sh4_read_long);
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nkeynes@375 | 284 | POP_r32(addr);
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nkeynes@375 | 285 | PUSH_r32(R_EAX);
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nkeynes@375 | 286 | ADD_imm8s_r32( 4, addr );
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nkeynes@375 | 287 | PUSH_r32(addr);
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nkeynes@375 | 288 | call_func0(sh4_read_long);
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nkeynes@377 | 289 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@375 | 290 | MOV_r32_r32( R_EAX, arg2b );
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nkeynes@375 | 291 | POP_r32(arg2a);
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nkeynes@361 | 292 | }
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nkeynes@361 | 293 |
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nkeynes@368 | 294 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@368 | 295 | static void check_priv( )
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nkeynes@368 | 296 | {
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nkeynes@368 | 297 | if( !sh4_x86.priv_checked ) {
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nkeynes@368 | 298 | sh4_x86.priv_checked = TRUE;
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nkeynes@368 | 299 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 300 | AND_imm32_r32( SR_MD, R_EAX );
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nkeynes@368 | 301 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 302 | JE_exit( EXIT_SLOT_ILLEGAL );
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nkeynes@368 | 303 | } else {
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nkeynes@368 | 304 | JE_exit( EXIT_ILLEGAL );
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nkeynes@368 | 305 | }
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nkeynes@368 | 306 | }
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nkeynes@368 | 307 | }
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nkeynes@368 | 308 |
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nkeynes@368 | 309 | static void check_fpuen( )
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nkeynes@368 | 310 | {
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nkeynes@368 | 311 | if( !sh4_x86.fpuen_checked ) {
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nkeynes@368 | 312 | sh4_x86.fpuen_checked = TRUE;
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nkeynes@368 | 313 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 314 | AND_imm32_r32( SR_FD, R_EAX );
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nkeynes@368 | 315 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 316 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
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nkeynes@368 | 317 | } else {
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nkeynes@368 | 318 | JNE_exit(EXIT_FPU_DISABLED);
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nkeynes@368 | 319 | }
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nkeynes@368 | 320 | }
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nkeynes@368 | 321 | }
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nkeynes@368 | 322 |
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nkeynes@368 | 323 | static void check_ralign16( int x86reg )
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nkeynes@368 | 324 | {
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nkeynes@368 | 325 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 326 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 327 | }
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nkeynes@368 | 328 |
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nkeynes@368 | 329 | static void check_walign16( int x86reg )
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nkeynes@368 | 330 | {
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nkeynes@368 | 331 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 332 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 333 | }
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nkeynes@368 | 334 |
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nkeynes@368 | 335 | static void check_ralign32( int x86reg )
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nkeynes@368 | 336 | {
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nkeynes@368 | 337 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 338 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 339 | }
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nkeynes@368 | 340 | static void check_walign32( int x86reg )
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nkeynes@368 | 341 | {
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nkeynes@368 | 342 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 343 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 344 | }
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nkeynes@368 | 345 |
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nkeynes@361 | 346 | #define UNDEF()
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nkeynes@361 | 347 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 348 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 349 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 350 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 351 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 352 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 353 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 354 |
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nkeynes@386 | 355 | #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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nkeynes@368 | 356 |
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nkeynes@368 | 357 |
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nkeynes@359 | 358 |
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nkeynes@359 | 359 | /**
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nkeynes@359 | 360 | * Emit the 'start of block' assembly. Sets up the stack frame and save
|
nkeynes@359 | 361 | * SI/DI as required
|
nkeynes@359 | 362 | */
|
nkeynes@408 | 363 | void sh4_translate_begin_block( sh4addr_t pc )
|
nkeynes@368 | 364 | {
|
nkeynes@368 | 365 | PUSH_r32(R_EBP);
|
nkeynes@359 | 366 | /* mov &sh4r, ebp */
|
nkeynes@359 | 367 | load_imm32( R_EBP, (uint32_t)&sh4r );
|
nkeynes@368 | 368 | PUSH_r32(R_ESI);
|
nkeynes@380 | 369 | XOR_r32_r32(R_ESI, R_ESI);
|
nkeynes@368 | 370 |
|
nkeynes@368 | 371 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@368 | 372 | sh4_x86.priv_checked = FALSE;
|
nkeynes@368 | 373 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@368 | 374 | sh4_x86.backpatch_posn = 0;
|
nkeynes@408 | 375 | sh4_x86.block_start_pc = pc;
|
nkeynes@368 | 376 | }
|
nkeynes@359 | 377 |
|
nkeynes@368 | 378 | /**
|
nkeynes@408 | 379 | * Exit the block to an absolute PC
|
nkeynes@408 | 380 | * Bytes: 30
|
nkeynes@368 | 381 | */
|
nkeynes@408 | 382 | void exit_block( sh4addr_t pc, sh4addr_t endpc )
|
nkeynes@368 | 383 | {
|
nkeynes@408 | 384 | load_imm32( R_ECX, pc ); // 5
|
nkeynes@408 | 385 | store_spreg( R_ECX, REG_OFFSET(pc) ); // 3
|
nkeynes@408 | 386 | MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
|
nkeynes@408 | 387 | AND_imm8s_r32( 0xFC, R_EAX ); // 3
|
nkeynes@408 | 388 | load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@408 | 389 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@374 | 390 | POP_r32(R_ESI);
|
nkeynes@374 | 391 | POP_r32(R_EBP);
|
nkeynes@368 | 392 | RET();
|
nkeynes@359 | 393 | }
|
nkeynes@359 | 394 |
|
nkeynes@359 | 395 | /**
|
nkeynes@408 | 396 | * Exit the block with sh4r.pc already written
|
nkeynes@408 | 397 | * Bytes: 16
|
nkeynes@408 | 398 | */
|
nkeynes@408 | 399 | void exit_block_pcset( pc )
|
nkeynes@408 | 400 | {
|
nkeynes@408 | 401 | XOR_r32_r32( R_EAX, R_EAX ); // 2
|
nkeynes@408 | 402 | load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@408 | 403 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@408 | 404 | POP_r32(R_ESI);
|
nkeynes@408 | 405 | POP_r32(R_EBP);
|
nkeynes@408 | 406 | RET();
|
nkeynes@408 | 407 | }
|
nkeynes@408 | 408 |
|
nkeynes@408 | 409 | /**
|
nkeynes@408 | 410 | * Write the block trailer (exception handling block)
|
nkeynes@359 | 411 | */
|
nkeynes@359 | 412 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@388 | 413 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@388 | 414 | uint8_t *end_ptr = xlat_output;
|
nkeynes@388 | 415 | // Exception termination. Jump block for various exception codes:
|
nkeynes@388 | 416 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@388 | 417 | JMP_rel8( 33, target1 );
|
nkeynes@388 | 418 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@388 | 419 | JMP_rel8( 26, target2 );
|
nkeynes@388 | 420 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@388 | 421 | JMP_rel8( 19, target3 );
|
nkeynes@388 | 422 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@388 | 423 | JMP_rel8( 12, target4 );
|
nkeynes@388 | 424 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@388 | 425 | JMP_rel8( 5, target5 );
|
nkeynes@388 | 426 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@388 | 427 | // target
|
nkeynes@388 | 428 | JMP_TARGET(target1);
|
nkeynes@388 | 429 | JMP_TARGET(target2);
|
nkeynes@388 | 430 | JMP_TARGET(target3);
|
nkeynes@388 | 431 | JMP_TARGET(target4);
|
nkeynes@388 | 432 | JMP_TARGET(target5);
|
nkeynes@388 | 433 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 434 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 435 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 436 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 437 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@388 | 438 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 439 | MUL_r32( R_ESI );
|
nkeynes@388 | 440 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@388 | 441 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 442 |
|
nkeynes@388 | 443 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
|
nkeynes@388 | 444 | CALL_r32( R_EAX ); // 2
|
nkeynes@388 | 445 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@408 | 446 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@388 | 447 | POP_r32(R_ESI);
|
nkeynes@388 | 448 | POP_r32(R_EBP);
|
nkeynes@388 | 449 | RET();
|
nkeynes@368 | 450 |
|
nkeynes@388 | 451 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@388 | 452 | }
|
nkeynes@368 | 453 |
|
nkeynes@359 | 454 | }
|
nkeynes@359 | 455 |
|
nkeynes@388 | 456 |
|
nkeynes@388 | 457 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 458 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 459 |
|
nkeynes@359 | 460 | /**
|
nkeynes@359 | 461 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 462 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 463 | *
|
nkeynes@359 | 464 | *
|
nkeynes@359 | 465 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 466 | * (eg a branch or
|
nkeynes@359 | 467 | */
|
nkeynes@408 | 468 | uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
|
nkeynes@359 | 469 | {
|
nkeynes@388 | 470 | uint32_t ir;
|
nkeynes@388 | 471 | /* Read instruction */
|
nkeynes@388 | 472 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 473 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 474 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 475 | } else {
|
nkeynes@388 | 476 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@388 | 477 | if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 478 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 479 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 480 | */
|
nkeynes@388 | 481 | sh4_icache = NULL;
|
nkeynes@388 | 482 | ir = sh4_read_word(pc);
|
nkeynes@388 | 483 | } else {
|
nkeynes@388 | 484 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 485 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 486 | }
|
nkeynes@388 | 487 | }
|
nkeynes@388 | 488 |
|
nkeynes@359 | 489 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 490 | case 0x0:
|
nkeynes@359 | 491 | switch( ir&0xF ) {
|
nkeynes@359 | 492 | case 0x2:
|
nkeynes@359 | 493 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 494 | case 0x0:
|
nkeynes@359 | 495 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 496 | case 0x0:
|
nkeynes@359 | 497 | { /* STC SR, Rn */
|
nkeynes@359 | 498 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 499 | check_priv();
|
nkeynes@374 | 500 | call_func0(sh4_read_sr);
|
nkeynes@368 | 501 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 502 | }
|
nkeynes@359 | 503 | break;
|
nkeynes@359 | 504 | case 0x1:
|
nkeynes@359 | 505 | { /* STC GBR, Rn */
|
nkeynes@359 | 506 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 507 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 508 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 509 | }
|
nkeynes@359 | 510 | break;
|
nkeynes@359 | 511 | case 0x2:
|
nkeynes@359 | 512 | { /* STC VBR, Rn */
|
nkeynes@359 | 513 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 514 | check_priv();
|
nkeynes@359 | 515 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 516 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 517 | }
|
nkeynes@359 | 518 | break;
|
nkeynes@359 | 519 | case 0x3:
|
nkeynes@359 | 520 | { /* STC SSR, Rn */
|
nkeynes@359 | 521 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 522 | check_priv();
|
nkeynes@359 | 523 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 524 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 525 | }
|
nkeynes@359 | 526 | break;
|
nkeynes@359 | 527 | case 0x4:
|
nkeynes@359 | 528 | { /* STC SPC, Rn */
|
nkeynes@359 | 529 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 530 | check_priv();
|
nkeynes@359 | 531 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 532 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 533 | }
|
nkeynes@359 | 534 | break;
|
nkeynes@359 | 535 | default:
|
nkeynes@359 | 536 | UNDEF();
|
nkeynes@359 | 537 | break;
|
nkeynes@359 | 538 | }
|
nkeynes@359 | 539 | break;
|
nkeynes@359 | 540 | case 0x1:
|
nkeynes@359 | 541 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 542 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 543 | check_priv();
|
nkeynes@374 | 544 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 545 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 546 | }
|
nkeynes@359 | 547 | break;
|
nkeynes@359 | 548 | }
|
nkeynes@359 | 549 | break;
|
nkeynes@359 | 550 | case 0x3:
|
nkeynes@359 | 551 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 552 | case 0x0:
|
nkeynes@359 | 553 | { /* BSRF Rn */
|
nkeynes@359 | 554 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 555 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 556 | SLOTILLEGAL();
|
nkeynes@374 | 557 | } else {
|
nkeynes@408 | 558 | load_imm32( R_ECX, pc + 4 );
|
nkeynes@408 | 559 | store_spreg( R_ECX, R_PR );
|
nkeynes@408 | 560 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
|
nkeynes@408 | 561 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 562 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 563 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 564 | exit_block_pcset(pc+2);
|
nkeynes@408 | 565 | return 4;
|
nkeynes@374 | 566 | }
|
nkeynes@359 | 567 | }
|
nkeynes@359 | 568 | break;
|
nkeynes@359 | 569 | case 0x2:
|
nkeynes@359 | 570 | { /* BRAF Rn */
|
nkeynes@359 | 571 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 572 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 573 | SLOTILLEGAL();
|
nkeynes@374 | 574 | } else {
|
nkeynes@408 | 575 | load_reg( R_EAX, Rn );
|
nkeynes@408 | 576 | ADD_imm32_r32( pc + 4, R_EAX );
|
nkeynes@408 | 577 | store_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@374 | 578 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 579 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 580 | exit_block_pcset(pc+2);
|
nkeynes@408 | 581 | return 4;
|
nkeynes@374 | 582 | }
|
nkeynes@359 | 583 | }
|
nkeynes@359 | 584 | break;
|
nkeynes@359 | 585 | case 0x8:
|
nkeynes@359 | 586 | { /* PREF @Rn */
|
nkeynes@359 | 587 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 588 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 589 | PUSH_r32( R_EAX );
|
nkeynes@374 | 590 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 591 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@380 | 592 | JNE_rel8(7, end);
|
nkeynes@374 | 593 | call_func0( sh4_flush_store_queue );
|
nkeynes@380 | 594 | JMP_TARGET(end);
|
nkeynes@377 | 595 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@359 | 596 | }
|
nkeynes@359 | 597 | break;
|
nkeynes@359 | 598 | case 0x9:
|
nkeynes@359 | 599 | { /* OCBI @Rn */
|
nkeynes@359 | 600 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 601 | }
|
nkeynes@359 | 602 | break;
|
nkeynes@359 | 603 | case 0xA:
|
nkeynes@359 | 604 | { /* OCBP @Rn */
|
nkeynes@359 | 605 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 606 | }
|
nkeynes@359 | 607 | break;
|
nkeynes@359 | 608 | case 0xB:
|
nkeynes@359 | 609 | { /* OCBWB @Rn */
|
nkeynes@359 | 610 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 611 | }
|
nkeynes@359 | 612 | break;
|
nkeynes@359 | 613 | case 0xC:
|
nkeynes@359 | 614 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 615 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 616 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 617 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 618 | check_walign32( R_ECX );
|
nkeynes@361 | 619 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 620 | }
|
nkeynes@359 | 621 | break;
|
nkeynes@359 | 622 | default:
|
nkeynes@359 | 623 | UNDEF();
|
nkeynes@359 | 624 | break;
|
nkeynes@359 | 625 | }
|
nkeynes@359 | 626 | break;
|
nkeynes@359 | 627 | case 0x4:
|
nkeynes@359 | 628 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 629 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 630 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 631 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 632 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 633 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 634 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 635 | }
|
nkeynes@359 | 636 | break;
|
nkeynes@359 | 637 | case 0x5:
|
nkeynes@359 | 638 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 639 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 640 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 641 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 642 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 643 | check_walign16( R_ECX );
|
nkeynes@361 | 644 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 645 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 646 | }
|
nkeynes@359 | 647 | break;
|
nkeynes@359 | 648 | case 0x6:
|
nkeynes@359 | 649 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 650 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 651 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 652 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 653 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 654 | check_walign32( R_ECX );
|
nkeynes@361 | 655 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 656 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 657 | }
|
nkeynes@359 | 658 | break;
|
nkeynes@359 | 659 | case 0x7:
|
nkeynes@359 | 660 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 661 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 662 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 663 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 664 | MUL_r32( R_ECX );
|
nkeynes@361 | 665 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 666 | }
|
nkeynes@359 | 667 | break;
|
nkeynes@359 | 668 | case 0x8:
|
nkeynes@359 | 669 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 670 | case 0x0:
|
nkeynes@359 | 671 | { /* CLRT */
|
nkeynes@374 | 672 | CLC();
|
nkeynes@374 | 673 | SETC_t();
|
nkeynes@359 | 674 | }
|
nkeynes@359 | 675 | break;
|
nkeynes@359 | 676 | case 0x1:
|
nkeynes@359 | 677 | { /* SETT */
|
nkeynes@374 | 678 | STC();
|
nkeynes@374 | 679 | SETC_t();
|
nkeynes@359 | 680 | }
|
nkeynes@359 | 681 | break;
|
nkeynes@359 | 682 | case 0x2:
|
nkeynes@359 | 683 | { /* CLRMAC */
|
nkeynes@374 | 684 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 685 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 686 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 687 | }
|
nkeynes@359 | 688 | break;
|
nkeynes@359 | 689 | case 0x3:
|
nkeynes@359 | 690 | { /* LDTLB */
|
nkeynes@359 | 691 | }
|
nkeynes@359 | 692 | break;
|
nkeynes@359 | 693 | case 0x4:
|
nkeynes@359 | 694 | { /* CLRS */
|
nkeynes@374 | 695 | CLC();
|
nkeynes@374 | 696 | SETC_sh4r(R_S);
|
nkeynes@359 | 697 | }
|
nkeynes@359 | 698 | break;
|
nkeynes@359 | 699 | case 0x5:
|
nkeynes@359 | 700 | { /* SETS */
|
nkeynes@374 | 701 | STC();
|
nkeynes@374 | 702 | SETC_sh4r(R_S);
|
nkeynes@359 | 703 | }
|
nkeynes@359 | 704 | break;
|
nkeynes@359 | 705 | default:
|
nkeynes@359 | 706 | UNDEF();
|
nkeynes@359 | 707 | break;
|
nkeynes@359 | 708 | }
|
nkeynes@359 | 709 | break;
|
nkeynes@359 | 710 | case 0x9:
|
nkeynes@359 | 711 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 712 | case 0x0:
|
nkeynes@359 | 713 | { /* NOP */
|
nkeynes@359 | 714 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 715 | }
|
nkeynes@359 | 716 | break;
|
nkeynes@359 | 717 | case 0x1:
|
nkeynes@359 | 718 | { /* DIV0U */
|
nkeynes@361 | 719 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 720 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 721 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 722 | store_spreg( R_EAX, R_T );
|
nkeynes@359 | 723 | }
|
nkeynes@359 | 724 | break;
|
nkeynes@359 | 725 | case 0x2:
|
nkeynes@359 | 726 | { /* MOVT Rn */
|
nkeynes@359 | 727 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 728 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 729 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 730 | }
|
nkeynes@359 | 731 | break;
|
nkeynes@359 | 732 | default:
|
nkeynes@359 | 733 | UNDEF();
|
nkeynes@359 | 734 | break;
|
nkeynes@359 | 735 | }
|
nkeynes@359 | 736 | break;
|
nkeynes@359 | 737 | case 0xA:
|
nkeynes@359 | 738 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 739 | case 0x0:
|
nkeynes@359 | 740 | { /* STS MACH, Rn */
|
nkeynes@359 | 741 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 742 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 743 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 744 | }
|
nkeynes@359 | 745 | break;
|
nkeynes@359 | 746 | case 0x1:
|
nkeynes@359 | 747 | { /* STS MACL, Rn */
|
nkeynes@359 | 748 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 749 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 750 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 751 | }
|
nkeynes@359 | 752 | break;
|
nkeynes@359 | 753 | case 0x2:
|
nkeynes@359 | 754 | { /* STS PR, Rn */
|
nkeynes@359 | 755 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 756 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 757 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 758 | }
|
nkeynes@359 | 759 | break;
|
nkeynes@359 | 760 | case 0x3:
|
nkeynes@359 | 761 | { /* STC SGR, Rn */
|
nkeynes@359 | 762 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 763 | check_priv();
|
nkeynes@359 | 764 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 765 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 766 | }
|
nkeynes@359 | 767 | break;
|
nkeynes@359 | 768 | case 0x5:
|
nkeynes@359 | 769 | { /* STS FPUL, Rn */
|
nkeynes@359 | 770 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 771 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 772 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 773 | }
|
nkeynes@359 | 774 | break;
|
nkeynes@359 | 775 | case 0x6:
|
nkeynes@359 | 776 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 777 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 778 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 779 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 780 | }
|
nkeynes@359 | 781 | break;
|
nkeynes@359 | 782 | case 0xF:
|
nkeynes@359 | 783 | { /* STC DBR, Rn */
|
nkeynes@359 | 784 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 785 | check_priv();
|
nkeynes@359 | 786 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 787 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 788 | }
|
nkeynes@359 | 789 | break;
|
nkeynes@359 | 790 | default:
|
nkeynes@359 | 791 | UNDEF();
|
nkeynes@359 | 792 | break;
|
nkeynes@359 | 793 | }
|
nkeynes@359 | 794 | break;
|
nkeynes@359 | 795 | case 0xB:
|
nkeynes@359 | 796 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 797 | case 0x0:
|
nkeynes@359 | 798 | { /* RTS */
|
nkeynes@374 | 799 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 800 | SLOTILLEGAL();
|
nkeynes@374 | 801 | } else {
|
nkeynes@408 | 802 | load_spreg( R_ECX, R_PR );
|
nkeynes@408 | 803 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 804 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 805 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 806 | exit_block_pcset(pc+2);
|
nkeynes@408 | 807 | return 4;
|
nkeynes@374 | 808 | }
|
nkeynes@359 | 809 | }
|
nkeynes@359 | 810 | break;
|
nkeynes@359 | 811 | case 0x1:
|
nkeynes@359 | 812 | { /* SLEEP */
|
nkeynes@388 | 813 | check_priv();
|
nkeynes@388 | 814 | call_func0( sh4_sleep );
|
nkeynes@388 | 815 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@394 | 816 | INC_r32(R_ESI);
|
nkeynes@408 | 817 | exit_block(pc+2, pc+2);
|
nkeynes@408 | 818 | return 2;
|
nkeynes@359 | 819 | }
|
nkeynes@359 | 820 | break;
|
nkeynes@359 | 821 | case 0x2:
|
nkeynes@359 | 822 | { /* RTE */
|
nkeynes@374 | 823 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 824 | SLOTILLEGAL();
|
nkeynes@374 | 825 | } else {
|
nkeynes@408 | 826 | check_priv();
|
nkeynes@408 | 827 | load_spreg( R_ECX, R_SPC );
|
nkeynes@408 | 828 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 829 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 830 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 831 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 832 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 833 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@408 | 834 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 835 | exit_block_pcset(pc+2);
|
nkeynes@408 | 836 | return 4;
|
nkeynes@374 | 837 | }
|
nkeynes@359 | 838 | }
|
nkeynes@359 | 839 | break;
|
nkeynes@359 | 840 | default:
|
nkeynes@359 | 841 | UNDEF();
|
nkeynes@359 | 842 | break;
|
nkeynes@359 | 843 | }
|
nkeynes@359 | 844 | break;
|
nkeynes@359 | 845 | case 0xC:
|
nkeynes@359 | 846 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 847 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 848 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 849 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 850 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 851 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 852 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 853 | }
|
nkeynes@359 | 854 | break;
|
nkeynes@359 | 855 | case 0xD:
|
nkeynes@359 | 856 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 857 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 858 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 859 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 860 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 861 | check_ralign16( R_ECX );
|
nkeynes@361 | 862 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 863 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 864 | }
|
nkeynes@359 | 865 | break;
|
nkeynes@359 | 866 | case 0xE:
|
nkeynes@359 | 867 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 868 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 869 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 870 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 871 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 872 | check_ralign32( R_ECX );
|
nkeynes@361 | 873 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 874 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 875 | }
|
nkeynes@359 | 876 | break;
|
nkeynes@359 | 877 | case 0xF:
|
nkeynes@359 | 878 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 879 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 880 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 881 | check_ralign32( R_ECX );
|
nkeynes@386 | 882 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 883 | check_ralign32( R_ECX );
|
nkeynes@386 | 884 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 885 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 886 | PUSH_r32( R_EAX );
|
nkeynes@386 | 887 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 888 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 889 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 890 | POP_r32( R_ECX );
|
nkeynes@386 | 891 | IMUL_r32( R_ECX );
|
nkeynes@386 | 892 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 893 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 894 |
|
nkeynes@386 | 895 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 896 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@386 | 897 | JE_rel8( 7, nosat );
|
nkeynes@386 | 898 | call_func0( signsat48 );
|
nkeynes@386 | 899 | JMP_TARGET( nosat );
|
nkeynes@359 | 900 | }
|
nkeynes@359 | 901 | break;
|
nkeynes@359 | 902 | default:
|
nkeynes@359 | 903 | UNDEF();
|
nkeynes@359 | 904 | break;
|
nkeynes@359 | 905 | }
|
nkeynes@359 | 906 | break;
|
nkeynes@359 | 907 | case 0x1:
|
nkeynes@359 | 908 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 909 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 910 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 911 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 912 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 913 | check_walign32( R_ECX );
|
nkeynes@361 | 914 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 915 | }
|
nkeynes@359 | 916 | break;
|
nkeynes@359 | 917 | case 0x2:
|
nkeynes@359 | 918 | switch( ir&0xF ) {
|
nkeynes@359 | 919 | case 0x0:
|
nkeynes@359 | 920 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 921 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 922 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 923 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 924 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 925 | }
|
nkeynes@359 | 926 | break;
|
nkeynes@359 | 927 | case 0x1:
|
nkeynes@359 | 928 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 929 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 930 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 931 | check_walign16( R_ECX );
|
nkeynes@386 | 932 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 933 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 934 | }
|
nkeynes@359 | 935 | break;
|
nkeynes@359 | 936 | case 0x2:
|
nkeynes@359 | 937 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 938 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 939 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 940 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 941 | check_walign32(R_ECX);
|
nkeynes@361 | 942 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 943 | }
|
nkeynes@359 | 944 | break;
|
nkeynes@359 | 945 | case 0x4:
|
nkeynes@359 | 946 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 947 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 948 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 949 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 950 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 951 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 952 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 953 | }
|
nkeynes@359 | 954 | break;
|
nkeynes@359 | 955 | case 0x5:
|
nkeynes@359 | 956 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 957 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 958 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 959 | check_walign16( R_ECX );
|
nkeynes@361 | 960 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 961 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@386 | 962 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 963 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 964 | }
|
nkeynes@359 | 965 | break;
|
nkeynes@359 | 966 | case 0x6:
|
nkeynes@359 | 967 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 968 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 969 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 970 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 971 | check_walign32( R_ECX );
|
nkeynes@361 | 972 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 973 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 974 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 975 | }
|
nkeynes@359 | 976 | break;
|
nkeynes@359 | 977 | case 0x7:
|
nkeynes@359 | 978 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 979 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 980 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 981 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 982 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 983 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 984 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 985 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 986 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 987 | SETNE_t();
|
nkeynes@359 | 988 | }
|
nkeynes@359 | 989 | break;
|
nkeynes@359 | 990 | case 0x8:
|
nkeynes@359 | 991 | { /* TST Rm, Rn */
|
nkeynes@359 | 992 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 993 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 994 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 995 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 996 | SETE_t();
|
nkeynes@359 | 997 | }
|
nkeynes@359 | 998 | break;
|
nkeynes@359 | 999 | case 0x9:
|
nkeynes@359 | 1000 | { /* AND Rm, Rn */
|
nkeynes@359 | 1001 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1002 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1003 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1004 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1005 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1006 | }
|
nkeynes@359 | 1007 | break;
|
nkeynes@359 | 1008 | case 0xA:
|
nkeynes@359 | 1009 | { /* XOR Rm, Rn */
|
nkeynes@359 | 1010 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1011 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1012 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1013 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1014 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1015 | }
|
nkeynes@359 | 1016 | break;
|
nkeynes@359 | 1017 | case 0xB:
|
nkeynes@359 | 1018 | { /* OR Rm, Rn */
|
nkeynes@359 | 1019 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1020 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1021 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1022 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1023 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1024 | }
|
nkeynes@359 | 1025 | break;
|
nkeynes@359 | 1026 | case 0xC:
|
nkeynes@359 | 1027 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 1028 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1029 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1030 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1031 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 1032 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 1033 | JE_rel8(13, target1);
|
nkeynes@368 | 1034 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1035 | JE_rel8(9, target2);
|
nkeynes@368 | 1036 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 1037 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 1038 | JE_rel8(2, target3);
|
nkeynes@368 | 1039 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1040 | JMP_TARGET(target1);
|
nkeynes@380 | 1041 | JMP_TARGET(target2);
|
nkeynes@380 | 1042 | JMP_TARGET(target3);
|
nkeynes@368 | 1043 | SETE_t();
|
nkeynes@359 | 1044 | }
|
nkeynes@359 | 1045 | break;
|
nkeynes@359 | 1046 | case 0xD:
|
nkeynes@359 | 1047 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1048 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1049 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1050 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1051 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1052 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1053 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1054 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1055 | }
|
nkeynes@359 | 1056 | break;
|
nkeynes@359 | 1057 | case 0xE:
|
nkeynes@359 | 1058 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1059 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1060 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1061 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1062 | MUL_r32( R_ECX );
|
nkeynes@374 | 1063 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1064 | }
|
nkeynes@359 | 1065 | break;
|
nkeynes@359 | 1066 | case 0xF:
|
nkeynes@359 | 1067 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1068 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1069 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1070 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1071 | MUL_r32( R_ECX );
|
nkeynes@374 | 1072 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1073 | }
|
nkeynes@359 | 1074 | break;
|
nkeynes@359 | 1075 | default:
|
nkeynes@359 | 1076 | UNDEF();
|
nkeynes@359 | 1077 | break;
|
nkeynes@359 | 1078 | }
|
nkeynes@359 | 1079 | break;
|
nkeynes@359 | 1080 | case 0x3:
|
nkeynes@359 | 1081 | switch( ir&0xF ) {
|
nkeynes@359 | 1082 | case 0x0:
|
nkeynes@359 | 1083 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1084 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1085 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1086 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1087 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1088 | SETE_t();
|
nkeynes@359 | 1089 | }
|
nkeynes@359 | 1090 | break;
|
nkeynes@359 | 1091 | case 0x2:
|
nkeynes@359 | 1092 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1093 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1094 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1095 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1096 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1097 | SETAE_t();
|
nkeynes@359 | 1098 | }
|
nkeynes@359 | 1099 | break;
|
nkeynes@359 | 1100 | case 0x3:
|
nkeynes@359 | 1101 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1102 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1103 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1104 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1105 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1106 | SETGE_t();
|
nkeynes@359 | 1107 | }
|
nkeynes@359 | 1108 | break;
|
nkeynes@359 | 1109 | case 0x4:
|
nkeynes@359 | 1110 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1111 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 1112 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1113 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 1114 | LDC_t();
|
nkeynes@386 | 1115 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1116 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1117 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 1118 | JE_rel8(5, mqequal);
|
nkeynes@386 | 1119 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1120 | JMP_rel8(3, end);
|
nkeynes@380 | 1121 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1122 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1123 | JMP_TARGET(end);
|
nkeynes@386 | 1124 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1125 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1126 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1127 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1128 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1129 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1130 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1131 | store_spreg( R_EAX, R_T );
|
nkeynes@359 | 1132 | }
|
nkeynes@359 | 1133 | break;
|
nkeynes@359 | 1134 | case 0x5:
|
nkeynes@359 | 1135 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1136 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1137 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1138 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1139 | MUL_r32(R_ECX);
|
nkeynes@361 | 1140 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1141 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1142 | }
|
nkeynes@359 | 1143 | break;
|
nkeynes@359 | 1144 | case 0x6:
|
nkeynes@359 | 1145 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1146 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1147 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1148 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1149 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1150 | SETA_t();
|
nkeynes@359 | 1151 | }
|
nkeynes@359 | 1152 | break;
|
nkeynes@359 | 1153 | case 0x7:
|
nkeynes@359 | 1154 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1155 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1156 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1157 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1158 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1159 | SETG_t();
|
nkeynes@359 | 1160 | }
|
nkeynes@359 | 1161 | break;
|
nkeynes@359 | 1162 | case 0x8:
|
nkeynes@359 | 1163 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1164 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1165 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1166 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1167 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1168 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1169 | }
|
nkeynes@359 | 1170 | break;
|
nkeynes@359 | 1171 | case 0xA:
|
nkeynes@359 | 1172 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1173 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1174 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1175 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1176 | LDC_t();
|
nkeynes@359 | 1177 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1178 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1179 | SETC_t();
|
nkeynes@359 | 1180 | }
|
nkeynes@359 | 1181 | break;
|
nkeynes@359 | 1182 | case 0xB:
|
nkeynes@359 | 1183 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1184 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1185 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1186 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1187 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1188 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1189 | SETO_t();
|
nkeynes@359 | 1190 | }
|
nkeynes@359 | 1191 | break;
|
nkeynes@359 | 1192 | case 0xC:
|
nkeynes@359 | 1193 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1194 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1195 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1196 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1197 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1198 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1199 | }
|
nkeynes@359 | 1200 | break;
|
nkeynes@359 | 1201 | case 0xD:
|
nkeynes@359 | 1202 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1203 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1204 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1205 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1206 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1207 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1208 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1209 | }
|
nkeynes@359 | 1210 | break;
|
nkeynes@359 | 1211 | case 0xE:
|
nkeynes@359 | 1212 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1213 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1214 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1215 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1216 | LDC_t();
|
nkeynes@359 | 1217 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1218 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1219 | SETC_t();
|
nkeynes@359 | 1220 | }
|
nkeynes@359 | 1221 | break;
|
nkeynes@359 | 1222 | case 0xF:
|
nkeynes@359 | 1223 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1224 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1225 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1226 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1227 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1228 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1229 | SETO_t();
|
nkeynes@359 | 1230 | }
|
nkeynes@359 | 1231 | break;
|
nkeynes@359 | 1232 | default:
|
nkeynes@359 | 1233 | UNDEF();
|
nkeynes@359 | 1234 | break;
|
nkeynes@359 | 1235 | }
|
nkeynes@359 | 1236 | break;
|
nkeynes@359 | 1237 | case 0x4:
|
nkeynes@359 | 1238 | switch( ir&0xF ) {
|
nkeynes@359 | 1239 | case 0x0:
|
nkeynes@359 | 1240 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1241 | case 0x0:
|
nkeynes@359 | 1242 | { /* SHLL Rn */
|
nkeynes@359 | 1243 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1244 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1245 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1246 | SETC_t();
|
nkeynes@359 | 1247 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1248 | }
|
nkeynes@359 | 1249 | break;
|
nkeynes@359 | 1250 | case 0x1:
|
nkeynes@359 | 1251 | { /* DT Rn */
|
nkeynes@359 | 1252 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1253 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1254 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1255 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1256 | SETE_t();
|
nkeynes@359 | 1257 | }
|
nkeynes@359 | 1258 | break;
|
nkeynes@359 | 1259 | case 0x2:
|
nkeynes@359 | 1260 | { /* SHAL Rn */
|
nkeynes@359 | 1261 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1262 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1263 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1264 | SETC_t();
|
nkeynes@359 | 1265 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1266 | }
|
nkeynes@359 | 1267 | break;
|
nkeynes@359 | 1268 | default:
|
nkeynes@359 | 1269 | UNDEF();
|
nkeynes@359 | 1270 | break;
|
nkeynes@359 | 1271 | }
|
nkeynes@359 | 1272 | break;
|
nkeynes@359 | 1273 | case 0x1:
|
nkeynes@359 | 1274 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1275 | case 0x0:
|
nkeynes@359 | 1276 | { /* SHLR Rn */
|
nkeynes@359 | 1277 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1278 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1279 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1280 | SETC_t();
|
nkeynes@359 | 1281 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1282 | }
|
nkeynes@359 | 1283 | break;
|
nkeynes@359 | 1284 | case 0x1:
|
nkeynes@359 | 1285 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1286 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1287 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1288 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1289 | SETGE_t();
|
nkeynes@359 | 1290 | }
|
nkeynes@359 | 1291 | break;
|
nkeynes@359 | 1292 | case 0x2:
|
nkeynes@359 | 1293 | { /* SHAR Rn */
|
nkeynes@359 | 1294 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1295 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1296 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1297 | SETC_t();
|
nkeynes@359 | 1298 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1299 | }
|
nkeynes@359 | 1300 | break;
|
nkeynes@359 | 1301 | default:
|
nkeynes@359 | 1302 | UNDEF();
|
nkeynes@359 | 1303 | break;
|
nkeynes@359 | 1304 | }
|
nkeynes@359 | 1305 | break;
|
nkeynes@359 | 1306 | case 0x2:
|
nkeynes@359 | 1307 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1308 | case 0x0:
|
nkeynes@359 | 1309 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1310 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1311 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1312 | check_walign32( R_ECX );
|
nkeynes@386 | 1313 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1314 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1315 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1316 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1317 | }
|
nkeynes@359 | 1318 | break;
|
nkeynes@359 | 1319 | case 0x1:
|
nkeynes@359 | 1320 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1321 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1322 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1323 | check_walign32( R_ECX );
|
nkeynes@386 | 1324 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1325 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1326 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1327 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1328 | }
|
nkeynes@359 | 1329 | break;
|
nkeynes@359 | 1330 | case 0x2:
|
nkeynes@359 | 1331 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1332 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1333 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1334 | check_walign32( R_ECX );
|
nkeynes@386 | 1335 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1336 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1337 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1338 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1339 | }
|
nkeynes@359 | 1340 | break;
|
nkeynes@359 | 1341 | case 0x3:
|
nkeynes@359 | 1342 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1343 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1344 | check_priv();
|
nkeynes@359 | 1345 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1346 | check_walign32( R_ECX );
|
nkeynes@386 | 1347 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1348 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1349 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1350 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1351 | }
|
nkeynes@359 | 1352 | break;
|
nkeynes@359 | 1353 | case 0x5:
|
nkeynes@359 | 1354 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1355 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1356 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1357 | check_walign32( R_ECX );
|
nkeynes@386 | 1358 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1359 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1360 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1361 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1362 | }
|
nkeynes@359 | 1363 | break;
|
nkeynes@359 | 1364 | case 0x6:
|
nkeynes@359 | 1365 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1366 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1367 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1368 | check_walign32( R_ECX );
|
nkeynes@386 | 1369 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1370 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1371 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1372 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1373 | }
|
nkeynes@359 | 1374 | break;
|
nkeynes@359 | 1375 | case 0xF:
|
nkeynes@359 | 1376 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1377 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1378 | check_priv();
|
nkeynes@359 | 1379 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1380 | check_walign32( R_ECX );
|
nkeynes@386 | 1381 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1382 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1383 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1384 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1385 | }
|
nkeynes@359 | 1386 | break;
|
nkeynes@359 | 1387 | default:
|
nkeynes@359 | 1388 | UNDEF();
|
nkeynes@359 | 1389 | break;
|
nkeynes@359 | 1390 | }
|
nkeynes@359 | 1391 | break;
|
nkeynes@359 | 1392 | case 0x3:
|
nkeynes@359 | 1393 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1394 | case 0x0:
|
nkeynes@359 | 1395 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1396 | case 0x0:
|
nkeynes@359 | 1397 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1398 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1399 | check_priv();
|
nkeynes@395 | 1400 | call_func0( sh4_read_sr );
|
nkeynes@374 | 1401 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1402 | check_walign32( R_ECX );
|
nkeynes@386 | 1403 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1404 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1405 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1406 | }
|
nkeynes@359 | 1407 | break;
|
nkeynes@359 | 1408 | case 0x1:
|
nkeynes@359 | 1409 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1410 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1411 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1412 | check_walign32( R_ECX );
|
nkeynes@386 | 1413 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1414 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1415 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1416 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1417 | }
|
nkeynes@359 | 1418 | break;
|
nkeynes@359 | 1419 | case 0x2:
|
nkeynes@359 | 1420 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1421 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1422 | check_priv();
|
nkeynes@359 | 1423 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1424 | check_walign32( R_ECX );
|
nkeynes@386 | 1425 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1426 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1427 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1428 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1429 | }
|
nkeynes@359 | 1430 | break;
|
nkeynes@359 | 1431 | case 0x3:
|
nkeynes@359 | 1432 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1433 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1434 | check_priv();
|
nkeynes@359 | 1435 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1436 | check_walign32( R_ECX );
|
nkeynes@386 | 1437 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1438 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1439 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1440 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1441 | }
|
nkeynes@359 | 1442 | break;
|
nkeynes@359 | 1443 | case 0x4:
|
nkeynes@359 | 1444 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1445 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1446 | check_priv();
|
nkeynes@359 | 1447 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1448 | check_walign32( R_ECX );
|
nkeynes@386 | 1449 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1450 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1451 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1452 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1453 | }
|
nkeynes@359 | 1454 | break;
|
nkeynes@359 | 1455 | default:
|
nkeynes@359 | 1456 | UNDEF();
|
nkeynes@359 | 1457 | break;
|
nkeynes@359 | 1458 | }
|
nkeynes@359 | 1459 | break;
|
nkeynes@359 | 1460 | case 0x1:
|
nkeynes@359 | 1461 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1462 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 1463 | check_priv();
|
nkeynes@374 | 1464 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1465 | check_walign32( R_ECX );
|
nkeynes@386 | 1466 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1467 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1468 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 1469 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1470 | }
|
nkeynes@359 | 1471 | break;
|
nkeynes@359 | 1472 | }
|
nkeynes@359 | 1473 | break;
|
nkeynes@359 | 1474 | case 0x4:
|
nkeynes@359 | 1475 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1476 | case 0x0:
|
nkeynes@359 | 1477 | { /* ROTL Rn */
|
nkeynes@359 | 1478 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1479 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1480 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1481 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1482 | SETC_t();
|
nkeynes@359 | 1483 | }
|
nkeynes@359 | 1484 | break;
|
nkeynes@359 | 1485 | case 0x2:
|
nkeynes@359 | 1486 | { /* ROTCL Rn */
|
nkeynes@359 | 1487 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1488 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1489 | LDC_t();
|
nkeynes@359 | 1490 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1491 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1492 | SETC_t();
|
nkeynes@359 | 1493 | }
|
nkeynes@359 | 1494 | break;
|
nkeynes@359 | 1495 | default:
|
nkeynes@359 | 1496 | UNDEF();
|
nkeynes@359 | 1497 | break;
|
nkeynes@359 | 1498 | }
|
nkeynes@359 | 1499 | break;
|
nkeynes@359 | 1500 | case 0x5:
|
nkeynes@359 | 1501 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1502 | case 0x0:
|
nkeynes@359 | 1503 | { /* ROTR Rn */
|
nkeynes@359 | 1504 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1505 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1506 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1507 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1508 | SETC_t();
|
nkeynes@359 | 1509 | }
|
nkeynes@359 | 1510 | break;
|
nkeynes@359 | 1511 | case 0x1:
|
nkeynes@359 | 1512 | { /* CMP/PL Rn */
|
nkeynes@359 | 1513 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1514 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1515 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1516 | SETG_t();
|
nkeynes@359 | 1517 | }
|
nkeynes@359 | 1518 | break;
|
nkeynes@359 | 1519 | case 0x2:
|
nkeynes@359 | 1520 | { /* ROTCR Rn */
|
nkeynes@359 | 1521 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1522 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1523 | LDC_t();
|
nkeynes@359 | 1524 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1525 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1526 | SETC_t();
|
nkeynes@359 | 1527 | }
|
nkeynes@359 | 1528 | break;
|
nkeynes@359 | 1529 | default:
|
nkeynes@359 | 1530 | UNDEF();
|
nkeynes@359 | 1531 | break;
|
nkeynes@359 | 1532 | }
|
nkeynes@359 | 1533 | break;
|
nkeynes@359 | 1534 | case 0x6:
|
nkeynes@359 | 1535 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1536 | case 0x0:
|
nkeynes@359 | 1537 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1538 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1539 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1540 | check_ralign32( R_EAX );
|
nkeynes@359 | 1541 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1542 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1543 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1544 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1545 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1546 | }
|
nkeynes@359 | 1547 | break;
|
nkeynes@359 | 1548 | case 0x1:
|
nkeynes@359 | 1549 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1550 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1551 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1552 | check_ralign32( R_EAX );
|
nkeynes@359 | 1553 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1554 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1555 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1556 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1557 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1558 | }
|
nkeynes@359 | 1559 | break;
|
nkeynes@359 | 1560 | case 0x2:
|
nkeynes@359 | 1561 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1562 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1563 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1564 | check_ralign32( R_EAX );
|
nkeynes@359 | 1565 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1566 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1567 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1568 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1569 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1570 | }
|
nkeynes@359 | 1571 | break;
|
nkeynes@359 | 1572 | case 0x3:
|
nkeynes@359 | 1573 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1574 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1575 | check_priv();
|
nkeynes@359 | 1576 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1577 | check_ralign32( R_EAX );
|
nkeynes@359 | 1578 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1579 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1580 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1581 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1582 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1583 | }
|
nkeynes@359 | 1584 | break;
|
nkeynes@359 | 1585 | case 0x5:
|
nkeynes@359 | 1586 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1587 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1588 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1589 | check_ralign32( R_EAX );
|
nkeynes@359 | 1590 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1591 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1592 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1593 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1594 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1595 | }
|
nkeynes@359 | 1596 | break;
|
nkeynes@359 | 1597 | case 0x6:
|
nkeynes@359 | 1598 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1599 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1600 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1601 | check_ralign32( R_EAX );
|
nkeynes@359 | 1602 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1603 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1604 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1605 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1606 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1607 | update_fr_bank( R_EAX );
|
nkeynes@359 | 1608 | }
|
nkeynes@359 | 1609 | break;
|
nkeynes@359 | 1610 | case 0xF:
|
nkeynes@359 | 1611 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1612 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1613 | check_priv();
|
nkeynes@359 | 1614 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1615 | check_ralign32( R_EAX );
|
nkeynes@359 | 1616 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1617 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1618 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1619 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1620 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1621 | }
|
nkeynes@359 | 1622 | break;
|
nkeynes@359 | 1623 | default:
|
nkeynes@359 | 1624 | UNDEF();
|
nkeynes@359 | 1625 | break;
|
nkeynes@359 | 1626 | }
|
nkeynes@359 | 1627 | break;
|
nkeynes@359 | 1628 | case 0x7:
|
nkeynes@359 | 1629 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1630 | case 0x0:
|
nkeynes@359 | 1631 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1632 | case 0x0:
|
nkeynes@359 | 1633 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1634 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1635 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1636 | SLOTILLEGAL();
|
nkeynes@386 | 1637 | } else {
|
nkeynes@386 | 1638 | check_priv();
|
nkeynes@386 | 1639 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1640 | check_ralign32( R_EAX );
|
nkeynes@386 | 1641 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1642 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 1643 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 1644 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 1645 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1646 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1647 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 1648 | }
|
nkeynes@359 | 1649 | }
|
nkeynes@359 | 1650 | break;
|
nkeynes@359 | 1651 | case 0x1:
|
nkeynes@359 | 1652 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1653 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1654 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1655 | check_ralign32( R_EAX );
|
nkeynes@359 | 1656 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1657 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1658 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1659 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1660 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1661 | }
|
nkeynes@359 | 1662 | break;
|
nkeynes@359 | 1663 | case 0x2:
|
nkeynes@359 | 1664 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1665 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1666 | check_priv();
|
nkeynes@359 | 1667 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1668 | check_ralign32( R_EAX );
|
nkeynes@359 | 1669 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1670 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1671 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1672 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1673 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1674 | }
|
nkeynes@359 | 1675 | break;
|
nkeynes@359 | 1676 | case 0x3:
|
nkeynes@359 | 1677 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1678 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1679 | check_priv();
|
nkeynes@359 | 1680 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1681 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1682 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1683 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1684 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1685 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1686 | }
|
nkeynes@359 | 1687 | break;
|
nkeynes@359 | 1688 | case 0x4:
|
nkeynes@359 | 1689 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1690 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1691 | check_priv();
|
nkeynes@359 | 1692 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1693 | check_ralign32( R_EAX );
|
nkeynes@359 | 1694 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1695 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1696 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1697 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1698 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1699 | }
|
nkeynes@359 | 1700 | break;
|
nkeynes@359 | 1701 | default:
|
nkeynes@359 | 1702 | UNDEF();
|
nkeynes@359 | 1703 | break;
|
nkeynes@359 | 1704 | }
|
nkeynes@359 | 1705 | break;
|
nkeynes@359 | 1706 | case 0x1:
|
nkeynes@359 | 1707 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1708 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 1709 | check_priv();
|
nkeynes@374 | 1710 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1711 | check_ralign32( R_EAX );
|
nkeynes@374 | 1712 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1713 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 1714 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 1715 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1716 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 1717 | }
|
nkeynes@359 | 1718 | break;
|
nkeynes@359 | 1719 | }
|
nkeynes@359 | 1720 | break;
|
nkeynes@359 | 1721 | case 0x8:
|
nkeynes@359 | 1722 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1723 | case 0x0:
|
nkeynes@359 | 1724 | { /* SHLL2 Rn */
|
nkeynes@359 | 1725 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1726 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1727 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1728 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1729 | }
|
nkeynes@359 | 1730 | break;
|
nkeynes@359 | 1731 | case 0x1:
|
nkeynes@359 | 1732 | { /* SHLL8 Rn */
|
nkeynes@359 | 1733 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1734 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1735 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1736 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1737 | }
|
nkeynes@359 | 1738 | break;
|
nkeynes@359 | 1739 | case 0x2:
|
nkeynes@359 | 1740 | { /* SHLL16 Rn */
|
nkeynes@359 | 1741 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1742 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1743 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1744 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1745 | }
|
nkeynes@359 | 1746 | break;
|
nkeynes@359 | 1747 | default:
|
nkeynes@359 | 1748 | UNDEF();
|
nkeynes@359 | 1749 | break;
|
nkeynes@359 | 1750 | }
|
nkeynes@359 | 1751 | break;
|
nkeynes@359 | 1752 | case 0x9:
|
nkeynes@359 | 1753 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1754 | case 0x0:
|
nkeynes@359 | 1755 | { /* SHLR2 Rn */
|
nkeynes@359 | 1756 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1757 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1758 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1759 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1760 | }
|
nkeynes@359 | 1761 | break;
|
nkeynes@359 | 1762 | case 0x1:
|
nkeynes@359 | 1763 | { /* SHLR8 Rn */
|
nkeynes@359 | 1764 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1765 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1766 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1767 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1768 | }
|
nkeynes@359 | 1769 | break;
|
nkeynes@359 | 1770 | case 0x2:
|
nkeynes@359 | 1771 | { /* SHLR16 Rn */
|
nkeynes@359 | 1772 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1773 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1774 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1775 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1776 | }
|
nkeynes@359 | 1777 | break;
|
nkeynes@359 | 1778 | default:
|
nkeynes@359 | 1779 | UNDEF();
|
nkeynes@359 | 1780 | break;
|
nkeynes@359 | 1781 | }
|
nkeynes@359 | 1782 | break;
|
nkeynes@359 | 1783 | case 0xA:
|
nkeynes@359 | 1784 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1785 | case 0x0:
|
nkeynes@359 | 1786 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1787 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1788 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1789 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1790 | }
|
nkeynes@359 | 1791 | break;
|
nkeynes@359 | 1792 | case 0x1:
|
nkeynes@359 | 1793 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1794 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1795 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1796 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1797 | }
|
nkeynes@359 | 1798 | break;
|
nkeynes@359 | 1799 | case 0x2:
|
nkeynes@359 | 1800 | { /* LDS Rm, PR */
|
nkeynes@359 | 1801 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1802 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1803 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1804 | }
|
nkeynes@359 | 1805 | break;
|
nkeynes@359 | 1806 | case 0x3:
|
nkeynes@359 | 1807 | { /* LDC Rm, SGR */
|
nkeynes@359 | 1808 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1809 | check_priv();
|
nkeynes@359 | 1810 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1811 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1812 | }
|
nkeynes@359 | 1813 | break;
|
nkeynes@359 | 1814 | case 0x5:
|
nkeynes@359 | 1815 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 1816 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1817 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1818 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1819 | }
|
nkeynes@359 | 1820 | break;
|
nkeynes@359 | 1821 | case 0x6:
|
nkeynes@359 | 1822 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 1823 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1824 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1825 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1826 | update_fr_bank( R_EAX );
|
nkeynes@359 | 1827 | }
|
nkeynes@359 | 1828 | break;
|
nkeynes@359 | 1829 | case 0xF:
|
nkeynes@359 | 1830 | { /* LDC Rm, DBR */
|
nkeynes@359 | 1831 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1832 | check_priv();
|
nkeynes@359 | 1833 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1834 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1835 | }
|
nkeynes@359 | 1836 | break;
|
nkeynes@359 | 1837 | default:
|
nkeynes@359 | 1838 | UNDEF();
|
nkeynes@359 | 1839 | break;
|
nkeynes@359 | 1840 | }
|
nkeynes@359 | 1841 | break;
|
nkeynes@359 | 1842 | case 0xB:
|
nkeynes@359 | 1843 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1844 | case 0x0:
|
nkeynes@359 | 1845 | { /* JSR @Rn */
|
nkeynes@359 | 1846 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1847 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1848 | SLOTILLEGAL();
|
nkeynes@374 | 1849 | } else {
|
nkeynes@374 | 1850 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1851 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1852 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1853 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1854 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1855 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1856 | exit_block_pcset(pc+2);
|
nkeynes@408 | 1857 | return 4;
|
nkeynes@374 | 1858 | }
|
nkeynes@359 | 1859 | }
|
nkeynes@359 | 1860 | break;
|
nkeynes@359 | 1861 | case 0x1:
|
nkeynes@359 | 1862 | { /* TAS.B @Rn */
|
nkeynes@359 | 1863 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 1864 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1865 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 1866 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1867 | SETE_t();
|
nkeynes@361 | 1868 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 1869 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1870 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1871 | }
|
nkeynes@359 | 1872 | break;
|
nkeynes@359 | 1873 | case 0x2:
|
nkeynes@359 | 1874 | { /* JMP @Rn */
|
nkeynes@359 | 1875 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1876 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1877 | SLOTILLEGAL();
|
nkeynes@374 | 1878 | } else {
|
nkeynes@408 | 1879 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1880 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1881 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 1882 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 1883 | exit_block_pcset(pc+2);
|
nkeynes@408 | 1884 | return 4;
|
nkeynes@374 | 1885 | }
|
nkeynes@359 | 1886 | }
|
nkeynes@359 | 1887 | break;
|
nkeynes@359 | 1888 | default:
|
nkeynes@359 | 1889 | UNDEF();
|
nkeynes@359 | 1890 | break;
|
nkeynes@359 | 1891 | }
|
nkeynes@359 | 1892 | break;
|
nkeynes@359 | 1893 | case 0xC:
|
nkeynes@359 | 1894 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 1895 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1896 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1897 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1898 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1899 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1900 | JGE_rel8(16, doshl);
|
nkeynes@361 | 1901 |
|
nkeynes@361 | 1902 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 1903 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1904 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 1905 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1906 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 1907 |
|
nkeynes@386 | 1908 | JMP_TARGET(emptysar);
|
nkeynes@386 | 1909 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 1910 | JMP_rel8(5, end2);
|
nkeynes@386 | 1911 |
|
nkeynes@380 | 1912 | JMP_TARGET(doshl);
|
nkeynes@361 | 1913 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 1914 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 1915 | JMP_TARGET(end);
|
nkeynes@386 | 1916 | JMP_TARGET(end2);
|
nkeynes@361 | 1917 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1918 | }
|
nkeynes@359 | 1919 | break;
|
nkeynes@359 | 1920 | case 0xD:
|
nkeynes@359 | 1921 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 1922 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1923 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 1924 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 1925 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1926 | JGE_rel8(15, doshl);
|
nkeynes@368 | 1927 |
|
nkeynes@386 | 1928 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 1929 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1930 | JE_rel8( 4, emptyshr );
|
nkeynes@386 | 1931 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1932 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 1933 |
|
nkeynes@386 | 1934 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 1935 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 1936 | JMP_rel8(5, end2);
|
nkeynes@386 | 1937 |
|
nkeynes@386 | 1938 | JMP_TARGET(doshl);
|
nkeynes@386 | 1939 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1940 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1941 | JMP_TARGET(end);
|
nkeynes@386 | 1942 | JMP_TARGET(end2);
|
nkeynes@368 | 1943 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1944 | }
|
nkeynes@359 | 1945 | break;
|
nkeynes@359 | 1946 | case 0xE:
|
nkeynes@359 | 1947 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1948 | case 0x0:
|
nkeynes@359 | 1949 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1950 | case 0x0:
|
nkeynes@359 | 1951 | { /* LDC Rm, SR */
|
nkeynes@359 | 1952 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1953 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1954 | SLOTILLEGAL();
|
nkeynes@386 | 1955 | } else {
|
nkeynes@386 | 1956 | check_priv();
|
nkeynes@386 | 1957 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 1958 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1959 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1960 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 1961 | }
|
nkeynes@359 | 1962 | }
|
nkeynes@359 | 1963 | break;
|
nkeynes@359 | 1964 | case 0x1:
|
nkeynes@359 | 1965 | { /* LDC Rm, GBR */
|
nkeynes@359 | 1966 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1967 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1968 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1969 | }
|
nkeynes@359 | 1970 | break;
|
nkeynes@359 | 1971 | case 0x2:
|
nkeynes@359 | 1972 | { /* LDC Rm, VBR */
|
nkeynes@359 | 1973 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1974 | check_priv();
|
nkeynes@359 | 1975 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1976 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1977 | }
|
nkeynes@359 | 1978 | break;
|
nkeynes@359 | 1979 | case 0x3:
|
nkeynes@359 | 1980 | { /* LDC Rm, SSR */
|
nkeynes@359 | 1981 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1982 | check_priv();
|
nkeynes@359 | 1983 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1984 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1985 | }
|
nkeynes@359 | 1986 | break;
|
nkeynes@359 | 1987 | case 0x4:
|
nkeynes@359 | 1988 | { /* LDC Rm, SPC */
|
nkeynes@359 | 1989 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1990 | check_priv();
|
nkeynes@359 | 1991 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1992 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1993 | }
|
nkeynes@359 | 1994 | break;
|
nkeynes@359 | 1995 | default:
|
nkeynes@359 | 1996 | UNDEF();
|
nkeynes@359 | 1997 | break;
|
nkeynes@359 | 1998 | }
|
nkeynes@359 | 1999 | break;
|
nkeynes@359 | 2000 | case 0x1:
|
nkeynes@359 | 2001 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2002 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 2003 | check_priv();
|
nkeynes@374 | 2004 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2005 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 2006 | }
|
nkeynes@359 | 2007 | break;
|
nkeynes@359 | 2008 | }
|
nkeynes@359 | 2009 | break;
|
nkeynes@359 | 2010 | case 0xF:
|
nkeynes@359 | 2011 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2012 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 2013 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2014 | check_ralign16( R_ECX );
|
nkeynes@386 | 2015 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 2016 | check_ralign16( R_ECX );
|
nkeynes@386 | 2017 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 2018 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2019 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2020 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2021 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 2022 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2023 | POP_r32( R_ECX );
|
nkeynes@386 | 2024 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2025 |
|
nkeynes@386 | 2026 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2027 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 2028 | JE_rel8( 47, nosat );
|
nkeynes@386 | 2029 |
|
nkeynes@386 | 2030 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2031 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 2032 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2033 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2034 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 2035 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2036 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2037 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 2038 |
|
nkeynes@386 | 2039 | JMP_TARGET(positive);
|
nkeynes@386 | 2040 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2041 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2042 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 2043 |
|
nkeynes@386 | 2044 | JMP_TARGET(nosat);
|
nkeynes@386 | 2045 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2046 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2047 | JMP_TARGET(end);
|
nkeynes@386 | 2048 | JMP_TARGET(end2);
|
nkeynes@386 | 2049 | JMP_TARGET(end3);
|
nkeynes@359 | 2050 | }
|
nkeynes@359 | 2051 | break;
|
nkeynes@359 | 2052 | }
|
nkeynes@359 | 2053 | break;
|
nkeynes@359 | 2054 | case 0x5:
|
nkeynes@359 | 2055 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2056 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 2057 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2058 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@374 | 2059 | check_ralign32( R_ECX );
|
nkeynes@361 | 2060 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2061 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2062 | }
|
nkeynes@359 | 2063 | break;
|
nkeynes@359 | 2064 | case 0x6:
|
nkeynes@359 | 2065 | switch( ir&0xF ) {
|
nkeynes@359 | 2066 | case 0x0:
|
nkeynes@359 | 2067 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2068 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2069 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2070 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 2071 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2072 | }
|
nkeynes@359 | 2073 | break;
|
nkeynes@359 | 2074 | case 0x1:
|
nkeynes@359 | 2075 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2076 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2077 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 2078 | check_ralign16( R_ECX );
|
nkeynes@361 | 2079 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2080 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2081 | }
|
nkeynes@359 | 2082 | break;
|
nkeynes@359 | 2083 | case 0x2:
|
nkeynes@359 | 2084 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2085 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2086 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 2087 | check_ralign32( R_ECX );
|
nkeynes@361 | 2088 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2089 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2090 | }
|
nkeynes@359 | 2091 | break;
|
nkeynes@359 | 2092 | case 0x3:
|
nkeynes@359 | 2093 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2094 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2095 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2096 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2097 | }
|
nkeynes@359 | 2098 | break;
|
nkeynes@359 | 2099 | case 0x4:
|
nkeynes@359 | 2100 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2101 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2102 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2103 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 2104 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 2105 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2106 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2107 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2108 | }
|
nkeynes@359 | 2109 | break;
|
nkeynes@359 | 2110 | case 0x5:
|
nkeynes@359 | 2111 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2112 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2113 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2114 | check_ralign16( R_EAX );
|
nkeynes@361 | 2115 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2116 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 2117 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2118 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2119 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2120 | }
|
nkeynes@359 | 2121 | break;
|
nkeynes@359 | 2122 | case 0x6:
|
nkeynes@359 | 2123 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2124 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2125 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2126 | check_ralign32( R_EAX );
|
nkeynes@361 | 2127 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2128 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 2129 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2130 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2131 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2132 | }
|
nkeynes@359 | 2133 | break;
|
nkeynes@359 | 2134 | case 0x7:
|
nkeynes@359 | 2135 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2136 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2137 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2138 | NOT_r32( R_EAX );
|
nkeynes@359 | 2139 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2140 | }
|
nkeynes@359 | 2141 | break;
|
nkeynes@359 | 2142 | case 0x8:
|
nkeynes@359 | 2143 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2144 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2145 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2146 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 2147 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2148 | }
|
nkeynes@359 | 2149 | break;
|
nkeynes@359 | 2150 | case 0x9:
|
nkeynes@359 | 2151 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2152 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2153 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2154 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2155 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2156 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2157 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2158 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2159 | }
|
nkeynes@359 | 2160 | break;
|
nkeynes@359 | 2161 | case 0xA:
|
nkeynes@359 | 2162 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2163 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2164 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2165 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2166 | LDC_t();
|
nkeynes@359 | 2167 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2168 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2169 | SETC_t();
|
nkeynes@359 | 2170 | }
|
nkeynes@359 | 2171 | break;
|
nkeynes@359 | 2172 | case 0xB:
|
nkeynes@359 | 2173 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2174 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2175 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2176 | NEG_r32( R_EAX );
|
nkeynes@359 | 2177 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2178 | }
|
nkeynes@359 | 2179 | break;
|
nkeynes@359 | 2180 | case 0xC:
|
nkeynes@359 | 2181 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2182 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2183 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2184 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2185 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2186 | }
|
nkeynes@359 | 2187 | break;
|
nkeynes@359 | 2188 | case 0xD:
|
nkeynes@359 | 2189 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2190 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2191 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2192 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2193 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2194 | }
|
nkeynes@359 | 2195 | break;
|
nkeynes@359 | 2196 | case 0xE:
|
nkeynes@359 | 2197 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2198 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2199 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2200 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2201 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2202 | }
|
nkeynes@359 | 2203 | break;
|
nkeynes@359 | 2204 | case 0xF:
|
nkeynes@359 | 2205 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2206 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2207 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2208 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2209 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2210 | }
|
nkeynes@359 | 2211 | break;
|
nkeynes@359 | 2212 | }
|
nkeynes@359 | 2213 | break;
|
nkeynes@359 | 2214 | case 0x7:
|
nkeynes@359 | 2215 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2216 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2217 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2218 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2219 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2220 | }
|
nkeynes@359 | 2221 | break;
|
nkeynes@359 | 2222 | case 0x8:
|
nkeynes@359 | 2223 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2224 | case 0x0:
|
nkeynes@359 | 2225 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2226 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2227 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2228 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 2229 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2230 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2231 | }
|
nkeynes@359 | 2232 | break;
|
nkeynes@359 | 2233 | case 0x1:
|
nkeynes@359 | 2234 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2235 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2236 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 2237 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2238 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2239 | check_walign16( R_ECX );
|
nkeynes@361 | 2240 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 2241 | }
|
nkeynes@359 | 2242 | break;
|
nkeynes@359 | 2243 | case 0x4:
|
nkeynes@359 | 2244 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2245 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2246 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2247 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2248 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2249 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2250 | }
|
nkeynes@359 | 2251 | break;
|
nkeynes@359 | 2252 | case 0x5:
|
nkeynes@359 | 2253 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2254 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2255 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2256 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2257 | check_ralign16( R_ECX );
|
nkeynes@361 | 2258 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2259 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2260 | }
|
nkeynes@359 | 2261 | break;
|
nkeynes@359 | 2262 | case 0x8:
|
nkeynes@359 | 2263 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2264 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2265 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2266 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2267 | SETE_t();
|
nkeynes@359 | 2268 | }
|
nkeynes@359 | 2269 | break;
|
nkeynes@359 | 2270 | case 0x9:
|
nkeynes@359 | 2271 | { /* BT disp */
|
nkeynes@359 | 2272 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2273 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2274 | SLOTILLEGAL();
|
nkeynes@374 | 2275 | } else {
|
nkeynes@374 | 2276 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 2277 | JE_rel8( 30, nottaken );
|
nkeynes@408 | 2278 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 2279 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2280 | exit_block( pc + 2, pc+2 );
|
nkeynes@408 | 2281 | return 2;
|
nkeynes@374 | 2282 | }
|
nkeynes@359 | 2283 | }
|
nkeynes@359 | 2284 | break;
|
nkeynes@359 | 2285 | case 0xB:
|
nkeynes@359 | 2286 | { /* BF disp */
|
nkeynes@359 | 2287 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2288 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2289 | SLOTILLEGAL();
|
nkeynes@374 | 2290 | } else {
|
nkeynes@374 | 2291 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 2292 | JNE_rel8( 30, nottaken );
|
nkeynes@408 | 2293 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 2294 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2295 | exit_block( pc + 2, pc + 2 );
|
nkeynes@408 | 2296 | return 2;
|
nkeynes@374 | 2297 | }
|
nkeynes@359 | 2298 | }
|
nkeynes@359 | 2299 | break;
|
nkeynes@359 | 2300 | case 0xD:
|
nkeynes@359 | 2301 | { /* BT/S disp */
|
nkeynes@359 | 2302 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2303 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2304 | SLOTILLEGAL();
|
nkeynes@374 | 2305 | } else {
|
nkeynes@408 | 2306 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2307 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 2308 | OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@408 | 2309 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 2310 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2311 | // not taken
|
nkeynes@408 | 2312 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@408 | 2313 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 2314 | exit_block( pc + 4, pc+4 );
|
nkeynes@408 | 2315 | return 4;
|
nkeynes@374 | 2316 | }
|
nkeynes@359 | 2317 | }
|
nkeynes@359 | 2318 | break;
|
nkeynes@359 | 2319 | case 0xF:
|
nkeynes@359 | 2320 | { /* BF/S disp */
|
nkeynes@359 | 2321 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2322 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2323 | SLOTILLEGAL();
|
nkeynes@374 | 2324 | } else {
|
nkeynes@408 | 2325 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2326 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@408 | 2327 | OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@408 | 2328 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 2329 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2330 | // not taken
|
nkeynes@408 | 2331 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@408 | 2332 | sh4_x86_translate_instruction(pc+2);
|
nkeynes@408 | 2333 | exit_block( pc + 4, pc+4 );
|
nkeynes@408 | 2334 | return 4;
|
nkeynes@374 | 2335 | }
|
nkeynes@359 | 2336 | }
|
nkeynes@359 | 2337 | break;
|
nkeynes@359 | 2338 | default:
|
nkeynes@359 | 2339 | UNDEF();
|
nkeynes@359 | 2340 | break;
|
nkeynes@359 | 2341 | }
|
nkeynes@359 | 2342 | break;
|
nkeynes@359 | 2343 | case 0x9:
|
nkeynes@359 | 2344 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2345 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@374 | 2346 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2347 | SLOTILLEGAL();
|
nkeynes@374 | 2348 | } else {
|
nkeynes@374 | 2349 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 2350 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 2351 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2352 | }
|
nkeynes@359 | 2353 | }
|
nkeynes@359 | 2354 | break;
|
nkeynes@359 | 2355 | case 0xA:
|
nkeynes@359 | 2356 | { /* BRA disp */
|
nkeynes@359 | 2357 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2358 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2359 | SLOTILLEGAL();
|
nkeynes@374 | 2360 | } else {
|
nkeynes@374 | 2361 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 2362 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 2363 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2364 | return 4;
|
nkeynes@374 | 2365 | }
|
nkeynes@359 | 2366 | }
|
nkeynes@359 | 2367 | break;
|
nkeynes@359 | 2368 | case 0xB:
|
nkeynes@359 | 2369 | { /* BSR disp */
|
nkeynes@359 | 2370 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2371 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2372 | SLOTILLEGAL();
|
nkeynes@374 | 2373 | } else {
|
nkeynes@374 | 2374 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 2375 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 2376 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@408 | 2377 | sh4_x86_translate_instruction( pc + 2 );
|
nkeynes@408 | 2378 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2379 | return 4;
|
nkeynes@374 | 2380 | }
|
nkeynes@359 | 2381 | }
|
nkeynes@359 | 2382 | break;
|
nkeynes@359 | 2383 | case 0xC:
|
nkeynes@359 | 2384 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2385 | case 0x0:
|
nkeynes@359 | 2386 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2387 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2388 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2389 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2390 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2391 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2392 | }
|
nkeynes@359 | 2393 | break;
|
nkeynes@359 | 2394 | case 0x1:
|
nkeynes@359 | 2395 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2396 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2397 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2398 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2399 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2400 | check_walign16( R_ECX );
|
nkeynes@361 | 2401 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 2402 | }
|
nkeynes@359 | 2403 | break;
|
nkeynes@359 | 2404 | case 0x2:
|
nkeynes@359 | 2405 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2406 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2407 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2408 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2409 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2410 | check_walign32( R_ECX );
|
nkeynes@361 | 2411 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2412 | }
|
nkeynes@359 | 2413 | break;
|
nkeynes@359 | 2414 | case 0x3:
|
nkeynes@359 | 2415 | { /* TRAPA #imm */
|
nkeynes@359 | 2416 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2417 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2418 | SLOTILLEGAL();
|
nkeynes@374 | 2419 | } else {
|
nkeynes@388 | 2420 | PUSH_imm32( imm );
|
nkeynes@388 | 2421 | call_func0( sh4_raise_trap );
|
nkeynes@388 | 2422 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@408 | 2423 | exit_block_pcset(pc);
|
nkeynes@408 | 2424 | return 2;
|
nkeynes@374 | 2425 | }
|
nkeynes@359 | 2426 | }
|
nkeynes@359 | 2427 | break;
|
nkeynes@359 | 2428 | case 0x4:
|
nkeynes@359 | 2429 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2430 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2431 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2432 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2433 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2434 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2435 | }
|
nkeynes@359 | 2436 | break;
|
nkeynes@359 | 2437 | case 0x5:
|
nkeynes@359 | 2438 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2439 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2440 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2441 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2442 | check_ralign16( R_ECX );
|
nkeynes@361 | 2443 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2444 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2445 | }
|
nkeynes@359 | 2446 | break;
|
nkeynes@359 | 2447 | case 0x6:
|
nkeynes@359 | 2448 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2449 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2450 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2451 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2452 | check_ralign32( R_ECX );
|
nkeynes@361 | 2453 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2454 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2455 | }
|
nkeynes@359 | 2456 | break;
|
nkeynes@359 | 2457 | case 0x7:
|
nkeynes@359 | 2458 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2459 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2460 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2461 | SLOTILLEGAL();
|
nkeynes@374 | 2462 | } else {
|
nkeynes@374 | 2463 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 2464 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 2465 | }
|
nkeynes@359 | 2466 | }
|
nkeynes@359 | 2467 | break;
|
nkeynes@359 | 2468 | case 0x8:
|
nkeynes@359 | 2469 | { /* TST #imm, R0 */
|
nkeynes@359 | 2470 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2471 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2472 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2473 | SETE_t();
|
nkeynes@359 | 2474 | }
|
nkeynes@359 | 2475 | break;
|
nkeynes@359 | 2476 | case 0x9:
|
nkeynes@359 | 2477 | { /* AND #imm, R0 */
|
nkeynes@359 | 2478 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2479 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2480 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2481 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2482 | }
|
nkeynes@359 | 2483 | break;
|
nkeynes@359 | 2484 | case 0xA:
|
nkeynes@359 | 2485 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2486 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2487 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2488 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2489 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2490 | }
|
nkeynes@359 | 2491 | break;
|
nkeynes@359 | 2492 | case 0xB:
|
nkeynes@359 | 2493 | { /* OR #imm, R0 */
|
nkeynes@359 | 2494 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2495 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2496 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2497 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2498 | }
|
nkeynes@359 | 2499 | break;
|
nkeynes@359 | 2500 | case 0xC:
|
nkeynes@359 | 2501 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2502 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2503 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2504 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 2505 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 2506 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 2507 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2508 | SETE_t();
|
nkeynes@359 | 2509 | }
|
nkeynes@359 | 2510 | break;
|
nkeynes@359 | 2511 | case 0xD:
|
nkeynes@359 | 2512 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2513 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2514 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2515 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2516 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2517 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2518 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2519 | POP_r32(R_ECX);
|
nkeynes@386 | 2520 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2521 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2522 | }
|
nkeynes@359 | 2523 | break;
|
nkeynes@359 | 2524 | case 0xE:
|
nkeynes@359 | 2525 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2526 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2527 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2528 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2529 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2530 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2531 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2532 | POP_r32(R_ECX);
|
nkeynes@359 | 2533 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2534 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2535 | }
|
nkeynes@359 | 2536 | break;
|
nkeynes@359 | 2537 | case 0xF:
|
nkeynes@359 | 2538 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2539 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2540 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2541 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2542 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2543 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2544 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2545 | POP_r32(R_ECX);
|
nkeynes@386 | 2546 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2547 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2548 | }
|
nkeynes@359 | 2549 | break;
|
nkeynes@359 | 2550 | }
|
nkeynes@359 | 2551 | break;
|
nkeynes@359 | 2552 | case 0xD:
|
nkeynes@359 | 2553 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2554 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2555 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2556 | SLOTILLEGAL();
|
nkeynes@374 | 2557 | } else {
|
nkeynes@388 | 2558 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@388 | 2559 | char *ptr = mem_get_region(target);
|
nkeynes@388 | 2560 | if( ptr != NULL ) {
|
nkeynes@388 | 2561 | MOV_moff32_EAX( (uint32_t)ptr );
|
nkeynes@388 | 2562 | } else {
|
nkeynes@388 | 2563 | load_imm32( R_ECX, target );
|
nkeynes@388 | 2564 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 2565 | }
|
nkeynes@386 | 2566 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2567 | }
|
nkeynes@359 | 2568 | }
|
nkeynes@359 | 2569 | break;
|
nkeynes@359 | 2570 | case 0xE:
|
nkeynes@359 | 2571 | { /* MOV #imm, Rn */
|
nkeynes@359 | 2572 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2573 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 2574 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2575 | }
|
nkeynes@359 | 2576 | break;
|
nkeynes@359 | 2577 | case 0xF:
|
nkeynes@359 | 2578 | switch( ir&0xF ) {
|
nkeynes@359 | 2579 | case 0x0:
|
nkeynes@359 | 2580 | { /* FADD FRm, FRn */
|
nkeynes@359 | 2581 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2582 | check_fpuen();
|
nkeynes@377 | 2583 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2584 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2585 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2586 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 2587 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2588 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2589 | FADDP_st(1);
|
nkeynes@377 | 2590 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2591 | JMP_rel8(11,end);
|
nkeynes@380 | 2592 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2593 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2594 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2595 | FADDP_st(1);
|
nkeynes@377 | 2596 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2597 | JMP_TARGET(end);
|
nkeynes@359 | 2598 | }
|
nkeynes@359 | 2599 | break;
|
nkeynes@359 | 2600 | case 0x1:
|
nkeynes@359 | 2601 | { /* FSUB FRm, FRn */
|
nkeynes@359 | 2602 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2603 | check_fpuen();
|
nkeynes@377 | 2604 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2605 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2606 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2607 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2608 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2609 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 2610 | FSUBP_st(1);
|
nkeynes@377 | 2611 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2612 | JMP_rel8(11, end);
|
nkeynes@380 | 2613 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2614 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2615 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 2616 | FSUBP_st(1);
|
nkeynes@377 | 2617 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2618 | JMP_TARGET(end);
|
nkeynes@359 | 2619 | }
|
nkeynes@359 | 2620 | break;
|
nkeynes@359 | 2621 | case 0x2:
|
nkeynes@359 | 2622 | { /* FMUL FRm, FRn */
|
nkeynes@359 | 2623 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2624 | check_fpuen();
|
nkeynes@377 | 2625 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2626 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2627 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2628 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2629 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2630 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2631 | FMULP_st(1);
|
nkeynes@377 | 2632 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2633 | JMP_rel8(11, end);
|
nkeynes@380 | 2634 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2635 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2636 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2637 | FMULP_st(1);
|
nkeynes@377 | 2638 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2639 | JMP_TARGET(end);
|
nkeynes@359 | 2640 | }
|
nkeynes@359 | 2641 | break;
|
nkeynes@359 | 2642 | case 0x3:
|
nkeynes@359 | 2643 | { /* FDIV FRm, FRn */
|
nkeynes@359 | 2644 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2645 | check_fpuen();
|
nkeynes@377 | 2646 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2647 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2648 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2649 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2650 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2651 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2652 | FDIVP_st(1);
|
nkeynes@377 | 2653 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2654 | JMP_rel8(11, end);
|
nkeynes@380 | 2655 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2656 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2657 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2658 | FDIVP_st(1);
|
nkeynes@377 | 2659 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2660 | JMP_TARGET(end);
|
nkeynes@359 | 2661 | }
|
nkeynes@359 | 2662 | break;
|
nkeynes@359 | 2663 | case 0x4:
|
nkeynes@359 | 2664 | { /* FCMP/EQ FRm, FRn */
|
nkeynes@359 | 2665 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2666 | check_fpuen();
|
nkeynes@377 | 2667 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2668 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2669 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2670 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2671 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2672 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2673 | JMP_rel8(6, end);
|
nkeynes@380 | 2674 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2675 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2676 | push_dr(R_EDX, FRn);
|
nkeynes@386 | 2677 | JMP_TARGET(end);
|
nkeynes@377 | 2678 | FCOMIP_st(1);
|
nkeynes@377 | 2679 | SETE_t();
|
nkeynes@377 | 2680 | FPOP_st();
|
nkeynes@359 | 2681 | }
|
nkeynes@359 | 2682 | break;
|
nkeynes@359 | 2683 | case 0x5:
|
nkeynes@359 | 2684 | { /* FCMP/GT FRm, FRn */
|
nkeynes@359 | 2685 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2686 | check_fpuen();
|
nkeynes@377 | 2687 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2688 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2689 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2690 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2691 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2692 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2693 | JMP_rel8(6, end);
|
nkeynes@380 | 2694 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2695 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2696 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 2697 | JMP_TARGET(end);
|
nkeynes@377 | 2698 | FCOMIP_st(1);
|
nkeynes@377 | 2699 | SETA_t();
|
nkeynes@377 | 2700 | FPOP_st();
|
nkeynes@359 | 2701 | }
|
nkeynes@359 | 2702 | break;
|
nkeynes@359 | 2703 | case 0x6:
|
nkeynes@359 | 2704 | { /* FMOV @(R0, Rm), FRn */
|
nkeynes@359 | 2705 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@377 | 2706 | check_fpuen();
|
nkeynes@375 | 2707 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 2708 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@375 | 2709 | check_ralign32( R_EDX );
|
nkeynes@375 | 2710 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2711 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2712 | JNE_rel8(19, doublesize);
|
nkeynes@375 | 2713 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 2714 | load_fr_bank( R_ECX );
|
nkeynes@375 | 2715 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 2716 | if( FRn&1 ) {
|
nkeynes@386 | 2717 | JMP_rel8(48, end);
|
nkeynes@380 | 2718 | JMP_TARGET(doublesize);
|
nkey |