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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 408:af496b734734
prev401:f79327f39818
next409:549e00835448
author nkeynes
date Fri Sep 28 07:27:20 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Change block signature to return pointer to next block (if known)
Rewrite block-exit code
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.16 2007-09-28 07:27:20 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    uint32_t block_start_pc;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   352
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   353
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   354
nkeynes@386
   355
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   356
nkeynes@368
   357
nkeynes@359
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   361
 * SI/DI as required
nkeynes@359
   362
 */
nkeynes@408
   363
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   364
{
nkeynes@368
   365
    PUSH_r32(R_EBP);
nkeynes@359
   366
    /* mov &sh4r, ebp */
nkeynes@359
   367
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@368
   368
    PUSH_r32(R_ESI);
nkeynes@380
   369
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   370
    
nkeynes@368
   371
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   372
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   373
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   374
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   375
    sh4_x86.block_start_pc = pc;
nkeynes@368
   376
}
nkeynes@359
   377
nkeynes@368
   378
/**
nkeynes@408
   379
 * Exit the block to an absolute PC
nkeynes@408
   380
 * Bytes: 30
nkeynes@368
   381
 */
nkeynes@408
   382
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@368
   383
{
nkeynes@408
   384
    load_imm32( R_ECX, pc );                            // 5
nkeynes@408
   385
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@408
   386
    MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
nkeynes@408
   387
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@408
   388
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   389
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@374
   390
    POP_r32(R_ESI);
nkeynes@374
   391
    POP_r32(R_EBP);
nkeynes@368
   392
    RET();
nkeynes@359
   393
}
nkeynes@359
   394
nkeynes@359
   395
/**
nkeynes@408
   396
 * Exit the block with sh4r.pc already written
nkeynes@408
   397
 * Bytes: 16
nkeynes@408
   398
 */
nkeynes@408
   399
void exit_block_pcset( pc )
nkeynes@408
   400
{
nkeynes@408
   401
    XOR_r32_r32( R_EAX, R_EAX );                       // 2
nkeynes@408
   402
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   403
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@408
   404
    POP_r32(R_ESI);
nkeynes@408
   405
    POP_r32(R_EBP);
nkeynes@408
   406
    RET();
nkeynes@408
   407
}
nkeynes@408
   408
nkeynes@408
   409
/**
nkeynes@408
   410
 * Write the block trailer (exception handling block)
nkeynes@359
   411
 */
nkeynes@359
   412
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@388
   413
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   414
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   415
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   416
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   417
	JMP_rel8( 33, target1 );
nkeynes@388
   418
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   419
	JMP_rel8( 26, target2 );
nkeynes@388
   420
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   421
	JMP_rel8( 19, target3 );
nkeynes@388
   422
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   423
	JMP_rel8( 12, target4 );
nkeynes@388
   424
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   425
	JMP_rel8( 5, target5 );
nkeynes@388
   426
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   427
	// target
nkeynes@388
   428
	JMP_TARGET(target1);
nkeynes@388
   429
	JMP_TARGET(target2);
nkeynes@388
   430
	JMP_TARGET(target3);
nkeynes@388
   431
	JMP_TARGET(target4);
nkeynes@388
   432
	JMP_TARGET(target5);
nkeynes@388
   433
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   434
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   435
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   436
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   437
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388
   438
	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   439
	MUL_r32( R_ESI );
nkeynes@388
   440
	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388
   441
	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   442
	
nkeynes@388
   443
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   444
	CALL_r32( R_EAX ); // 2
nkeynes@388
   445
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@408
   446
	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@388
   447
	POP_r32(R_ESI);
nkeynes@388
   448
	POP_r32(R_EBP);
nkeynes@388
   449
	RET();
nkeynes@368
   450
nkeynes@388
   451
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   452
    }
nkeynes@368
   453
nkeynes@359
   454
}
nkeynes@359
   455
nkeynes@388
   456
nkeynes@388
   457
extern uint16_t *sh4_icache;
nkeynes@388
   458
extern uint32_t sh4_icache_addr;
nkeynes@388
   459
nkeynes@359
   460
/**
nkeynes@359
   461
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   462
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   463
 * 
nkeynes@359
   464
 *
nkeynes@359
   465
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   466
 * (eg a branch or 
nkeynes@359
   467
 */
nkeynes@408
   468
uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
nkeynes@359
   469
{
nkeynes@388
   470
    uint32_t ir;
nkeynes@388
   471
    /* Read instruction */
nkeynes@388
   472
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   473
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   474
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   475
    } else {
nkeynes@388
   476
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   477
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   478
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   479
	     * region, fallback on the full-blown memory read
nkeynes@388
   480
	     */
nkeynes@388
   481
	    sh4_icache = NULL;
nkeynes@388
   482
	    ir = sh4_read_word(pc);
nkeynes@388
   483
	} else {
nkeynes@388
   484
	    sh4_icache_addr = pageaddr;
nkeynes@388
   485
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   486
	}
nkeynes@388
   487
    }
nkeynes@388
   488
nkeynes@359
   489
%%
nkeynes@359
   490
/* ALU operations */
nkeynes@359
   491
ADD Rm, Rn {:
nkeynes@359
   492
    load_reg( R_EAX, Rm );
nkeynes@359
   493
    load_reg( R_ECX, Rn );
nkeynes@359
   494
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   495
    store_reg( R_ECX, Rn );
nkeynes@359
   496
:}
nkeynes@359
   497
ADD #imm, Rn {:  
nkeynes@359
   498
    load_reg( R_EAX, Rn );
nkeynes@359
   499
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   500
    store_reg( R_EAX, Rn );
nkeynes@359
   501
:}
nkeynes@359
   502
ADDC Rm, Rn {:
nkeynes@359
   503
    load_reg( R_EAX, Rm );
nkeynes@359
   504
    load_reg( R_ECX, Rn );
nkeynes@359
   505
    LDC_t();
nkeynes@359
   506
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   507
    store_reg( R_ECX, Rn );
nkeynes@359
   508
    SETC_t();
nkeynes@359
   509
:}
nkeynes@359
   510
ADDV Rm, Rn {:
nkeynes@359
   511
    load_reg( R_EAX, Rm );
nkeynes@359
   512
    load_reg( R_ECX, Rn );
nkeynes@359
   513
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   514
    store_reg( R_ECX, Rn );
nkeynes@359
   515
    SETO_t();
nkeynes@359
   516
:}
nkeynes@359
   517
AND Rm, Rn {:
nkeynes@359
   518
    load_reg( R_EAX, Rm );
nkeynes@359
   519
    load_reg( R_ECX, Rn );
nkeynes@359
   520
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   521
    store_reg( R_ECX, Rn );
nkeynes@359
   522
:}
nkeynes@359
   523
AND #imm, R0 {:  
nkeynes@359
   524
    load_reg( R_EAX, 0 );
nkeynes@359
   525
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   526
    store_reg( R_EAX, 0 );
nkeynes@359
   527
:}
nkeynes@359
   528
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   529
    load_reg( R_EAX, 0 );
nkeynes@359
   530
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   531
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   532
    PUSH_r32(R_ECX);
nkeynes@386
   533
    call_func0(sh4_read_byte);
nkeynes@386
   534
    POP_r32(R_ECX);
nkeynes@386
   535
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   536
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   537
:}
nkeynes@359
   538
CMP/EQ Rm, Rn {:  
nkeynes@359
   539
    load_reg( R_EAX, Rm );
nkeynes@359
   540
    load_reg( R_ECX, Rn );
nkeynes@359
   541
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   542
    SETE_t();
nkeynes@359
   543
:}
nkeynes@359
   544
CMP/EQ #imm, R0 {:  
nkeynes@359
   545
    load_reg( R_EAX, 0 );
nkeynes@359
   546
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   547
    SETE_t();
nkeynes@359
   548
:}
nkeynes@359
   549
CMP/GE Rm, Rn {:  
nkeynes@359
   550
    load_reg( R_EAX, Rm );
nkeynes@359
   551
    load_reg( R_ECX, Rn );
nkeynes@359
   552
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   553
    SETGE_t();
nkeynes@359
   554
:}
nkeynes@359
   555
CMP/GT Rm, Rn {: 
nkeynes@359
   556
    load_reg( R_EAX, Rm );
nkeynes@359
   557
    load_reg( R_ECX, Rn );
nkeynes@359
   558
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   559
    SETG_t();
nkeynes@359
   560
:}
nkeynes@359
   561
CMP/HI Rm, Rn {:  
nkeynes@359
   562
    load_reg( R_EAX, Rm );
nkeynes@359
   563
    load_reg( R_ECX, Rn );
nkeynes@359
   564
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   565
    SETA_t();
nkeynes@359
   566
:}
nkeynes@359
   567
CMP/HS Rm, Rn {: 
nkeynes@359
   568
    load_reg( R_EAX, Rm );
nkeynes@359
   569
    load_reg( R_ECX, Rn );
nkeynes@359
   570
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   571
    SETAE_t();
nkeynes@359
   572
 :}
nkeynes@359
   573
CMP/PL Rn {: 
nkeynes@359
   574
    load_reg( R_EAX, Rn );
nkeynes@359
   575
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   576
    SETG_t();
nkeynes@359
   577
:}
nkeynes@359
   578
CMP/PZ Rn {:  
nkeynes@359
   579
    load_reg( R_EAX, Rn );
nkeynes@359
   580
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   581
    SETGE_t();
nkeynes@359
   582
:}
nkeynes@361
   583
CMP/STR Rm, Rn {:  
nkeynes@368
   584
    load_reg( R_EAX, Rm );
nkeynes@368
   585
    load_reg( R_ECX, Rn );
nkeynes@368
   586
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   587
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   588
    JE_rel8(13, target1);
nkeynes@368
   589
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   590
    JE_rel8(9, target2);
nkeynes@368
   591
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   592
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   593
    JE_rel8(2, target3);
nkeynes@368
   594
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   595
    JMP_TARGET(target1);
nkeynes@380
   596
    JMP_TARGET(target2);
nkeynes@380
   597
    JMP_TARGET(target3);
nkeynes@368
   598
    SETE_t();
nkeynes@361
   599
:}
nkeynes@361
   600
DIV0S Rm, Rn {:
nkeynes@361
   601
    load_reg( R_EAX, Rm );
nkeynes@386
   602
    load_reg( R_ECX, Rn );
nkeynes@361
   603
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   604
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   605
    store_spreg( R_EAX, R_M );
nkeynes@361
   606
    store_spreg( R_ECX, R_Q );
nkeynes@361
   607
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   608
    SETNE_t();
nkeynes@361
   609
:}
nkeynes@361
   610
DIV0U {:  
nkeynes@361
   611
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   612
    store_spreg( R_EAX, R_Q );
nkeynes@361
   613
    store_spreg( R_EAX, R_M );
nkeynes@361
   614
    store_spreg( R_EAX, R_T );
nkeynes@361
   615
:}
nkeynes@386
   616
DIV1 Rm, Rn {:
nkeynes@386
   617
    load_spreg( R_ECX, R_M );
nkeynes@386
   618
    load_reg( R_EAX, Rn );
nkeynes@374
   619
    LDC_t();
nkeynes@386
   620
    RCL1_r32( R_EAX );
nkeynes@386
   621
    SETC_r8( R_DL ); // Q'
nkeynes@386
   622
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   623
    JE_rel8(5, mqequal);
nkeynes@386
   624
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   625
    JMP_rel8(3, end);
nkeynes@380
   626
    JMP_TARGET(mqequal);
nkeynes@386
   627
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   628
    JMP_TARGET(end);
nkeynes@386
   629
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   630
    SETC_r8(R_AL); // tmp1
nkeynes@386
   631
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   632
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   633
    store_spreg( R_ECX, R_Q );
nkeynes@386
   634
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   635
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   636
    store_spreg( R_EAX, R_T );
nkeynes@374
   637
:}
nkeynes@361
   638
DMULS.L Rm, Rn {:  
nkeynes@361
   639
    load_reg( R_EAX, Rm );
nkeynes@361
   640
    load_reg( R_ECX, Rn );
nkeynes@361
   641
    IMUL_r32(R_ECX);
nkeynes@361
   642
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   643
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   644
:}
nkeynes@361
   645
DMULU.L Rm, Rn {:  
nkeynes@361
   646
    load_reg( R_EAX, Rm );
nkeynes@361
   647
    load_reg( R_ECX, Rn );
nkeynes@361
   648
    MUL_r32(R_ECX);
nkeynes@361
   649
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   650
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   651
:}
nkeynes@359
   652
DT Rn {:  
nkeynes@359
   653
    load_reg( R_EAX, Rn );
nkeynes@382
   654
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   655
    store_reg( R_EAX, Rn );
nkeynes@359
   656
    SETE_t();
nkeynes@359
   657
:}
nkeynes@359
   658
EXTS.B Rm, Rn {:  
nkeynes@359
   659
    load_reg( R_EAX, Rm );
nkeynes@359
   660
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   661
    store_reg( R_EAX, Rn );
nkeynes@359
   662
:}
nkeynes@361
   663
EXTS.W Rm, Rn {:  
nkeynes@361
   664
    load_reg( R_EAX, Rm );
nkeynes@361
   665
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   666
    store_reg( R_EAX, Rn );
nkeynes@361
   667
:}
nkeynes@361
   668
EXTU.B Rm, Rn {:  
nkeynes@361
   669
    load_reg( R_EAX, Rm );
nkeynes@361
   670
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   671
    store_reg( R_EAX, Rn );
nkeynes@361
   672
:}
nkeynes@361
   673
EXTU.W Rm, Rn {:  
nkeynes@361
   674
    load_reg( R_EAX, Rm );
nkeynes@361
   675
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   676
    store_reg( R_EAX, Rn );
nkeynes@361
   677
:}
nkeynes@386
   678
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   679
    load_reg( R_ECX, Rm );
nkeynes@386
   680
    check_ralign32( R_ECX );
nkeynes@386
   681
    load_reg( R_ECX, Rn );
nkeynes@386
   682
    check_ralign32( R_ECX );
nkeynes@386
   683
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   684
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   685
    PUSH_r32( R_EAX );
nkeynes@386
   686
    load_reg( R_ECX, Rm );
nkeynes@386
   687
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   688
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   689
    POP_r32( R_ECX );
nkeynes@386
   690
    IMUL_r32( R_ECX );
nkeynes@386
   691
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   692
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   693
nkeynes@386
   694
    load_spreg( R_ECX, R_S );
nkeynes@386
   695
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   696
    JE_rel8( 7, nosat );
nkeynes@386
   697
    call_func0( signsat48 );
nkeynes@386
   698
    JMP_TARGET( nosat );
nkeynes@386
   699
:}
nkeynes@386
   700
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   701
    load_reg( R_ECX, Rm );
nkeynes@386
   702
    check_ralign16( R_ECX );
nkeynes@386
   703
    load_reg( R_ECX, Rn );
nkeynes@386
   704
    check_ralign16( R_ECX );
nkeynes@386
   705
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   706
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   707
    PUSH_r32( R_EAX );
nkeynes@386
   708
    load_reg( R_ECX, Rm );
nkeynes@386
   709
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   710
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   711
    POP_r32( R_ECX );
nkeynes@386
   712
    IMUL_r32( R_ECX );
nkeynes@386
   713
nkeynes@386
   714
    load_spreg( R_ECX, R_S );
nkeynes@386
   715
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   716
    JE_rel8( 47, nosat );
nkeynes@386
   717
nkeynes@386
   718
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   719
    JNO_rel8( 51, end );            // 2
nkeynes@386
   720
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   721
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   722
    JS_rel8( 13, positive );        // 2
nkeynes@386
   723
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   724
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   725
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   726
nkeynes@386
   727
    JMP_TARGET(positive);
nkeynes@386
   728
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   729
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   730
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   731
nkeynes@386
   732
    JMP_TARGET(nosat);
nkeynes@386
   733
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   734
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   735
    JMP_TARGET(end);
nkeynes@386
   736
    JMP_TARGET(end2);
nkeynes@386
   737
    JMP_TARGET(end3);
nkeynes@386
   738
:}
nkeynes@359
   739
MOVT Rn {:  
nkeynes@359
   740
    load_spreg( R_EAX, R_T );
nkeynes@359
   741
    store_reg( R_EAX, Rn );
nkeynes@359
   742
:}
nkeynes@361
   743
MUL.L Rm, Rn {:  
nkeynes@361
   744
    load_reg( R_EAX, Rm );
nkeynes@361
   745
    load_reg( R_ECX, Rn );
nkeynes@361
   746
    MUL_r32( R_ECX );
nkeynes@361
   747
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   748
:}
nkeynes@374
   749
MULS.W Rm, Rn {:
nkeynes@374
   750
    load_reg16s( R_EAX, Rm );
nkeynes@374
   751
    load_reg16s( R_ECX, Rn );
nkeynes@374
   752
    MUL_r32( R_ECX );
nkeynes@374
   753
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   754
:}
nkeynes@374
   755
MULU.W Rm, Rn {:  
nkeynes@374
   756
    load_reg16u( R_EAX, Rm );
nkeynes@374
   757
    load_reg16u( R_ECX, Rn );
nkeynes@374
   758
    MUL_r32( R_ECX );
nkeynes@374
   759
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   760
:}
nkeynes@359
   761
NEG Rm, Rn {:
nkeynes@359
   762
    load_reg( R_EAX, Rm );
nkeynes@359
   763
    NEG_r32( R_EAX );
nkeynes@359
   764
    store_reg( R_EAX, Rn );
nkeynes@359
   765
:}
nkeynes@359
   766
NEGC Rm, Rn {:  
nkeynes@359
   767
    load_reg( R_EAX, Rm );
nkeynes@359
   768
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   769
    LDC_t();
nkeynes@359
   770
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   771
    store_reg( R_ECX, Rn );
nkeynes@359
   772
    SETC_t();
nkeynes@359
   773
:}
nkeynes@359
   774
NOT Rm, Rn {:  
nkeynes@359
   775
    load_reg( R_EAX, Rm );
nkeynes@359
   776
    NOT_r32( R_EAX );
nkeynes@359
   777
    store_reg( R_EAX, Rn );
nkeynes@359
   778
:}
nkeynes@359
   779
OR Rm, Rn {:  
nkeynes@359
   780
    load_reg( R_EAX, Rm );
nkeynes@359
   781
    load_reg( R_ECX, Rn );
nkeynes@359
   782
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   783
    store_reg( R_ECX, Rn );
nkeynes@359
   784
:}
nkeynes@359
   785
OR #imm, R0 {:
nkeynes@359
   786
    load_reg( R_EAX, 0 );
nkeynes@359
   787
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   788
    store_reg( R_EAX, 0 );
nkeynes@359
   789
:}
nkeynes@374
   790
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   791
    load_reg( R_EAX, 0 );
nkeynes@374
   792
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   793
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   794
    PUSH_r32(R_ECX);
nkeynes@386
   795
    call_func0(sh4_read_byte);
nkeynes@386
   796
    POP_r32(R_ECX);
nkeynes@386
   797
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   798
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   799
:}
nkeynes@359
   800
ROTCL Rn {:
nkeynes@359
   801
    load_reg( R_EAX, Rn );
nkeynes@359
   802
    LDC_t();
nkeynes@359
   803
    RCL1_r32( R_EAX );
nkeynes@359
   804
    store_reg( R_EAX, Rn );
nkeynes@359
   805
    SETC_t();
nkeynes@359
   806
:}
nkeynes@359
   807
ROTCR Rn {:  
nkeynes@359
   808
    load_reg( R_EAX, Rn );
nkeynes@359
   809
    LDC_t();
nkeynes@359
   810
    RCR1_r32( R_EAX );
nkeynes@359
   811
    store_reg( R_EAX, Rn );
nkeynes@359
   812
    SETC_t();
nkeynes@359
   813
:}
nkeynes@359
   814
ROTL Rn {:  
nkeynes@359
   815
    load_reg( R_EAX, Rn );
nkeynes@359
   816
    ROL1_r32( R_EAX );
nkeynes@359
   817
    store_reg( R_EAX, Rn );
nkeynes@359
   818
    SETC_t();
nkeynes@359
   819
:}
nkeynes@359
   820
ROTR Rn {:  
nkeynes@359
   821
    load_reg( R_EAX, Rn );
nkeynes@359
   822
    ROR1_r32( R_EAX );
nkeynes@359
   823
    store_reg( R_EAX, Rn );
nkeynes@359
   824
    SETC_t();
nkeynes@359
   825
:}
nkeynes@359
   826
SHAD Rm, Rn {:
nkeynes@359
   827
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   828
    load_reg( R_EAX, Rn );
nkeynes@361
   829
    load_reg( R_ECX, Rm );
nkeynes@361
   830
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   831
    JGE_rel8(16, doshl);
nkeynes@361
   832
                    
nkeynes@361
   833
    NEG_r32( R_ECX );      // 2
nkeynes@361
   834
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   835
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   836
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   837
    JMP_rel8(10, end);          // 2
nkeynes@386
   838
nkeynes@386
   839
    JMP_TARGET(emptysar);
nkeynes@386
   840
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   841
    JMP_rel8(5, end2);
nkeynes@382
   842
nkeynes@380
   843
    JMP_TARGET(doshl);
nkeynes@361
   844
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   845
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   846
    JMP_TARGET(end);
nkeynes@386
   847
    JMP_TARGET(end2);
nkeynes@361
   848
    store_reg( R_EAX, Rn );
nkeynes@359
   849
:}
nkeynes@359
   850
SHLD Rm, Rn {:  
nkeynes@368
   851
    load_reg( R_EAX, Rn );
nkeynes@368
   852
    load_reg( R_ECX, Rm );
nkeynes@382
   853
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   854
    JGE_rel8(15, doshl);
nkeynes@368
   855
nkeynes@382
   856
    NEG_r32( R_ECX );      // 2
nkeynes@382
   857
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   858
    JE_rel8( 4, emptyshr );
nkeynes@382
   859
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   860
    JMP_rel8(9, end);          // 2
nkeynes@386
   861
nkeynes@386
   862
    JMP_TARGET(emptyshr);
nkeynes@386
   863
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   864
    JMP_rel8(5, end2);
nkeynes@382
   865
nkeynes@382
   866
    JMP_TARGET(doshl);
nkeynes@382
   867
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   868
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   869
    JMP_TARGET(end);
nkeynes@386
   870
    JMP_TARGET(end2);
nkeynes@368
   871
    store_reg( R_EAX, Rn );
nkeynes@359
   872
:}
nkeynes@359
   873
SHAL Rn {: 
nkeynes@359
   874
    load_reg( R_EAX, Rn );
nkeynes@359
   875
    SHL1_r32( R_EAX );
nkeynes@397
   876
    SETC_t();
nkeynes@359
   877
    store_reg( R_EAX, Rn );
nkeynes@359
   878
:}
nkeynes@359
   879
SHAR Rn {:  
nkeynes@359
   880
    load_reg( R_EAX, Rn );
nkeynes@359
   881
    SAR1_r32( R_EAX );
nkeynes@397
   882
    SETC_t();
nkeynes@359
   883
    store_reg( R_EAX, Rn );
nkeynes@359
   884
:}
nkeynes@359
   885
SHLL Rn {:  
nkeynes@359
   886
    load_reg( R_EAX, Rn );
nkeynes@359
   887
    SHL1_r32( R_EAX );
nkeynes@397
   888
    SETC_t();
nkeynes@359
   889
    store_reg( R_EAX, Rn );
nkeynes@359
   890
:}
nkeynes@359
   891
SHLL2 Rn {:
nkeynes@359
   892
    load_reg( R_EAX, Rn );
nkeynes@359
   893
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   894
    store_reg( R_EAX, Rn );
nkeynes@359
   895
:}
nkeynes@359
   896
SHLL8 Rn {:  
nkeynes@359
   897
    load_reg( R_EAX, Rn );
nkeynes@359
   898
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   899
    store_reg( R_EAX, Rn );
nkeynes@359
   900
:}
nkeynes@359
   901
SHLL16 Rn {:  
nkeynes@359
   902
    load_reg( R_EAX, Rn );
nkeynes@359
   903
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   904
    store_reg( R_EAX, Rn );
nkeynes@359
   905
:}
nkeynes@359
   906
SHLR Rn {:  
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@359
   908
    SHR1_r32( R_EAX );
nkeynes@397
   909
    SETC_t();
nkeynes@359
   910
    store_reg( R_EAX, Rn );
nkeynes@359
   911
:}
nkeynes@359
   912
SHLR2 Rn {:  
nkeynes@359
   913
    load_reg( R_EAX, Rn );
nkeynes@359
   914
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   915
    store_reg( R_EAX, Rn );
nkeynes@359
   916
:}
nkeynes@359
   917
SHLR8 Rn {:  
nkeynes@359
   918
    load_reg( R_EAX, Rn );
nkeynes@359
   919
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   920
    store_reg( R_EAX, Rn );
nkeynes@359
   921
:}
nkeynes@359
   922
SHLR16 Rn {:  
nkeynes@359
   923
    load_reg( R_EAX, Rn );
nkeynes@359
   924
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   925
    store_reg( R_EAX, Rn );
nkeynes@359
   926
:}
nkeynes@359
   927
SUB Rm, Rn {:  
nkeynes@359
   928
    load_reg( R_EAX, Rm );
nkeynes@359
   929
    load_reg( R_ECX, Rn );
nkeynes@359
   930
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   931
    store_reg( R_ECX, Rn );
nkeynes@359
   932
:}
nkeynes@359
   933
SUBC Rm, Rn {:  
nkeynes@359
   934
    load_reg( R_EAX, Rm );
nkeynes@359
   935
    load_reg( R_ECX, Rn );
nkeynes@359
   936
    LDC_t();
nkeynes@359
   937
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   938
    store_reg( R_ECX, Rn );
nkeynes@394
   939
    SETC_t();
nkeynes@359
   940
:}
nkeynes@359
   941
SUBV Rm, Rn {:  
nkeynes@359
   942
    load_reg( R_EAX, Rm );
nkeynes@359
   943
    load_reg( R_ECX, Rn );
nkeynes@359
   944
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   945
    store_reg( R_ECX, Rn );
nkeynes@359
   946
    SETO_t();
nkeynes@359
   947
:}
nkeynes@359
   948
SWAP.B Rm, Rn {:  
nkeynes@359
   949
    load_reg( R_EAX, Rm );
nkeynes@359
   950
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   951
    store_reg( R_EAX, Rn );
nkeynes@359
   952
:}
nkeynes@359
   953
SWAP.W Rm, Rn {:  
nkeynes@359
   954
    load_reg( R_EAX, Rm );
nkeynes@359
   955
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   956
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   957
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   958
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   959
    store_reg( R_ECX, Rn );
nkeynes@359
   960
:}
nkeynes@361
   961
TAS.B @Rn {:  
nkeynes@361
   962
    load_reg( R_ECX, Rn );
nkeynes@361
   963
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   964
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   965
    SETE_t();
nkeynes@361
   966
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   967
    load_reg( R_ECX, Rn );
nkeynes@361
   968
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   969
:}
nkeynes@361
   970
TST Rm, Rn {:  
nkeynes@361
   971
    load_reg( R_EAX, Rm );
nkeynes@361
   972
    load_reg( R_ECX, Rn );
nkeynes@361
   973
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   974
    SETE_t();
nkeynes@361
   975
:}
nkeynes@368
   976
TST #imm, R0 {:  
nkeynes@368
   977
    load_reg( R_EAX, 0 );
nkeynes@368
   978
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   979
    SETE_t();
nkeynes@368
   980
:}
nkeynes@368
   981
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   982
    load_reg( R_EAX, 0);
nkeynes@368
   983
    load_reg( R_ECX, R_GBR);
nkeynes@368
   984
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   985
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
   986
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   987
    SETE_t();
nkeynes@368
   988
:}
nkeynes@359
   989
XOR Rm, Rn {:  
nkeynes@359
   990
    load_reg( R_EAX, Rm );
nkeynes@359
   991
    load_reg( R_ECX, Rn );
nkeynes@359
   992
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   993
    store_reg( R_ECX, Rn );
nkeynes@359
   994
:}
nkeynes@359
   995
XOR #imm, R0 {:  
nkeynes@359
   996
    load_reg( R_EAX, 0 );
nkeynes@359
   997
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   998
    store_reg( R_EAX, 0 );
nkeynes@359
   999
:}
nkeynes@359
  1000
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1001
    load_reg( R_EAX, 0 );
nkeynes@359
  1002
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1003
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1004
    PUSH_r32(R_ECX);
nkeynes@386
  1005
    call_func0(sh4_read_byte);
nkeynes@386
  1006
    POP_r32(R_ECX);
nkeynes@359
  1007
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1008
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1009
:}
nkeynes@361
  1010
XTRCT Rm, Rn {:
nkeynes@361
  1011
    load_reg( R_EAX, Rm );
nkeynes@394
  1012
    load_reg( R_ECX, Rn );
nkeynes@394
  1013
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1014
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1015
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1016
    store_reg( R_ECX, Rn );
nkeynes@359
  1017
:}
nkeynes@359
  1018
nkeynes@359
  1019
/* Data move instructions */
nkeynes@359
  1020
MOV Rm, Rn {:  
nkeynes@359
  1021
    load_reg( R_EAX, Rm );
nkeynes@359
  1022
    store_reg( R_EAX, Rn );
nkeynes@359
  1023
:}
nkeynes@359
  1024
MOV #imm, Rn {:  
nkeynes@359
  1025
    load_imm32( R_EAX, imm );
nkeynes@359
  1026
    store_reg( R_EAX, Rn );
nkeynes@359
  1027
:}
nkeynes@359
  1028
MOV.B Rm, @Rn {:  
nkeynes@359
  1029
    load_reg( R_EAX, Rm );
nkeynes@359
  1030
    load_reg( R_ECX, Rn );
nkeynes@359
  1031
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1032
:}
nkeynes@359
  1033
MOV.B Rm, @-Rn {:  
nkeynes@359
  1034
    load_reg( R_EAX, Rm );
nkeynes@359
  1035
    load_reg( R_ECX, Rn );
nkeynes@382
  1036
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1037
    store_reg( R_ECX, Rn );
nkeynes@359
  1038
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1039
:}
nkeynes@359
  1040
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1041
    load_reg( R_EAX, 0 );
nkeynes@359
  1042
    load_reg( R_ECX, Rn );
nkeynes@359
  1043
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1044
    load_reg( R_EAX, Rm );
nkeynes@359
  1045
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1046
:}
nkeynes@359
  1047
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1048
    load_reg( R_EAX, 0 );
nkeynes@359
  1049
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1050
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1051
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1052
:}
nkeynes@359
  1053
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1054
    load_reg( R_EAX, 0 );
nkeynes@359
  1055
    load_reg( R_ECX, Rn );
nkeynes@359
  1056
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1057
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1058
:}
nkeynes@359
  1059
MOV.B @Rm, Rn {:  
nkeynes@359
  1060
    load_reg( R_ECX, Rm );
nkeynes@359
  1061
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1062
    store_reg( R_EAX, Rn );
nkeynes@359
  1063
:}
nkeynes@359
  1064
MOV.B @Rm+, Rn {:  
nkeynes@359
  1065
    load_reg( R_ECX, Rm );
nkeynes@359
  1066
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1067
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1068
    store_reg( R_EAX, Rm );
nkeynes@359
  1069
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1070
    store_reg( R_EAX, Rn );
nkeynes@359
  1071
:}
nkeynes@359
  1072
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1073
    load_reg( R_EAX, 0 );
nkeynes@359
  1074
    load_reg( R_ECX, Rm );
nkeynes@359
  1075
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1076
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1077
    store_reg( R_EAX, Rn );
nkeynes@359
  1078
:}
nkeynes@359
  1079
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1080
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1081
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1082
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1083
    store_reg( R_EAX, 0 );
nkeynes@359
  1084
:}
nkeynes@359
  1085
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1086
    load_reg( R_ECX, Rm );
nkeynes@359
  1087
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1088
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1089
    store_reg( R_EAX, 0 );
nkeynes@359
  1090
:}
nkeynes@374
  1091
MOV.L Rm, @Rn {:
nkeynes@361
  1092
    load_reg( R_EAX, Rm );
nkeynes@361
  1093
    load_reg( R_ECX, Rn );
nkeynes@374
  1094
    check_walign32(R_ECX);
nkeynes@361
  1095
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1096
:}
nkeynes@361
  1097
MOV.L Rm, @-Rn {:  
nkeynes@361
  1098
    load_reg( R_EAX, Rm );
nkeynes@361
  1099
    load_reg( R_ECX, Rn );
nkeynes@374
  1100
    check_walign32( R_ECX );
nkeynes@361
  1101
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1102
    store_reg( R_ECX, Rn );
nkeynes@361
  1103
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1104
:}
nkeynes@361
  1105
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1106
    load_reg( R_EAX, 0 );
nkeynes@361
  1107
    load_reg( R_ECX, Rn );
nkeynes@361
  1108
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1109
    check_walign32( R_ECX );
nkeynes@361
  1110
    load_reg( R_EAX, Rm );
nkeynes@361
  1111
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1112
:}
nkeynes@361
  1113
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1114
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1115
    load_reg( R_EAX, 0 );
nkeynes@361
  1116
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1117
    check_walign32( R_ECX );
nkeynes@361
  1118
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1119
:}
nkeynes@361
  1120
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1121
    load_reg( R_ECX, Rn );
nkeynes@361
  1122
    load_reg( R_EAX, Rm );
nkeynes@361
  1123
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1124
    check_walign32( R_ECX );
nkeynes@361
  1125
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1126
:}
nkeynes@361
  1127
MOV.L @Rm, Rn {:  
nkeynes@361
  1128
    load_reg( R_ECX, Rm );
nkeynes@374
  1129
    check_ralign32( R_ECX );
nkeynes@361
  1130
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1131
    store_reg( R_EAX, Rn );
nkeynes@361
  1132
:}
nkeynes@361
  1133
MOV.L @Rm+, Rn {:  
nkeynes@361
  1134
    load_reg( R_EAX, Rm );
nkeynes@382
  1135
    check_ralign32( R_EAX );
nkeynes@361
  1136
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1137
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1138
    store_reg( R_EAX, Rm );
nkeynes@361
  1139
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1140
    store_reg( R_EAX, Rn );
nkeynes@361
  1141
:}
nkeynes@361
  1142
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1143
    load_reg( R_EAX, 0 );
nkeynes@361
  1144
    load_reg( R_ECX, Rm );
nkeynes@361
  1145
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1146
    check_ralign32( R_ECX );
nkeynes@361
  1147
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1148
    store_reg( R_EAX, Rn );
nkeynes@361
  1149
:}
nkeynes@361
  1150
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1151
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1152
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1153
    check_ralign32( R_ECX );
nkeynes@361
  1154
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1155
    store_reg( R_EAX, 0 );
nkeynes@361
  1156
:}
nkeynes@361
  1157
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1158
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1159
	SLOTILLEGAL();
nkeynes@374
  1160
    } else {
nkeynes@388
  1161
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  1162
	char *ptr = mem_get_region(target);
nkeynes@388
  1163
	if( ptr != NULL ) {
nkeynes@388
  1164
	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  1165
	} else {
nkeynes@388
  1166
	    load_imm32( R_ECX, target );
nkeynes@388
  1167
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1168
	}
nkeynes@382
  1169
	store_reg( R_EAX, Rn );
nkeynes@374
  1170
    }
nkeynes@361
  1171
:}
nkeynes@361
  1172
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1173
    load_reg( R_ECX, Rm );
nkeynes@361
  1174
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1175
    check_ralign32( R_ECX );
nkeynes@361
  1176
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1177
    store_reg( R_EAX, Rn );
nkeynes@361
  1178
:}
nkeynes@361
  1179
MOV.W Rm, @Rn {:  
nkeynes@361
  1180
    load_reg( R_ECX, Rn );
nkeynes@374
  1181
    check_walign16( R_ECX );
nkeynes@382
  1182
    load_reg( R_EAX, Rm );
nkeynes@382
  1183
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1184
:}
nkeynes@361
  1185
MOV.W Rm, @-Rn {:  
nkeynes@361
  1186
    load_reg( R_ECX, Rn );
nkeynes@374
  1187
    check_walign16( R_ECX );
nkeynes@361
  1188
    load_reg( R_EAX, Rm );
nkeynes@361
  1189
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1190
    store_reg( R_ECX, Rn );
nkeynes@361
  1191
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1192
:}
nkeynes@361
  1193
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1194
    load_reg( R_EAX, 0 );
nkeynes@361
  1195
    load_reg( R_ECX, Rn );
nkeynes@361
  1196
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1197
    check_walign16( R_ECX );
nkeynes@361
  1198
    load_reg( R_EAX, Rm );
nkeynes@361
  1199
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1200
:}
nkeynes@361
  1201
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1202
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1203
    load_reg( R_EAX, 0 );
nkeynes@361
  1204
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1205
    check_walign16( R_ECX );
nkeynes@361
  1206
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1207
:}
nkeynes@361
  1208
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1209
    load_reg( R_ECX, Rn );
nkeynes@361
  1210
    load_reg( R_EAX, 0 );
nkeynes@361
  1211
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1212
    check_walign16( R_ECX );
nkeynes@361
  1213
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1214
:}
nkeynes@361
  1215
MOV.W @Rm, Rn {:  
nkeynes@361
  1216
    load_reg( R_ECX, Rm );
nkeynes@374
  1217
    check_ralign16( R_ECX );
nkeynes@361
  1218
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1219
    store_reg( R_EAX, Rn );
nkeynes@361
  1220
:}
nkeynes@361
  1221
MOV.W @Rm+, Rn {:  
nkeynes@361
  1222
    load_reg( R_EAX, Rm );
nkeynes@374
  1223
    check_ralign16( R_EAX );
nkeynes@361
  1224
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1225
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1226
    store_reg( R_EAX, Rm );
nkeynes@361
  1227
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1228
    store_reg( R_EAX, Rn );
nkeynes@361
  1229
:}
nkeynes@361
  1230
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1231
    load_reg( R_EAX, 0 );
nkeynes@361
  1232
    load_reg( R_ECX, Rm );
nkeynes@361
  1233
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1234
    check_ralign16( R_ECX );
nkeynes@361
  1235
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1236
    store_reg( R_EAX, Rn );
nkeynes@361
  1237
:}
nkeynes@361
  1238
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1239
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1240
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1241
    check_ralign16( R_ECX );
nkeynes@361
  1242
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1243
    store_reg( R_EAX, 0 );
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1246
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1247
	SLOTILLEGAL();
nkeynes@374
  1248
    } else {
nkeynes@374
  1249
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1250
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1251
	store_reg( R_EAX, Rn );
nkeynes@374
  1252
    }
nkeynes@361
  1253
:}
nkeynes@361
  1254
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1255
    load_reg( R_ECX, Rm );
nkeynes@361
  1256
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1257
    check_ralign16( R_ECX );
nkeynes@361
  1258
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1259
    store_reg( R_EAX, 0 );
nkeynes@361
  1260
:}
nkeynes@361
  1261
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1262
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1263
	SLOTILLEGAL();
nkeynes@374
  1264
    } else {
nkeynes@374
  1265
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1266
	store_reg( R_ECX, 0 );
nkeynes@374
  1267
    }
nkeynes@361
  1268
:}
nkeynes@361
  1269
MOVCA.L R0, @Rn {:  
nkeynes@361
  1270
    load_reg( R_EAX, 0 );
nkeynes@361
  1271
    load_reg( R_ECX, Rn );
nkeynes@374
  1272
    check_walign32( R_ECX );
nkeynes@361
  1273
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1274
:}
nkeynes@359
  1275
nkeynes@359
  1276
/* Control transfer instructions */
nkeynes@374
  1277
BF disp {:
nkeynes@374
  1278
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1279
	SLOTILLEGAL();
nkeynes@374
  1280
    } else {
nkeynes@374
  1281
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1282
	JNE_rel8( 30, nottaken );
nkeynes@408
  1283
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1284
	JMP_TARGET(nottaken);
nkeynes@408
  1285
	exit_block( pc + 2, pc + 2 );
nkeynes@408
  1286
	return 2;
nkeynes@374
  1287
    }
nkeynes@374
  1288
:}
nkeynes@374
  1289
BF/S disp {:
nkeynes@374
  1290
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1291
	SLOTILLEGAL();
nkeynes@374
  1292
    } else {
nkeynes@408
  1293
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1294
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1295
	OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@408
  1296
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1297
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1298
	// not taken
nkeynes@408
  1299
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1300
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1301
	exit_block( pc + 4, pc+4 );
nkeynes@408
  1302
	return 4;
nkeynes@374
  1303
    }
nkeynes@374
  1304
:}
nkeynes@374
  1305
BRA disp {:  
nkeynes@374
  1306
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1307
	SLOTILLEGAL();
nkeynes@374
  1308
    } else {
nkeynes@374
  1309
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1310
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1311
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1312
	return 4;
nkeynes@374
  1313
    }
nkeynes@374
  1314
:}
nkeynes@374
  1315
BRAF Rn {:  
nkeynes@374
  1316
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1317
	SLOTILLEGAL();
nkeynes@374
  1318
    } else {
nkeynes@408
  1319
	load_reg( R_EAX, Rn );
nkeynes@408
  1320
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1321
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1322
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1323
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1324
	exit_block_pcset(pc+2);
nkeynes@408
  1325
	return 4;
nkeynes@374
  1326
    }
nkeynes@374
  1327
:}
nkeynes@374
  1328
BSR disp {:  
nkeynes@374
  1329
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1330
	SLOTILLEGAL();
nkeynes@374
  1331
    } else {
nkeynes@374
  1332
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1333
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1334
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1335
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1336
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1337
	return 4;
nkeynes@374
  1338
    }
nkeynes@374
  1339
:}
nkeynes@374
  1340
BSRF Rn {:  
nkeynes@374
  1341
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1342
	SLOTILLEGAL();
nkeynes@374
  1343
    } else {
nkeynes@408
  1344
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1345
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1346
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1347
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1348
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1349
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1350
	exit_block_pcset(pc+2);
nkeynes@408
  1351
	return 4;
nkeynes@374
  1352
    }
nkeynes@374
  1353
:}
nkeynes@374
  1354
BT disp {:
nkeynes@374
  1355
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1356
	SLOTILLEGAL();
nkeynes@374
  1357
    } else {
nkeynes@374
  1358
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1359
	JE_rel8( 30, nottaken );
nkeynes@408
  1360
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1361
	JMP_TARGET(nottaken);
nkeynes@408
  1362
	exit_block( pc + 2, pc+2 );
nkeynes@408
  1363
	return 2;
nkeynes@374
  1364
    }
nkeynes@374
  1365
:}
nkeynes@374
  1366
BT/S disp {:
nkeynes@374
  1367
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1368
	SLOTILLEGAL();
nkeynes@374
  1369
    } else {
nkeynes@408
  1370
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1371
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@408
  1372
	OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@408
  1373
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1374
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1375
	// not taken
nkeynes@408
  1376
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1377
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1378
	exit_block( pc + 4, pc+4 );
nkeynes@408
  1379
	return 4;
nkeynes@374
  1380
    }
nkeynes@374
  1381
:}
nkeynes@374
  1382
JMP @Rn {:  
nkeynes@374
  1383
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1384
	SLOTILLEGAL();
nkeynes@374
  1385
    } else {
nkeynes@408
  1386
	load_reg( R_ECX, Rn );
nkeynes@408
  1387
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1388
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1389
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1390
	exit_block_pcset(pc+2);
nkeynes@408
  1391
	return 4;
nkeynes@374
  1392
    }
nkeynes@374
  1393
:}
nkeynes@374
  1394
JSR @Rn {:  
nkeynes@374
  1395
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1396
	SLOTILLEGAL();
nkeynes@374
  1397
    } else {
nkeynes@374
  1398
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1399
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1400
	load_reg( R_ECX, Rn );
nkeynes@408
  1401
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1402
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1403
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1404
	exit_block_pcset(pc+2);
nkeynes@408
  1405
	return 4;
nkeynes@374
  1406
    }
nkeynes@374
  1407
:}
nkeynes@374
  1408
RTE {:  
nkeynes@374
  1409
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1410
	SLOTILLEGAL();
nkeynes@374
  1411
    } else {
nkeynes@408
  1412
	check_priv();
nkeynes@408
  1413
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1414
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1415
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1416
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1417
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1418
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1419
	sh4_x86.fpuen_checked = FALSE;
nkeynes@408
  1420
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1421
	exit_block_pcset(pc+2);
nkeynes@408
  1422
	return 4;
nkeynes@374
  1423
    }
nkeynes@374
  1424
:}
nkeynes@374
  1425
RTS {:  
nkeynes@374
  1426
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1427
	SLOTILLEGAL();
nkeynes@374
  1428
    } else {
nkeynes@408
  1429
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1430
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1431
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1432
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1433
	exit_block_pcset(pc+2);
nkeynes@408
  1434
	return 4;
nkeynes@374
  1435
    }
nkeynes@374
  1436
:}
nkeynes@374
  1437
TRAPA #imm {:  
nkeynes@374
  1438
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1439
	SLOTILLEGAL();
nkeynes@374
  1440
    } else {
nkeynes@388
  1441
	PUSH_imm32( imm );
nkeynes@388
  1442
	call_func0( sh4_raise_trap );
nkeynes@388
  1443
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@408
  1444
	exit_block_pcset(pc);
nkeynes@408
  1445
	return 2;
nkeynes@374
  1446
    }
nkeynes@374
  1447
:}
nkeynes@374
  1448
UNDEF {:  
nkeynes@374
  1449
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1450
	SLOTILLEGAL();
nkeynes@374
  1451
    } else {
nkeynes@386
  1452
	JMP_exit(EXIT_ILLEGAL);
nkeynes@408
  1453
	return 2;
nkeynes@374
  1454
    }
nkeynes@368
  1455
:}
nkeynes@374
  1456
nkeynes@374
  1457
CLRMAC {:  
nkeynes@374
  1458
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1459
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1460
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1461
:}
nkeynes@374
  1462
CLRS {:
nkeynes@374
  1463
    CLC();
nkeynes@374
  1464
    SETC_sh4r(R_S);
nkeynes@368
  1465
:}
nkeynes@374
  1466
CLRT {:  
nkeynes@374
  1467
    CLC();
nkeynes@374
  1468
    SETC_t();
nkeynes@359
  1469
:}
nkeynes@374
  1470
SETS {:  
nkeynes@374
  1471
    STC();
nkeynes@374
  1472
    SETC_sh4r(R_S);
nkeynes@359
  1473
:}
nkeynes@374
  1474
SETT {:  
nkeynes@374
  1475
    STC();
nkeynes@374
  1476
    SETC_t();
nkeynes@374
  1477
:}
nkeynes@359
  1478
nkeynes@375
  1479
/* Floating point moves */
nkeynes@375
  1480
FMOV FRm, FRn {:  
nkeynes@375
  1481
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1482
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1483
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1484
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1485
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1486
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1487
     */
nkeynes@377
  1488
    check_fpuen();
nkeynes@375
  1489
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1490
    load_fr_bank( R_EDX );
nkeynes@375
  1491
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1492
    JNE_rel8(8, doublesize);
nkeynes@375
  1493
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1494
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1495
    if( FRm&1 ) {
nkeynes@386
  1496
	JMP_rel8(24, end);
nkeynes@380
  1497
	JMP_TARGET(doublesize);
nkeynes@375
  1498
	load_xf_bank( R_ECX ); 
nkeynes@375
  1499
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1500
	if( FRn&1 ) {
nkeynes@375
  1501
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1502
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1503
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1504
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1505
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1506
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1507
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1508
	}
nkeynes@380
  1509
	JMP_TARGET(end);
nkeynes@375
  1510
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1511
	if( FRn&1 ) {
nkeynes@386
  1512
	    JMP_rel8(24, end);
nkeynes@375
  1513
	    load_xf_bank( R_ECX );
nkeynes@375
  1514
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1515
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1516
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1517
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1518
	    JMP_TARGET(end);
nkeynes@375
  1519
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1520
	    JMP_rel8(12, end);
nkeynes@375
  1521
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1522
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1523
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1524
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1525
	    JMP_TARGET(end);
nkeynes@375
  1526
	}
nkeynes@375
  1527
    }
nkeynes@375
  1528
:}
nkeynes@375
  1529
FMOV FRm, @Rn {:  
nkeynes@377
  1530
    check_fpuen();
nkeynes@375
  1531
    load_reg( R_EDX, Rn );
nkeynes@375
  1532
    check_walign32( R_EDX );
nkeynes@375
  1533
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1534
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1535
    JNE_rel8(20, doublesize);
nkeynes@377
  1536
    load_fr_bank( R_ECX );
nkeynes@375
  1537
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1538
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1539
    if( FRm&1 ) {
nkeynes@386
  1540
	JMP_rel8( 48, end );
nkeynes@380
  1541
	JMP_TARGET(doublesize);
nkeynes@375
  1542
	load_xf_bank( R_ECX );
nkeynes@380
  1543
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1544
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1545
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1546
	JMP_TARGET(end);
nkeynes@375
  1547
    } else {
nkeynes@380
  1548
	JMP_rel8( 39, end );
nkeynes@380
  1549
	JMP_TARGET(doublesize);
nkeynes@377
  1550
	load_fr_bank( R_ECX );
nkeynes@380
  1551
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1552
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1553
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1554
	JMP_TARGET(end);
nkeynes@375
  1555
    }
nkeynes@375
  1556
:}
nkeynes@375
  1557
FMOV @Rm, FRn {:  
nkeynes@377
  1558
    check_fpuen();
nkeynes@375
  1559
    load_reg( R_EDX, Rm );
nkeynes@375
  1560
    check_ralign32( R_EDX );
nkeynes@375
  1561
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1562
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1563
    JNE_rel8(19, doublesize);
nkeynes@375
  1564
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1565
    load_fr_bank( R_ECX );
nkeynes@375
  1566
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1567
    if( FRn&1 ) {
nkeynes@386
  1568
	JMP_rel8(48, end);
nkeynes@380
  1569
	JMP_TARGET(doublesize);
nkeynes@375
  1570
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1571
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1572
	load_xf_bank( R_ECX );
nkeynes@380
  1573
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1574
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1575
	JMP_TARGET(end);
nkeynes@375
  1576
    } else {
nkeynes@380
  1577
	JMP_rel8(36, end);
nkeynes@380
  1578
	JMP_TARGET(doublesize);
nkeynes@375
  1579
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1580
	load_fr_bank( R_ECX );
nkeynes@380
  1581
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1582
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1583
	JMP_TARGET(end);
nkeynes@375
  1584
    }
nkeynes@375
  1585
:}
nkeynes@377
  1586
FMOV FRm, @-Rn {:  
nkeynes@377
  1587
    check_fpuen();
nkeynes@377
  1588
    load_reg( R_EDX, Rn );
nkeynes@377
  1589
    check_walign32( R_EDX );
nkeynes@377
  1590
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1591
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@382
  1592
    JNE_rel8(26, doublesize);
nkeynes@377
  1593
    load_fr_bank( R_ECX );
nkeynes@377
  1594
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1595
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1596
    store_reg( R_EDX, Rn );
nkeynes@377
  1597
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1598
    if( FRm&1 ) {
nkeynes@386
  1599
	JMP_rel8( 54, end );
nkeynes@380
  1600
	JMP_TARGET(doublesize);
nkeynes@377
  1601
	load_xf_bank( R_ECX );
nkeynes@380
  1602
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1603
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1604
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1605
	store_reg( R_EDX, Rn );
nkeynes@380
  1606
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1607
	JMP_TARGET(end);
nkeynes@377
  1608
    } else {
nkeynes@382
  1609
	JMP_rel8( 45, end );
nkeynes@380
  1610
	JMP_TARGET(doublesize);
nkeynes@377
  1611
	load_fr_bank( R_ECX );
nkeynes@380
  1612
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1613
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1614
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1615
	store_reg( R_EDX, Rn );
nkeynes@380
  1616
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1617
	JMP_TARGET(end);
nkeynes@377
  1618
    }
nkeynes@377
  1619
:}
nkeynes@377
  1620
FMOV @Rm+, FRn {:  
nkeynes@377
  1621
    check_fpuen();
nkeynes@377
  1622
    load_reg( R_EDX, Rm );
nkeynes@377
  1623
    check_ralign32( R_EDX );
nkeynes@377
  1624
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1625
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1626
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1627
    JNE_rel8(25, doublesize);
nkeynes@377
  1628
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1629
    store_reg( R_EAX, Rm );
nkeynes@377
  1630
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1631
    load_fr_bank( R_ECX );
nkeynes@377
  1632
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1633
    if( FRn&1 ) {
nkeynes@386
  1634
	JMP_rel8(54, end);
nkeynes@380
  1635
	JMP_TARGET(doublesize);
nkeynes@377
  1636
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1637
	store_reg(R_EAX, Rm);
nkeynes@377
  1638
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1639
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1640
	load_xf_bank( R_ECX );
nkeynes@380
  1641
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1642
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1643
	JMP_TARGET(end);
nkeynes@377
  1644
    } else {
nkeynes@380
  1645
	JMP_rel8(42, end);
nkeynes@377
  1646
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1647
	store_reg(R_EAX, Rm);
nkeynes@377
  1648
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1649
	load_fr_bank( R_ECX );
nkeynes@380
  1650
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1651
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1652
	JMP_TARGET(end);
nkeynes@377
  1653
    }
nkeynes@377
  1654
:}
nkeynes@377
  1655
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1656
    check_fpuen();
nkeynes@377
  1657
    load_reg( R_EDX, Rn );
nkeynes@377
  1658
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1659
    check_walign32( R_EDX );
nkeynes@377
  1660
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1661
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1662
    JNE_rel8(20, doublesize);
nkeynes@377
  1663
    load_fr_bank( R_ECX );
nkeynes@377
  1664
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1665
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1666
    if( FRm&1 ) {
nkeynes@386
  1667
	JMP_rel8( 48, end );
nkeynes@380
  1668
	JMP_TARGET(doublesize);
nkeynes@377
  1669
	load_xf_bank( R_ECX );
nkeynes@380
  1670
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1671
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1672
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1673
	JMP_TARGET(end);
nkeynes@377
  1674
    } else {
nkeynes@380
  1675
	JMP_rel8( 39, end );
nkeynes@380
  1676
	JMP_TARGET(doublesize);
nkeynes@377
  1677
	load_fr_bank( R_ECX );
nkeynes@380
  1678
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1679
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1680
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1681
	JMP_TARGET(end);
nkeynes@377
  1682
    }
nkeynes@377
  1683
:}
nkeynes@377
  1684
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1685
    check_fpuen();
nkeynes@377
  1686
    load_reg( R_EDX, Rm );
nkeynes@377
  1687
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1688
    check_ralign32( R_EDX );
nkeynes@377
  1689
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1690
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1691
    JNE_rel8(19, doublesize);
nkeynes@377
  1692
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1693
    load_fr_bank( R_ECX );
nkeynes@377
  1694
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1695
    if( FRn&1 ) {
nkeynes@386
  1696
	JMP_rel8(48, end);
nkeynes@380
  1697
	JMP_TARGET(doublesize);
nkeynes@377
  1698
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1699
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1700
	load_xf_bank( R_ECX );
nkeynes@380
  1701
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1702
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1703
	JMP_TARGET(end);
nkeynes@377
  1704
    } else {
nkeynes@380
  1705
	JMP_rel8(36, end);
nkeynes@380
  1706
	JMP_TARGET(doublesize);
nkeynes@377
  1707
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1708
	load_fr_bank( R_ECX );
nkeynes@380
  1709
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1710
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1711
	JMP_TARGET(end);
nkeynes@377
  1712
    }
nkeynes@377
  1713
:}
nkeynes@377
  1714
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1715
    check_fpuen();
nkeynes@377
  1716
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1717
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1718
    JNE_rel8(8, end);
nkeynes@377
  1719
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1720
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1721
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1722
    JMP_TARGET(end);
nkeynes@377
  1723
:}
nkeynes@377
  1724
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1725
    check_fpuen();
nkeynes@377
  1726
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1727
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1728
    JNE_rel8(11, end);
nkeynes@377
  1729
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1730
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1731
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1732
    JMP_TARGET(end);
nkeynes@377
  1733
:}
nkeynes@377
  1734
nkeynes@377
  1735
FLOAT FPUL, FRn {:  
nkeynes@377
  1736
    check_fpuen();
nkeynes@377
  1737
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1738
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1739
    FILD_sh4r(R_FPUL);
nkeynes@377
  1740
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1741
    JNE_rel8(5, doubleprec);
nkeynes@377
  1742
    pop_fr( R_EDX, FRn );
nkeynes@380
  1743
    JMP_rel8(3, end);
nkeynes@380
  1744
    JMP_TARGET(doubleprec);
nkeynes@377
  1745
    pop_dr( R_EDX, FRn );
nkeynes@380
  1746
    JMP_TARGET(end);
nkeynes@377
  1747
:}
nkeynes@377
  1748
FTRC FRm, FPUL {:  
nkeynes@377
  1749
    check_fpuen();
nkeynes@388
  1750
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1751
    load_fr_bank( R_EDX );
nkeynes@388
  1752
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1753
    JNE_rel8(5, doubleprec);
nkeynes@388
  1754
    push_fr( R_EDX, FRm );
nkeynes@388
  1755
    JMP_rel8(3, doop);
nkeynes@388
  1756
    JMP_TARGET(doubleprec);
nkeynes@388
  1757
    push_dr( R_EDX, FRm );
nkeynes@388
  1758
    JMP_TARGET( doop );
nkeynes@388
  1759
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1760
    FILD_r32ind( R_ECX );
nkeynes@388
  1761
    FCOMIP_st(1);
nkeynes@394
  1762
    JNA_rel8( 32, sat );
nkeynes@388
  1763
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1764
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1765
    FCOMIP_st(1);                   // 2
nkeynes@394
  1766
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1767
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1768
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1769
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1770
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1771
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1772
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1773
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1774
nkeynes@388
  1775
    JMP_TARGET(sat);
nkeynes@388
  1776
    JMP_TARGET(sat2);
nkeynes@388
  1777
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1778
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1779
    FPOP_st();
nkeynes@388
  1780
    JMP_TARGET(end);
nkeynes@377
  1781
:}
nkeynes@377
  1782
FLDS FRm, FPUL {:  
nkeynes@377
  1783
    check_fpuen();
nkeynes@377
  1784
    load_fr_bank( R_ECX );
nkeynes@377
  1785
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1786
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1787
:}
nkeynes@377
  1788
FSTS FPUL, FRn {:  
nkeynes@377
  1789
    check_fpuen();
nkeynes@377
  1790
    load_fr_bank( R_ECX );
nkeynes@377
  1791
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1792
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1793
:}
nkeynes@377
  1794
FCNVDS FRm, FPUL {:  
nkeynes@377
  1795
    check_fpuen();
nkeynes@377
  1796
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1797
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1798
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1799
    load_fr_bank( R_ECX );
nkeynes@377
  1800
    push_dr( R_ECX, FRm );
nkeynes@377
  1801
    pop_fpul();
nkeynes@380
  1802
    JMP_TARGET(end);
nkeynes@377
  1803
:}
nkeynes@377
  1804
FCNVSD FPUL, FRn {:  
nkeynes@377
  1805
    check_fpuen();
nkeynes@377
  1806
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1807
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1808
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1809
    load_fr_bank( R_ECX );
nkeynes@377
  1810
    push_fpul();
nkeynes@377
  1811
    pop_dr( R_ECX, FRn );
nkeynes@380
  1812
    JMP_TARGET(end);
nkeynes@377
  1813
:}
nkeynes@375
  1814
nkeynes@359
  1815
/* Floating point instructions */
nkeynes@374
  1816
FABS FRn {:  
nkeynes@377
  1817
    check_fpuen();
nkeynes@374
  1818
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1819
    load_fr_bank( R_EDX );
nkeynes@374
  1820
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1821
    JNE_rel8(10, doubleprec);
nkeynes@374
  1822
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1823
    FABS_st0(); // 2
nkeynes@374
  1824
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1825
    JMP_rel8(8,end); // 2
nkeynes@380
  1826
    JMP_TARGET(doubleprec);
nkeynes@374
  1827
    push_dr(R_EDX, FRn);
nkeynes@374
  1828
    FABS_st0();
nkeynes@374
  1829
    pop_dr(R_EDX, FRn);
nkeynes@380
  1830
    JMP_TARGET(end);
nkeynes@374
  1831
:}
nkeynes@377
  1832
FADD FRm, FRn {:  
nkeynes@377
  1833
    check_fpuen();
nkeynes@375
  1834
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1835
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1836
    load_fr_bank( R_EDX );
nkeynes@380
  1837
    JNE_rel8(13,doubleprec);
nkeynes@377
  1838
    push_fr(R_EDX, FRm);
nkeynes@377
  1839
    push_fr(R_EDX, FRn);
nkeynes@377
  1840
    FADDP_st(1);
nkeynes@377
  1841
    pop_fr(R_EDX, FRn);
nkeynes@380
  1842
    JMP_rel8(11,end);
nkeynes@380
  1843
    JMP_TARGET(doubleprec);
nkeynes@377
  1844
    push_dr(R_EDX, FRm);
nkeynes@377
  1845
    push_dr(R_EDX, FRn);
nkeynes@377
  1846
    FADDP_st(1);
nkeynes@377
  1847
    pop_dr(R_EDX, FRn);
nkeynes@380
  1848
    JMP_TARGET(end);
nkeynes@375
  1849
:}
nkeynes@377
  1850
FDIV FRm, FRn {:  
nkeynes@377
  1851
    check_fpuen();
nkeynes@375
  1852
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1853
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1854
    load_fr_bank( R_EDX );
nkeynes@380
  1855
    JNE_rel8(13, doubleprec);
nkeynes@377
  1856
    push_fr(R_EDX, FRn);
nkeynes@377
  1857
    push_fr(R_EDX, FRm);
nkeynes@377
  1858
    FDIVP_st(1);
nkeynes@377
  1859
    pop_fr(R_EDX, FRn);
nkeynes@380
  1860
    JMP_rel8(11, end);
nkeynes@380
  1861
    JMP_TARGET(doubleprec);
nkeynes@377
  1862
    push_dr(R_EDX, FRn);
nkeynes@377
  1863
    push_dr(R_EDX, FRm);
nkeynes@377
  1864
    FDIVP_st(1);
nkeynes@377
  1865
    pop_dr(R_EDX, FRn);
nkeynes@380
  1866
    JMP_TARGET(end);
nkeynes@375
  1867
:}
nkeynes@375
  1868
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1869
    check_fpuen();
nkeynes@375
  1870
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1871
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1872
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1873
    JNE_rel8(18, doubleprec);
nkeynes@375
  1874
    push_fr( R_EDX, 0 );
nkeynes@375
  1875
    push_fr( R_EDX, FRm );
nkeynes@375
  1876
    FMULP_st(1);
nkeynes@375
  1877
    push_fr( R_EDX, FRn );
nkeynes@375
  1878
    FADDP_st(1);
nkeynes@375
  1879
    pop_fr( R_EDX, FRn );
nkeynes@380
  1880
    JMP_rel8(16, end);
nkeynes@380
  1881
    JMP_TARGET(doubleprec);
nkeynes@375
  1882
    push_dr( R_EDX, 0 );
nkeynes@375
  1883
    push_dr( R_EDX, FRm );
nkeynes@375
  1884
    FMULP_st(1);
nkeynes@375
  1885
    push_dr( R_EDX, FRn );
nkeynes@375
  1886
    FADDP_st(1);
nkeynes@375
  1887
    pop_dr( R_EDX, FRn );
nkeynes@380
  1888
    JMP_TARGET(end);
nkeynes@375
  1889
:}
nkeynes@375
  1890
nkeynes@377
  1891
FMUL FRm, FRn {:  
nkeynes@377
  1892
    check_fpuen();
nkeynes@377
  1893
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1894
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1895
    load_fr_bank( R_EDX );
nkeynes@380
  1896
    JNE_rel8(13, doubleprec);
nkeynes@377
  1897
    push_fr(R_EDX, FRm);
nkeynes@377
  1898
    push_fr(R_EDX, FRn);
nkeynes@377
  1899
    FMULP_st(1);
nkeynes@377
  1900
    pop_fr(R_EDX, FRn);
nkeynes@380
  1901
    JMP_rel8(11, end);
nkeynes@380
  1902
    JMP_TARGET(doubleprec);
nkeynes@377
  1903
    push_dr(R_EDX, FRm);
nkeynes@377
  1904
    push_dr(R_EDX, FRn);
nkeynes@377
  1905
    FMULP_st(1);
nkeynes@377
  1906
    pop_dr(R_EDX, FRn);
nkeynes@380
  1907
    JMP_TARGET(end);
nkeynes@377
  1908
:}
nkeynes@377
  1909
FNEG FRn {:  
nkeynes@377
  1910
    check_fpuen();
nkeynes@377
  1911
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1912
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1913
    load_fr_bank( R_EDX );
nkeynes@380
  1914
    JNE_rel8(10, doubleprec);
nkeynes@377
  1915
    push_fr(R_EDX, FRn);
nkeynes@377
  1916
    FCHS_st0();
nkeynes@377
  1917
    pop_fr(R_EDX, FRn);
nkeynes@380
  1918
    JMP_rel8(8, end);
nkeynes@380
  1919
    JMP_TARGET(doubleprec);
nkeynes@377
  1920
    push_dr(R_EDX, FRn);
nkeynes@377
  1921
    FCHS_st0();
nkeynes@377
  1922
    pop_dr(R_EDX, FRn);
nkeynes@380
  1923
    JMP_TARGET(end);
nkeynes@377
  1924
:}
nkeynes@377
  1925
FSRRA FRn {:  
nkeynes@377
  1926
    check_fpuen();
nkeynes@377
  1927
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1928
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1929
    load_fr_bank( R_EDX );
nkeynes@380
  1930
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1931
    FLD1_st0();
nkeynes@377
  1932
    push_fr(R_EDX, FRn);
nkeynes@377
  1933
    FSQRT_st0();
nkeynes@377
  1934
    FDIVP_st(1);
nkeynes@377
  1935
    pop_fr(R_EDX, FRn);
nkeynes@380
  1936
    JMP_TARGET(end);
nkeynes@377
  1937
:}
nkeynes@377
  1938
FSQRT FRn {:  
nkeynes@377
  1939
    check_fpuen();
nkeynes@377
  1940
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1941
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1942
    load_fr_bank( R_EDX );
nkeynes@380
  1943
    JNE_rel8(10, doubleprec);
nkeynes@377
  1944
    push_fr(R_EDX, FRn);
nkeynes@377
  1945
    FSQRT_st0();
nkeynes@377
  1946
    pop_fr(R_EDX, FRn);
nkeynes@380
  1947
    JMP_rel8(8, end);
nkeynes@380
  1948
    JMP_TARGET(doubleprec);
nkeynes@377
  1949
    push_dr(R_EDX, FRn);
nkeynes@377
  1950
    FSQRT_st0();
nkeynes@377
  1951
    pop_dr(R_EDX, FRn);
nkeynes@380
  1952
    JMP_TARGET(end);
nkeynes@377
  1953
:}
nkeynes@377
  1954
FSUB FRm, FRn {:  
nkeynes@377
  1955
    check_fpuen();
nkeynes@377
  1956
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1957
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1958
    load_fr_bank( R_EDX );
nkeynes@380
  1959
    JNE_rel8(13, doubleprec);
nkeynes@377
  1960
    push_fr(R_EDX, FRn);
nkeynes@377
  1961
    push_fr(R_EDX, FRm);
nkeynes@388
  1962
    FSUBP_st(1);
nkeynes@377
  1963
    pop_fr(R_EDX, FRn);
nkeynes@380
  1964
    JMP_rel8(11, end);
nkeynes@380
  1965
    JMP_TARGET(doubleprec);
nkeynes@377
  1966
    push_dr(R_EDX, FRn);
nkeynes@377
  1967
    push_dr(R_EDX, FRm);
nkeynes@388
  1968
    FSUBP_st(1);
nkeynes@377
  1969
    pop_dr(R_EDX, FRn);
nkeynes@380
  1970
    JMP_TARGET(end);
nkeynes@377
  1971
:}
nkeynes@377
  1972
nkeynes@377
  1973
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1974
    check_fpuen();
nkeynes@377
  1975
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1976
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1977
    load_fr_bank( R_EDX );
nkeynes@380
  1978
    JNE_rel8(8, doubleprec);
nkeynes@377
  1979
    push_fr(R_EDX, FRm);
nkeynes@377
  1980
    push_fr(R_EDX, FRn);
nkeynes@380
  1981
    JMP_rel8(6, end);
nkeynes@380
  1982
    JMP_TARGET(doubleprec);
nkeynes@377
  1983
    push_dr(R_EDX, FRm);
nkeynes@377
  1984
    push_dr(R_EDX, FRn);
nkeynes@382
  1985
    JMP_TARGET(end);
nkeynes@377
  1986
    FCOMIP_st(1);
nkeynes@377
  1987
    SETE_t();
nkeynes@377
  1988
    FPOP_st();
nkeynes@377
  1989
:}
nkeynes@377
  1990
FCMP/GT FRm, FRn {:  
nkeynes@377
  1991
    check_fpuen();
nkeynes@377
  1992
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1993
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1994
    load_fr_bank( R_EDX );
nkeynes@380
  1995
    JNE_rel8(8, doubleprec);
nkeynes@377
  1996
    push_fr(R_EDX, FRm);
nkeynes@377
  1997
    push_fr(R_EDX, FRn);
nkeynes@380
  1998
    JMP_rel8(6, end);
nkeynes@380
  1999
    JMP_TARGET(doubleprec);
nkeynes@377
  2000
    push_dr(R_EDX, FRm);
nkeynes@377
  2001
    push_dr(R_EDX, FRn);
nkeynes@380
  2002
    JMP_TARGET(end);
nkeynes@377
  2003
    FCOMIP_st(1);
nkeynes@377
  2004
    SETA_t();
nkeynes@377
  2005
    FPOP_st();
nkeynes@377
  2006
:}
nkeynes@377
  2007
nkeynes@377
  2008
FSCA FPUL, FRn {:  
nkeynes@377
  2009
    check_fpuen();
nkeynes@388
  2010
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2011
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2012
    JNE_rel8( 21, doubleprec );
nkeynes@388
  2013
    load_fr_bank( R_ECX );
nkeynes@388
  2014
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2015
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2016
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2017
    JMP_TARGET(doubleprec);
nkeynes@377
  2018
:}
nkeynes@377
  2019
FIPR FVm, FVn {:  
nkeynes@377
  2020
    check_fpuen();
nkeynes@388
  2021
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2022
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2023
    JNE_rel8(44, doubleprec);
nkeynes@388
  2024
    
nkeynes@388
  2025
    load_fr_bank( R_ECX );
nkeynes@388
  2026
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2027
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2028
    FMULP_st(1);
nkeynes@388
  2029
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2030
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2031
    FMULP_st(1);
nkeynes@388
  2032
    FADDP_st(1);
nkeynes@388
  2033
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2034
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2035
    FMULP_st(1);
nkeynes@388
  2036
    FADDP_st(1);
nkeynes@388
  2037
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2038
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2039
    FMULP_st(1);
nkeynes@388
  2040
    FADDP_st(1);
nkeynes@388
  2041
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2042
    JMP_TARGET(doubleprec);
nkeynes@377
  2043
:}
nkeynes@377
  2044
FTRV XMTRX, FVn {:  
nkeynes@377
  2045
    check_fpuen();
nkeynes@388
  2046
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2047
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2048
    JNE_rel8( 30, doubleprec );
nkeynes@388
  2049
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2050
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2051
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2052
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2053
    JMP_TARGET(doubleprec);
nkeynes@377
  2054
:}
nkeynes@377
  2055
nkeynes@377
  2056
FRCHG {:  
nkeynes@377
  2057
    check_fpuen();
nkeynes@377
  2058
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2059
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2060
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2061
    update_fr_bank( R_ECX );
nkeynes@377
  2062
:}
nkeynes@377
  2063
FSCHG {:  
nkeynes@377
  2064
    check_fpuen();
nkeynes@377
  2065
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2066
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2067
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2068
:}
nkeynes@359
  2069
nkeynes@359
  2070
/* Processor control instructions */
nkeynes@368
  2071
LDC Rm, SR {:
nkeynes@386
  2072
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2073
	SLOTILLEGAL();
nkeynes@386
  2074
    } else {
nkeynes@386
  2075
	check_priv();
nkeynes@386
  2076
	load_reg( R_EAX, Rm );
nkeynes@386
  2077
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2078
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2079
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2080
    }
nkeynes@368
  2081
:}
nkeynes@359
  2082
LDC Rm, GBR {: 
nkeynes@359
  2083
    load_reg( R_EAX, Rm );
nkeynes@359
  2084
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2085
:}
nkeynes@359
  2086
LDC Rm, VBR {:  
nkeynes@386
  2087
    check_priv();
nkeynes@359
  2088
    load_reg( R_EAX, Rm );
nkeynes@359
  2089
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2090
:}
nkeynes@359
  2091
LDC Rm, SSR {:  
nkeynes@386
  2092
    check_priv();
nkeynes@359
  2093
    load_reg( R_EAX, Rm );
nkeynes@359
  2094
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2095
:}
nkeynes@359
  2096
LDC Rm, SGR {:  
nkeynes@386
  2097
    check_priv();
nkeynes@359
  2098
    load_reg( R_EAX, Rm );
nkeynes@359
  2099
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2100
:}
nkeynes@359
  2101
LDC Rm, SPC {:  
nkeynes@386
  2102
    check_priv();
nkeynes@359
  2103
    load_reg( R_EAX, Rm );
nkeynes@359
  2104
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2105
:}
nkeynes@359
  2106
LDC Rm, DBR {:  
nkeynes@386
  2107
    check_priv();
nkeynes@359
  2108
    load_reg( R_EAX, Rm );
nkeynes@359
  2109
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2110
:}
nkeynes@374
  2111
LDC Rm, Rn_BANK {:  
nkeynes@386
  2112
    check_priv();
nkeynes@374
  2113
    load_reg( R_EAX, Rm );
nkeynes@374
  2114
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  2115
:}
nkeynes@359
  2116
LDC.L @Rm+, GBR {:  
nkeynes@359
  2117
    load_reg( R_EAX, Rm );
nkeynes@395
  2118
    check_ralign32( R_EAX );
nkeynes@359
  2119
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2120
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2121
    store_reg( R_EAX, Rm );
nkeynes@359
  2122
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2123
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2124
:}
nkeynes@368
  2125
LDC.L @Rm+, SR {:
nkeynes@386
  2126
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2127
	SLOTILLEGAL();
nkeynes@386
  2128
    } else {
nkeynes@386
  2129
	check_priv();
nkeynes@386
  2130
	load_reg( R_EAX, Rm );
nkeynes@395
  2131
	check_ralign32( R_EAX );
nkeynes@386
  2132
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2133
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2134
	store_reg( R_EAX, Rm );
nkeynes@386
  2135
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2136
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2137
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2138
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2139
    }
nkeynes@359
  2140
:}
nkeynes@359
  2141
LDC.L @Rm+, VBR {:  
nkeynes@386
  2142
    check_priv();
nkeynes@359
  2143
    load_reg( R_EAX, Rm );
nkeynes@395
  2144
    check_ralign32( R_EAX );
nkeynes@359
  2145
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2146
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2147
    store_reg( R_EAX, Rm );
nkeynes@359
  2148
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2149
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2150
:}
nkeynes@359
  2151
LDC.L @Rm+, SSR {:
nkeynes@386
  2152
    check_priv();
nkeynes@359
  2153
    load_reg( R_EAX, Rm );
nkeynes@359
  2154
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2155
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2156
    store_reg( R_EAX, Rm );
nkeynes@359
  2157
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2158
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2159
:}
nkeynes@359
  2160
LDC.L @Rm+, SGR {:  
nkeynes@386
  2161
    check_priv();
nkeynes@359
  2162
    load_reg( R_EAX, Rm );
nkeynes@395
  2163
    check_ralign32( R_EAX );
nkeynes@359
  2164
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2165
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2166
    store_reg( R_EAX, Rm );
nkeynes@359
  2167
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2168
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2169
:}
nkeynes@359
  2170
LDC.L @Rm+, SPC {:  
nkeynes@386
  2171
    check_priv();
nkeynes@359
  2172
    load_reg( R_EAX, Rm );
nkeynes@395
  2173
    check_ralign32( R_EAX );
nkeynes@359
  2174
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2175
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2176
    store_reg( R_EAX, Rm );
nkeynes@359
  2177
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2178
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2179
:}
nkeynes@359
  2180
LDC.L @Rm+, DBR {:  
nkeynes@386
  2181
    check_priv();
nkeynes@359
  2182
    load_reg( R_EAX, Rm );
nkeynes@395
  2183
    check_ralign32( R_EAX );
nkeynes@359
  2184
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2185
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2186
    store_reg( R_EAX, Rm );
nkeynes@359
  2187
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2188
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2189
:}
nkeynes@359
  2190
LDC.L @Rm+, Rn_BANK {:  
nkeynes@386
  2191
    check_priv();
nkeynes@374
  2192
    load_reg( R_EAX, Rm );
nkeynes@395
  2193
    check_ralign32( R_EAX );
nkeynes@374
  2194
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2195
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2196
    store_reg( R_EAX, Rm );
nkeynes@374
  2197
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2198
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  2199
:}
nkeynes@359
  2200
LDS Rm, FPSCR {:  
nkeynes@359
  2201
    load_reg( R_EAX, Rm );
nkeynes@359
  2202
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2203
    update_fr_bank( R_EAX );
nkeynes@359
  2204
:}
nkeynes@359
  2205
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2206
    load_reg( R_EAX, Rm );
nkeynes@395
  2207
    check_ralign32( R_EAX );
nkeynes@359
  2208
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2209
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2210
    store_reg( R_EAX, Rm );
nkeynes@359
  2211
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2212
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2213
    update_fr_bank( R_EAX );
nkeynes@359
  2214
:}
nkeynes@359
  2215
LDS Rm, FPUL {:  
nkeynes@359
  2216
    load_reg( R_EAX, Rm );
nkeynes@359
  2217
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2218
:}
nkeynes@359
  2219
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2220
    load_reg( R_EAX, Rm );
nkeynes@395
  2221
    check_ralign32( R_EAX );
nkeynes@359
  2222
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2223
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2224
    store_reg( R_EAX, Rm );
nkeynes@359
  2225
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2226
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2227
:}
nkeynes@359
  2228
LDS Rm, MACH {: 
nkeynes@359
  2229
    load_reg( R_EAX, Rm );
nkeynes@359
  2230
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2231
:}
nkeynes@359
  2232
LDS.L @Rm+, MACH {:  
nkeynes@359
  2233
    load_reg( R_EAX, Rm );
nkeynes@395
  2234
    check_ralign32( R_EAX );
nkeynes@359
  2235
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2236
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2237
    store_reg( R_EAX, Rm );
nkeynes@359
  2238
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2239
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2240
:}
nkeynes@359
  2241
LDS Rm, MACL {:  
nkeynes@359
  2242
    load_reg( R_EAX, Rm );
nkeynes@359
  2243
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2244
:}
nkeynes@359
  2245
LDS.L @Rm+, MACL {:  
nkeynes@359
  2246
    load_reg( R_EAX, Rm );
nkeynes@395
  2247
    check_ralign32( R_EAX );
nkeynes@359
  2248
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2249
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2250
    store_reg( R_EAX, Rm );
nkeynes@359
  2251
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2252
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2253
:}
nkeynes@359
  2254
LDS Rm, PR {:  
nkeynes@359
  2255
    load_reg( R_EAX, Rm );
nkeynes@359
  2256
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2257
:}
nkeynes@359
  2258
LDS.L @Rm+, PR {:  
nkeynes@359
  2259
    load_reg( R_EAX, Rm );
nkeynes@395
  2260
    check_ralign32( R_EAX );
nkeynes@359
  2261
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2262
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2263
    store_reg( R_EAX, Rm );
nkeynes@359
  2264
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2265
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2266
:}
nkeynes@359
  2267
LDTLB {:  :}
nkeynes@359
  2268
OCBI @Rn {:  :}
nkeynes@359
  2269
OCBP @Rn {:  :}
nkeynes@359
  2270
OCBWB @Rn {:  :}
nkeynes@374
  2271
PREF @Rn {:
nkeynes@374
  2272
    load_reg( R_EAX, Rn );
nkeynes@374
  2273
    PUSH_r32( R_EAX );
nkeynes@374
  2274
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2275
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2276
    JNE_rel8(7, end);
nkeynes@374
  2277
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2278
    JMP_TARGET(end);
nkeynes@377
  2279
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2280
:}
nkeynes@388
  2281
SLEEP {: 
nkeynes@388
  2282
    check_priv();
nkeynes@388
  2283
    call_func0( sh4_sleep );
nkeynes@388
  2284
    sh4_x86.in_delay_slot = FALSE;
nkeynes@394
  2285
    INC_r32(R_ESI);
nkeynes@408
  2286
    exit_block(pc+2, pc+2);
nkeynes@408
  2287
    return 2;
nkeynes@388
  2288
:}
nkeynes@386
  2289
STC SR, Rn {:
nkeynes@386
  2290
    check_priv();
nkeynes@386
  2291
    call_func0(sh4_read_sr);
nkeynes@386
  2292
    store_reg( R_EAX, Rn );
nkeynes@359
  2293
:}
nkeynes@359
  2294
STC GBR, Rn {:  
nkeynes@359
  2295
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2296
    store_reg( R_EAX, Rn );
nkeynes@359
  2297
:}
nkeynes@359
  2298
STC VBR, Rn {:  
nkeynes@386
  2299
    check_priv();
nkeynes@359
  2300
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2301
    store_reg( R_EAX, Rn );
nkeynes@359
  2302
:}
nkeynes@359
  2303
STC SSR, Rn {:  
nkeynes@386
  2304
    check_priv();
nkeynes@359
  2305
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2306
    store_reg( R_EAX, Rn );
nkeynes@359
  2307
:}
nkeynes@359
  2308
STC SPC, Rn {:  
nkeynes@386
  2309
    check_priv();
nkeynes@359
  2310
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2311
    store_reg( R_EAX, Rn );
nkeynes@359
  2312
:}
nkeynes@359
  2313
STC SGR, Rn {:  
nkeynes@386
  2314
    check_priv();
nkeynes@359
  2315
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2316
    store_reg( R_EAX, Rn );
nkeynes@359
  2317
:}
nkeynes@359
  2318
STC DBR, Rn {:  
nkeynes@386
  2319
    check_priv();
nkeynes@359
  2320
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2321
    store_reg( R_EAX, Rn );
nkeynes@359
  2322
:}
nkeynes@374
  2323
STC Rm_BANK, Rn {:
nkeynes@386
  2324
    check_priv();
nkeynes@374
  2325
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2326
    store_reg( R_EAX, Rn );
nkeynes@359
  2327
:}
nkeynes@374
  2328
STC.L SR, @-Rn {:
nkeynes@386
  2329
    check_priv();
nkeynes@395
  2330
    call_func0( sh4_read_sr );
nkeynes@368
  2331
    load_reg( R_ECX, Rn );
nkeynes@395
  2332
    check_walign32( R_ECX );
nkeynes@382
  2333
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2334
    store_reg( R_ECX, Rn );
nkeynes@368
  2335
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2336
:}
nkeynes@359
  2337
STC.L VBR, @-Rn {:  
nkeynes@386
  2338
    check_priv();
nkeynes@359
  2339
    load_reg( R_ECX, Rn );
nkeynes@395
  2340
    check_walign32( R_ECX );
nkeynes@382
  2341
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2342
    store_reg( R_ECX, Rn );
nkeynes@359
  2343
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2344
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2345
:}
nkeynes@359
  2346
STC.L SSR, @-Rn {:  
nkeynes@386
  2347
    check_priv();
nkeynes@359
  2348
    load_reg( R_ECX, Rn );
nkeynes@395
  2349
    check_walign32( R_ECX );
nkeynes@382
  2350
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2351
    store_reg( R_ECX, Rn );
nkeynes@359
  2352
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2353
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2354
:}
nkeynes@359
  2355
STC.L SPC, @-Rn {:  
nkeynes@386
  2356
    check_priv();
nkeynes@359
  2357
    load_reg( R_ECX, Rn );
nkeynes@395
  2358
    check_walign32( R_ECX );
nkeynes@382
  2359
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2360
    store_reg( R_ECX, Rn );
nkeynes@359
  2361
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2362
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2363
:}
nkeynes@359
  2364
STC.L SGR, @-Rn {:  
nkeynes@386
  2365
    check_priv();
nkeynes@359
  2366
    load_reg( R_ECX, Rn );
nkeynes@395
  2367
    check_walign32( R_ECX );
nkeynes@382
  2368
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2369
    store_reg( R_ECX, Rn );
nkeynes@359
  2370
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2371
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2372
:}
nkeynes@359
  2373
STC.L DBR, @-Rn {:  
nkeynes@386
  2374
    check_priv();
nkeynes@359
  2375
    load_reg( R_ECX, Rn );
nkeynes@395
  2376
    check_walign32( R_ECX );
nkeynes@382
  2377
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2378
    store_reg( R_ECX, Rn );
nkeynes@359
  2379
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2380
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2381
:}
nkeynes@374
  2382
STC.L Rm_BANK, @-Rn {:  
nkeynes@386
  2383
    check_priv();
nkeynes@374
  2384
    load_reg( R_ECX, Rn );
nkeynes@395
  2385
    check_walign32( R_ECX );
nkeynes@382
  2386
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2387
    store_reg( R_ECX, Rn );
nkeynes@374
  2388
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2389
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2390
:}
nkeynes@359
  2391
STC.L GBR, @-Rn {:  
nkeynes@359
  2392
    load_reg( R_ECX, Rn );
nkeynes@395
  2393
    check_walign32( R_ECX );
nkeynes@382
  2394
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2395
    store_reg( R_ECX, Rn );
nkeynes@359
  2396
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2397
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2398
:}
nkeynes@359
  2399
STS FPSCR, Rn {:  
nkeynes@359
  2400
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2401
    store_reg( R_EAX, Rn );
nkeynes@359
  2402
:}
nkeynes@359
  2403
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2404
    load_reg( R_ECX, Rn );
nkeynes@395
  2405
    check_walign32( R_ECX );
nkeynes@382
  2406
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2407
    store_reg( R_ECX, Rn );
nkeynes@359
  2408
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2409
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2410
:}
nkeynes@359
  2411
STS FPUL, Rn {:  
nkeynes@359
  2412
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2413
    store_reg( R_EAX, Rn );
nkeynes@359
  2414
:}
nkeynes@359
  2415
STS.L FPUL, @-Rn {:  
nkeynes@359
  2416
    load_reg( R_ECX, Rn );
nkeynes@395
  2417
    check_walign32( R_ECX );
nkeynes@382
  2418
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2419
    store_reg( R_ECX, Rn );
nkeynes@359
  2420
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2421
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2422
:}
nkeynes@359
  2423
STS MACH, Rn {:  
nkeynes@359
  2424
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2425
    store_reg( R_EAX, Rn );
nkeynes@359
  2426
:}
nkeynes@359
  2427
STS.L MACH, @-Rn {:  
nkeynes@359
  2428
    load_reg( R_ECX, Rn );
nkeynes@395
  2429
    check_walign32( R_ECX );
nkeynes@382
  2430
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2431
    store_reg( R_ECX, Rn );
nkeynes@359
  2432
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2433
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2434
:}
nkeynes@359
  2435
STS MACL, Rn {:  
nkeynes@359
  2436
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2437
    store_reg( R_EAX, Rn );
nkeynes@359
  2438
:}
nkeynes@359
  2439
STS.L MACL, @-Rn {:  
nkeynes@359
  2440
    load_reg( R_ECX, Rn );
nkeynes@395
  2441
    check_walign32( R_ECX );
nkeynes@382
  2442
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2443
    store_reg( R_ECX, Rn );
nkeynes@359
  2444
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2445
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2446
:}
nkeynes@359
  2447
STS PR, Rn {:  
nkeynes@359
  2448
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2449
    store_reg( R_EAX, Rn );
nkeynes@359
  2450
:}
nkeynes@359
  2451
STS.L PR, @-Rn {:  
nkeynes@359
  2452
    load_reg( R_ECX, Rn );
nkeynes@395
  2453
    check_walign32( R_ECX );
nkeynes@382
  2454
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2455
    store_reg( R_ECX, Rn );
nkeynes@359
  2456
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2457
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2458
:}
nkeynes@359
  2459
nkeynes@359
  2460
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2461
%%
nkeynes@374
  2462
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2463
	ADD_imm8s_r32(2,R_ESI);
nkeynes@374
  2464
	sh4_x86.in_delay_slot = FALSE;
nkeynes@386
  2465
    } else {
nkeynes@386
  2466
	INC_r32(R_ESI);
nkeynes@374
  2467
    }
nkeynes@359
  2468
    return 0;
nkeynes@359
  2469
}
.