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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1301:b76840ccf94b
prev1298:d0eb2307b847
author nkeynes
date Wed May 27 09:42:24 2015 +1000 (5 years ago)
permissions -rw-r--r--
last change Fix stack alignment when calling the end-block callback (broken on OS X)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4dasm.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "xlat/xlatdasm.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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#define SH4_MODE_UNKNOWN -1
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    uint8_t *code;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    uint32_t sh4_mode;     /* Mirror of sh4r.xlat_sh4_mode */
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    int tstate;
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    /* mode settings */
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    gboolean tlb_on; /* True if tlb translation is active */
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    struct mem_region_fn **priv_address_space;
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    struct mem_region_fn **user_address_space;
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    /* Instrumentation */
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    xlat_block_begin_callback_t begin_callback;
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    xlat_block_end_callback_t end_callback;
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    gboolean fastmem;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint8_t sh4_entry_stub[128];
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typedef FASTCALL void (*entry_point_t)(void *);
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entry_point_t sh4_translate_enter;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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static void sh4_x86_translate_unlink_block( void *use_list );
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static struct xlat_target_fns x86_target_fns = {
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	sh4_x86_translate_unlink_block
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};	
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_set_address_space( struct mem_region_fn **priv, struct mem_region_fn **user )
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{
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    sh4_x86.priv_address_space = priv;
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    sh4_x86.user_address_space = user;
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}
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void sh4_translate_write_entry_stub(void)
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{
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	mem_unprotect(sh4_entry_stub, sizeof(sh4_entry_stub));
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	xlat_output = sh4_entry_stub;
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	PUSH_r32(REG_EBP);
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	MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
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	PUSH_r32(REG_EBX);
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	PUSH_r32(REG_SAVE1);
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	PUSH_r32(REG_SAVE2);
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#if SIZEOF_VOID_P == 8
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    PUSH_r32(REG_SAVE3);
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    PUSH_r32(REG_SAVE4);
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    CALL_r32( REG_ARG1 );
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    POP_r32(REG_SAVE4);
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    POP_r32(REG_SAVE3);
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#else
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    SUBL_imms_r32( 8, REG_ESP ); 
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	CALL_r32( REG_ARG1 );
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	ADDL_imms_r32( 8, REG_ESP );
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#endif
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	POP_r32(REG_SAVE2);	
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	POP_r32(REG_SAVE1);
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	POP_r32(REG_EBX);
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	POP_r32(REG_EBP);
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	RET();
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	sh4_translate_enter = (entry_point_t)sh4_entry_stub;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.begin_callback = NULL;
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    sh4_x86.end_callback = NULL;
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    sh4_x86.fastmem = TRUE;
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    sh4_x86.sse3_enabled = is_sse3_supported();
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    xlat_set_target_fns(&x86_target_fns);
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    sh4_translate_set_address_space( sh4_address_space, sh4_user_address_space );
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    sh4_translate_write_entry_stub();
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}
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void sh4_translate_set_callbacks( xlat_block_begin_callback_t begin, xlat_block_end_callback_t end )
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{
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    sh4_x86.begin_callback = begin;
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    sh4_x86.end_callback = end;
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}
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void sh4_translate_set_fastmem( gboolean flag )
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{
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    sh4_x86.fastmem = flag;
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JBE_label(label) JCC_cc_rel8(X86_COND_BE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JP_label(label)  JCC_cc_rel8(X86_COND_P,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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#define LOAD_t() if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; }     
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) LOAD_t() \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) LOAD_t() \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991
   303
#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991
   304
#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   305
#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   306
#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   307
#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   308
#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   309
#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   310
#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991
   311
#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377
   312
nkeynes@991
   313
#ifdef ENABLE_SH4STATS
nkeynes@995
   314
#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991
   315
#else
nkeynes@991
   316
#define COUNT_INST(id)
nkeynes@991
   317
#endif
nkeynes@377
   318
nkeynes@374
   319
nkeynes@368
   320
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   321
nkeynes@416
   322
#define check_priv( ) \
nkeynes@1112
   323
    if( (sh4_x86.sh4_mode & SR_MD) == 0 ) { \
nkeynes@937
   324
        if( sh4_x86.in_delay_slot ) { \
nkeynes@1191
   325
            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2), 4 ); \
nkeynes@937
   326
        } else { \
nkeynes@1191
   327
            exit_block_exc(EXC_ILLEGAL, pc, 2); \
nkeynes@937
   328
        } \
nkeynes@956
   329
        sh4_x86.branch_taken = TRUE; \
nkeynes@937
   330
        sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@937
   331
        return 2; \
nkeynes@937
   332
    }
nkeynes@416
   333
nkeynes@416
   334
#define check_fpuen( ) \
nkeynes@416
   335
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   336
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995
   337
	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991
   338
	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416
   339
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   340
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   341
	} else {\
nkeynes@586
   342
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   343
	}\
nkeynes@875
   344
	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416
   345
    }
nkeynes@416
   346
nkeynes@586
   347
#define check_ralign16( x86reg ) \
nkeynes@991
   348
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   349
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   350
nkeynes@586
   351
#define check_walign16( x86reg ) \
nkeynes@991
   352
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   353
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   354
nkeynes@586
   355
#define check_ralign32( x86reg ) \
nkeynes@991
   356
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   357
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   358
nkeynes@586
   359
#define check_walign32( x86reg ) \
nkeynes@991
   360
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   361
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   362
nkeynes@732
   363
#define check_ralign64( x86reg ) \
nkeynes@991
   364
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   365
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732
   366
nkeynes@732
   367
#define check_walign64( x86reg ) \
nkeynes@991
   368
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   369
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732
   370
nkeynes@1125
   371
#define address_space() ((sh4_x86.sh4_mode&SR_MD) ? (uintptr_t)sh4_x86.priv_address_space : (uintptr_t)sh4_x86.user_address_space)
nkeynes@1004
   372
nkeynes@824
   373
#define UNDEF(ir)
nkeynes@939
   374
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@939
   375
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@586
   376
 */
nkeynes@941
   377
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   378
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   379
{
nkeynes@1292
   380
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1112
   381
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@1292
   382
        CALL1_r32disp_r32(REG_CALLPTR, offset, addr_reg);
nkeynes@995
   383
    } else {
nkeynes@995
   384
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   385
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   386
        }
nkeynes@995
   387
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   388
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   389
        CALL2_r32disp_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   390
    }
nkeynes@995
   391
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   392
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   393
    }
nkeynes@995
   394
}
nkeynes@995
   395
nkeynes@995
   396
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   397
{
nkeynes@1292
   398
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1112
   399
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@1292
   400
        CALL2_r32disp_r32_r32(REG_CALLPTR, offset, addr_reg, value_reg);
nkeynes@995
   401
    } else {
nkeynes@995
   402
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   403
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   404
	}        
nkeynes@995
   405
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   406
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   407
        }
nkeynes@995
   408
#if MAX_REG_ARG > 2        
nkeynes@995
   409
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   410
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   411
        CALL3_r32disp_r32_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   412
#else
nkeynes@995
   413
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   414
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   415
        CALL3_r32disp_r32_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   416
#endif
nkeynes@995
   417
    }
nkeynes@995
   418
}
nkeynes@995
   419
#else
nkeynes@995
   420
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   421
{
nkeynes@1292
   422
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1292
   423
    CALL1_r32disp_r32(REG_CALLPTR, offset, addr_reg);
nkeynes@995
   424
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   425
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   426
    }
nkeynes@995
   427
}     
nkeynes@995
   428
nkeynes@996
   429
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   430
{
nkeynes@1292
   431
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1292
   432
    CALL2_r32disp_r32_r32(REG_CALLPTR, offset, addr_reg, value_reg);
nkeynes@995
   433
}
nkeynes@941
   434
#endif
nkeynes@939
   435
                
nkeynes@995
   436
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   437
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   438
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   439
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   440
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   441
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   442
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   443
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   444
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@368
   445
nkeynes@1191
   446
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@539
   447
nkeynes@1182
   448
/** Offset of xlat_sh4_mode field relative to the code pointer */ 
nkeynes@1186
   449
#define XLAT_SH4_MODE_CODE_OFFSET  (int32_t)(offsetof(struct xlat_cache_block, xlat_sh4_mode) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   450
#define XLAT_CHAIN_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, chain) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   451
#define XLAT_ACTIVE_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, active) - offsetof(struct xlat_cache_block,code) )
nkeynes@1182
   452
nkeynes@901
   453
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   454
{
nkeynes@1112
   455
	sh4_x86.code = xlat_output;
nkeynes@901
   456
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   457
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   458
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   459
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   460
    sh4_x86.block_start_pc = pc;
nkeynes@939
   461
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   463
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   464
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@1112
   465
    sh4_x86.sh4_mode = sh4r.xlat_sh4_mode;
nkeynes@1125
   466
    if( sh4_x86.begin_callback ) {
nkeynes@1125
   467
        CALL_ptr( sh4_x86.begin_callback );
nkeynes@1125
   468
    }
nkeynes@1218
   469
    if( sh4_profile_blocks ) {
nkeynes@1186
   470
    	MOVP_immptr_rptr( sh4_x86.code + XLAT_ACTIVE_CODE_OFFSET, REG_EAX );
nkeynes@1182
   471
    	ADDL_imms_r32disp( 1, REG_EAX, 0 );
nkeynes@1182
   472
    }  
nkeynes@901
   473
}
nkeynes@901
   474
nkeynes@901
   475
nkeynes@593
   476
uint32_t sh4_translate_end_block_size()
nkeynes@593
   477
{
nkeynes@1196
   478
	uint32_t epilogue_size = EPILOGUE_SIZE;
nkeynes@1196
   479
	if( sh4_x86.end_callback ) {
nkeynes@1196
   480
	    epilogue_size += (CALL1_PTR_MIN_SIZE - 1);
nkeynes@1196
   481
	}
nkeynes@596
   482
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1196
   483
        epilogue_size += (sh4_x86.backpatch_posn*(12+CALL1_PTR_MIN_SIZE));
nkeynes@596
   484
    } else {
nkeynes@1196
   485
        epilogue_size += (3*(12+CALL1_PTR_MIN_SIZE)) + (sh4_x86.backpatch_posn-3)*(15+CALL1_PTR_MIN_SIZE);
nkeynes@596
   486
    }
nkeynes@1196
   487
    return epilogue_size;
nkeynes@593
   488
}
nkeynes@593
   489
nkeynes@593
   490
nkeynes@590
   491
/**
nkeynes@590
   492
 * Embed a breakpoint into the generated code
nkeynes@590
   493
 */
nkeynes@586
   494
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   495
{
nkeynes@995
   496
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   497
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   499
}
nkeynes@590
   500
nkeynes@601
   501
nkeynes@601
   502
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   503
nkeynes@1112
   504
/**
nkeynes@1112
   505
 * Test if the loaded target code pointer in %eax is valid, and if so jump
nkeynes@1112
   506
 * directly into it, bypassing the normal exit.
nkeynes@1112
   507
 */
nkeynes@1112
   508
static void jump_next_block()
nkeynes@1112
   509
{
nkeynes@1149
   510
	uint8_t *ptr = xlat_output;
nkeynes@1112
   511
	TESTP_rptr_rptr(REG_EAX, REG_EAX);
nkeynes@1112
   512
	JE_label(nocode);
nkeynes@1112
   513
	if( sh4_x86.sh4_mode == SH4_MODE_UNKNOWN ) {
nkeynes@1112
   514
	    /* sr/fpscr was changed, possibly updated xlat_sh4_mode, so reload it */
nkeynes@1112
   515
	    MOVL_rbpdisp_r32( REG_OFFSET(xlat_sh4_mode), REG_ECX );
nkeynes@1112
   516
	    CMPL_r32_r32disp( REG_ECX, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   517
	} else {
nkeynes@1112
   518
	    CMPL_imms_r32disp( sh4_x86.sh4_mode, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   519
	}
nkeynes@1112
   520
	JNE_label(wrongmode);
nkeynes@1125
   521
	if( sh4_x86.end_callback ) {
nkeynes@1125
   522
	    PUSH_r32(REG_EAX);
nkeynes@1125
   523
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   524
	    JMP_rptr(REG_ECX);
nkeynes@1125
   525
	} else {
nkeynes@1125
   526
	    JMP_rptr(REG_EAX);
nkeynes@1125
   527
	}
nkeynes@1149
   528
	JMP_TARGET(wrongmode);
nkeynes@1176
   529
	MOVP_rptrdisp_rptr( REG_EAX, XLAT_CHAIN_CODE_OFFSET, REG_EAX );
nkeynes@1149
   530
	int rel = ptr - xlat_output;
nkeynes@1149
   531
    JMP_prerel(rel);
nkeynes@1149
   532
	JMP_TARGET(nocode); 
nkeynes@1112
   533
}
nkeynes@1112
   534
nkeynes@1186
   535
/**
nkeynes@1186
   536
 * 
nkeynes@1186
   537
 */
nkeynes@1263
   538
void FASTCALL sh4_translate_link_block( uint32_t pc )
nkeynes@1186
   539
{
nkeynes@1186
   540
    uint8_t *target = (uint8_t *)xlat_get_code_by_vma(pc);
nkeynes@1186
   541
    while( target != NULL && sh4r.xlat_sh4_mode != XLAT_BLOCK_MODE(target) ) {
nkeynes@1186
   542
        target = XLAT_BLOCK_CHAIN(target);
nkeynes@1186
   543
	}
nkeynes@1186
   544
    if( target == NULL ) {
nkeynes@1186
   545
        target = sh4_translate_basic_block( pc );
nkeynes@1186
   546
    }
nkeynes@1186
   547
    uint8_t *backpatch = ((uint8_t *)__builtin_return_address(0)) - (CALL1_PTR_MIN_SIZE);
nkeynes@1186
   548
    *backpatch = 0xE9;
nkeynes@1292
   549
    *(uint32_t *)(backpatch+1) = (uint32_t)(target-backpatch)-5;
nkeynes@1186
   550
    *(void **)(backpatch+5) = XLAT_BLOCK_FOR_CODE(target)->use_list;
nkeynes@1186
   551
    XLAT_BLOCK_FOR_CODE(target)->use_list = backpatch; 
nkeynes@1186
   552
nkeynes@1198
   553
    uint8_t * volatile *retptr = ((uint8_t * volatile *)__builtin_frame_address(0))+1;
nkeynes@1186
   554
    assert( *retptr == ((uint8_t *)__builtin_return_address(0)) );
nkeynes@1186
   555
	*retptr = backpatch;
nkeynes@1186
   556
}
nkeynes@1186
   557
nkeynes@1186
   558
static void emit_translate_and_backpatch()
nkeynes@1186
   559
{
nkeynes@1186
   560
    /* NB: this is either 7 bytes (i386) or 12 bytes (x86-64) */
nkeynes@1263
   561
    CALL1_ptr_r32(sh4_translate_link_block, REG_ARG1);
nkeynes@1186
   562
nkeynes@1186
   563
    /* When patched, the jmp instruction will be 5 bytes (either platform) -
nkeynes@1186
   564
     * we need to reserve sizeof(void*) bytes for the use-list
nkeynes@1186
   565
	 * pointer
nkeynes@1186
   566
	 */ 
nkeynes@1186
   567
    if( sizeof(void*) == 8 ) {
nkeynes@1186
   568
        NOP();
nkeynes@1186
   569
    } else {
nkeynes@1186
   570
        NOP2();
nkeynes@1186
   571
    }
nkeynes@1186
   572
}
nkeynes@1186
   573
nkeynes@1186
   574
/**
nkeynes@1186
   575
 * If we're jumping to a fixed address (or at least fixed relative to the
nkeynes@1186
   576
 * current PC, then we can do a direct branch. REG_ARG1 should contain
nkeynes@1186
   577
 * the PC at this point.
nkeynes@1186
   578
 */
nkeynes@1186
   579
static void jump_next_block_fixed_pc( sh4addr_t pc )
nkeynes@1186
   580
{
nkeynes@1186
   581
	if( IS_IN_ICACHE(pc) ) {
nkeynes@1194
   582
	    if( sh4_x86.sh4_mode != SH4_MODE_UNKNOWN && sh4_x86.end_callback == NULL ) {
nkeynes@1186
   583
	        /* Fixed address, in cache, and fixed SH4 mode - generate a call to the
nkeynes@1186
   584
	         * fetch-and-backpatch routine, which will replace the call with a branch */
nkeynes@1186
   585
           emit_translate_and_backpatch();	         
nkeynes@1186
   586
           return;
nkeynes@1186
   587
		} else {
nkeynes@1186
   588
            MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@1186
   589
            ANDP_imms_rptr( -4, REG_EAX );
nkeynes@1186
   590
        }
nkeynes@1186
   591
	} else if( sh4_x86.tlb_on ) {
nkeynes@1186
   592
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@1186
   593
    } else {
nkeynes@1186
   594
        CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@1186
   595
    }
nkeynes@1186
   596
    jump_next_block();
nkeynes@1186
   597
nkeynes@1186
   598
nkeynes@1186
   599
}
nkeynes@1186
   600
nkeynes@1214
   601
static void sh4_x86_translate_unlink_block( void *use_list )
nkeynes@1186
   602
{
nkeynes@1186
   603
	uint8_t *tmp = xlat_output; /* In case something is active, which should never happen */
nkeynes@1186
   604
	void *next = use_list;
nkeynes@1186
   605
	while( next != NULL ) {
nkeynes@1186
   606
    	xlat_output = (uint8_t *)next;
nkeynes@1186
   607
 	    next = *(void **)(xlat_output+5);
nkeynes@1186
   608
 		emit_translate_and_backpatch();
nkeynes@1186
   609
 	}
nkeynes@1186
   610
 	xlat_output = tmp;
nkeynes@1186
   611
}
nkeynes@1186
   612
nkeynes@1186
   613
nkeynes@1186
   614
nkeynes@1125
   615
static void exit_block()
nkeynes@1125
   616
{
nkeynes@1125
   617
	if( sh4_x86.end_callback ) {
nkeynes@1301
   618
	    CALL_ptr(sh4_x86.end_callback);
nkeynes@1125
   619
	}
nkeynes@1301
   620
	RET();
nkeynes@1125
   621
}
nkeynes@1125
   622
nkeynes@590
   623
/**
nkeynes@995
   624
 * Exit the block with sh4r.pc already written
nkeynes@995
   625
 */
nkeynes@995
   626
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   627
{
nkeynes@995
   628
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   629
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   630
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   631
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   632
    JBE_label(exitloop);
nkeynes@995
   633
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   634
    if( sh4_x86.tlb_on ) {
nkeynes@995
   635
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   636
    } else {
nkeynes@995
   637
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   638
    }
nkeynes@1112
   639
    
nkeynes@1112
   640
    jump_next_block();
nkeynes@1112
   641
    JMP_TARGET(exitloop);
nkeynes@995
   642
    exit_block();
nkeynes@995
   643
}
nkeynes@995
   644
nkeynes@995
   645
/**
nkeynes@995
   646
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   647
 */
nkeynes@995
   648
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   649
{
nkeynes@995
   650
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   651
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   652
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   653
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   654
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   655
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   656
    JBE_label(exitloop);
nkeynes@995
   657
    if( sh4_x86.tlb_on ) {
nkeynes@995
   658
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   659
    } else {
nkeynes@995
   660
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   661
    }
nkeynes@1112
   662
	
nkeynes@1112
   663
	jump_next_block();
nkeynes@1112
   664
    JMP_TARGET(exitloop);
nkeynes@995
   665
    exit_block();
nkeynes@995
   666
}
nkeynes@995
   667
nkeynes@995
   668
nkeynes@995
   669
/**
nkeynes@995
   670
 * Exit the block to an absolute PC
nkeynes@995
   671
 */
nkeynes@995
   672
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   673
{
nkeynes@1112
   674
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   675
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   676
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   677
nkeynes@1112
   678
    MOVL_imm32_r32( pc, REG_ARG1 );
nkeynes@1112
   679
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   680
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   681
    JBE_label(exitloop);
nkeynes@1186
   682
    jump_next_block_fixed_pc(pc);    
nkeynes@1112
   683
    JMP_TARGET(exitloop);
nkeynes@995
   684
    exit_block();
nkeynes@995
   685
}
nkeynes@995
   686
nkeynes@995
   687
/**
nkeynes@995
   688
 * Exit the block to a relative PC
nkeynes@995
   689
 */
nkeynes@995
   690
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   691
{
nkeynes@1112
   692
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   693
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   694
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   695
nkeynes@1112
   696
	if( pc == sh4_x86.block_start_pc && sh4_x86.sh4_mode == sh4r.xlat_sh4_mode ) {
nkeynes@1112
   697
	    /* Special case for tight loops - the PC doesn't change, and
nkeynes@1112
   698
	     * we already know the target address. Just check events pending before
nkeynes@1112
   699
	     * looping.
nkeynes@1112
   700
	     */
nkeynes@1112
   701
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1292
   702
        uint32_t backdisp = ((uintptr_t)(sh4_x86.code - xlat_output));
nkeynes@1112
   703
        JCC_cc_prerel(X86_COND_A, backdisp);
nkeynes@1112
   704
	} else {
nkeynes@1112
   705
        MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ARG1 );
nkeynes@1112
   706
        ADDL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@1112
   707
        MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   708
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   709
        JBE_label(exitloop2);
nkeynes@1186
   710
        
nkeynes@1186
   711
        jump_next_block_fixed_pc(pc);
nkeynes@1112
   712
        JMP_TARGET(exitloop2);
nkeynes@995
   713
    }
nkeynes@995
   714
    exit_block();
nkeynes@995
   715
}
nkeynes@995
   716
nkeynes@995
   717
/**
nkeynes@995
   718
 * Exit unconditionally with a general exception
nkeynes@995
   719
 */
nkeynes@1191
   720
void exit_block_exc( int code, sh4addr_t pc, int inst_adjust )
nkeynes@995
   721
{
nkeynes@995
   722
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   723
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@1191
   724
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc + inst_adjust)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   725
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   726
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   727
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   728
    exit_block();
nkeynes@995
   729
}    
nkeynes@995
   730
nkeynes@995
   731
/**
nkeynes@590
   732
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   733
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   734
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   735
 *
nkeynes@601
   736
 * Performs:
nkeynes@601
   737
 *   Set PC = endpc
nkeynes@601
   738
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   739
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   740
 *   Call sh4_execute_instruction
nkeynes@601
   741
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   742
 */
nkeynes@601
   743
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   744
{
nkeynes@995
   745
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   746
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   747
    
nkeynes@995
   748
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   749
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   750
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   751
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   752
nkeynes@1112
   753
    CALL_ptr( sh4_execute_instruction );
nkeynes@926
   754
    exit_block();
nkeynes@590
   755
} 
nkeynes@539
   756
nkeynes@359
   757
/**
nkeynes@995
   758
 * Write the block trailer (exception handling block)
nkeynes@995
   759
 */
nkeynes@995
   760
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   761
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   762
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   763
        exit_block_rel( pc, pc );
nkeynes@995
   764
    }
nkeynes@995
   765
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   766
        unsigned int i;
nkeynes@995
   767
        // Exception raised - cleanup and exit
nkeynes@995
   768
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   769
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   770
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   771
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   772
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@1191
   773
        INC_r32( REG_EDX );  /* Add 1 for the aborting instruction itself */ 
nkeynes@995
   774
        MULL_r32( REG_EDX );
nkeynes@995
   775
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   776
        exit_block();
nkeynes@995
   777
nkeynes@995
   778
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   779
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   780
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   781
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   782
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   783
                } else {
nkeynes@995
   784
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   785
                }
nkeynes@995
   786
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   787
                int rel = end_ptr - xlat_output;
nkeynes@995
   788
                JMP_prerel(rel);
nkeynes@995
   789
            } else {
nkeynes@995
   790
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   791
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   792
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   793
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   794
                int rel = end_ptr - xlat_output;
nkeynes@995
   795
                JMP_prerel(rel);
nkeynes@995
   796
            }
nkeynes@995
   797
        }
nkeynes@995
   798
    }
nkeynes@995
   799
}
nkeynes@539
   800
nkeynes@359
   801
/**
nkeynes@359
   802
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   803
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   804
 * 
nkeynes@586
   805
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   806
 *
nkeynes@359
   807
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   808
 * (eg a branch or 
nkeynes@359
   809
 */
nkeynes@590
   810
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   811
{
nkeynes@388
   812
    uint32_t ir;
nkeynes@586
   813
    /* Read instruction from icache */
nkeynes@586
   814
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   815
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   816
    
nkeynes@586
   817
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   818
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   819
    }
nkeynes@1003
   820
    
nkeynes@1003
   821
    /* check for breakpoints at this pc */
nkeynes@1003
   822
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   823
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   824
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   825
            break;
nkeynes@1003
   826
        }
nkeynes@571
   827
    }
nkeynes@359
   828
%%
nkeynes@359
   829
/* ALU operations */
nkeynes@359
   830
ADD Rm, Rn {:
nkeynes@671
   831
    COUNT_INST(I_ADD);
nkeynes@991
   832
    load_reg( REG_EAX, Rm );
nkeynes@991
   833
    load_reg( REG_ECX, Rn );
nkeynes@991
   834
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   835
    store_reg( REG_ECX, Rn );
nkeynes@417
   836
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   837
:}
nkeynes@359
   838
ADD #imm, Rn {:  
nkeynes@671
   839
    COUNT_INST(I_ADDI);
nkeynes@991
   840
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   842
:}
nkeynes@359
   843
ADDC Rm, Rn {:
nkeynes@671
   844
    COUNT_INST(I_ADDC);
nkeynes@417
   845
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   846
        LDC_t();
nkeynes@417
   847
    }
nkeynes@991
   848
    load_reg( REG_EAX, Rm );
nkeynes@991
   849
    load_reg( REG_ECX, Rn );
nkeynes@991
   850
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   851
    store_reg( REG_ECX, Rn );
nkeynes@359
   852
    SETC_t();
nkeynes@417
   853
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   854
:}
nkeynes@359
   855
ADDV Rm, Rn {:
nkeynes@671
   856
    COUNT_INST(I_ADDV);
nkeynes@991
   857
    load_reg( REG_EAX, Rm );
nkeynes@991
   858
    load_reg( REG_ECX, Rn );
nkeynes@991
   859
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   860
    store_reg( REG_ECX, Rn );
nkeynes@359
   861
    SETO_t();
nkeynes@417
   862
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   863
:}
nkeynes@359
   864
AND Rm, Rn {:
nkeynes@671
   865
    COUNT_INST(I_AND);
nkeynes@991
   866
    load_reg( REG_EAX, Rm );
nkeynes@991
   867
    load_reg( REG_ECX, Rn );
nkeynes@991
   868
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   869
    store_reg( REG_ECX, Rn );
nkeynes@417
   870
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   871
:}
nkeynes@359
   872
AND #imm, R0 {:  
nkeynes@671
   873
    COUNT_INST(I_ANDI);
nkeynes@991
   874
    load_reg( REG_EAX, 0 );
nkeynes@991
   875
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   876
    store_reg( REG_EAX, 0 );
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   878
:}
nkeynes@359
   879
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   880
    COUNT_INST(I_ANDB);
nkeynes@991
   881
    load_reg( REG_EAX, 0 );
nkeynes@991
   882
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@1292
   883
    MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
   884
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@1292
   885
    MOVL_r32_r32(REG_SAVE1, REG_EAX);
nkeynes@991
   886
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   887
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   888
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   889
:}
nkeynes@359
   890
CMP/EQ Rm, Rn {:  
nkeynes@671
   891
    COUNT_INST(I_CMPEQ);
nkeynes@991
   892
    load_reg( REG_EAX, Rm );
nkeynes@991
   893
    load_reg( REG_ECX, Rn );
nkeynes@991
   894
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   895
    SETE_t();
nkeynes@417
   896
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   897
:}
nkeynes@359
   898
CMP/EQ #imm, R0 {:  
nkeynes@671
   899
    COUNT_INST(I_CMPEQI);
nkeynes@991
   900
    load_reg( REG_EAX, 0 );
nkeynes@991
   901
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   902
    SETE_t();
nkeynes@417
   903
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   904
:}
nkeynes@359
   905
CMP/GE Rm, Rn {:  
nkeynes@671
   906
    COUNT_INST(I_CMPGE);
nkeynes@991
   907
    load_reg( REG_EAX, Rm );
nkeynes@991
   908
    load_reg( REG_ECX, Rn );
nkeynes@991
   909
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   910
    SETGE_t();
nkeynes@417
   911
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   912
:}
nkeynes@359
   913
CMP/GT Rm, Rn {: 
nkeynes@671
   914
    COUNT_INST(I_CMPGT);
nkeynes@991
   915
    load_reg( REG_EAX, Rm );
nkeynes@991
   916
    load_reg( REG_ECX, Rn );
nkeynes@991
   917
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   918
    SETG_t();
nkeynes@417
   919
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   920
:}
nkeynes@359
   921
CMP/HI Rm, Rn {:  
nkeynes@671
   922
    COUNT_INST(I_CMPHI);
nkeynes@991
   923
    load_reg( REG_EAX, Rm );
nkeynes@991
   924
    load_reg( REG_ECX, Rn );
nkeynes@991
   925
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   926
    SETA_t();
nkeynes@417
   927
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   928
:}
nkeynes@359
   929
CMP/HS Rm, Rn {: 
nkeynes@671
   930
    COUNT_INST(I_CMPHS);
nkeynes@991
   931
    load_reg( REG_EAX, Rm );
nkeynes@991
   932
    load_reg( REG_ECX, Rn );
nkeynes@991
   933
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   934
    SETAE_t();
nkeynes@417
   935
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   936
 :}
nkeynes@359
   937
CMP/PL Rn {: 
nkeynes@671
   938
    COUNT_INST(I_CMPPL);
nkeynes@991
   939
    load_reg( REG_EAX, Rn );
nkeynes@991
   940
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   941
    SETG_t();
nkeynes@417
   942
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   943
:}
nkeynes@359
   944
CMP/PZ Rn {:  
nkeynes@671
   945
    COUNT_INST(I_CMPPZ);
nkeynes@991
   946
    load_reg( REG_EAX, Rn );
nkeynes@991
   947
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   948
    SETGE_t();
nkeynes@417
   949
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   950
:}
nkeynes@361
   951
CMP/STR Rm, Rn {:  
nkeynes@671
   952
    COUNT_INST(I_CMPSTR);
nkeynes@991
   953
    load_reg( REG_EAX, Rm );
nkeynes@991
   954
    load_reg( REG_ECX, Rn );
nkeynes@991
   955
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   956
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   957
    JE_label(target1);
nkeynes@991
   958
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   959
    JE_label(target2);
nkeynes@991
   960
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   961
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   962
    JE_label(target3);
nkeynes@991
   963
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   964
    JMP_TARGET(target1);
nkeynes@380
   965
    JMP_TARGET(target2);
nkeynes@380
   966
    JMP_TARGET(target3);
nkeynes@368
   967
    SETE_t();
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   969
:}
nkeynes@361
   970
DIV0S Rm, Rn {:
nkeynes@671
   971
    COUNT_INST(I_DIV0S);
nkeynes@991
   972
    load_reg( REG_EAX, Rm );
nkeynes@991
   973
    load_reg( REG_ECX, Rn );
nkeynes@991
   974
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   975
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
   976
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   977
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   978
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   979
    SETNE_t();
nkeynes@417
   980
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   981
:}
nkeynes@361
   982
DIV0U {:  
nkeynes@671
   983
    COUNT_INST(I_DIV0U);
nkeynes@991
   984
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
   985
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
   986
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   987
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   988
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   989
:}
nkeynes@386
   990
DIV1 Rm, Rn {:
nkeynes@671
   991
    COUNT_INST(I_DIV1);
nkeynes@995
   992
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
   993
    load_reg( REG_EAX, Rn );
nkeynes@417
   994
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   995
	LDC_t();
nkeynes@417
   996
    }
nkeynes@991
   997
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   998
    SETC_r8( REG_DL ); // Q'
nkeynes@991
   999
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
  1000
    JE_label(mqequal);
nkeynes@991
  1001
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1002
    JMP_label(end);
nkeynes@380
  1003
    JMP_TARGET(mqequal);
nkeynes@991
  1004
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
  1005
    JMP_TARGET(end);
nkeynes@991
  1006
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
  1007
    SETC_r8(REG_AL); // tmp1
nkeynes@991
  1008
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
  1009
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
  1010
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1011
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
  1012
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
  1013
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1014
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1015
:}
nkeynes@361
  1016
DMULS.L Rm, Rn {:  
nkeynes@671
  1017
    COUNT_INST(I_DMULS);
nkeynes@991
  1018
    load_reg( REG_EAX, Rm );
nkeynes@991
  1019
    load_reg( REG_ECX, Rn );
nkeynes@991
  1020
    IMULL_r32(REG_ECX);
nkeynes@995
  1021
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1022
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1023
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1024
:}
nkeynes@361
  1025
DMULU.L Rm, Rn {:  
nkeynes@671
  1026
    COUNT_INST(I_DMULU);
nkeynes@991
  1027
    load_reg( REG_EAX, Rm );
nkeynes@991
  1028
    load_reg( REG_ECX, Rn );
nkeynes@991
  1029
    MULL_r32(REG_ECX);
nkeynes@995
  1030
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1031
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
  1032
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1033
:}
nkeynes@359
  1034
DT Rn {:  
nkeynes@671
  1035
    COUNT_INST(I_DT);
nkeynes@991
  1036
    load_reg( REG_EAX, Rn );
nkeynes@991
  1037
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
  1038
    store_reg( REG_EAX, Rn );
nkeynes@359
  1039
    SETE_t();
nkeynes@417
  1040
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1041
:}
nkeynes@359
  1042
EXTS.B Rm, Rn {:  
nkeynes@671
  1043
    COUNT_INST(I_EXTSB);
nkeynes@991
  1044
    load_reg( REG_EAX, Rm );
nkeynes@991
  1045
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1046
    store_reg( REG_EAX, Rn );
nkeynes@359
  1047
:}
nkeynes@361
  1048
EXTS.W Rm, Rn {:  
nkeynes@671
  1049
    COUNT_INST(I_EXTSW);
nkeynes@991
  1050
    load_reg( REG_EAX, Rm );
nkeynes@991
  1051
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1052
    store_reg( REG_EAX, Rn );
nkeynes@361
  1053
:}
nkeynes@361
  1054
EXTU.B Rm, Rn {:  
nkeynes@671
  1055
    COUNT_INST(I_EXTUB);
nkeynes@991
  1056
    load_reg( REG_EAX, Rm );
nkeynes@991
  1057
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1058
    store_reg( REG_EAX, Rn );
nkeynes@361
  1059
:}
nkeynes@361
  1060
EXTU.W Rm, Rn {:  
nkeynes@671
  1061
    COUNT_INST(I_EXTUW);
nkeynes@991
  1062
    load_reg( REG_EAX, Rm );
nkeynes@991
  1063
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1064
    store_reg( REG_EAX, Rn );
nkeynes@361
  1065
:}
nkeynes@586
  1066
MAC.L @Rm+, @Rn+ {:
nkeynes@671
  1067
    COUNT_INST(I_MACL);
nkeynes@586
  1068
    if( Rm == Rn ) {
nkeynes@991
  1069
	load_reg( REG_EAX, Rm );
nkeynes@991
  1070
	check_ralign32( REG_EAX );
nkeynes@991
  1071
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@1292
  1072
	MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
  1073
	load_reg( REG_EAX, Rm );
nkeynes@991
  1074
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1075
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1076
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
  1077
    } else {
nkeynes@991
  1078
	load_reg( REG_EAX, Rm );
nkeynes@991
  1079
	check_ralign32( REG_EAX );
nkeynes@991
  1080
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@1292
  1081
	MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
  1082
	load_reg( REG_EAX, Rn );
nkeynes@991
  1083
	check_ralign32( REG_EAX );
nkeynes@991
  1084
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1085
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
  1086
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1087
    }
nkeynes@939
  1088
    
nkeynes@1292
  1089
    IMULL_r32( REG_SAVE1 );
nkeynes@991
  1090
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
  1091
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
  1092
nkeynes@995
  1093
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1094
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
  1095
    JE_label( nosat );
nkeynes@995
  1096
    CALL_ptr( signsat48 );
nkeynes@386
  1097
    JMP_TARGET( nosat );
nkeynes@417
  1098
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1099
:}
nkeynes@386
  1100
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
  1101
    COUNT_INST(I_MACW);
nkeynes@586
  1102
    if( Rm == Rn ) {
nkeynes@991
  1103
	load_reg( REG_EAX, Rm );
nkeynes@991
  1104
	check_ralign16( REG_EAX );
nkeynes@991
  1105
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@1292
  1106
        MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1107
	load_reg( REG_EAX, Rm );
nkeynes@991
  1108
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
  1109
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1110
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1111
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  1112
	// adding a page-boundary check to skip the second translation
nkeynes@586
  1113
    } else {
nkeynes@1193
  1114
	load_reg( REG_EAX, Rn );
nkeynes@991
  1115
	check_ralign16( REG_EAX );
nkeynes@991
  1116
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@1292
  1117
        MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@1193
  1118
	load_reg( REG_EAX, Rm );
nkeynes@991
  1119
	check_ralign16( REG_EAX );
nkeynes@991
  1120
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1121
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
  1122
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1123
    }
nkeynes@1292
  1124
    IMULL_r32( REG_SAVE1 );
nkeynes@995
  1125
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1126
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
  1127
    JE_label( nosat );
nkeynes@386
  1128
nkeynes@991
  1129
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1130
    JNO_label( end );            // 2
nkeynes@995
  1131
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
  1132
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
  1133
    JS_label( positive );        // 2
nkeynes@995
  1134
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
  1135
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1136
    JMP_label(end2);           // 2
nkeynes@386
  1137
nkeynes@386
  1138
    JMP_TARGET(positive);
nkeynes@995
  1139
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
  1140
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1141
    JMP_label(end3);            // 2
nkeynes@386
  1142
nkeynes@386
  1143
    JMP_TARGET(nosat);
nkeynes@991
  1144
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1145
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
  1146
    JMP_TARGET(end);
nkeynes@386
  1147
    JMP_TARGET(end2);
nkeynes@386
  1148
    JMP_TARGET(end3);
nkeynes@417
  1149
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1150
:}
nkeynes@359
  1151
MOVT Rn {:  
nkeynes@671
  1152
    COUNT_INST(I_MOVT);
nkeynes@995
  1153
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
  1154
    store_reg( REG_EAX, Rn );
nkeynes@359
  1155
:}
nkeynes@361
  1156
MUL.L Rm, Rn {:  
nkeynes@671
  1157
    COUNT_INST(I_MULL);
nkeynes@991
  1158
    load_reg( REG_EAX, Rm );
nkeynes@991
  1159
    load_reg( REG_ECX, Rn );
nkeynes@991
  1160
    MULL_r32( REG_ECX );
nkeynes@995
  1161
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1163
:}
nkeynes@374
  1164
MULS.W Rm, Rn {:
nkeynes@671
  1165
    COUNT_INST(I_MULSW);
nkeynes@995
  1166
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1167
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1168
    MULL_r32( REG_ECX );
nkeynes@995
  1169
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1171
:}
nkeynes@374
  1172
MULU.W Rm, Rn {:  
nkeynes@671
  1173
    COUNT_INST(I_MULUW);
nkeynes@995
  1174
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1175
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1176
    MULL_r32( REG_ECX );
nkeynes@995
  1177
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1179
:}
nkeynes@359
  1180
NEG Rm, Rn {:
nkeynes@671
  1181
    COUNT_INST(I_NEG);
nkeynes@991
  1182
    load_reg( REG_EAX, Rm );
nkeynes@991
  1183
    NEGL_r32( REG_EAX );
nkeynes@991
  1184
    store_reg( REG_EAX, Rn );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1186
:}
nkeynes@359
  1187
NEGC Rm, Rn {:  
nkeynes@671
  1188
    COUNT_INST(I_NEGC);
nkeynes@991
  1189
    load_reg( REG_EAX, Rm );
nkeynes@991
  1190
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
  1191
    LDC_t();
nkeynes@991
  1192
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1193
    store_reg( REG_ECX, Rn );
nkeynes@359
  1194
    SETC_t();
nkeynes@417
  1195
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1196
:}
nkeynes@359
  1197
NOT Rm, Rn {:  
nkeynes@671
  1198
    COUNT_INST(I_NOT);
nkeynes@991
  1199
    load_reg( REG_EAX, Rm );
nkeynes@991
  1200
    NOTL_r32( REG_EAX );
nkeynes@991
  1201
    store_reg( REG_EAX, Rn );
nkeynes@417
  1202
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1203
:}
nkeynes@359
  1204
OR Rm, Rn {:  
nkeynes@671
  1205
    COUNT_INST(I_OR);
nkeynes@991
  1206
    load_reg( REG_EAX, Rm );
nkeynes@991
  1207
    load_reg( REG_ECX, Rn );
nkeynes@991
  1208
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1209
    store_reg( REG_ECX, Rn );
nkeynes@417
  1210
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1211
:}
nkeynes@359
  1212
OR #imm, R0 {:
nkeynes@671
  1213
    COUNT_INST(I_ORI);
nkeynes@991
  1214
    load_reg( REG_EAX, 0 );
nkeynes@991
  1215
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1216
    store_reg( REG_EAX, 0 );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1218
:}
nkeynes@374
  1219
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1220
    COUNT_INST(I_ORB);
nkeynes@991
  1221
    load_reg( REG_EAX, 0 );
nkeynes@991
  1222
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@1292
  1223
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1224
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@1292
  1225
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1226
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1227
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1229
:}
nkeynes@359
  1230
ROTCL Rn {:
nkeynes@671
  1231
    COUNT_INST(I_ROTCL);
nkeynes@991
  1232
    load_reg( REG_EAX, Rn );
nkeynes@417
  1233
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1234
	LDC_t();
nkeynes@417
  1235
    }
nkeynes@991
  1236
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1237
    store_reg( REG_EAX, Rn );
nkeynes@359
  1238
    SETC_t();
nkeynes@417
  1239
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1240
:}
nkeynes@359
  1241
ROTCR Rn {:  
nkeynes@671
  1242
    COUNT_INST(I_ROTCR);
nkeynes@991
  1243
    load_reg( REG_EAX, Rn );
nkeynes@417
  1244
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1245
	LDC_t();
nkeynes@417
  1246
    }
nkeynes@991
  1247
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1248
    store_reg( REG_EAX, Rn );
nkeynes@359
  1249
    SETC_t();
nkeynes@417
  1250
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1251
:}
nkeynes@359
  1252
ROTL Rn {:  
nkeynes@671
  1253
    COUNT_INST(I_ROTL);
nkeynes@991
  1254
    load_reg( REG_EAX, Rn );
nkeynes@991
  1255
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1256
    store_reg( REG_EAX, Rn );
nkeynes@359
  1257
    SETC_t();
nkeynes@417
  1258
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1259
:}
nkeynes@359
  1260
ROTR Rn {:  
nkeynes@671
  1261
    COUNT_INST(I_ROTR);
nkeynes@991
  1262
    load_reg( REG_EAX, Rn );
nkeynes@991
  1263
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1264
    store_reg( REG_EAX, Rn );
nkeynes@359
  1265
    SETC_t();
nkeynes@417
  1266
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1267
:}
nkeynes@359
  1268
SHAD Rm, Rn {:
nkeynes@671
  1269
    COUNT_INST(I_SHAD);
nkeynes@359
  1270
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1271
    load_reg( REG_EAX, Rn );
nkeynes@991
  1272
    load_reg( REG_ECX, Rm );
nkeynes@991
  1273
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1274
    JGE_label(doshl);
nkeynes@361
  1275
                    
nkeynes@991
  1276
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1277
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1278
    JE_label(emptysar);     // 2
nkeynes@991
  1279
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1280
    JMP_label(end);          // 2
nkeynes@386
  1281
nkeynes@386
  1282
    JMP_TARGET(emptysar);
nkeynes@991
  1283
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1284
    JMP_label(end2);
nkeynes@382
  1285
nkeynes@380
  1286
    JMP_TARGET(doshl);
nkeynes@991
  1287
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1288
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1289
    JMP_TARGET(end);
nkeynes@386
  1290
    JMP_TARGET(end2);
nkeynes@991
  1291
    store_reg( REG_EAX, Rn );
nkeynes@417
  1292
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1293
:}
nkeynes@359
  1294
SHLD Rm, Rn {:  
nkeynes@671
  1295
    COUNT_INST(I_SHLD);
nkeynes@991
  1296
    load_reg( REG_EAX, Rn );
nkeynes@991
  1297
    load_reg( REG_ECX, Rm );
nkeynes@991
  1298
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1299
    JGE_label(doshl);
nkeynes@368
  1300
nkeynes@991
  1301
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1302
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1303
    JE_label(emptyshr );
nkeynes@991
  1304
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1305
    JMP_label(end);          // 2
nkeynes@386
  1306
nkeynes@386
  1307
    JMP_TARGET(emptyshr);
nkeynes@991
  1308
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1309
    JMP_label(end2);
nkeynes@382
  1310
nkeynes@382
  1311
    JMP_TARGET(doshl);
nkeynes@991
  1312
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1313
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1314
    JMP_TARGET(end);
nkeynes@386
  1315
    JMP_TARGET(end2);
nkeynes@991
  1316
    store_reg( REG_EAX, Rn );
nkeynes@417
  1317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1318
:}
nkeynes@359
  1319
SHAL Rn {: 
nkeynes@671
  1320
    COUNT_INST(I_SHAL);
nkeynes@991
  1321
    load_reg( REG_EAX, Rn );
nkeynes@991
  1322
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1323
    SETC_t();
nkeynes@991
  1324
    store_reg( REG_EAX, Rn );
nkeynes@417
  1325
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1326
:}
nkeynes@359
  1327
SHAR Rn {:  
nkeynes@671
  1328
    COUNT_INST(I_SHAR);
nkeynes@991
  1329
    load_reg( REG_EAX, Rn );
nkeynes@991
  1330
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1331
    SETC_t();
nkeynes@991
  1332
    store_reg( REG_EAX, Rn );
nkeynes@417
  1333
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1334
:}
nkeynes@359
  1335
SHLL Rn {:  
nkeynes@671
  1336
    COUNT_INST(I_SHLL);
nkeynes@991
  1337
    load_reg( REG_EAX, Rn );
nkeynes@991
  1338
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1339
    SETC_t();
nkeynes@991
  1340
    store_reg( REG_EAX, Rn );
nkeynes@417
  1341
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1342
:}
nkeynes@359
  1343
SHLL2 Rn {:
nkeynes@671
  1344
    COUNT_INST(I_SHLL);
nkeynes@991
  1345
    load_reg( REG_EAX, Rn );
nkeynes@991
  1346
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1347
    store_reg( REG_EAX, Rn );
nkeynes@417
  1348
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1349
:}
nkeynes@359
  1350
SHLL8 Rn {:  
nkeynes@671
  1351
    COUNT_INST(I_SHLL);
nkeynes@991
  1352
    load_reg( REG_EAX, Rn );
nkeynes@991
  1353
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1354
    store_reg( REG_EAX, Rn );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1356
:}
nkeynes@359
  1357
SHLL16 Rn {:  
nkeynes@671
  1358
    COUNT_INST(I_SHLL);
nkeynes@991
  1359
    load_reg( REG_EAX, Rn );
nkeynes@991
  1360
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1361
    store_reg( REG_EAX, Rn );
nkeynes@417
  1362
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1363
:}
nkeynes@359
  1364
SHLR Rn {:  
nkeynes@671
  1365
    COUNT_INST(I_SHLR);
nkeynes@991
  1366
    load_reg( REG_EAX, Rn );
nkeynes@991
  1367
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1368
    SETC_t();
nkeynes@991
  1369
    store_reg( REG_EAX, Rn );
nkeynes@417
  1370
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1371
:}
nkeynes@359
  1372
SHLR2 Rn {:  
nkeynes@671
  1373
    COUNT_INST(I_SHLR);
nkeynes@991
  1374
    load_reg( REG_EAX, Rn );
nkeynes@991
  1375
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1376
    store_reg( REG_EAX, Rn );
nkeynes@417
  1377
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1378
:}
nkeynes@359
  1379
SHLR8 Rn {:  
nkeynes@671
  1380
    COUNT_INST(I_SHLR);
nkeynes@991
  1381
    load_reg( REG_EAX, Rn );
nkeynes@991
  1382
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1383
    store_reg( REG_EAX, Rn );
nkeynes@417
  1384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1385
:}
nkeynes@359
  1386
SHLR16 Rn {:  
nkeynes@671
  1387
    COUNT_INST(I_SHLR);
nkeynes@991
  1388
    load_reg( REG_EAX, Rn );
nkeynes@991
  1389
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1390
    store_reg( REG_EAX, Rn );
nkeynes@417
  1391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1392
:}
nkeynes@359
  1393
SUB Rm, Rn {:  
nkeynes@671
  1394
    COUNT_INST(I_SUB);
nkeynes@991
  1395
    load_reg( REG_EAX, Rm );
nkeynes@991
  1396
    load_reg( REG_ECX, Rn );
nkeynes@991
  1397
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1398
    store_reg( REG_ECX, Rn );
nkeynes@417
  1399
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1400
:}
nkeynes@359
  1401
SUBC Rm, Rn {:  
nkeynes@671
  1402
    COUNT_INST(I_SUBC);
nkeynes@991
  1403
    load_reg( REG_EAX, Rm );
nkeynes@991
  1404
    load_reg( REG_ECX, Rn );
nkeynes@417
  1405
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1406
	LDC_t();
nkeynes@417
  1407
    }
nkeynes@991
  1408
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1409
    store_reg( REG_ECX, Rn );
nkeynes@394
  1410
    SETC_t();
nkeynes@417
  1411
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1412
:}
nkeynes@359
  1413
SUBV Rm, Rn {:  
nkeynes@671
  1414
    COUNT_INST(I_SUBV);
nkeynes@991
  1415
    load_reg( REG_EAX, Rm );
nkeynes@991
  1416
    load_reg( REG_ECX, Rn );
nkeynes@991
  1417
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1418
    store_reg( REG_ECX, Rn );
nkeynes@359
  1419
    SETO_t();
nkeynes@417
  1420
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1421
:}
nkeynes@359
  1422
SWAP.B Rm, Rn {:  
nkeynes@671
  1423
    COUNT_INST(I_SWAPB);
nkeynes@991
  1424
    load_reg( REG_EAX, Rm );
nkeynes@991
  1425
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1426
    store_reg( REG_EAX, Rn );
nkeynes@359
  1427
:}
nkeynes@359
  1428
SWAP.W Rm, Rn {:  
nkeynes@671
  1429
    COUNT_INST(I_SWAPB);
nkeynes@991
  1430
    load_reg( REG_EAX, Rm );
nkeynes@991
  1431
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1432
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1433
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1434
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1435
    store_reg( REG_ECX, Rn );
nkeynes@417
  1436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1437
:}
nkeynes@361
  1438
TAS.B @Rn {:  
nkeynes@671
  1439
    COUNT_INST(I_TASB);
nkeynes@991
  1440
    load_reg( REG_EAX, Rn );
nkeynes@1292
  1441
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1442
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1443
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1444
    SETE_t();
nkeynes@991
  1445
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@1292
  1446
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1447
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1449
:}
nkeynes@361
  1450
TST Rm, Rn {:  
nkeynes@671
  1451
    COUNT_INST(I_TST);
nkeynes@991
  1452
    load_reg( REG_EAX, Rm );
nkeynes@991
  1453
    load_reg( REG_ECX, Rn );
nkeynes@991
  1454
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1455
    SETE_t();
nkeynes@417
  1456
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1457
:}
nkeynes@368
  1458
TST #imm, R0 {:  
nkeynes@671
  1459
    COUNT_INST(I_TSTI);
nkeynes@991
  1460
    load_reg( REG_EAX, 0 );
nkeynes@991
  1461
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1462
    SETE_t();
nkeynes@417
  1463
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1464
:}
nkeynes@368
  1465
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1466
    COUNT_INST(I_TSTB);
nkeynes@991
  1467
    load_reg( REG_EAX, 0);
nkeynes@991
  1468
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1469
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1470
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1471
    SETE_t();
nkeynes@417
  1472
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1473
:}
nkeynes@359
  1474
XOR Rm, Rn {:  
nkeynes@671
  1475
    COUNT_INST(I_XOR);
nkeynes@991
  1476
    load_reg( REG_EAX, Rm );
nkeynes@991
  1477
    load_reg( REG_ECX, Rn );
nkeynes@991
  1478
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1479
    store_reg( REG_ECX, Rn );
nkeynes@417
  1480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1481
:}
nkeynes@359
  1482
XOR #imm, R0 {:  
nkeynes@671
  1483
    COUNT_INST(I_XORI);
nkeynes@991
  1484
    load_reg( REG_EAX, 0 );
nkeynes@991
  1485
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1486
    store_reg( REG_EAX, 0 );
nkeynes@417
  1487
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1488
:}
nkeynes@359
  1489
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1490
    COUNT_INST(I_XORB);
nkeynes@991
  1491
    load_reg( REG_EAX, 0 );
nkeynes@991
  1492
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@1292
  1493
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1494
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@1292
  1495
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1496
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1497
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1499
:}
nkeynes@361
  1500
XTRCT Rm, Rn {:
nkeynes@671
  1501
    COUNT_INST(I_XTRCT);
nkeynes@991
  1502
    load_reg( REG_EAX, Rm );
nkeynes@991
  1503
    load_reg( REG_ECX, Rn );
nkeynes@991
  1504
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1505
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1506
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1507
    store_reg( REG_ECX, Rn );
nkeynes@417
  1508
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1509
:}
nkeynes@359
  1510
nkeynes@359
  1511
/* Data move instructions */
nkeynes@359
  1512
MOV Rm, Rn {:  
nkeynes@671
  1513
    COUNT_INST(I_MOV);
nkeynes@991
  1514
    load_reg( REG_EAX, Rm );
nkeynes@991
  1515
    store_reg( REG_EAX, Rn );
nkeynes@359
  1516
:}
nkeynes@359
  1517
MOV #imm, Rn {:  
nkeynes@671
  1518
    COUNT_INST(I_MOVI);
nkeynes@995
  1519
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1520
    store_reg( REG_EAX, Rn );
nkeynes@359
  1521
:}
nkeynes@359
  1522
MOV.B Rm, @Rn {:  
nkeynes@671
  1523
    COUNT_INST(I_MOVB);
nkeynes@991
  1524
    load_reg( REG_EAX, Rn );
nkeynes@991
  1525
    load_reg( REG_EDX, Rm );
nkeynes@991
  1526
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1527
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1528
:}
nkeynes@359
  1529
MOV.B Rm, @-Rn {:  
nkeynes@671
  1530
    COUNT_INST(I_MOVB);
nkeynes@991
  1531
    load_reg( REG_EAX, Rn );
nkeynes@991
  1532
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1533
    load_reg( REG_EDX, Rm );
nkeynes@991
  1534
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1535
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1537
:}
nkeynes@359
  1538
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1539
    COUNT_INST(I_MOVB);
nkeynes@991
  1540
    load_reg( REG_EAX, 0 );
nkeynes@991
  1541
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1542
    load_reg( REG_EDX, Rm );
nkeynes@991
  1543
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1544
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1545
:}
nkeynes@359
  1546
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1547
    COUNT_INST(I_MOVB);
nkeynes@995
  1548
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1549
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1550
    load_reg( REG_EDX, 0 );
nkeynes@991
  1551
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1552
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1553
:}
nkeynes@359
  1554
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1555
    COUNT_INST(I_MOVB);
nkeynes@991
  1556
    load_reg( REG_EAX, Rn );
nkeynes@991
  1557
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1558
    load_reg( REG_EDX, 0 );
nkeynes@991
  1559
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1561
:}
nkeynes@359
  1562
MOV.B @Rm, Rn {:  
nkeynes@671
  1563
    COUNT_INST(I_MOVB);
nkeynes@991
  1564
    load_reg( REG_EAX, Rm );
nkeynes@991
  1565
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1566
    store_reg( REG_EAX, Rn );
nkeynes@417
  1567
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1568
:}
nkeynes@359
  1569
MOV.B @Rm+, Rn {:  
nkeynes@671
  1570
    COUNT_INST(I_MOVB);
nkeynes@991
  1571
    load_reg( REG_EAX, Rm );
nkeynes@991
  1572
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@939
  1573
    if( Rm != Rn ) {
nkeynes@991
  1574
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1575
    }
nkeynes@991
  1576
    store_reg( REG_EAX, Rn );
nkeynes@417
  1577
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1578
:}
nkeynes@359
  1579
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1580
    COUNT_INST(I_MOVB);
nkeynes@991
  1581
    load_reg( REG_EAX, 0 );
nkeynes@991
  1582
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1583
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1584
    store_reg( REG_EAX, Rn );
nkeynes@417
  1585
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1586
:}
nkeynes@359
  1587
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1588
    COUNT_INST(I_MOVB);
nkeynes@995
  1589
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1590
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1591
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1592
    store_reg( REG_EAX, 0 );
nkeynes@417
  1593
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1594
:}
nkeynes@359
  1595
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1596
    COUNT_INST(I_MOVB);
nkeynes@991
  1597
    load_reg( REG_EAX, Rm );
nkeynes@991
  1598
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1599
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1600
    store_reg( REG_EAX, 0 );
nkeynes@417
  1601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1602
:}
nkeynes@374
  1603
MOV.L Rm, @Rn {:
nkeynes@671
  1604
    COUNT_INST(I_MOVL);
nkeynes@991
  1605
    load_reg( REG_EAX, Rn );
nkeynes@991
  1606
    check_walign32(REG_EAX);
nkeynes@991
  1607
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1608
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1609
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1610
    JNE_label( notsq );
nkeynes@991
  1611
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1612
    load_reg( REG_EDX, Rm );
nkeynes@991
  1613
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1614
    JMP_label(end);
nkeynes@930
  1615
    JMP_TARGET(notsq);
nkeynes@991
  1616
    load_reg( REG_EDX, Rm );
nkeynes@991
  1617
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1618
    JMP_TARGET(end);
nkeynes@417
  1619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1620
:}
nkeynes@361
  1621
MOV.L Rm, @-Rn {:  
nkeynes@671
  1622
    COUNT_INST(I_MOVL);
nkeynes@991
  1623
    load_reg( REG_EAX, Rn );
nkeynes@991
  1624
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1625
    check_walign32( REG_EAX );
nkeynes@991
  1626
    load_reg( REG_EDX, Rm );
nkeynes@991
  1627
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1628
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1629
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1630
:}
nkeynes@361
  1631
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1632
    COUNT_INST(I_MOVL);
nkeynes@991
  1633
    load_reg( REG_EAX, 0 );
nkeynes@991
  1634
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1635
    check_walign32( REG_EAX );
nkeynes@991
  1636
    load_reg( REG_EDX, Rm );
nkeynes@991
  1637
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1638
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1639
:}
nkeynes@361
  1640
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1641
    COUNT_INST(I_MOVL);
nkeynes@995
  1642
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1643
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1644
    check_walign32( REG_EAX );
nkeynes@991
  1645
    load_reg( REG_EDX, 0 );
nkeynes@991
  1646
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1647
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1648
:}
nkeynes@361
  1649
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1650
    COUNT_INST(I_MOVL);
nkeynes@991
  1651
    load_reg( REG_EAX, Rn );
nkeynes@991
  1652
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1653
    check_walign32( REG_EAX );
nkeynes@991
  1654
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1655
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1656
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1657
    JNE_label( notsq );
nkeynes@991
  1658
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1659
    load_reg( REG_EDX, Rm );
nkeynes@991
  1660
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1661
    JMP_label(end);
nkeynes@930
  1662
    JMP_TARGET(notsq);
nkeynes@991
  1663
    load_reg( REG_EDX, Rm );
nkeynes@991
  1664
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1665
    JMP_TARGET(end);
nkeynes@417
  1666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1667
:}
nkeynes@361
  1668
MOV.L @Rm, Rn {:  
nkeynes@671
  1669
    COUNT_INST(I_MOVL);
nkeynes@991
  1670
    load_reg( REG_EAX, Rm );
nkeynes@991
  1671
    check_ralign32( REG_EAX );
nkeynes@991
  1672
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1673
    store_reg( REG_EAX, Rn );
nkeynes@417
  1674
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1675
:}
nkeynes@361
  1676
MOV.L @Rm+, Rn {:  
nkeynes@671
  1677
    COUNT_INST(I_MOVL);
nkeynes@991
  1678
    load_reg( REG_EAX, Rm );
nkeynes@991
  1679
    check_ralign32( REG_EAX );
nkeynes@991
  1680
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@939
  1681
    if( Rm != Rn ) {
nkeynes@991
  1682
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1683
    }
nkeynes@991
  1684
    store_reg( REG_EAX, Rn );
nkeynes@417
  1685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1686
:}
nkeynes@361
  1687
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1688
    COUNT_INST(I_MOVL);
nkeynes@991
  1689
    load_reg( REG_EAX, 0 );
nkeynes@991
  1690
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1691
    check_ralign32( REG_EAX );
nkeynes@991
  1692
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1693
    store_reg( REG_EAX, Rn );
nkeynes@417
  1694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1695
:}
nkeynes@361
  1696
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1697
    COUNT_INST(I_MOVL);
nkeynes@995
  1698
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1699
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1700
    check_ralign32( REG_EAX );
nkeynes@991
  1701
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1702
    store_reg( REG_EAX, 0 );
nkeynes@417
  1703
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1704
:}
nkeynes@361
  1705
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1706
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1707
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1708
	SLOTILLEGAL();
nkeynes@374
  1709
    } else {
nkeynes@388
  1710
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@1125
  1711
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1712
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1713
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1714
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1715
nkeynes@586
  1716
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1717
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1718
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1719
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1720
	    // behaviour though.
nkeynes@586
  1721
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1722
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1723
	} else {
nkeynes@586
  1724
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1725
	    // different virtual address than the translation was done with,
nkeynes@586
  1726
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1727
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1728
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1729
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1730
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1731
	}
nkeynes@991
  1732
	store_reg( REG_EAX, Rn );
nkeynes@374
  1733
    }
nkeynes@361
  1734
:}
nkeynes@361
  1735
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1736
    COUNT_INST(I_MOVL);
nkeynes@991
  1737
    load_reg( REG_EAX, Rm );
nkeynes@991
  1738
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1739
    check_ralign32( REG_EAX );
nkeynes@991
  1740
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1741
    store_reg( REG_EAX, Rn );
nkeynes@417
  1742
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1743
:}
nkeynes@361
  1744
MOV.W Rm, @Rn {:  
nkeynes@671
  1745
    COUNT_INST(I_MOVW);
nkeynes@991
  1746
    load_reg( REG_EAX, Rn );
nkeynes@991
  1747
    check_walign16( REG_EAX );
nkeynes@991
  1748
    load_reg( REG_EDX, Rm );
nkeynes@991
  1749
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1750
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1751
:}
nkeynes@361
  1752
MOV.W Rm, @-Rn {:  
nkeynes@671
  1753
    COUNT_INST(I_MOVW);
nkeynes@991
  1754
    load_reg( REG_EAX, Rn );
nkeynes@991
  1755
    check_walign16( REG_EAX );
nkeynes@991
  1756
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1757
    load_reg( REG_EDX, Rm );
nkeynes@991
  1758
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1759
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1760
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1761
:}
nkeynes@361
  1762
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1763
    COUNT_INST(I_MOVW);
nkeynes@991
  1764
    load_reg( REG_EAX, 0 );
nkeynes@991
  1765
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1766
    check_walign16( REG_EAX );
nkeynes@991
  1767
    load_reg( REG_EDX, Rm );
nkeynes@991
  1768
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1769
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1770
:}
nkeynes@361
  1771
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1772
    COUNT_INST(I_MOVW);
nkeynes@995
  1773
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1774
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1775
    check_walign16( REG_EAX );
nkeynes@991
  1776
    load_reg( REG_EDX, 0 );
nkeynes@991
  1777
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1778
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1779
:}
nkeynes@361
  1780
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1781
    COUNT_INST(I_MOVW);
nkeynes@991
  1782
    load_reg( REG_EAX, Rn );
nkeynes@991
  1783
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1784
    check_walign16( REG_EAX );
nkeynes@991
  1785
    load_reg( REG_EDX, 0 );
nkeynes@991
  1786
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1787
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1788
:}
nkeynes@361
  1789
MOV.W @Rm, Rn {:  
nkeynes@671
  1790
    COUNT_INST(I_MOVW);
nkeynes@991
  1791
    load_reg( REG_EAX, Rm );
nkeynes@991
  1792
    check_ralign16( REG_EAX );
nkeynes@991
  1793
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1794
    store_reg( REG_EAX, Rn );
nkeynes@417
  1795
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1796
:}
nkeynes@361
  1797
MOV.W @Rm+, Rn {:  
nkeynes@671
  1798
    COUNT_INST(I_MOVW);
nkeynes@991
  1799
    load_reg( REG_EAX, Rm );
nkeynes@991
  1800
    check_ralign16( REG_EAX );
nkeynes@991
  1801
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@939
  1802
    if( Rm != Rn ) {
nkeynes@991
  1803
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1804
    }
nkeynes@991
  1805
    store_reg( REG_EAX, Rn );
nkeynes@417
  1806
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1807
:}
nkeynes@361
  1808
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1809
    COUNT_INST(I_MOVW);
nkeynes@991
  1810
    load_reg( REG_EAX, 0 );
nkeynes@991
  1811
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1812
    check_ralign16( REG_EAX );
nkeynes@991
  1813
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1814
    store_reg( REG_EAX, Rn );
nkeynes@417
  1815
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1816
:}
nkeynes@361
  1817
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1818
    COUNT_INST(I_MOVW);
nkeynes@995
  1819
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1820
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1821
    check_ralign16( REG_EAX );
nkeynes@991
  1822
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1823
    store_reg( REG_EAX, 0 );
nkeynes@417
  1824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1825
:}
nkeynes@361
  1826
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1827
    COUNT_INST(I_MOVW);
nkeynes@374
  1828
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1829
	SLOTILLEGAL();
nkeynes@374
  1830
    } else {
nkeynes@586
  1831
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1832
	uint32_t target = pc + disp + 4;
nkeynes@1125
  1833
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1834
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1835
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1836
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1837
	} else {
nkeynes@995
  1838
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1839
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1840
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1841
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1842
	}
nkeynes@991
  1843
	store_reg( REG_EAX, Rn );
nkeynes@374
  1844
    }
nkeynes@361
  1845
:}
nkeynes@361
  1846
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1847
    COUNT_INST(I_MOVW);
nkeynes@991
  1848
    load_reg( REG_EAX, Rm );
nkeynes@991
  1849
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1850
    check_ralign16( REG_EAX );
nkeynes@991
  1851
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1852
    store_reg( REG_EAX, 0 );
nkeynes@417
  1853
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1854
:}
nkeynes@361
  1855
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1856
    COUNT_INST(I_MOVA);
nkeynes@374
  1857
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1858
	SLOTILLEGAL();
nkeynes@374
  1859
    } else {
nkeynes@995
  1860
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1861
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1862
	store_reg( REG_ECX, 0 );
nkeynes@586
  1863
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1864
    }
nkeynes@361
  1865
:}
nkeynes@361
  1866
MOVCA.L R0, @Rn {:  
nkeynes@671
  1867
    COUNT_INST(I_MOVCA);
nkeynes@991
  1868
    load_reg( REG_EAX, Rn );
nkeynes@991
  1869
    check_walign32( REG_EAX );
nkeynes@991
  1870
    load_reg( REG_EDX, 0 );
nkeynes@991
  1871
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1873
:}
nkeynes@359
  1874
nkeynes@359
  1875
/* Control transfer instructions */
nkeynes@374
  1876
BF disp {:
nkeynes@671
  1877
    COUNT_INST(I_BF);
nkeynes@374
  1878
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1879
	SLOTILLEGAL();
nkeynes@374
  1880
    } else {
nkeynes@586
  1881
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1882
	JT_label( nottaken );
nkeynes@586
  1883
	exit_block_rel(target, pc+2 );
nkeynes@380
  1884
	JMP_TARGET(nottaken);
nkeynes@408
  1885
	return 2;
nkeynes@374
  1886
    }
nkeynes@374
  1887
:}
nkeynes@374
  1888
BF/S disp {:
nkeynes@671
  1889
    COUNT_INST(I_BFS);
nkeynes@374
  1890
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1891
	SLOTILLEGAL();
nkeynes@374
  1892
    } else {
nkeynes@590
  1893
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1894
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1895
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1896
	    JT_label(nottaken);
nkeynes@991
  1897
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1898
	    JMP_TARGET(nottaken);
nkeynes@991
  1899
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1900
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1901
	    exit_block_emu(pc+2);
nkeynes@601
  1902
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1903
	    return 2;
nkeynes@601
  1904
	} else {
nkeynes@1197
  1905
	    LOAD_t();
nkeynes@601
  1906
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1907
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1908
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1909
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1910
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1911
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1912
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1913
	    
nkeynes@601
  1914
	    // not taken
nkeynes@601
  1915
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1916
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1917
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1918
	    return 4;
nkeynes@417
  1919
	}
nkeynes@374
  1920
    }
nkeynes@374
  1921
:}
nkeynes@374
  1922
BRA disp {:  
nkeynes@671
  1923
    COUNT_INST(I_BRA);
nkeynes@374
  1924
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1925
	SLOTILLEGAL();
nkeynes@374
  1926
    } else {
nkeynes@590
  1927
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1928
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1929
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1930
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1931
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1932
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1933
	    exit_block_emu(pc+2);
nkeynes@601
  1934
	    return 2;
nkeynes@601
  1935
	} else {
nkeynes@601
  1936
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1937
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1938
	    return 4;
nkeynes@601
  1939
	}
nkeynes@374
  1940
    }
nkeynes@374
  1941
:}
nkeynes@374
  1942
BRAF Rn {:  
nkeynes@671
  1943
    COUNT_INST(I_BRAF);
nkeynes@374
  1944
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1945
	SLOTILLEGAL();
nkeynes@374
  1946
    } else {
nkeynes@995
  1947
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1948
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1949
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1950
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1951
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1952
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1953
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1954
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1955
	    exit_block_emu(pc+2);
nkeynes@601
  1956
	    return 2;
nkeynes@601
  1957
	} else {
nkeynes@601
  1958
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1959
	    exit_block_newpcset(pc+4);
nkeynes@601
  1960
	    return 4;
nkeynes@601
  1961
	}
nkeynes@374
  1962
    }
nkeynes@374
  1963
:}
nkeynes@374
  1964
BSR disp {:  
nkeynes@671
  1965
    COUNT_INST(I_BSR);
nkeynes@374
  1966
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1967
	SLOTILLEGAL();
nkeynes@374
  1968
    } else {
nkeynes@995
  1969
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1970
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1971
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  1972
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1973
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1974
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1975
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1976
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  1977
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1978
	    exit_block_emu(pc+2);
nkeynes@601
  1979
	    return 2;
nkeynes@601
  1980
	} else {
nkeynes@601
  1981
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1982
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1983
	    return 4;
nkeynes@601
  1984
	}
nkeynes@374
  1985
    }
nkeynes@374
  1986
:}
nkeynes@374
  1987
BSRF Rn {:  
nkeynes@671
  1988
    COUNT_INST(I_BSRF);
nkeynes@374
  1989
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1990
	SLOTILLEGAL();
nkeynes@374
  1991
    } else {
nkeynes@995
  1992
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1993
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1994
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1995
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1996
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1997
nkeynes@601
  1998
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1999
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2000
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2001
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2002
	    exit_block_emu(pc+2);
nkeynes@601
  2003
	    return 2;
nkeynes@601
  2004
	} else {
nkeynes@601
  2005
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2006
	    exit_block_newpcset(pc+4);
nkeynes@601
  2007
	    return 4;
nkeynes@601
  2008
	}
nkeynes@374
  2009
    }
nkeynes@374
  2010
:}
nkeynes@374
  2011
BT disp {:
nkeynes@671
  2012
    COUNT_INST(I_BT);
nkeynes@374
  2013
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2014
	SLOTILLEGAL();
nkeynes@374
  2015
    } else {
nkeynes@586
  2016
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  2017
	JF_label( nottaken );
nkeynes@586
  2018
	exit_block_rel(target, pc+2 );
nkeynes@380
  2019
	JMP_TARGET(nottaken);
nkeynes@408
  2020
	return 2;
nkeynes@374
  2021
    }
nkeynes@374
  2022
:}
nkeynes@374
  2023
BT/S disp {:
nkeynes@671
  2024
    COUNT_INST(I_BTS);
nkeynes@374
  2025
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2026
	SLOTILLEGAL();
nkeynes@374
  2027
    } else {
nkeynes@590
  2028
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2029
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  2030
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  2031
	    JF_label(nottaken);
nkeynes@991
  2032
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  2033
	    JMP_TARGET(nottaken);
nkeynes@991
  2034
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  2035
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2036
	    exit_block_emu(pc+2);
nkeynes@601
  2037
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2038
	    return 2;
nkeynes@601
  2039
	} else {
nkeynes@1197
  2040
		LOAD_t();
nkeynes@991
  2041
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  2042
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  2043
nkeynes@879
  2044
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  2045
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  2046
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  2047
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2048
	    // not taken
nkeynes@601
  2049
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  2050
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  2051
	    sh4_translate_instruction(pc+2);
nkeynes@601
  2052
	    return 4;
nkeynes@417
  2053
	}
nkeynes@374
  2054
    }
nkeynes@374
  2055
:}
nkeynes@374
  2056
JMP @Rn {:  
nkeynes@671
  2057
    COUNT_INST(I_JMP);
nkeynes@374
  2058
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2059
	SLOTILLEGAL();
nkeynes@374
  2060
    } else {
nkeynes@991
  2061
	load_reg( REG_ECX, Rn );
nkeynes@995
  2062
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2063
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2064
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2065
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2066
	    exit_block_emu(pc+2);
nkeynes@601
  2067
	    return 2;
nkeynes@601
  2068
	} else {
nkeynes@601
  2069
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2070
	    exit_block_newpcset(pc+4);
nkeynes@601
  2071
	    return 4;
nkeynes@601
  2072
	}
nkeynes@374
  2073
    }
nkeynes@374
  2074
:}
nkeynes@374
  2075
JSR @Rn {:  
nkeynes@671
  2076
    COUNT_INST(I_JSR);
nkeynes@374
  2077
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2078
	SLOTILLEGAL();
nkeynes@374
  2079
    } else {
nkeynes@995
  2080
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2081
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2082
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2083
	load_reg( REG_ECX, Rn );
nkeynes@995
  2084
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  2085
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2086
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2087
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2088
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2089
	    exit_block_emu(pc+2);
nkeynes@601
  2090
	    return 2;
nkeynes@601
  2091
	} else {
nkeynes@601
  2092
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2093
	    exit_block_newpcset(pc+4);
nkeynes@601
  2094
	    return 4;
nkeynes@601
  2095
	}
nkeynes@374
  2096
    }
nkeynes@374
  2097
:}
nkeynes@374
  2098
RTE {:  
nkeynes@671
  2099
    COUNT_INST(I_RTE);
nkeynes@374
  2100
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2101
	SLOTILLEGAL();
nkeynes@374
  2102
    } else {
nkeynes@408
  2103
	check_priv();
nkeynes@995
  2104
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  2105
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  2106
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  2107
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  2108
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  2109
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2110
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2111
	sh4_x86.branch_taken = TRUE;
nkeynes@1112
  2112
    sh4_x86.sh4_mode = SH4_MODE_UNKNOWN;
nkeynes@601
  2113
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2114
	    exit_block_emu(pc+2);
nkeynes@601
  2115
	    return 2;
nkeynes@601
  2116
	} else {
nkeynes@601
  2117
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2118
	    exit_block_newpcset(pc+4);
nkeynes@601
  2119
	    return 4;
nkeynes@601
  2120
	}
nkeynes@374
  2121
    }
nkeynes@374
  2122
:}
nkeynes@374
  2123
RTS {:  
nkeynes@671
  2124
    COUNT_INST(I_RTS);
nkeynes@374
  2125
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2126
	SLOTILLEGAL();
nkeynes@374
  2127
    } else {
nkeynes@995
  2128
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  2129
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2130
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2131
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2132
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2133
	    exit_block_emu(pc+2);
nkeynes@601
  2134
	    return 2;
nkeynes@601
  2135
	} else {
nkeynes@601
  2136
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2137
	    exit_block_newpcset(pc+4);
nkeynes@601
  2138
	    return 4;
nkeynes@601
  2139
	}
nkeynes@374
  2140
    }
nkeynes@374
  2141
:}
nkeynes@374
  2142
TRAPA #imm {:  
nkeynes@671
  2143
    COUNT_INST(I_TRAPA);
nkeynes@374
  2144
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2145
	SLOTILLEGAL();
nkeynes@374
  2146
    } else {
nkeynes@995
  2147
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  2148
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  2149
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  2150
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  2151
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  2152
	exit_block_pcset(pc+2);
nkeynes@409
  2153
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2154
	return 2;
nkeynes@374
  2155
    }
nkeynes@374
  2156
:}
nkeynes@374
  2157
UNDEF {:  
nkeynes@671
  2158
    COUNT_INST(I_UNDEF);
nkeynes@374
  2159
    if( sh4_x86.in_delay_slot ) {
nkeynes@1191
  2160
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4);    
nkeynes@374
  2161
    } else {
nkeynes@1191
  2162
	exit_block_exc(EXC_ILLEGAL, pc, 2);    
nkeynes@408
  2163
	return 2;
nkeynes@374
  2164
    }
nkeynes@368
  2165
:}
nkeynes@374
  2166
nkeynes@374
  2167
CLRMAC {:  
nkeynes@671
  2168
    COUNT_INST(I_CLRMAC);
nkeynes@991
  2169
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  2170
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  2171
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2172
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2173
:}
nkeynes@374
  2174
CLRS {:
nkeynes@671
  2175
    COUNT_INST(I_CLRS);
nkeynes@374
  2176
    CLC();
nkeynes@991
  2177
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2179
:}
nkeynes@374
  2180
CLRT {:  
nkeynes@671
  2181
    COUNT_INST(I_CLRT);
nkeynes@374
  2182
    CLC();
nkeynes@374
  2183
    SETC_t();
nkeynes@417
  2184
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2185
:}
nkeynes@374
  2186
SETS {:  
nkeynes@671
  2187
    COUNT_INST(I_SETS);
nkeynes@374
  2188
    STC();
nkeynes@991
  2189
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2191
:}
nkeynes@374
  2192
SETT {:  
nkeynes@671
  2193
    COUNT_INST(I_SETT);
nkeynes@374
  2194
    STC();
nkeynes@374
  2195
    SETC_t();
nkeynes@417
  2196
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  2197
:}
nkeynes@359
  2198
nkeynes@375
  2199
/* Floating point moves */
nkeynes@375
  2200
FMOV FRm, FRn {:  
nkeynes@671
  2201
    COUNT_INST(I_FMOV1);
nkeynes@377
  2202
    check_fpuen();
nkeynes@901
  2203
    if( sh4_x86.double_size ) {
nkeynes@991
  2204
        load_dr0( REG_EAX, FRm );
nkeynes@991
  2205
        load_dr1( REG_ECX, FRm );
nkeynes@991
  2206
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2207
        store_dr1( REG_ECX, FRn );
nkeynes@901
  2208
    } else {
nkeynes@991
  2209
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  2210
        store_fr( REG_EAX, FRn );
nkeynes@901
  2211
    }
nkeynes@375
  2212
:}
nkeynes@416
  2213
FMOV FRm, @Rn {: 
nkeynes@671
  2214
    COUNT_INST(I_FMOV2);
nkeynes@586
  2215
    check_fpuen();
nkeynes@991
  2216
    load_reg( REG_EAX, Rn );
nkeynes@901
  2217
    if( sh4_x86.double_size ) {
nkeynes@991
  2218
        check_walign64( REG_EAX );
nkeynes@991
  2219
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2220
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2221
        load_reg( REG_EAX, Rn );
nkeynes@991
  2222
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2223
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2224
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2225
    } else {
nkeynes@991
  2226
        check_walign32( REG_EAX );
nkeynes@991
  2227
        load_fr( REG_EDX, FRm );
nkeynes@991
  2228
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2229
    }
nkeynes@417
  2230
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2231
:}
nkeynes@375
  2232
FMOV @Rm, FRn {:  
nkeynes@671
  2233
    COUNT_INST(I_FMOV5);
nkeynes@586
  2234
    check_fpuen();
nkeynes@991
  2235
    load_reg( REG_EAX, Rm );
nkeynes@901
  2236
    if( sh4_x86.double_size ) {
nkeynes@991
  2237
        check_ralign64( REG_EAX );
nkeynes@991
  2238
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2239
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2240
        load_reg( REG_EAX, Rm );
nkeynes@991
  2241
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2242
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2243
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2244
    } else {
nkeynes@991
  2245
        check_ralign32( REG_EAX );
nkeynes@991
  2246
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2247
        store_fr( REG_EAX, FRn );
nkeynes@901
  2248
    }
nkeynes@417
  2249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2250
:}
nkeynes@377
  2251
FMOV FRm, @-Rn {:  
nkeynes@671
  2252
    COUNT_INST(I_FMOV3);
nkeynes@586
  2253
    check_fpuen();
nkeynes@991
  2254
    load_reg( REG_EAX, Rn );
nkeynes@901
  2255
    if( sh4_x86.double_size ) {
nkeynes@991
  2256
        check_walign64( REG_EAX );
nkeynes@991
  2257
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2258
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2259
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2260
        load_reg( REG_EAX, Rn );
nkeynes@991
  2261
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2262
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2263
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2264
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2265
    } else {
nkeynes@991
  2266
        check_walign32( REG_EAX );
nkeynes@991
  2267
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2268
        load_fr( REG_EDX, FRm );
nkeynes@991
  2269
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2270
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2271
    }
nkeynes@417
  2272
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2273
:}
nkeynes@416
  2274
FMOV @Rm+, FRn {:
nkeynes@671
  2275
    COUNT_INST(I_FMOV6);
nkeynes@586
  2276
    check_fpuen();
nkeynes@991
  2277
    load_reg( REG_EAX, Rm );
nkeynes@901
  2278
    if( sh4_x86.double_size ) {
nkeynes@991
  2279
        check_ralign64( REG_EAX );
nkeynes@991
  2280
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2281
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2282
        load_reg( REG_EAX, Rm );
nkeynes@991
  2283
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2284
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2285
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2286
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2287
    } else {
nkeynes@991
  2288
        check_ralign32( REG_EAX );
nkeynes@991
  2289
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2290
        store_fr( REG_EAX, FRn );
nkeynes@991
  2291
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2292
    }
nkeynes@417
  2293
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2294
:}
nkeynes@377
  2295
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2296
    COUNT_INST(I_FMOV4);
nkeynes@586
  2297
    check_fpuen();
nkeynes@991
  2298
    load_reg( REG_EAX, Rn );
nkeynes@991
  2299
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2300
    if( sh4_x86.double_size ) {
nkeynes@991
  2301
        check_walign64( REG_EAX );
nkeynes@991
  2302
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2303
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2304
        load_reg( REG_EAX, Rn );
nkeynes@991
  2305
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2306
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2307
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2308
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2309
    } else {
nkeynes@991
  2310
        check_walign32( REG_EAX );
nkeynes@991
  2311
        load_fr( REG_EDX, FRm );
nkeynes@991
  2312
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2313
    }
nkeynes@417
  2314
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2315
:}
nkeynes@377
  2316
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2317
    COUNT_INST(I_FMOV7);
nkeynes@586
  2318
    check_fpuen();
nkeynes@991
  2319
    load_reg( REG_EAX, Rm );
nkeynes@991
  2320
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2321
    if( sh4_x86.double_size ) {
nkeynes@991
  2322
        check_ralign64( REG_EAX );
nkeynes@991
  2323
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2324
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2325
        load_reg( REG_EAX, Rm );
nkeynes@991
  2326
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2327
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2328
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2329
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2330
    } else {
nkeynes@991
  2331
        check_ralign32( REG_EAX );
nkeynes@991
  2332
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2333
        store_fr( REG_EAX, FRn );
nkeynes@901
  2334
    }
nkeynes@417
  2335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2336
:}
nkeynes@377
  2337
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2338
    COUNT_INST(I_FLDI0);
nkeynes@377
  2339
    check_fpuen();
nkeynes@901
  2340
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2341
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2342
        store_fr( REG_EAX, FRn );
nkeynes@901
  2343
    }
nkeynes@417
  2344
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2345
:}
nkeynes@377
  2346
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2347
    COUNT_INST(I_FLDI1);
nkeynes@377
  2348
    check_fpuen();
nkeynes@901
  2349
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2350
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2351
        store_fr( REG_EAX, FRn );
nkeynes@901
  2352
    }
nkeynes@377
  2353
:}
nkeynes@377
  2354
nkeynes@377
  2355
FLOAT FPUL, FRn {:  
nkeynes@671
  2356
    COUNT_INST(I_FLOAT);
nkeynes@377
  2357
    check_fpuen();
nkeynes@991
  2358
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2359
    if( sh4_x86.double_prec ) {
nkeynes@901
  2360
        pop_dr( FRn );
nkeynes@901
  2361
    } else {
nkeynes@901
  2362
        pop_fr( FRn );
nkeynes@901
  2363
    }
nkeynes@377
  2364
:}
nkeynes@377
  2365
FTRC FRm, FPUL {:  
nkeynes@671
  2366
    COUNT_INST(I_FTRC);
nkeynes@377
  2367
    check_fpuen();
nkeynes@901
  2368
    if( sh4_x86.double_prec ) {
nkeynes@901
  2369
        push_dr( FRm );
nkeynes@901
  2370
    } else {
nkeynes@901
  2371
        push_fr( FRm );
nkeynes@901
  2372
    }
nkeynes@1197
  2373
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@1197
  2374
    FILD_r32disp( REG_ECX, 0 );
nkeynes@1197
  2375
    FCOMIP_st(1);              
nkeynes@1197
  2376
    JAE_label( sat );     
nkeynes@1197
  2377
    JP_label( sat2 );       
nkeynes@995
  2378
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2379
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2380
    FCOMIP_st(1);
nkeynes@1197
  2381
    JNA_label( sat3 );
nkeynes@995
  2382
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2383
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2384
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2385
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2386
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2387
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2388
    JMP_label(end);             
nkeynes@388
  2389
nkeynes@388
  2390
    JMP_TARGET(sat);
nkeynes@388
  2391
    JMP_TARGET(sat2);
nkeynes@1197
  2392
    JMP_TARGET(sat3);
nkeynes@991
  2393
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2394
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2395
    FPOP_st();
nkeynes@388
  2396
    JMP_TARGET(end);
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2398
:}
nkeynes@377
  2399
FLDS FRm, FPUL {:  
nkeynes@671
  2400
    COUNT_INST(I_FLDS);
nkeynes@377
  2401
    check_fpuen();
nkeynes@991
  2402
    load_fr( REG_EAX, FRm );
nkeynes@995
  2403
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2404
:}
nkeynes@377
  2405
FSTS FPUL, FRn {:  
nkeynes@671
  2406
    COUNT_INST(I_FSTS);
nkeynes@377
  2407
    check_fpuen();
nkeynes@995
  2408
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2409
    store_fr( REG_EAX, FRn );
nkeynes@377
  2410
:}
nkeynes@377
  2411
FCNVDS FRm, FPUL {:  
nkeynes@671
  2412
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2413
    check_fpuen();
nkeynes@901
  2414
    if( sh4_x86.double_prec ) {
nkeynes@901
  2415
        push_dr( FRm );
nkeynes@901
  2416
        pop_fpul();
nkeynes@901
  2417
    }
nkeynes@377
  2418
:}
nkeynes@377
  2419
FCNVSD FPUL, FRn {:  
nkeynes@671
  2420
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2421
    check_fpuen();
nkeynes@901
  2422
    if( sh4_x86.double_prec ) {
nkeynes@901
  2423
        push_fpul();
nkeynes@901
  2424
        pop_dr( FRn );
nkeynes@901
  2425
    }
nkeynes@377
  2426
:}
nkeynes@375
  2427
nkeynes@359
  2428
/* Floating point instructions */
nkeynes@374
  2429
FABS FRn {:  
nkeynes@671
  2430
    COUNT_INST(I_FABS);
nkeynes@377
  2431
    check_fpuen();
nkeynes@901
  2432
    if( sh4_x86.double_prec ) {
nkeynes@901
  2433
        push_dr(FRn);
nkeynes@901
  2434
        FABS_st0();
nkeynes@901
  2435
        pop_dr(FRn);
nkeynes@901
  2436
    } else {
nkeynes@901
  2437
        push_fr(FRn);
nkeynes@901
  2438
        FABS_st0();
nkeynes@901
  2439
        pop_fr(FRn);
nkeynes@901
  2440
    }
nkeynes@374
  2441
:}
nkeynes@377
  2442
FADD FRm, FRn {:  
nkeynes@671
  2443
    COUNT_INST(I_FADD);
nkeynes@377
  2444
    check_fpuen();
nkeynes@901
  2445
    if( sh4_x86.double_prec ) {
nkeynes@901
  2446
        push_dr(FRm);
nkeynes@901
  2447
        push_dr(FRn);
nkeynes@901
  2448
        FADDP_st(1);
nkeynes@901
  2449
        pop_dr(FRn);
nkeynes@901
  2450
    } else {
nkeynes@901
  2451
        push_fr(FRm);
nkeynes@901
  2452
        push_fr(FRn);
nkeynes@901
  2453
        FADDP_st(1);
nkeynes@901
  2454
        pop_fr(FRn);
nkeynes@901
  2455
    }
nkeynes@375
  2456
:}
nkeynes@377
  2457
FDIV FRm, FRn {:  
nkeynes@671
  2458
    COUNT_INST(I_FDIV);
nkeynes@377
  2459
    check_fpuen();
nkeynes@901
  2460
    if( sh4_x86.double_prec ) {
nkeynes@901
  2461
        push_dr(FRn);
nkeynes@901
  2462
        push_dr(FRm);
nkeynes@901
  2463
        FDIVP_st(1);
nkeynes@901
  2464
        pop_dr(FRn);
nkeynes@901
  2465
    } else {
nkeynes@901
  2466
        push_fr(FRn);
nkeynes@901
  2467
        push_fr(FRm);
nkeynes@901
  2468
        FDIVP_st(1);
nkeynes@901
  2469
        pop_fr(FRn);
nkeynes@901
  2470
    }
nkeynes@375
  2471
:}
nkeynes@375
  2472
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2473
    COUNT_INST(I_FMAC);
nkeynes@377
  2474
    check_fpuen();
nkeynes@901
  2475
    if( sh4_x86.double_prec ) {
nkeynes@901
  2476
        push_dr( 0 );
nkeynes@901
  2477
        push_dr( FRm );
nkeynes@901
  2478
        FMULP_st(1);
nkeynes@901
  2479
        push_dr( FRn );
nkeynes@901
  2480
        FADDP_st(1);
nkeynes@901
  2481
        pop_dr( FRn );
nkeynes@901
  2482
    } else {
nkeynes@901
  2483
        push_fr( 0 );
nkeynes@901
  2484
        push_fr( FRm );
nkeynes@901
  2485
        FMULP_st(1);
nkeynes@901
  2486
        push_fr( FRn );
nkeynes@901
  2487
        FADDP_st(1);
nkeynes@901
  2488
        pop_fr( FRn );
nkeynes@901
  2489
    }
nkeynes@375
  2490
:}
nkeynes@375
  2491
nkeynes@377
  2492
FMUL FRm, FRn {:  
nkeynes@671
  2493
    COUNT_INST(I_FMUL);
nkeynes@377
  2494
    check_fpuen();
nkeynes@901
  2495
    if( sh4_x86.double_prec ) {
nkeynes@901
  2496
        push_dr(FRm);
nkeynes@901
  2497
        push_dr(FRn);
nkeynes@901
  2498
        FMULP_st(1);
nkeynes@901
  2499
        pop_dr(FRn);
nkeynes@901
  2500
    } else {
nkeynes@901
  2501
        push_fr(FRm);
nkeynes@901
  2502
        push_fr(FRn);
nkeynes@901
  2503
        FMULP_st(1);
nkeynes@901
  2504
        pop_fr(FRn);
nkeynes@901
  2505
    }
nkeynes@377
  2506
:}
nkeynes@377
  2507
FNEG FRn {:  
nkeynes@671
  2508
    COUNT_INST(I_FNEG);
nkeynes@377
  2509
    check_fpuen();
nkeynes@901
  2510
    if( sh4_x86.double_prec ) {
nkeynes@901
  2511
        push_dr(FRn);
nkeynes@901
  2512
        FCHS_st0();
nkeynes@901
  2513
        pop_dr(FRn);
nkeynes@901
  2514
    } else {
nkeynes@901
  2515
        push_fr(FRn);
nkeynes@901
  2516
        FCHS_st0();
nkeynes@901
  2517
        pop_fr(FRn);
nkeynes@901
  2518
    }
nkeynes@377
  2519
:}
nkeynes@377
  2520
FSRRA FRn {:  
nkeynes@671
  2521
    COUNT_INST(I_FSRRA);
nkeynes@377
  2522
    check_fpuen();
nkeynes@901
  2523
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2524
        FLD1_st0();
nkeynes@901
  2525
        push_fr(FRn);
nkeynes@901
  2526
        FSQRT_st0();
nkeynes@901
  2527
        FDIVP_st(1);
nkeynes@901
  2528
        pop_fr(FRn);
nkeynes@901
  2529
    }
nkeynes@377
  2530
:}
nkeynes@377
  2531
FSQRT FRn {:  
nkeynes@671
  2532
    COUNT_INST(I_FSQRT);
nkeynes@377
  2533
    check_fpuen();
nkeynes@901
  2534
    if( sh4_x86.double_prec ) {
nkeynes@901
  2535
        push_dr(FRn);
nkeynes@901
  2536
        FSQRT_st0();
nkeynes@901
  2537
        pop_dr(FRn);
nkeynes@901
  2538
    } else {
nkeynes@901
  2539
        push_fr(FRn);
nkeynes@901
  2540
        FSQRT_st0();
nkeynes@901
  2541
        pop_fr(FRn);
nkeynes@901
  2542
    }
nkeynes@377
  2543
:}
nkeynes@377
  2544
FSUB FRm, FRn {:  
nkeynes@671
  2545
    COUNT_INST(I_FSUB);
nkeynes@377
  2546
    check_fpuen();
nkeynes@901
  2547
    if( sh4_x86.double_prec ) {
nkeynes@901
  2548
        push_dr(FRn);
nkeynes@901
  2549
        push_dr(FRm);
nkeynes@901
  2550
        FSUBP_st(1);
nkeynes@901
  2551
        pop_dr(FRn);
nkeynes@901
  2552
    } else {
nkeynes@901
  2553
        push_fr(FRn);
nkeynes@901
  2554
        push_fr(FRm);
nkeynes@901
  2555
        FSUBP_st(1);
nkeynes@901
  2556
        pop_fr(FRn);
nkeynes@901
  2557
    }
nkeynes@377
  2558
:}
nkeynes@377
  2559
nkeynes@377
  2560
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2561
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2562
    check_fpuen();
nkeynes@901
  2563
    if( sh4_x86.double_prec ) {
nkeynes@901
  2564
        push_dr(FRm);
nkeynes@901
  2565
        push_dr(FRn);
nkeynes@901
  2566
    } else {
nkeynes@901
  2567
        push_fr(FRm);
nkeynes@901
  2568
        push_fr(FRn);
nkeynes@901
  2569
    }
nkeynes@1197
  2570
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@1197
  2571
    XORL_r32_r32(REG_EDX, REG_EDX);
nkeynes@377
  2572
    FCOMIP_st(1);
nkeynes@1197
  2573
    SETCCB_cc_r8(X86_COND_NP, REG_DL);
nkeynes@1197
  2574
    CMOVCCL_cc_r32_r32(X86_COND_E, REG_EDX, REG_EAX);
nkeynes@1197
  2575
    MOVL_r32_rbpdisp(REG_EAX, R_T);
nkeynes@377
  2576
    FPOP_st();
nkeynes@1197
  2577
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2578
:}
nkeynes@377
  2579
FCMP/GT FRm, FRn {:  
nkeynes@671
  2580
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2581
    check_fpuen();
nkeynes@901
  2582
    if( sh4_x86.double_prec ) {
nkeynes@901
  2583
        push_dr(FRm);
nkeynes@901
  2584
        push_dr(FRn);
nkeynes@901
  2585
    } else {
nkeynes@901
  2586
        push_fr(FRm);
nkeynes@901
  2587
        push_fr(FRn);
nkeynes@901
  2588
    }
nkeynes@377
  2589
    FCOMIP_st(1);
nkeynes@377
  2590
    SETA_t();
nkeynes@377
  2591
    FPOP_st();
nkeynes@901
  2592
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2593
:}
nkeynes@377
  2594
nkeynes@377
  2595
FSCA FPUL, FRn {:  
nkeynes@671
  2596
    COUNT_INST(I_FSCA);
nkeynes@377
  2597
    check_fpuen();
nkeynes@901
  2598
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2599
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2600
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2601
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2602
    }
nkeynes@417
  2603
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2604
:}
nkeynes@377
  2605
FIPR FVm, FVn {:  
nkeynes@671
  2606
    COUNT_INST(I_FIPR);
nkeynes@377
  2607
    check_fpuen();
nkeynes@901
  2608
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2609
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2610
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2611
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2612
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2613
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2614
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2615
        } else {
nkeynes@904
  2616
            push_fr( FVm<<2 );
nkeynes@903
  2617
            push_fr( FVn<<2 );
nkeynes@903
  2618
            FMULP_st(1);
nkeynes@903
  2619
            push_fr( (FVm<<2)+1);
nkeynes@903
  2620
            push_fr( (FVn<<2)+1);
nkeynes@903
  2621
            FMULP_st(1);
nkeynes@903
  2622
            FADDP_st(1);
nkeynes@903
  2623
            push_fr( (FVm<<2)+2);
nkeynes@903
  2624
            push_fr( (FVn<<2)+2);
nkeynes@903
  2625
            FMULP_st(1);
nkeynes@903
  2626
            FADDP_st(1);
nkeynes@903
  2627
            push_fr( (FVm<<2)+3);
nkeynes@903
  2628
            push_fr( (FVn<<2)+3);
nkeynes@903
  2629
            FMULP_st(1);
nkeynes@903
  2630
            FADDP_st(1);
nkeynes@903
  2631
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2632
        }
nkeynes@901
  2633
    }
nkeynes@377
  2634
:}
nkeynes@377
  2635
FTRV XMTRX, FVn {:  
nkeynes@671
  2636
    COUNT_INST(I_FTRV);
nkeynes@377
  2637
    check_fpuen();
nkeynes@901
  2638
    if( sh4_x86.double_prec == 0 ) {
nkeynes@1194
  2639
        if( sh4_x86.sse3_enabled && sh4_x86.begin_callback == NULL ) {
nkeynes@1194
  2640
        	/* FIXME: For now, disable this inlining when we're running in shadow mode -
nkeynes@1194
  2641
        	 * it gives slightly different results from the emu core. Need to
nkeynes@1194
  2642
        	 * fix the precision so both give the right results.
nkeynes@1194
  2643
        	 */
nkeynes@991
  2644
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2645
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2646
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2647
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2648
nkeynes@991
  2649
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2650
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2651
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2652
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2653
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2654
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2655
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2656
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2657
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2658
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2659
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2660
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2661
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2662
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2663
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2664
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2665
        } else {
nkeynes@991
  2666
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@995
  2667
            CALL1_ptr_r32( sh4_ftrv, REG_EAX );
nkeynes@903
  2668
        }
nkeynes@901
  2669
    }
nkeynes@417
  2670
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2671
:}