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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 855:b937948d79d9
prev833:1ea87e0221f8
next929:fd8cb0c82f5f
author nkeynes
date Wed Sep 10 02:03:20 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Initial impl of the alternate PVR DMA channel
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "sh4/sh4.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "pvr2/pvr2.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static uint32_t asic_run_slice( uint32_t nanosecs );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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        NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 60
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#define G2_BIT4_TICKS 160
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#define G2_BIT0_ON_TICKS 120
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#define G2_BIT0_OFF_TICKS 420
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struct asic_g2_state {
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    int bit5_off_timer;
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    int bit4_on_timer;
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    int bit4_off_timer;
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    int bit0_on_timer;
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    int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static uint32_t asic_run_slice( uint32_t nanosecs )
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{
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    g2_update_fifo_status(nanosecs);
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    if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit5_off_timer = -1;
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    } else {
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        g2_state.bit5_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit4_off_timer = -1;
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    } else {
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        g2_state.bit4_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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        g2_state.bit4_on_timer = -1;
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    } else {
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        g2_state.bit4_on_timer -= nanosecs;
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    }
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    if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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        g2_state.bit0_off_timer = -1;
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    } else {
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        g2_state.bit0_off_timer -= nanosecs;
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    }
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    if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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        g2_state.bit0_on_timer = -1;
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    } else {
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        g2_state.bit0_on_timer -= nanosecs;
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    }
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    return nanosecs;
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}
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0xFF, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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        return 1;
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    else
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        return 0;
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}
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/**
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 * Setup the timers for the 3 FIFO status bits following a write through the G2
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 * bus from the SH4 side. The timing is roughly as follows: (times are
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 * approximate based on software readings - I wouldn't take this as gospel but
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 * it seems to be enough to fool most programs). 
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 *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
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 *   40ns: Bit 5 goes low and bit 4 goes high
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 *  120ns: Bit 4 goes low, bit 0 goes high
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 *  240ns: Bit 0 goes low.
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 *
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 * Additional writes while the FIFO is in operation extend the time that the
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 * bits remain high as one might expect, without altering the time at which
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 * they initially go high.
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 */
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void asic_g2_write_word()
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{
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    if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    } else {
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        g2_state.bit5_off_timer += G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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    } else {
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        g2_state.bit4_off_timer += G2_BIT4_TICKS;
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    }
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    if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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    }
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    if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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        g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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        g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_update_fifo_status( uint32_t nanos )
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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        val = val & (~0x20);
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        g2_state.bit5_off_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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        val = val | 0x10;
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        g2_state.bit4_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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        val = val & (~0x10);
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        g2_state.bit4_off_timer = -1;
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    } 
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    if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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        val = val | 0x01;
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        g2_state.bit0_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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        val = val & (~0x01);
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        g2_state.bit0_off_timer = -1;
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    } 
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    MMIO_WRITE( ASIC, G2STATUS, val );
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    return val;
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}   
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static int g2_read_status() {
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    return g2_update_fifo_status( sh4r.slice_cycle );
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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    if( event >= 64 ) { /* Third word */
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        asic_event( EVENT_CASCADE2 );
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    } else if( event >= 32 ) { /* Second word */
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        asic_event( EVENT_CASCADE1 );
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    }
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    if( result == 0 ) {
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        /* clear cascades if necessary */
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        if( event >= 64 ) {
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            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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        } else if( event >= 32 ) {
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            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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        }
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    }
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<12; i+=4 ) {
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        bits = MMIO_READ( ASIC, PIRQ0 + i );
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        setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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        setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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        setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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        intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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        intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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        intc_clear_interrupt( INT_IRQ9 );
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}
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void asic_event_mask_changed( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<12; i+=4 ) {
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        bits = MMIO_READ( ASIC, PIRQ0 + i );
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        setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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        setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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        setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 ) 
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        intc_clear_interrupt( INT_IRQ13 );
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    else
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        intc_raise_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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        intc_clear_interrupt( INT_IRQ11 );
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    else
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        intc_raise_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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        intc_clear_interrupt( INT_IRQ9 );
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    else
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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{
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    uint32_t offset = channel << 5;
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    if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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        if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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            uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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            uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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            uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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            uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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            // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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            unsigned char buf[length];
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            if( dir == 0 ) { /* SH4 to device */
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                mem_copy_from_sh4( buf, sh4addr, length );
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                mem_copy_to_sh4( extaddr, buf, length );
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            } else { /* Device to SH4 */
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                mem_copy_from_sh4( buf, extaddr, length );
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                mem_copy_to_sh4( sh4addr, buf, length );
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            }
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            MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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            asic_event( EVENT_G2_DMA0 + channel );
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        } else {
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            MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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        }
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    }
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   313
}
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void asic_ide_dma_transfer( )
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{	
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    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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        if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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            MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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            uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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            uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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            // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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   324
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            uint32_t xfer = ide_read_data_dma( addr, length );
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            MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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            MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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            asic_event( EVENT_IDE_DMA );            
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        } else { /* 0 */
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   330
            MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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        }
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    }
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}
nkeynes@155
   334
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void pvr_dma_transfer( )
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   336
{
nkeynes@325
   337
    sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
nkeynes@325
   338
    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@430
   339
    unsigned char *data = alloca( count );
nkeynes@325
   340
    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@325
   341
    if( rcount != count )
nkeynes@736
   342
        WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@736
   343
nkeynes@325
   344
    pvr2_dma_write( destaddr, data, rcount );
nkeynes@736
   345
nkeynes@325
   346
    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@325
   347
    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@325
   348
    if( destaddr & 0x01000000 ) { /* Write to texture RAM */
nkeynes@736
   349
        MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
nkeynes@325
   350
    }
nkeynes@325
   351
    asic_event( EVENT_PVR_DMA );
nkeynes@325
   352
}
nkeynes@155
   353
nkeynes@855
   354
void pvr_dma2_transfer()
nkeynes@855
   355
{
nkeynes@855
   356
    if( MMIO_READ( EXTDMA, PVRDMA2CTL2 ) == 1 ) {
nkeynes@855
   357
        if( MMIO_READ( EXTDMA, PVRDMA2CTL1 ) == 1 ) {
nkeynes@855
   358
            sh4addr_t extaddr = MMIO_READ( EXTDMA, PVRDMA2EXT );
nkeynes@855
   359
            sh4addr_t sh4addr = MMIO_READ( EXTDMA, PVRDMA2SH4 );
nkeynes@855
   360
            int dir = MMIO_READ( EXTDMA, PVRDMA2DIR );
nkeynes@855
   361
            uint32_t length = MMIO_READ( EXTDMA, PVRDMA2SIZ );
nkeynes@855
   362
            unsigned char buf[length];
nkeynes@855
   363
            if( dir == 0 ) { /* SH4 to PVR */
nkeynes@855
   364
                mem_copy_from_sh4( buf, sh4addr, length );
nkeynes@855
   365
                mem_copy_to_sh4( extaddr, buf, length );
nkeynes@855
   366
            } else { /* PVR to SH4 */
nkeynes@855
   367
                mem_copy_from_sh4( buf, extaddr, length );
nkeynes@855
   368
                mem_copy_to_sh4( sh4addr, buf, length );
nkeynes@855
   369
            }
nkeynes@855
   370
            MMIO_WRITE( EXTDMA, PVRDMA2CTL2, 0 );
nkeynes@855
   371
            asic_event( EVENT_PVR_DMA2 );
nkeynes@855
   372
        }
nkeynes@855
   373
    }
nkeynes@855
   374
}
nkeynes@855
   375
nkeynes@728
   376
void sort_dma_transfer( )
nkeynes@728
   377
{
nkeynes@728
   378
    sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
nkeynes@728
   379
    sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
nkeynes@728
   380
    int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
nkeynes@753
   381
    int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
nkeynes@753
   382
    int count = 1;
nkeynes@736
   383
nkeynes@753
   384
    uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
nkeynes@753
   385
    uint16_t *table16 = (uint16_t *)table32;
nkeynes@753
   386
    uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
nkeynes@753
   387
    while(1) {
nkeynes@753
   388
        next &= 0x07FFFFFF;
nkeynes@753
   389
        if( next == 1 ) {
nkeynes@753
   390
            next = table_size ? (*table32++) : (uint32_t)(*table16++);
nkeynes@753
   391
            count++;
nkeynes@753
   392
            continue;
nkeynes@753
   393
        } else if( next == 2 ) {
nkeynes@753
   394
            asic_event( EVENT_SORT_DMA );
nkeynes@753
   395
            break;
nkeynes@753
   396
        } 
nkeynes@753
   397
        uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
nkeynes@753
   398
        if( data == NULL ) {
nkeynes@753
   399
            break;
nkeynes@753
   400
        }
nkeynes@753
   401
nkeynes@753
   402
        uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
nkeynes@753
   403
        if( poly == NULL ) {
nkeynes@753
   404
            asic_event( EVENT_SORT_DMA_ERR );
nkeynes@753
   405
            break;
nkeynes@753
   406
        }
nkeynes@753
   407
        uint32_t size = poly[6] & 0xFF;
nkeynes@753
   408
        if( size == 0 ) {
nkeynes@753
   409
            size = 0x100;
nkeynes@753
   410
        }
nkeynes@753
   411
        next = poly[7];
nkeynes@753
   412
        pvr2_ta_write( (unsigned char *)data, size<<5 );
nkeynes@753
   413
    }
nkeynes@753
   414
nkeynes@753
   415
    MMIO_WRITE( ASIC, SORTDMACNT, count );
nkeynes@753
   416
    MMIO_WRITE( ASIC, SORTDMACTL, 0 );
nkeynes@728
   417
}
nkeynes@728
   418
nkeynes@1
   419
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
nkeynes@1
   420
{
nkeynes@1
   421
    switch( reg ) {
nkeynes@125
   422
    case PIRQ1:
nkeynes@736
   423
        break; /* Treat this as read-only for the moment */
nkeynes@56
   424
    case PIRQ0:
nkeynes@736
   425
        val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
nkeynes@736
   426
        MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
nkeynes@736
   427
        asic_check_cleared_events();
nkeynes@736
   428
        break;
nkeynes@56
   429
    case PIRQ2:
nkeynes@736
   430
        /* Clear any events */
nkeynes@736
   431
        val = MMIO_READ(ASIC, reg)&(~val);
nkeynes@736
   432
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   433
        if( val == 0 ) { /* all clear - clear the cascade bit */
nkeynes@736
   434
            MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
nkeynes@736
   435
        }
nkeynes@736
   436
        asic_check_cleared_events();
nkeynes@736
   437
        break;
nkeynes@594
   438
    case IRQA0:
nkeynes@594
   439
    case IRQA1:
nkeynes@594
   440
    case IRQA2:
nkeynes@594
   441
    case IRQB0:
nkeynes@594
   442
    case IRQB1:
nkeynes@594
   443
    case IRQB2:
nkeynes@594
   444
    case IRQC0:
nkeynes@594
   445
    case IRQC1:
nkeynes@594
   446
    case IRQC2:
nkeynes@736
   447
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   448
        asic_event_mask_changed();
nkeynes@736
   449
        break;
nkeynes@244
   450
    case SYSRESET:
nkeynes@736
   451
        if( val == 0x7611 ) {
nkeynes@736
   452
            dreamcast_reset();
nkeynes@736
   453
        } else {
nkeynes@736
   454
            WARN( "Unknown value %08X written to SYSRESET port", val );
nkeynes@736
   455
        }
nkeynes@736
   456
        break;
nkeynes@56
   457
    case MAPLE_STATE:
nkeynes@736
   458
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   459
        if( val & 1 ) {
nkeynes@736
   460
            uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@736
   461
            maple_handle_buffer( maple_addr );
nkeynes@736
   462
            MMIO_WRITE( ASIC, reg, 0 );
nkeynes@736
   463
        }
nkeynes@736
   464
        break;
nkeynes@325
   465
    case PVRDMADEST:
nkeynes@736
   466
        MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
nkeynes@736
   467
        break;
nkeynes@325
   468
    case PVRDMACNT: 
nkeynes@736
   469
        MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
nkeynes@736
   470
        break;
nkeynes@56
   471
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@736
   472
        val = val & 0x01;
nkeynes@736
   473
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   474
        if( val == 1 ) {
nkeynes@736
   475
            pvr_dma_transfer();
nkeynes@736
   476
        }
nkeynes@736
   477
        break;
nkeynes@728
   478
    case SORTDMATBL: case SORTDMADATA:
nkeynes@728
   479
        MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
nkeynes@728
   480
        break;
nkeynes@753
   481
    case SORTDMATSIZ: case SORTDMAASIZ:
nkeynes@728
   482
        MMIO_WRITE( ASIC, reg, (val & 1) );
nkeynes@728
   483
        break;
nkeynes@728
   484
    case SORTDMACTL:
nkeynes@728
   485
        val = val & 1;
nkeynes@728
   486
        MMIO_WRITE( ASIC, reg, val );
nkeynes@728
   487
        if( val == 1 ) {
nkeynes@728
   488
            sort_dma_transfer();
nkeynes@728
   489
        }
nkeynes@728
   490
        break;
nkeynes@325
   491
    case MAPLE_DMA:
nkeynes@736
   492
        MMIO_WRITE( ASIC, reg, val );
nkeynes@736
   493
        break;
nkeynes@56
   494
    default:
nkeynes@736
   495
        MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   496
    }
nkeynes@1
   497
}
nkeynes@1
   498
nkeynes@1
   499
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   500
{
nkeynes@1
   501
    int32_t val;
nkeynes@1
   502
    switch( reg ) {
nkeynes@94
   503
    case PIRQ0:
nkeynes@94
   504
    case PIRQ1:
nkeynes@94
   505
    case PIRQ2:
nkeynes@94
   506
    case IRQA0:
nkeynes@94
   507
    case IRQA1:
nkeynes@94
   508
    case IRQA2:
nkeynes@94
   509
    case IRQB0:
nkeynes@94
   510
    case IRQB1:
nkeynes@94
   511
    case IRQB2:
nkeynes@94
   512
    case IRQC0:
nkeynes@94
   513
    case IRQC1:
nkeynes@94
   514
    case IRQC2:
nkeynes@158
   515
    case MAPLE_STATE:
nkeynes@736
   516
        val = MMIO_READ(ASIC, reg);
nkeynes@736
   517
        return val;            
nkeynes@94
   518
    case G2STATUS:
nkeynes@736
   519
        return g2_read_status();
nkeynes@94
   520
    default:
nkeynes@736
   521
        val = MMIO_READ(ASIC, reg);
nkeynes@736
   522
        return val;
nkeynes@1
   523
    }
nkeynes@736
   524
nkeynes@1
   525
}
nkeynes@1
   526
nkeynes@1
   527
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   528
{
nkeynes@244
   529
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@736
   530
        return; /* disabled */
nkeynes@244
   531
    }
nkeynes@244
   532
nkeynes@2
   533
    switch( reg ) {
nkeynes@125
   534
    case IDEALTSTATUS: /* Device control */
nkeynes@736
   535
        ide_write_control( val );
nkeynes@736
   536
        break;
nkeynes@125
   537
    case IDEDATA:
nkeynes@736
   538
        ide_write_data_pio( val );
nkeynes@736
   539
        break;
nkeynes@125
   540
    case IDEFEAT:
nkeynes@736
   541
        if( ide_can_write_regs() )
nkeynes@736
   542
            idereg.feature = (uint8_t)val;
nkeynes@736
   543
        break;
nkeynes@125
   544
    case IDECOUNT:
nkeynes@736
   545
        if( ide_can_write_regs() )
nkeynes@736
   546
            idereg.count = (uint8_t)val;
nkeynes@736
   547
        break;
nkeynes@125
   548
    case IDELBA0:
nkeynes@736
   549
        if( ide_can_write_regs() )
nkeynes@736
   550
            idereg.lba0 = (uint8_t)val;
nkeynes@736
   551
        break;
nkeynes@125
   552
    case IDELBA1:
nkeynes@736
   553
        if( ide_can_write_regs() )
nkeynes@736
   554
            idereg.lba1 = (uint8_t)val;
nkeynes@736
   555
        break;
nkeynes@125
   556
    case IDELBA2:
nkeynes@736
   557
        if( ide_can_write_regs() )
nkeynes@736
   558
            idereg.lba2 = (uint8_t)val;
nkeynes@736
   559
        break;
nkeynes@125
   560
    case IDEDEV:
nkeynes@736
   561
        if( ide_can_write_regs() )
nkeynes@736
   562
            idereg.device = (uint8_t)val;
nkeynes@736
   563
        break;
nkeynes@125
   564
    case IDECMD:
nkeynes@736
   565
        if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@736
   566
            ide_write_command( (uint8_t)val );
nkeynes@736
   567
        }
nkeynes@736
   568
        break;
nkeynes@334
   569
    case IDEDMASH4:
nkeynes@736
   570
        MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
nkeynes@736
   571
        break;
nkeynes@334
   572
    case IDEDMASIZ:
nkeynes@736
   573
        MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
nkeynes@736
   574
        break;
nkeynes@549
   575
    case IDEDMADIR:
nkeynes@736
   576
        MMIO_WRITE( EXTDMA, reg, val & 1 );
nkeynes@736
   577
        break;
nkeynes@125
   578
    case IDEDMACTL1:
nkeynes@125
   579
    case IDEDMACTL2:
nkeynes@736
   580
        MMIO_WRITE( EXTDMA, reg, val & 0x01 );
nkeynes@736
   581
        asic_ide_dma_transfer( );
nkeynes@736
   582
        break;
nkeynes@244
   583
    case IDEACTIVATE:
nkeynes@736
   584
        if( val == 0x001FFFFF ) {
nkeynes@736
   585
            idereg.interface_enabled = TRUE;
nkeynes@736
   586
            /* Conventional wisdom says that this is necessary but not
nkeynes@736
   587
             * sufficient to enable the IDE interface.
nkeynes@736
   588
             */
nkeynes@736
   589
        } else if( val == 0x000042FE ) {
nkeynes@736
   590
            idereg.interface_enabled = FALSE;
nkeynes@736
   591
        }
nkeynes@736
   592
        break;
nkeynes@549
   593
    case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
nkeynes@549
   594
    case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
nkeynes@549
   595
    case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
nkeynes@549
   596
    case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
nkeynes@736
   597
        MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
nkeynes@736
   598
        break;
nkeynes@549
   599
    case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
nkeynes@736
   600
        MMIO_WRITE( EXTDMA, reg, val & 0x07 );
nkeynes@736
   601
        break;
nkeynes@549
   602
    case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
nkeynes@736
   603
        MMIO_WRITE( EXTDMA, reg, val & 0x01 );
nkeynes@736
   604
        break;
nkeynes@302
   605
    case G2DMA0CTL1:
nkeynes@302
   606
    case G2DMA0CTL2:
nkeynes@736
   607
        MMIO_WRITE( EXTDMA, reg, val & 1);
nkeynes@736
   608
        g2_dma_transfer( 0 );
nkeynes@736
   609
        break;
nkeynes@302
   610
    case G2DMA0STOP:
nkeynes@736
   611
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   612
        break;
nkeynes@302
   613
    case G2DMA1CTL1:
nkeynes@302
   614
    case G2DMA1CTL2:
nkeynes@736
   615
        MMIO_WRITE( EXTDMA, reg, val & 1);
nkeynes@736
   616
        g2_dma_transfer( 1 );
nkeynes@736
   617
        break;
nkeynes@279
   618
nkeynes@302
   619
    case G2DMA1STOP:
nkeynes@736
   620
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   621
        break;
nkeynes@302
   622
    case G2DMA2CTL1:
nkeynes@302
   623
    case G2DMA2CTL2:
nkeynes@736
   624
        MMIO_WRITE( EXTDMA, reg, val &1 );
nkeynes@736
   625
        g2_dma_transfer( 2 );
nkeynes@736
   626
        break;
nkeynes@302
   627
    case G2DMA2STOP:
nkeynes@736
   628
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   629
        break;
nkeynes@302
   630
    case G2DMA3CTL1:
nkeynes@302
   631
    case G2DMA3CTL2:
nkeynes@736
   632
        MMIO_WRITE( EXTDMA, reg, val &1 );
nkeynes@736
   633
        g2_dma_transfer( 3 );
nkeynes@736
   634
        break;
nkeynes@302
   635
    case G2DMA3STOP:
nkeynes@736
   636
        MMIO_WRITE( EXTDMA, reg, val & 0x37 );
nkeynes@736
   637
        break;
nkeynes@279
   638
    case PVRDMA2CTL1:
nkeynes@279
   639
    case PVRDMA2CTL2:
nkeynes@855
   640
        MMIO_WRITE( EXTDMA, reg, val & 1 );
nkeynes@855
   641
        pvr_dma2_transfer();
nkeynes@736
   642
        break;
nkeynes@125
   643
    default:
nkeynes@736
   644
        MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   645
    }
nkeynes@1
   646
}
nkeynes@1
   647
nkeynes@1
   648
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   649
{
nkeynes@56
   650
    uint32_t val;
nkeynes@244
   651
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@736
   652
        return 0xFFFFFFFF; /* disabled */
nkeynes@244
   653
    }
nkeynes@244
   654
nkeynes@1
   655
    switch( reg ) {
nkeynes@158
   656
    case IDEALTSTATUS: 
nkeynes@736
   657
        val = idereg.status;
nkeynes@736
   658
        return val;
nkeynes@158
   659
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   660
    case IDEFEAT: return idereg.error;
nkeynes@158
   661
    case IDECOUNT:return idereg.count;
nkeynes@342
   662
    case IDELBA0: return ide_get_drive_status();
nkeynes@158
   663
    case IDELBA1: return idereg.lba1;
nkeynes@158
   664
    case IDELBA2: return idereg.lba2;
nkeynes@158
   665
    case IDEDEV: return idereg.device;
nkeynes@158
   666
    case IDECMD:
nkeynes@736
   667
        val = ide_read_status();
nkeynes@736
   668
        return val;
nkeynes@158
   669
    default:
nkeynes@736
   670
        val = MMIO_READ( EXTDMA, reg );
nkeynes@736
   671
        return val;
nkeynes@1
   672
    }
nkeynes@1
   673
}
nkeynes@1
   674
.