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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1065:bc1cc0c54917
prev1008:4c8211637afc
prev584:5c29dd7297df
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author nkeynes
date Sun Jul 05 13:52:50 2009 +1000 (10 years ago)
permissions -rw-r--r--
last change No-op merge lxdream-mmu to remove head (actually merged long ago)
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_rbpdisp(R_FPUL)
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#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
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#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
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        } else { \
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            exit_block_exc(EXC_ILLEGAL, pc); \
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        } \
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        sh4_x86.branch_taken = TRUE; \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
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	ANDL_imms_r32( SR_FD, REG_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define address_space() ((sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space)
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   295
nkeynes@824
   296
#define UNDEF(ir)
nkeynes@953
   297
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@953
   298
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@953
   299
 */
nkeynes@953
   300
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   301
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   302
{
nkeynes@1004
   303
    decode_address(address_space(), addr_reg);
nkeynes@995
   304
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   305
        CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   306
    } else {
nkeynes@995
   307
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   308
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   309
        }
nkeynes@995
   310
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   311
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   312
        CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   313
    }
nkeynes@995
   314
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   315
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   316
    }
nkeynes@995
   317
}
nkeynes@995
   318
nkeynes@995
   319
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   320
{
nkeynes@1004
   321
    decode_address(address_space(), addr_reg);
nkeynes@995
   322
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   323
        CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   324
    } else {
nkeynes@995
   325
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   326
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   327
	}        
nkeynes@995
   328
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   329
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   330
        }
nkeynes@995
   331
#if MAX_REG_ARG > 2        
nkeynes@995
   332
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   333
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   334
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   335
#else
nkeynes@995
   336
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   337
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   338
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   339
#endif
nkeynes@995
   340
    }
nkeynes@995
   341
}
nkeynes@995
   342
#else
nkeynes@995
   343
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   344
{
nkeynes@1004
   345
    decode_address(address_space(), addr_reg);
nkeynes@995
   346
    CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   347
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   348
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   349
    }
nkeynes@995
   350
}     
nkeynes@995
   351
nkeynes@996
   352
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   353
{
nkeynes@1004
   354
    decode_address(address_space(), addr_reg);
nkeynes@995
   355
    CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   356
}
nkeynes@953
   357
#endif
nkeynes@953
   358
                
nkeynes@995
   359
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   360
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   361
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   362
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   363
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   364
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   365
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   366
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   367
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@361
   368
nkeynes@956
   369
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   370
nkeynes@901
   371
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   372
{
nkeynes@927
   373
    enter_block();
nkeynes@1004
   374
    MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
nkeynes@901
   375
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   376
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   377
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   378
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   379
    sh4_x86.block_start_pc = pc;
nkeynes@953
   380
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   382
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   383
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   384
}
nkeynes@901
   385
nkeynes@901
   386
nkeynes@593
   387
uint32_t sh4_translate_end_block_size()
nkeynes@593
   388
{
nkeynes@596
   389
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1008
   390
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*24);
nkeynes@596
   391
    } else {
nkeynes@1008
   392
        return EPILOGUE_SIZE + 72 + (sh4_x86.backpatch_posn-3)*27;
nkeynes@596
   393
    }
nkeynes@593
   394
}
nkeynes@593
   395
nkeynes@361
   396
nkeynes@571
   397
/**
nkeynes@590
   398
 * Embed a breakpoint into the generated code
nkeynes@571
   399
 */
nkeynes@577
   400
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@577
   401
{
nkeynes@995
   402
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   403
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@577
   405
}
nkeynes@590
   406
nkeynes@601
   407
nkeynes@601
   408
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   409
nkeynes@590
   410
/**
nkeynes@995
   411
 * Exit the block with sh4r.pc already written
nkeynes@995
   412
 */
nkeynes@995
   413
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   414
{
nkeynes@995
   415
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   416
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   417
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   418
    if( sh4_x86.tlb_on ) {
nkeynes@995
   419
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   420
    } else {
nkeynes@995
   421
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   422
    }
nkeynes@995
   423
    exit_block();
nkeynes@995
   424
}
nkeynes@995
   425
nkeynes@995
   426
/**
nkeynes@995
   427
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   428
 */
nkeynes@995
   429
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   430
{
nkeynes@995
   431
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   432
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   433
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   434
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@995
   435
    if( sh4_x86.tlb_on ) {
nkeynes@995
   436
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   437
    } else {
nkeynes@995
   438
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   439
    }
nkeynes@995
   440
    exit_block();
nkeynes@995
   441
}
nkeynes@995
   442
nkeynes@995
   443
nkeynes@995
   444
/**
nkeynes@995
   445
 * Exit the block to an absolute PC
nkeynes@995
   446
 */
nkeynes@995
   447
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   448
{
nkeynes@995
   449
    MOVL_imm32_r32( pc, REG_ECX );
nkeynes@995
   450
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   451
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   452
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   453
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   454
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   455
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   456
    } else {
nkeynes@995
   457
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   458
    }
nkeynes@995
   459
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   460
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   461
    exit_block();
nkeynes@995
   462
}
nkeynes@995
   463
nkeynes@995
   464
/**
nkeynes@995
   465
 * Exit the block to a relative PC
nkeynes@995
   466
 */
nkeynes@995
   467
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   468
{
nkeynes@995
   469
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   470
    ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@995
   471
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   472
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   473
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   474
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   475
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   476
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   477
    } else {
nkeynes@995
   478
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   479
    }
nkeynes@995
   480
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   481
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   482
    exit_block();
nkeynes@995
   483
}
nkeynes@995
   484
nkeynes@995
   485
/**
nkeynes@995
   486
 * Exit unconditionally with a general exception
nkeynes@995
   487
 */
nkeynes@995
   488
void exit_block_exc( int code, sh4addr_t pc )
nkeynes@995
   489
{
nkeynes@995
   490
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   491
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   492
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   493
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   494
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   495
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   496
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   497
    if( sh4_x86.tlb_on ) {
nkeynes@995
   498
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   499
    } else {
nkeynes@995
   500
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   501
    }
nkeynes@995
   502
nkeynes@995
   503
    exit_block();
nkeynes@995
   504
}    
nkeynes@995
   505
nkeynes@995
   506
/**
nkeynes@590
   507
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   508
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   509
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   510
 *
nkeynes@601
   511
 * Performs:
nkeynes@601
   512
 *   Set PC = endpc
nkeynes@601
   513
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   514
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   515
 *   Call sh4_execute_instruction
nkeynes@601
   516
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   517
 */
nkeynes@601
   518
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   519
{
nkeynes@995
   520
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   521
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@577
   522
    
nkeynes@995
   523
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   524
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   525
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   526
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   527
nkeynes@995
   528
    CALL_ptr( sh4_execute_instruction );    
nkeynes@995
   529
    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@590
   530
    if( sh4_x86.tlb_on ) {
nkeynes@995
   531
	CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX);
nkeynes@590
   532
    } else {
nkeynes@995
   533
	CALL1_ptr_r32(xlat_get_code,REG_EAX);
nkeynes@590
   534
    }
nkeynes@926
   535
    exit_block();
nkeynes@590
   536
} 
nkeynes@539
   537
nkeynes@359
   538
/**
nkeynes@995
   539
 * Write the block trailer (exception handling block)
nkeynes@995
   540
 */
nkeynes@995
   541
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   542
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   543
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   544
        exit_block_rel( pc, pc );
nkeynes@995
   545
    }
nkeynes@995
   546
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   547
        unsigned int i;
nkeynes@995
   548
        // Exception raised - cleanup and exit
nkeynes@995
   549
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   550
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   551
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   552
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   553
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@995
   554
        MULL_r32( REG_EDX );
nkeynes@995
   555
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   556
        MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   557
        if( sh4_x86.tlb_on ) {
nkeynes@995
   558
            CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@995
   559
        } else {
nkeynes@995
   560
            CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@995
   561
        }
nkeynes@995
   562
        exit_block();
nkeynes@995
   563
nkeynes@995
   564
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   565
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   566
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   567
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   568
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   569
                } else {
nkeynes@995
   570
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   571
                }
nkeynes@995
   572
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   573
                int rel = end_ptr - xlat_output;
nkeynes@995
   574
                JMP_prerel(rel);
nkeynes@995
   575
            } else {
nkeynes@995
   576
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   577
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   578
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   579
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   580
                int rel = end_ptr - xlat_output;
nkeynes@995
   581
                JMP_prerel(rel);
nkeynes@995
   582
            }
nkeynes@995
   583
        }
nkeynes@995
   584
    }
nkeynes@995
   585
}
nkeynes@539
   586
nkeynes@359
   587
/**
nkeynes@359
   588
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   589
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   590
 * 
nkeynes@577
   591
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   592
 *
nkeynes@359
   593
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   594
 * (eg a branch or 
nkeynes@359
   595
 */
nkeynes@590
   596
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   597
{
nkeynes@388
   598
    uint32_t ir;
nkeynes@577
   599
    /* Read instruction from icache */
nkeynes@577
   600
    assert( IS_IN_ICACHE(pc) );
nkeynes@577
   601
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@577
   602
    
nkeynes@571
   603
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   604
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   605
    }
nkeynes@1003
   606
    
nkeynes@1003
   607
    /* check for breakpoints at this pc */
nkeynes@1003
   608
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   609
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   610
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   611
            break;
nkeynes@1003
   612
        }
nkeynes@571
   613
    }
nkeynes@359
   614
%%
nkeynes@359
   615
/* ALU operations */
nkeynes@359
   616
ADD Rm, Rn {:
nkeynes@671
   617
    COUNT_INST(I_ADD);
nkeynes@991
   618
    load_reg( REG_EAX, Rm );
nkeynes@991
   619
    load_reg( REG_ECX, Rn );
nkeynes@991
   620
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   621
    store_reg( REG_ECX, Rn );
nkeynes@417
   622
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   623
:}
nkeynes@359
   624
ADD #imm, Rn {:  
nkeynes@671
   625
    COUNT_INST(I_ADDI);
nkeynes@991
   626
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   627
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   628
:}
nkeynes@359
   629
ADDC Rm, Rn {:
nkeynes@671
   630
    COUNT_INST(I_ADDC);
nkeynes@417
   631
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   632
        LDC_t();
nkeynes@417
   633
    }
nkeynes@991
   634
    load_reg( REG_EAX, Rm );
nkeynes@991
   635
    load_reg( REG_ECX, Rn );
nkeynes@991
   636
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   637
    store_reg( REG_ECX, Rn );
nkeynes@359
   638
    SETC_t();
nkeynes@417
   639
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   640
:}
nkeynes@359
   641
ADDV Rm, Rn {:
nkeynes@671
   642
    COUNT_INST(I_ADDV);
nkeynes@991
   643
    load_reg( REG_EAX, Rm );
nkeynes@991
   644
    load_reg( REG_ECX, Rn );
nkeynes@991
   645
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   646
    store_reg( REG_ECX, Rn );
nkeynes@359
   647
    SETO_t();
nkeynes@417
   648
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   649
:}
nkeynes@359
   650
AND Rm, Rn {:
nkeynes@671
   651
    COUNT_INST(I_AND);
nkeynes@991
   652
    load_reg( REG_EAX, Rm );
nkeynes@991
   653
    load_reg( REG_ECX, Rn );
nkeynes@991
   654
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   655
    store_reg( REG_ECX, Rn );
nkeynes@417
   656
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   657
:}
nkeynes@359
   658
AND #imm, R0 {:  
nkeynes@671
   659
    COUNT_INST(I_ANDI);
nkeynes@991
   660
    load_reg( REG_EAX, 0 );
nkeynes@991
   661
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   662
    store_reg( REG_EAX, 0 );
nkeynes@417
   663
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   664
:}
nkeynes@359
   665
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   666
    COUNT_INST(I_ANDB);
nkeynes@991
   667
    load_reg( REG_EAX, 0 );
nkeynes@991
   668
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   669
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   670
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   671
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   672
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   673
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   674
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   675
:}
nkeynes@359
   676
CMP/EQ Rm, Rn {:  
nkeynes@671
   677
    COUNT_INST(I_CMPEQ);
nkeynes@991
   678
    load_reg( REG_EAX, Rm );
nkeynes@991
   679
    load_reg( REG_ECX, Rn );
nkeynes@991
   680
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   681
    SETE_t();
nkeynes@417
   682
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   683
:}
nkeynes@359
   684
CMP/EQ #imm, R0 {:  
nkeynes@671
   685
    COUNT_INST(I_CMPEQI);
nkeynes@991
   686
    load_reg( REG_EAX, 0 );
nkeynes@991
   687
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   688
    SETE_t();
nkeynes@417
   689
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   690
:}
nkeynes@359
   691
CMP/GE Rm, Rn {:  
nkeynes@671
   692
    COUNT_INST(I_CMPGE);
nkeynes@991
   693
    load_reg( REG_EAX, Rm );
nkeynes@991
   694
    load_reg( REG_ECX, Rn );
nkeynes@991
   695
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   696
    SETGE_t();
nkeynes@417
   697
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   698
:}
nkeynes@359
   699
CMP/GT Rm, Rn {: 
nkeynes@671
   700
    COUNT_INST(I_CMPGT);
nkeynes@991
   701
    load_reg( REG_EAX, Rm );
nkeynes@991
   702
    load_reg( REG_ECX, Rn );
nkeynes@991
   703
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   704
    SETG_t();
nkeynes@417
   705
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   706
:}
nkeynes@359
   707
CMP/HI Rm, Rn {:  
nkeynes@671
   708
    COUNT_INST(I_CMPHI);
nkeynes@991
   709
    load_reg( REG_EAX, Rm );
nkeynes@991
   710
    load_reg( REG_ECX, Rn );
nkeynes@991
   711
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   712
    SETA_t();
nkeynes@417
   713
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   714
:}
nkeynes@359
   715
CMP/HS Rm, Rn {: 
nkeynes@671
   716
    COUNT_INST(I_CMPHS);
nkeynes@991
   717
    load_reg( REG_EAX, Rm );
nkeynes@991
   718
    load_reg( REG_ECX, Rn );
nkeynes@991
   719
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   720
    SETAE_t();
nkeynes@417
   721
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   722
 :}
nkeynes@359
   723
CMP/PL Rn {: 
nkeynes@671
   724
    COUNT_INST(I_CMPPL);
nkeynes@991
   725
    load_reg( REG_EAX, Rn );
nkeynes@991
   726
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   727
    SETG_t();
nkeynes@417
   728
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   729
:}
nkeynes@359
   730
CMP/PZ Rn {:  
nkeynes@671
   731
    COUNT_INST(I_CMPPZ);
nkeynes@991
   732
    load_reg( REG_EAX, Rn );
nkeynes@991
   733
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   734
    SETGE_t();
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   736
:}
nkeynes@361
   737
CMP/STR Rm, Rn {:  
nkeynes@671
   738
    COUNT_INST(I_CMPSTR);
nkeynes@991
   739
    load_reg( REG_EAX, Rm );
nkeynes@991
   740
    load_reg( REG_ECX, Rn );
nkeynes@991
   741
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   742
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   743
    JE_label(target1);
nkeynes@991
   744
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   745
    JE_label(target2);
nkeynes@991
   746
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   747
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   748
    JE_label(target3);
nkeynes@991
   749
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   750
    JMP_TARGET(target1);
nkeynes@380
   751
    JMP_TARGET(target2);
nkeynes@380
   752
    JMP_TARGET(target3);
nkeynes@368
   753
    SETE_t();
nkeynes@417
   754
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   755
:}
nkeynes@361
   756
DIV0S Rm, Rn {:
nkeynes@671
   757
    COUNT_INST(I_DIV0S);
nkeynes@991
   758
    load_reg( REG_EAX, Rm );
nkeynes@991
   759
    load_reg( REG_ECX, Rn );
nkeynes@991
   760
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   761
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
   762
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   763
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   764
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   765
    SETNE_t();
nkeynes@417
   766
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   767
:}
nkeynes@361
   768
DIV0U {:  
nkeynes@671
   769
    COUNT_INST(I_DIV0U);
nkeynes@991
   770
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
   771
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
   772
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   773
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   774
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   775
:}
nkeynes@386
   776
DIV1 Rm, Rn {:
nkeynes@671
   777
    COUNT_INST(I_DIV1);
nkeynes@995
   778
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
   779
    load_reg( REG_EAX, Rn );
nkeynes@417
   780
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   781
	LDC_t();
nkeynes@417
   782
    }
nkeynes@991
   783
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   784
    SETC_r8( REG_DL ); // Q'
nkeynes@991
   785
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
   786
    JE_label(mqequal);
nkeynes@991
   787
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
   788
    JMP_label(end);
nkeynes@380
   789
    JMP_TARGET(mqequal);
nkeynes@991
   790
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
   791
    JMP_TARGET(end);
nkeynes@991
   792
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
   793
    SETC_r8(REG_AL); // tmp1
nkeynes@991
   794
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
   795
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
   796
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   797
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
   798
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
   799
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   801
:}
nkeynes@361
   802
DMULS.L Rm, Rn {:  
nkeynes@671
   803
    COUNT_INST(I_DMULS);
nkeynes@991
   804
    load_reg( REG_EAX, Rm );
nkeynes@991
   805
    load_reg( REG_ECX, Rn );
nkeynes@991
   806
    IMULL_r32(REG_ECX);
nkeynes@995
   807
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   808
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   809
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   810
:}
nkeynes@361
   811
DMULU.L Rm, Rn {:  
nkeynes@671
   812
    COUNT_INST(I_DMULU);
nkeynes@991
   813
    load_reg( REG_EAX, Rm );
nkeynes@991
   814
    load_reg( REG_ECX, Rn );
nkeynes@991
   815
    MULL_r32(REG_ECX);
nkeynes@995
   816
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   817
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
   818
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   819
:}
nkeynes@359
   820
DT Rn {:  
nkeynes@671
   821
    COUNT_INST(I_DT);
nkeynes@991
   822
    load_reg( REG_EAX, Rn );
nkeynes@991
   823
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
   824
    store_reg( REG_EAX, Rn );
nkeynes@359
   825
    SETE_t();
nkeynes@417
   826
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   827
:}
nkeynes@359
   828
EXTS.B Rm, Rn {:  
nkeynes@671
   829
    COUNT_INST(I_EXTSB);
nkeynes@991
   830
    load_reg( REG_EAX, Rm );
nkeynes@991
   831
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   832
    store_reg( REG_EAX, Rn );
nkeynes@359
   833
:}
nkeynes@361
   834
EXTS.W Rm, Rn {:  
nkeynes@671
   835
    COUNT_INST(I_EXTSW);
nkeynes@991
   836
    load_reg( REG_EAX, Rm );
nkeynes@991
   837
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   838
    store_reg( REG_EAX, Rn );
nkeynes@361
   839
:}
nkeynes@361
   840
EXTU.B Rm, Rn {:  
nkeynes@671
   841
    COUNT_INST(I_EXTUB);
nkeynes@991
   842
    load_reg( REG_EAX, Rm );
nkeynes@991
   843
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   844
    store_reg( REG_EAX, Rn );
nkeynes@361
   845
:}
nkeynes@361
   846
EXTU.W Rm, Rn {:  
nkeynes@671
   847
    COUNT_INST(I_EXTUW);
nkeynes@991
   848
    load_reg( REG_EAX, Rm );
nkeynes@991
   849
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   850
    store_reg( REG_EAX, Rn );
nkeynes@361
   851
:}
nkeynes@571
   852
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   853
    COUNT_INST(I_MACL);
nkeynes@571
   854
    if( Rm == Rn ) {
nkeynes@991
   855
	load_reg( REG_EAX, Rm );
nkeynes@991
   856
	check_ralign32( REG_EAX );
nkeynes@991
   857
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   858
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   859
	load_reg( REG_EAX, Rm );
nkeynes@991
   860
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
   861
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   862
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@571
   863
    } else {
nkeynes@991
   864
	load_reg( REG_EAX, Rm );
nkeynes@991
   865
	check_ralign32( REG_EAX );
nkeynes@991
   866
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   867
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   868
	load_reg( REG_EAX, Rn );
nkeynes@991
   869
	check_ralign32( REG_EAX );
nkeynes@991
   870
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   871
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
   872
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@571
   873
    }
nkeynes@953
   874
    
nkeynes@991
   875
    IMULL_rspdisp( 0 );
nkeynes@991
   876
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
   877
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@571
   878
nkeynes@995
   879
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   880
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
   881
    JE_label( nosat );
nkeynes@995
   882
    CALL_ptr( signsat48 );
nkeynes@386
   883
    JMP_TARGET( nosat );
nkeynes@417
   884
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   885
:}
nkeynes@386
   886
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   887
    COUNT_INST(I_MACW);
nkeynes@571
   888
    if( Rm == Rn ) {
nkeynes@991
   889
	load_reg( REG_EAX, Rm );
nkeynes@991
   890
	check_ralign16( REG_EAX );
nkeynes@991
   891
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   892
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   893
	load_reg( REG_EAX, Rm );
nkeynes@991
   894
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
   895
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   896
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@571
   897
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571
   898
	// adding a page-boundary check to skip the second translation
nkeynes@571
   899
    } else {
nkeynes@991
   900
	load_reg( REG_EAX, Rm );
nkeynes@991
   901
	check_ralign16( REG_EAX );
nkeynes@991
   902
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   903
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   904
	load_reg( REG_EAX, Rn );
nkeynes@991
   905
	check_ralign16( REG_EAX );
nkeynes@991
   906
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   907
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
   908
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@571
   909
    }
nkeynes@991
   910
    IMULL_rspdisp( 0 );
nkeynes@995
   911
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   912
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
   913
    JE_label( nosat );
nkeynes@386
   914
nkeynes@991
   915
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   916
    JNO_label( end );            // 2
nkeynes@995
   917
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
   918
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
   919
    JS_label( positive );        // 2
nkeynes@995
   920
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
   921
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
   922
    JMP_label(end2);           // 2
nkeynes@386
   923
nkeynes@386
   924
    JMP_TARGET(positive);
nkeynes@995
   925
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
   926
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
   927
    JMP_label(end3);            // 2
nkeynes@386
   928
nkeynes@386
   929
    JMP_TARGET(nosat);
nkeynes@991
   930
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   931
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
   932
    JMP_TARGET(end);
nkeynes@386
   933
    JMP_TARGET(end2);
nkeynes@386
   934
    JMP_TARGET(end3);
nkeynes@417
   935
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   936
:}
nkeynes@359
   937
MOVT Rn {:  
nkeynes@671
   938
    COUNT_INST(I_MOVT);
nkeynes@995
   939
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
   940
    store_reg( REG_EAX, Rn );
nkeynes@359
   941
:}
nkeynes@361
   942
MUL.L Rm, Rn {:  
nkeynes@671
   943
    COUNT_INST(I_MULL);
nkeynes@991
   944
    load_reg( REG_EAX, Rm );
nkeynes@991
   945
    load_reg( REG_ECX, Rn );
nkeynes@991
   946
    MULL_r32( REG_ECX );
nkeynes@995
   947
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   949
:}
nkeynes@374
   950
MULS.W Rm, Rn {:
nkeynes@671
   951
    COUNT_INST(I_MULSW);
nkeynes@995
   952
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
   953
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
   954
    MULL_r32( REG_ECX );
nkeynes@995
   955
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   956
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   957
:}
nkeynes@374
   958
MULU.W Rm, Rn {:  
nkeynes@671
   959
    COUNT_INST(I_MULUW);
nkeynes@995
   960
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
   961
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
   962
    MULL_r32( REG_ECX );
nkeynes@995
   963
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   964
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   965
:}
nkeynes@359
   966
NEG Rm, Rn {:
nkeynes@671
   967
    COUNT_INST(I_NEG);
nkeynes@991
   968
    load_reg( REG_EAX, Rm );
nkeynes@991
   969
    NEGL_r32( REG_EAX );
nkeynes@991
   970
    store_reg( REG_EAX, Rn );
nkeynes@417
   971
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   972
:}
nkeynes@359
   973
NEGC Rm, Rn {:  
nkeynes@671
   974
    COUNT_INST(I_NEGC);
nkeynes@991
   975
    load_reg( REG_EAX, Rm );
nkeynes@991
   976
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
   977
    LDC_t();
nkeynes@991
   978
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   979
    store_reg( REG_ECX, Rn );
nkeynes@359
   980
    SETC_t();
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   982
:}
nkeynes@359
   983
NOT Rm, Rn {:  
nkeynes@671
   984
    COUNT_INST(I_NOT);
nkeynes@991
   985
    load_reg( REG_EAX, Rm );
nkeynes@991
   986
    NOTL_r32( REG_EAX );
nkeynes@991
   987
    store_reg( REG_EAX, Rn );
nkeynes@417
   988
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   989
:}
nkeynes@359
   990
OR Rm, Rn {:  
nkeynes@671
   991
    COUNT_INST(I_OR);
nkeynes@991
   992
    load_reg( REG_EAX, Rm );
nkeynes@991
   993
    load_reg( REG_ECX, Rn );
nkeynes@991
   994
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   995
    store_reg( REG_ECX, Rn );
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   997
:}
nkeynes@359
   998
OR #imm, R0 {:
nkeynes@671
   999
    COUNT_INST(I_ORI);
nkeynes@991
  1000
    load_reg( REG_EAX, 0 );
nkeynes@991
  1001
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1002
    store_reg( REG_EAX, 0 );
nkeynes@417
  1003
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1004
:}
nkeynes@374
  1005
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1006
    COUNT_INST(I_ORB);
nkeynes@991
  1007
    load_reg( REG_EAX, 0 );
nkeynes@991
  1008
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1009
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1010
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1011
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1012
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1013
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1014
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1015
:}
nkeynes@359
  1016
ROTCL Rn {:
nkeynes@671
  1017
    COUNT_INST(I_ROTCL);
nkeynes@991
  1018
    load_reg( REG_EAX, Rn );
nkeynes@417
  1019
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1020
	LDC_t();
nkeynes@417
  1021
    }
nkeynes@991
  1022
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1023
    store_reg( REG_EAX, Rn );
nkeynes@359
  1024
    SETC_t();
nkeynes@417
  1025
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1026
:}
nkeynes@359
  1027
ROTCR Rn {:  
nkeynes@671
  1028
    COUNT_INST(I_ROTCR);
nkeynes@991
  1029
    load_reg( REG_EAX, Rn );
nkeynes@417
  1030
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1031
	LDC_t();
nkeynes@417
  1032
    }
nkeynes@991
  1033
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1034
    store_reg( REG_EAX, Rn );
nkeynes@359
  1035
    SETC_t();
nkeynes@417
  1036
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1037
:}
nkeynes@359
  1038
ROTL Rn {:  
nkeynes@671
  1039
    COUNT_INST(I_ROTL);
nkeynes@991
  1040
    load_reg( REG_EAX, Rn );
nkeynes@991
  1041
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1042
    store_reg( REG_EAX, Rn );
nkeynes@359
  1043
    SETC_t();
nkeynes@417
  1044
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1045
:}
nkeynes@359
  1046
ROTR Rn {:  
nkeynes@671
  1047
    COUNT_INST(I_ROTR);
nkeynes@991
  1048
    load_reg( REG_EAX, Rn );
nkeynes@991
  1049
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1050
    store_reg( REG_EAX, Rn );
nkeynes@359
  1051
    SETC_t();
nkeynes@417
  1052
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1053
:}
nkeynes@359
  1054
SHAD Rm, Rn {:
nkeynes@671
  1055
    COUNT_INST(I_SHAD);
nkeynes@359
  1056
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1057
    load_reg( REG_EAX, Rn );
nkeynes@991
  1058
    load_reg( REG_ECX, Rm );
nkeynes@991
  1059
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1060
    JGE_label(doshl);
nkeynes@361
  1061
                    
nkeynes@991
  1062
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1063
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1064
    JE_label(emptysar);     // 2
nkeynes@991
  1065
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1066
    JMP_label(end);          // 2
nkeynes@386
  1067
nkeynes@386
  1068
    JMP_TARGET(emptysar);
nkeynes@991
  1069
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1070
    JMP_label(end2);
nkeynes@382
  1071
nkeynes@380
  1072
    JMP_TARGET(doshl);
nkeynes@991
  1073
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1074
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1075
    JMP_TARGET(end);
nkeynes@386
  1076
    JMP_TARGET(end2);
nkeynes@991
  1077
    store_reg( REG_EAX, Rn );
nkeynes@417
  1078
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1079
:}
nkeynes@359
  1080
SHLD Rm, Rn {:  
nkeynes@671
  1081
    COUNT_INST(I_SHLD);
nkeynes@991
  1082
    load_reg( REG_EAX, Rn );
nkeynes@991
  1083
    load_reg( REG_ECX, Rm );
nkeynes@991
  1084
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1085
    JGE_label(doshl);
nkeynes@368
  1086
nkeynes@991
  1087
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1088
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1089
    JE_label(emptyshr );
nkeynes@991
  1090
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1091
    JMP_label(end);          // 2
nkeynes@386
  1092
nkeynes@386
  1093
    JMP_TARGET(emptyshr);
nkeynes@991
  1094
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1095
    JMP_label(end2);
nkeynes@382
  1096
nkeynes@382
  1097
    JMP_TARGET(doshl);
nkeynes@991
  1098
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1099
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1100
    JMP_TARGET(end);
nkeynes@386
  1101
    JMP_TARGET(end2);
nkeynes@991
  1102
    store_reg( REG_EAX, Rn );
nkeynes@417
  1103
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1104
:}
nkeynes@359
  1105
SHAL Rn {: 
nkeynes@671
  1106
    COUNT_INST(I_SHAL);
nkeynes@991
  1107
    load_reg( REG_EAX, Rn );
nkeynes@991
  1108
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1109
    SETC_t();
nkeynes@991
  1110
    store_reg( REG_EAX, Rn );
nkeynes@417
  1111
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1112
:}
nkeynes@359
  1113
SHAR Rn {:  
nkeynes@671
  1114
    COUNT_INST(I_SHAR);
nkeynes@991
  1115
    load_reg( REG_EAX, Rn );
nkeynes@991
  1116
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1117
    SETC_t();
nkeynes@991
  1118
    store_reg( REG_EAX, Rn );
nkeynes@417
  1119
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1120
:}
nkeynes@359
  1121
SHLL Rn {:  
nkeynes@671
  1122
    COUNT_INST(I_SHLL);
nkeynes@991
  1123
    load_reg( REG_EAX, Rn );
nkeynes@991
  1124
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1125
    SETC_t();
nkeynes@991
  1126
    store_reg( REG_EAX, Rn );
nkeynes@417
  1127
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1128
:}
nkeynes@359
  1129
SHLL2 Rn {:
nkeynes@671
  1130
    COUNT_INST(I_SHLL);
nkeynes@991
  1131
    load_reg( REG_EAX, Rn );
nkeynes@991
  1132
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1133
    store_reg( REG_EAX, Rn );
nkeynes@417
  1134
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1135
:}
nkeynes@359
  1136
SHLL8 Rn {:  
nkeynes@671
  1137
    COUNT_INST(I_SHLL);
nkeynes@991
  1138
    load_reg( REG_EAX, Rn );
nkeynes@991
  1139
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1140
    store_reg( REG_EAX, Rn );
nkeynes@417
  1141
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1142
:}
nkeynes@359
  1143
SHLL16 Rn {:  
nkeynes@671
  1144
    COUNT_INST(I_SHLL);
nkeynes@991
  1145
    load_reg( REG_EAX, Rn );
nkeynes@991
  1146
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1147
    store_reg( REG_EAX, Rn );
nkeynes@417
  1148
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1149
:}
nkeynes@359
  1150
SHLR Rn {:  
nkeynes@671
  1151
    COUNT_INST(I_SHLR);
nkeynes@991
  1152
    load_reg( REG_EAX, Rn );
nkeynes@991
  1153
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1154
    SETC_t();
nkeynes@991
  1155
    store_reg( REG_EAX, Rn );
nkeynes@417
  1156
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1157
:}
nkeynes@359
  1158
SHLR2 Rn {:  
nkeynes@671
  1159
    COUNT_INST(I_SHLR);
nkeynes@991
  1160
    load_reg( REG_EAX, Rn );
nkeynes@991
  1161
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1162
    store_reg( REG_EAX, Rn );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1164
:}
nkeynes@359
  1165
SHLR8 Rn {:  
nkeynes@671
  1166
    COUNT_INST(I_SHLR);
nkeynes@991
  1167
    load_reg( REG_EAX, Rn );
nkeynes@991
  1168
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1169
    store_reg( REG_EAX, Rn );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1171
:}
nkeynes@359
  1172
SHLR16 Rn {:  
nkeynes@671
  1173
    COUNT_INST(I_SHLR);
nkeynes@991
  1174
    load_reg( REG_EAX, Rn );
nkeynes@991
  1175
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1176
    store_reg( REG_EAX, Rn );
nkeynes@417
  1177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1178
:}
nkeynes@359
  1179
SUB Rm, Rn {:  
nkeynes@671
  1180
    COUNT_INST(I_SUB);
nkeynes@991
  1181
    load_reg( REG_EAX, Rm );
nkeynes@991
  1182
    load_reg( REG_ECX, Rn );
nkeynes@991
  1183
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1184
    store_reg( REG_ECX, Rn );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1186
:}
nkeynes@359
  1187
SUBC Rm, Rn {:  
nkeynes@671
  1188
    COUNT_INST(I_SUBC);
nkeynes@991
  1189
    load_reg( REG_EAX, Rm );
nkeynes@991
  1190
    load_reg( REG_ECX, Rn );
nkeynes@417
  1191
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1192
	LDC_t();
nkeynes@417
  1193
    }
nkeynes@991
  1194
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1195
    store_reg( REG_ECX, Rn );
nkeynes@394
  1196
    SETC_t();
nkeynes@417
  1197
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1198
:}
nkeynes@359
  1199
SUBV Rm, Rn {:  
nkeynes@671
  1200
    COUNT_INST(I_SUBV);
nkeynes@991
  1201
    load_reg( REG_EAX, Rm );
nkeynes@991
  1202
    load_reg( REG_ECX, Rn );
nkeynes@991
  1203
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1204
    store_reg( REG_ECX, Rn );
nkeynes@359
  1205
    SETO_t();
nkeynes@417
  1206
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1207
:}
nkeynes@359
  1208
SWAP.B Rm, Rn {:  
nkeynes@671
  1209
    COUNT_INST(I_SWAPB);
nkeynes@991
  1210
    load_reg( REG_EAX, Rm );
nkeynes@991
  1211
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1212
    store_reg( REG_EAX, Rn );
nkeynes@359
  1213
:}
nkeynes@359
  1214
SWAP.W Rm, Rn {:  
nkeynes@671
  1215
    COUNT_INST(I_SWAPB);
nkeynes@991
  1216
    load_reg( REG_EAX, Rm );
nkeynes@991
  1217
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1218
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1219
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1220
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1221
    store_reg( REG_ECX, Rn );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@361
  1224
TAS.B @Rn {:  
nkeynes@671
  1225
    COUNT_INST(I_TASB);
nkeynes@991
  1226
    load_reg( REG_EAX, Rn );
nkeynes@991
  1227
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1228
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1229
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1230
    SETE_t();
nkeynes@991
  1231
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1232
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1233
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1235
:}
nkeynes@361
  1236
TST Rm, Rn {:  
nkeynes@671
  1237
    COUNT_INST(I_TST);
nkeynes@991
  1238
    load_reg( REG_EAX, Rm );
nkeynes@991
  1239
    load_reg( REG_ECX, Rn );
nkeynes@991
  1240
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1241
    SETE_t();
nkeynes@417
  1242
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1243
:}
nkeynes@368
  1244
TST #imm, R0 {:  
nkeynes@671
  1245
    COUNT_INST(I_TSTI);
nkeynes@991
  1246
    load_reg( REG_EAX, 0 );
nkeynes@991
  1247
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1248
    SETE_t();
nkeynes@417
  1249
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1250
:}
nkeynes@368
  1251
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1252
    COUNT_INST(I_TSTB);
nkeynes@991
  1253
    load_reg( REG_EAX, 0);
nkeynes@991
  1254
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1255
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1256
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1257
    SETE_t();
nkeynes@417
  1258
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1259
:}
nkeynes@359
  1260
XOR Rm, Rn {:  
nkeynes@671
  1261
    COUNT_INST(I_XOR);
nkeynes@991
  1262
    load_reg( REG_EAX, Rm );
nkeynes@991
  1263
    load_reg( REG_ECX, Rn );
nkeynes@991
  1264
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1265
    store_reg( REG_ECX, Rn );
nkeynes@417
  1266
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1267
:}
nkeynes@359
  1268
XOR #imm, R0 {:  
nkeynes@671
  1269
    COUNT_INST(I_XORI);
nkeynes@991
  1270
    load_reg( REG_EAX, 0 );
nkeynes@991
  1271
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1272
    store_reg( REG_EAX, 0 );
nkeynes@417
  1273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1274
:}
nkeynes@359
  1275
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1276
    COUNT_INST(I_XORB);
nkeynes@991
  1277
    load_reg( REG_EAX, 0 );
nkeynes@991
  1278
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1279
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1280
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1281
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1282
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1283
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1284
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1285
:}
nkeynes@361
  1286
XTRCT Rm, Rn {:
nkeynes@671
  1287
    COUNT_INST(I_XTRCT);
nkeynes@991
  1288
    load_reg( REG_EAX, Rm );
nkeynes@991
  1289
    load_reg( REG_ECX, Rn );
nkeynes@991
  1290
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1291
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1292
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1293
    store_reg( REG_ECX, Rn );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1295
:}
nkeynes@359
  1296
nkeynes@359
  1297
/* Data move instructions */
nkeynes@359
  1298
MOV Rm, Rn {:  
nkeynes@671
  1299
    COUNT_INST(I_MOV);
nkeynes@991
  1300
    load_reg( REG_EAX, Rm );
nkeynes@991
  1301
    store_reg( REG_EAX, Rn );
nkeynes@359
  1302
:}
nkeynes@359
  1303
MOV #imm, Rn {:  
nkeynes@671
  1304
    COUNT_INST(I_MOVI);
nkeynes@995
  1305
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1306
    store_reg( REG_EAX, Rn );
nkeynes@359
  1307
:}
nkeynes@359
  1308
MOV.B Rm, @Rn {:  
nkeynes@671
  1309
    COUNT_INST(I_MOVB);
nkeynes@991
  1310
    load_reg( REG_EAX, Rn );
nkeynes@991
  1311
    load_reg( REG_EDX, Rm );
nkeynes@991
  1312
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1314
:}
nkeynes@359
  1315
MOV.B Rm, @-Rn {:  
nkeynes@671
  1316
    COUNT_INST(I_MOVB);
nkeynes@991
  1317
    load_reg( REG_EAX, Rn );
nkeynes@991
  1318
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1319
    load_reg( REG_EDX, Rm );
nkeynes@991
  1320
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1321
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1323
:}
nkeynes@359
  1324
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1325
    COUNT_INST(I_MOVB);
nkeynes@991
  1326
    load_reg( REG_EAX, 0 );
nkeynes@991
  1327
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1328
    load_reg( REG_EDX, Rm );
nkeynes@991
  1329
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1330
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1331
:}
nkeynes@359
  1332
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1333
    COUNT_INST(I_MOVB);
nkeynes@995
  1334
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1335
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1336
    load_reg( REG_EDX, 0 );
nkeynes@991
  1337
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1338
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1339
:}
nkeynes@359
  1340
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1341
    COUNT_INST(I_MOVB);
nkeynes@991
  1342
    load_reg( REG_EAX, Rn );
nkeynes@991
  1343
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1344
    load_reg( REG_EDX, 0 );
nkeynes@991
  1345
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1347
:}
nkeynes@359
  1348
MOV.B @Rm, Rn {:  
nkeynes@671
  1349
    COUNT_INST(I_MOVB);
nkeynes@991
  1350
    load_reg( REG_EAX, Rm );
nkeynes@991
  1351
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1352
    store_reg( REG_EAX, Rn );
nkeynes@417
  1353
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1354
:}
nkeynes@359
  1355
MOV.B @Rm+, Rn {:  
nkeynes@671
  1356
    COUNT_INST(I_MOVB);
nkeynes@991
  1357
    load_reg( REG_EAX, Rm );
nkeynes@991
  1358
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@953
  1359
    if( Rm != Rn ) {
nkeynes@991
  1360
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@953
  1361
    }
nkeynes@991
  1362
    store_reg( REG_EAX, Rn );
nkeynes@417
  1363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1364
:}
nkeynes@359
  1365
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1366
    COUNT_INST(I_MOVB);
nkeynes@991
  1367
    load_reg( REG_EAX, 0 );
nkeynes@991
  1368
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1369
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1370
    store_reg( REG_EAX, Rn );
nkeynes@417
  1371
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1372
:}
nkeynes@359
  1373
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1374
    COUNT_INST(I_MOVB);
nkeynes@995
  1375
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1376
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1377
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1378
    store_reg( REG_EAX, 0 );
nkeynes@417
  1379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1380
:}
nkeynes@359
  1381
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1382
    COUNT_INST(I_MOVB);
nkeynes@991
  1383
    load_reg( REG_EAX, Rm );
nkeynes@991
  1384
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1385
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1386
    store_reg( REG_EAX, 0 );
nkeynes@417
  1387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1388
:}
nkeynes@374
  1389
MOV.L Rm, @Rn {:
nkeynes@671
  1390
    COUNT_INST(I_MOVL);
nkeynes@991
  1391
    load_reg( REG_EAX, Rn );
nkeynes@991
  1392
    check_walign32(REG_EAX);
nkeynes@991
  1393
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1394
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1395
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1396
    JNE_label( notsq );
nkeynes@991
  1397
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1398
    load_reg( REG_EDX, Rm );
nkeynes@991
  1399
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1400
    JMP_label(end);
nkeynes@953
  1401
    JMP_TARGET(notsq);
nkeynes@991
  1402
    load_reg( REG_EDX, Rm );
nkeynes@991
  1403
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1404
    JMP_TARGET(end);
nkeynes@417
  1405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1406
:}
nkeynes@361
  1407
MOV.L Rm, @-Rn {:  
nkeynes@671
  1408
    COUNT_INST(I_MOVL);
nkeynes@991
  1409
    load_reg( REG_EAX, Rn );
nkeynes@991
  1410
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1411
    check_walign32( REG_EAX );
nkeynes@991
  1412
    load_reg( REG_EDX, Rm );
nkeynes@991
  1413
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1414
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1416
:}
nkeynes@361
  1417
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1418
    COUNT_INST(I_MOVL);
nkeynes@991
  1419
    load_reg( REG_EAX, 0 );
nkeynes@991
  1420
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1421
    check_walign32( REG_EAX );
nkeynes@991
  1422
    load_reg( REG_EDX, Rm );
nkeynes@991
  1423
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1425
:}
nkeynes@361
  1426
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1427
    COUNT_INST(I_MOVL);
nkeynes@995
  1428
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1429
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1430
    check_walign32( REG_EAX );
nkeynes@991
  1431
    load_reg( REG_EDX, 0 );
nkeynes@991
  1432
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1433
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1434
:}
nkeynes@361
  1435
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1436
    COUNT_INST(I_MOVL);
nkeynes@991
  1437
    load_reg( REG_EAX, Rn );
nkeynes@991
  1438
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1439
    check_walign32( REG_EAX );
nkeynes@991
  1440
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1441
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1442
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1443
    JNE_label( notsq );
nkeynes@991
  1444
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1445
    load_reg( REG_EDX, Rm );
nkeynes@991
  1446
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1447
    JMP_label(end);
nkeynes@953
  1448
    JMP_TARGET(notsq);
nkeynes@991
  1449
    load_reg( REG_EDX, Rm );
nkeynes@991
  1450
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1451
    JMP_TARGET(end);
nkeynes@417
  1452
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1453
:}
nkeynes@361
  1454
MOV.L @Rm, Rn {:  
nkeynes@671
  1455
    COUNT_INST(I_MOVL);
nkeynes@991
  1456
    load_reg( REG_EAX, Rm );
nkeynes@991
  1457
    check_ralign32( REG_EAX );
nkeynes@991
  1458
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1459
    store_reg( REG_EAX, Rn );
nkeynes@417
  1460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1461
:}
nkeynes@361
  1462
MOV.L @Rm+, Rn {:  
nkeynes@671
  1463
    COUNT_INST(I_MOVL);
nkeynes@991
  1464
    load_reg( REG_EAX, Rm );
nkeynes@991
  1465
    check_ralign32( REG_EAX );
nkeynes@991
  1466
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@953
  1467
    if( Rm != Rn ) {
nkeynes@991
  1468
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@953
  1469
    }
nkeynes@991
  1470
    store_reg( REG_EAX, Rn );
nkeynes@417
  1471
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1472
:}
nkeynes@361
  1473
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1474
    COUNT_INST(I_MOVL);
nkeynes@991
  1475
    load_reg( REG_EAX, 0 );
nkeynes@991
  1476
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1477
    check_ralign32( REG_EAX );
nkeynes@991
  1478
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1479
    store_reg( REG_EAX, Rn );
nkeynes@417
  1480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1481
:}
nkeynes@361
  1482
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1483
    COUNT_INST(I_MOVL);
nkeynes@995
  1484
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1485
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1486
    check_ralign32( REG_EAX );
nkeynes@991
  1487
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1488
    store_reg( REG_EAX, 0 );
nkeynes@417
  1489
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1490
:}
nkeynes@361
  1491
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1492
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1493
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1494
	SLOTILLEGAL();
nkeynes@374
  1495
    } else {
nkeynes@388
  1496
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  1497
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1498
	    // If the target address is in the same page as the code, it's
nkeynes@569
  1499
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  1500
	    // memory subsystem. (this is a big performance win)
nkeynes@569
  1501
nkeynes@569
  1502
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  1503
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  1504
	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  1505
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  1506
	    // behaviour though.
nkeynes@569
  1507
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1508
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1509
	} else {
nkeynes@569
  1510
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  1511
	    // different virtual address than the translation was done with,
nkeynes@569
  1512
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1513
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1514
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1515
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@569
  1516
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1517
	}
nkeynes@991
  1518
	store_reg( REG_EAX, Rn );
nkeynes@374
  1519
    }
nkeynes@361
  1520
:}
nkeynes@361
  1521
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1522
    COUNT_INST(I_MOVL);
nkeynes@991
  1523
    load_reg( REG_EAX, Rm );
nkeynes@991
  1524
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1525
    check_ralign32( REG_EAX );
nkeynes@991
  1526
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1527
    store_reg( REG_EAX, Rn );
nkeynes@417
  1528
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1529
:}
nkeynes@361
  1530
MOV.W Rm, @Rn {:  
nkeynes@671
  1531
    COUNT_INST(I_MOVW);
nkeynes@991
  1532
    load_reg( REG_EAX, Rn );
nkeynes@991
  1533
    check_walign16( REG_EAX );
nkeynes@991
  1534
    load_reg( REG_EDX, Rm );
nkeynes@991
  1535
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1537
:}
nkeynes@361
  1538
MOV.W Rm, @-Rn {:  
nkeynes@671
  1539
    COUNT_INST(I_MOVW);
nkeynes@991
  1540
    load_reg( REG_EAX, Rn );
nkeynes@991
  1541
    check_walign16( REG_EAX );
nkeynes@991
  1542
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1543
    load_reg( REG_EDX, Rm );
nkeynes@991
  1544
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1545
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1546
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1547
:}
nkeynes@361
  1548
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1549
    COUNT_INST(I_MOVW);
nkeynes@991
  1550
    load_reg( REG_EAX, 0 );
nkeynes@991
  1551
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1552
    check_walign16( REG_EAX );
nkeynes@991
  1553
    load_reg( REG_EDX, Rm );
nkeynes@991
  1554
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1556
:}
nkeynes@361
  1557
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1558
    COUNT_INST(I_MOVW);
nkeynes@995
  1559
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1560
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1561
    check_walign16( REG_EAX );
nkeynes@991
  1562
    load_reg( REG_EDX, 0 );
nkeynes@991
  1563
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1564
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1565
:}
nkeynes@361
  1566
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1567
    COUNT_INST(I_MOVW);
nkeynes@991
  1568
    load_reg( REG_EAX, Rn );
nkeynes@991
  1569
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1570
    check_walign16( REG_EAX );
nkeynes@991
  1571
    load_reg( REG_EDX, 0 );
nkeynes@991
  1572
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1573
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1574
:}
nkeynes@361
  1575
MOV.W @Rm, Rn {:  
nkeynes@671
  1576
    COUNT_INST(I_MOVW);
nkeynes@991
  1577
    load_reg( REG_EAX, Rm );
nkeynes@991
  1578
    check_ralign16( REG_EAX );
nkeynes@991
  1579
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1580
    store_reg( REG_EAX, Rn );
nkeynes@417
  1581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1582
:}
nkeynes@361
  1583
MOV.W @Rm+, Rn {:  
nkeynes@671
  1584
    COUNT_INST(I_MOVW);
nkeynes@991
  1585
    load_reg( REG_EAX, Rm );
nkeynes@991
  1586
    check_ralign16( REG_EAX );
nkeynes@991
  1587
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@953
  1588
    if( Rm != Rn ) {
nkeynes@991
  1589
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@953
  1590
    }
nkeynes@991
  1591
    store_reg( REG_EAX, Rn );
nkeynes@417
  1592
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1593
:}
nkeynes@361
  1594
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1595
    COUNT_INST(I_MOVW);
nkeynes@991
  1596
    load_reg( REG_EAX, 0 );
nkeynes@991
  1597
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1598
    check_ralign16( REG_EAX );
nkeynes@991
  1599
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1600
    store_reg( REG_EAX, Rn );
nkeynes@417
  1601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1602
:}
nkeynes@361
  1603
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1604
    COUNT_INST(I_MOVW);
nkeynes@995
  1605
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1606
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1607
    check_ralign16( REG_EAX );
nkeynes@991
  1608
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1609
    store_reg( REG_EAX, 0 );
nkeynes@417
  1610
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1611
:}
nkeynes@361
  1612
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1613
    COUNT_INST(I_MOVW);
nkeynes@374
  1614
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1615
	SLOTILLEGAL();
nkeynes@374
  1616
    } else {
nkeynes@569
  1617
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  1618
	uint32_t target = pc + disp + 4;
nkeynes@569
  1619
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1620
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1621
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1622
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@569
  1623
	} else {
nkeynes@995
  1624
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1625
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1626
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@569
  1627
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  1628
	}
nkeynes@991
  1629
	store_reg( REG_EAX, Rn );
nkeynes@374
  1630
    }
nkeynes@361
  1631
:}
nkeynes@361
  1632
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1633
    COUNT_INST(I_MOVW);
nkeynes@991
  1634
    load_reg( REG_EAX, Rm );
nkeynes@991
  1635
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1636
    check_ralign16( REG_EAX );
nkeynes@991
  1637
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1638
    store_reg( REG_EAX, 0 );
nkeynes@417
  1639
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1640
:}
nkeynes@361
  1641
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1642
    COUNT_INST(I_MOVA);
nkeynes@374
  1643
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1644
	SLOTILLEGAL();
nkeynes@374
  1645
    } else {
nkeynes@995
  1646
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1647
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1648
	store_reg( REG_ECX, 0 );
nkeynes@571
  1649
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1650
    }
nkeynes@361
  1651
:}
nkeynes@361
  1652
MOVCA.L R0, @Rn {:  
nkeynes@671
  1653
    COUNT_INST(I_MOVCA);
nkeynes@991
  1654
    load_reg( REG_EAX, Rn );
nkeynes@991
  1655
    check_walign32( REG_EAX );
nkeynes@991
  1656
    load_reg( REG_EDX, 0 );
nkeynes@991
  1657
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1658
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1659
:}
nkeynes@359
  1660
nkeynes@359
  1661
/* Control transfer instructions */
nkeynes@374
  1662
BF disp {:
nkeynes@671
  1663
    COUNT_INST(I_BF);
nkeynes@374
  1664
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1665
	SLOTILLEGAL();
nkeynes@374
  1666
    } else {
nkeynes@571
  1667
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1668
	JT_label( nottaken );
nkeynes@571
  1669
	exit_block_rel(target, pc+2 );
nkeynes@380
  1670
	JMP_TARGET(nottaken);
nkeynes@408
  1671
	return 2;
nkeynes@374
  1672
    }
nkeynes@374
  1673
:}
nkeynes@374
  1674
BF/S disp {:
nkeynes@671
  1675
    COUNT_INST(I_BFS);
nkeynes@374
  1676
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1677
	SLOTILLEGAL();
nkeynes@374
  1678
    } else {
nkeynes@590
  1679
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1680
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1681
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1682
	    JT_label(nottaken);
nkeynes@991
  1683
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1684
	    JMP_TARGET(nottaken);
nkeynes@991
  1685
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1686
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1687
	    exit_block_emu(pc+2);
nkeynes@601
  1688
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1689
	    return 2;
nkeynes@601
  1690
	} else {
nkeynes@601
  1691
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1692
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1693
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1694
	    }
nkeynes@601
  1695
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1696
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1697
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1698
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1699
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1700
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1701
	    
nkeynes@601
  1702
	    // not taken
nkeynes@601
  1703
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1704
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1705
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1706
	    return 4;
nkeynes@417
  1707
	}
nkeynes@374
  1708
    }
nkeynes@374
  1709
:}
nkeynes@374
  1710
BRA disp {:  
nkeynes@671
  1711
    COUNT_INST(I_BRA);
nkeynes@374
  1712
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1713
	SLOTILLEGAL();
nkeynes@374
  1714
    } else {
nkeynes@590
  1715
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1716
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1717
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1718
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1719
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1720
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1721
	    exit_block_emu(pc+2);
nkeynes@601
  1722
	    return 2;
nkeynes@601
  1723
	} else {
nkeynes@601
  1724
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1725
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1726
	    return 4;
nkeynes@601
  1727
	}
nkeynes@374
  1728
    }
nkeynes@374
  1729
:}
nkeynes@374
  1730
BRAF Rn {:  
nkeynes@671
  1731
    COUNT_INST(I_BRAF);
nkeynes@374
  1732
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1733
	SLOTILLEGAL();
nkeynes@374
  1734
    } else {
nkeynes@995
  1735
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1736
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1737
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1738
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1739
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1740
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1741
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1742
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1743
	    exit_block_emu(pc+2);
nkeynes@601
  1744
	    return 2;
nkeynes@601
  1745
	} else {
nkeynes@601
  1746
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1747
	    exit_block_newpcset(pc+4);
nkeynes@601
  1748
	    return 4;
nkeynes@601
  1749
	}
nkeynes@374
  1750
    }
nkeynes@374
  1751
:}
nkeynes@374
  1752
BSR disp {:  
nkeynes@671
  1753
    COUNT_INST(I_BSR);
nkeynes@374
  1754
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1755
	SLOTILLEGAL();
nkeynes@374
  1756
    } else {
nkeynes@995
  1757
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1758
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1759
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  1760
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1761
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1762
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1763
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1764
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  1765
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1766
	    exit_block_emu(pc+2);
nkeynes@601
  1767
	    return 2;
nkeynes@601
  1768
	} else {
nkeynes@601
  1769
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1770
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1771
	    return 4;
nkeynes@601
  1772
	}
nkeynes@374
  1773
    }
nkeynes@374
  1774
:}
nkeynes@374
  1775
BSRF Rn {:  
nkeynes@671
  1776
    COUNT_INST(I_BSRF);
nkeynes@374
  1777
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1778
	SLOTILLEGAL();
nkeynes@374
  1779
    } else {
nkeynes@995
  1780
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1781
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1782
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1783
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1784
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1785
nkeynes@601
  1786
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1787
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1788
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1789
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1790
	    exit_block_emu(pc+2);
nkeynes@601
  1791
	    return 2;
nkeynes@601
  1792
	} else {
nkeynes@601
  1793
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1794
	    exit_block_newpcset(pc+4);
nkeynes@601
  1795
	    return 4;
nkeynes@601
  1796
	}
nkeynes@374
  1797
    }
nkeynes@374
  1798
:}
nkeynes@374
  1799
BT disp {:
nkeynes@671
  1800
    COUNT_INST(I_BT);
nkeynes@374
  1801
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1802
	SLOTILLEGAL();
nkeynes@374
  1803
    } else {
nkeynes@571
  1804
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1805
	JF_label( nottaken );
nkeynes@571
  1806
	exit_block_rel(target, pc+2 );
nkeynes@380
  1807
	JMP_TARGET(nottaken);
nkeynes@408
  1808
	return 2;
nkeynes@374
  1809
    }
nkeynes@374
  1810
:}
nkeynes@374
  1811
BT/S disp {:
nkeynes@671
  1812
    COUNT_INST(I_BTS);
nkeynes@374
  1813
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1814
	SLOTILLEGAL();
nkeynes@374
  1815
    } else {
nkeynes@590
  1816
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1817
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1818
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1819
	    JF_label(nottaken);
nkeynes@991
  1820
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1821
	    JMP_TARGET(nottaken);
nkeynes@991
  1822
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1823
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1824
	    exit_block_emu(pc+2);
nkeynes@601
  1825
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1826
	    return 2;
nkeynes@601
  1827
	} else {
nkeynes@601
  1828
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1829
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1830
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1831
	    }
nkeynes@991
  1832
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  1833
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  1834
nkeynes@879
  1835
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1836
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1837
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1838
	    // not taken
nkeynes@601
  1839
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1840
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1841
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1842
	    return 4;
nkeynes@417
  1843
	}
nkeynes@374
  1844
    }
nkeynes@374
  1845
:}
nkeynes@374
  1846
JMP @Rn {:  
nkeynes@671
  1847
    COUNT_INST(I_JMP);
nkeynes@374
  1848
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1849
	SLOTILLEGAL();
nkeynes@374
  1850
    } else {
nkeynes@991
  1851
	load_reg( REG_ECX, Rn );
nkeynes@995
  1852
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1853
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1854
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1855
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1856
	    exit_block_emu(pc+2);
nkeynes@601
  1857
	    return 2;
nkeynes@601
  1858
	} else {
nkeynes@601
  1859
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1860
	    exit_block_newpcset(pc+4);
nkeynes@601
  1861
	    return 4;
nkeynes@601
  1862
	}
nkeynes@374
  1863
    }
nkeynes@374
  1864
:}
nkeynes@374
  1865
JSR @Rn {:  
nkeynes@671
  1866
    COUNT_INST(I_JSR);
nkeynes@374
  1867
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1868
	SLOTILLEGAL();
nkeynes@374
  1869
    } else {
nkeynes@995
  1870
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1871
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1872
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1873
	load_reg( REG_ECX, Rn );
nkeynes@995
  1874
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  1875
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1876
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1877
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1878
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1879
	    exit_block_emu(pc+2);
nkeynes@601
  1880
	    return 2;
nkeynes@601
  1881
	} else {
nkeynes@601
  1882
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1883
	    exit_block_newpcset(pc+4);
nkeynes@601
  1884
	    return 4;
nkeynes@601
  1885
	}
nkeynes@374
  1886
    }
nkeynes@374
  1887
:}
nkeynes@374
  1888
RTE {:  
nkeynes@671
  1889
    COUNT_INST(I_RTE);
nkeynes@374
  1890
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1891
	SLOTILLEGAL();
nkeynes@374
  1892
    } else {
nkeynes@408
  1893
	check_priv();
nkeynes@995
  1894
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  1895
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  1896
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  1897
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  1898
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1899
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1900
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1901
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1902
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1903
	    exit_block_emu(pc+2);
nkeynes@601
  1904
	    return 2;
nkeynes@601
  1905
	} else {
nkeynes@601
  1906
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1907
	    exit_block_newpcset(pc+4);
nkeynes@601
  1908
	    return 4;
nkeynes@601
  1909
	}
nkeynes@374
  1910
    }
nkeynes@374
  1911
:}
nkeynes@374
  1912
RTS {:  
nkeynes@671
  1913
    COUNT_INST(I_RTS);
nkeynes@374
  1914
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1915
	SLOTILLEGAL();
nkeynes@374
  1916
    } else {
nkeynes@995
  1917
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  1918
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1919
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1920
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1921
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1922
	    exit_block_emu(pc+2);
nkeynes@601
  1923
	    return 2;
nkeynes@601
  1924
	} else {
nkeynes@601
  1925
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1926
	    exit_block_newpcset(pc+4);
nkeynes@601
  1927
	    return 4;
nkeynes@601
  1928
	}
nkeynes@374
  1929
    }
nkeynes@374
  1930
:}
nkeynes@374
  1931
TRAPA #imm {:  
nkeynes@671
  1932
    COUNT_INST(I_TRAPA);
nkeynes@374
  1933
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1934
	SLOTILLEGAL();
nkeynes@374
  1935
    } else {
nkeynes@995
  1936
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  1937
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  1938
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  1939
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  1940
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  1941
	exit_block_pcset(pc+2);
nkeynes@409
  1942
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1943
	return 2;
nkeynes@374
  1944
    }
nkeynes@374
  1945
:}
nkeynes@374
  1946
UNDEF {:  
nkeynes@671
  1947
    COUNT_INST(I_UNDEF);
nkeynes@374
  1948
    if( sh4_x86.in_delay_slot ) {
nkeynes@956
  1949
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
nkeynes@374
  1950
    } else {
nkeynes@956
  1951
	exit_block_exc(EXC_ILLEGAL, pc);    
nkeynes@408
  1952
	return 2;
nkeynes@374
  1953
    }
nkeynes@368
  1954
:}
nkeynes@374
  1955
nkeynes@374
  1956
CLRMAC {:  
nkeynes@671
  1957
    COUNT_INST(I_CLRMAC);
nkeynes@991
  1958
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  1959
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  1960
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  1961
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1962
:}
nkeynes@374
  1963
CLRS {:
nkeynes@671
  1964
    COUNT_INST(I_CLRS);
nkeynes@374
  1965
    CLC();
nkeynes@991
  1966
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1967
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1968
:}
nkeynes@374
  1969
CLRT {:  
nkeynes@671
  1970
    COUNT_INST(I_CLRT);
nkeynes@374
  1971
    CLC();
nkeynes@374
  1972
    SETC_t();
nkeynes@417
  1973
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1974
:}
nkeynes@374
  1975
SETS {:  
nkeynes@671
  1976
    COUNT_INST(I_SETS);
nkeynes@374
  1977
    STC();
nkeynes@991
  1978
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1979
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1980
:}
nkeynes@374
  1981
SETT {:  
nkeynes@671
  1982
    COUNT_INST(I_SETT);
nkeynes@374
  1983
    STC();
nkeynes@374
  1984
    SETC_t();
nkeynes@417
  1985
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1986
:}
nkeynes@359
  1987
nkeynes@375
  1988
/* Floating point moves */
nkeynes@375
  1989
FMOV FRm, FRn {:  
nkeynes@671
  1990
    COUNT_INST(I_FMOV1);
nkeynes@377
  1991
    check_fpuen();
nkeynes@901
  1992
    if( sh4_x86.double_size ) {
nkeynes@991
  1993
        load_dr0( REG_EAX, FRm );
nkeynes@991
  1994
        load_dr1( REG_ECX, FRm );
nkeynes@991
  1995
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1996
        store_dr1( REG_ECX, FRn );
nkeynes@901
  1997
    } else {
nkeynes@991
  1998
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  1999
        store_fr( REG_EAX, FRn );
nkeynes@375
  2000
    }
nkeynes@375
  2001
:}
nkeynes@416
  2002
FMOV FRm, @Rn {: 
nkeynes@671
  2003
    COUNT_INST(I_FMOV2);
nkeynes@559
  2004
    check_fpuen();
nkeynes@991
  2005
    load_reg( REG_EAX, Rn );
nkeynes@901
  2006
    if( sh4_x86.double_size ) {
nkeynes@991
  2007
        check_walign64( REG_EAX );
nkeynes@991
  2008
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2009
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2010
        load_reg( REG_EAX, Rn );
nkeynes@991
  2011
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2012
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2013
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@375
  2014
    } else {
nkeynes@991
  2015
        check_walign32( REG_EAX );
nkeynes@991
  2016
        load_fr( REG_EDX, FRm );
nkeynes@991
  2017
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@375
  2018
    }
nkeynes@417
  2019
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2020
:}
nkeynes@375
  2021
FMOV @Rm, FRn {:  
nkeynes@671
  2022
    COUNT_INST(I_FMOV5);
nkeynes@559
  2023
    check_fpuen();
nkeynes@991
  2024
    load_reg( REG_EAX, Rm );
nkeynes@901
  2025
    if( sh4_x86.double_size ) {
nkeynes@991
  2026
        check_ralign64( REG_EAX );
nkeynes@991
  2027
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2028
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2029
        load_reg( REG_EAX, Rm );
nkeynes@991
  2030
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2031
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2032
        store_dr1( REG_EAX, FRn );
nkeynes@375
  2033
    } else {
nkeynes@991
  2034
        check_ralign32( REG_EAX );
nkeynes@991
  2035
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2036
        store_fr( REG_EAX, FRn );
nkeynes@375
  2037
    }
nkeynes@417
  2038
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2039
:}
nkeynes@377
  2040
FMOV FRm, @-Rn {:  
nkeynes@671
  2041
    COUNT_INST(I_FMOV3);
nkeynes@559
  2042
    check_fpuen();
nkeynes@991
  2043
    load_reg( REG_EAX, Rn );
nkeynes@901
  2044
    if( sh4_x86.double_size ) {
nkeynes@991
  2045
        check_walign64( REG_EAX );
nkeynes@991
  2046
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2047
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2048
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2049
        load_reg( REG_EAX, Rn );
nkeynes@991
  2050
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2051
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2052
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2053
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@377
  2054
    } else {
nkeynes@991
  2055
        check_walign32( REG_EAX );
nkeynes@991
  2056
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2057
        load_fr( REG_EDX, FRm );
nkeynes@991
  2058
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2059
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@377
  2060
    }
nkeynes@417
  2061
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2062
:}
nkeynes@416
  2063
FMOV @Rm+, FRn {:
nkeynes@671
  2064
    COUNT_INST(I_FMOV6);
nkeynes@559
  2065
    check_fpuen();
nkeynes@991
  2066
    load_reg( REG_EAX, Rm );
nkeynes@901
  2067
    if( sh4_x86.double_size ) {
nkeynes@991
  2068
        check_ralign64( REG_EAX );
nkeynes@991
  2069
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2070
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2071
        load_reg( REG_EAX, Rm );
nkeynes@991
  2072
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2073
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2074
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2075
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@377
  2076
    } else {
nkeynes@991
  2077
        check_ralign32( REG_EAX );
nkeynes@991
  2078
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2079
        store_fr( REG_EAX, FRn );
nkeynes@991
  2080
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@377
  2081
    }
nkeynes@417
  2082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2083
:}
nkeynes@377
  2084
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2085
    COUNT_INST(I_FMOV4);
nkeynes@559
  2086
    check_fpuen();
nkeynes@991
  2087
    load_reg( REG_EAX, Rn );
nkeynes@991
  2088
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2089
    if( sh4_x86.double_size ) {
nkeynes@991
  2090
        check_walign64( REG_EAX );
nkeynes@991
  2091
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2092
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2093
        load_reg( REG_EAX, Rn );
nkeynes@991
  2094
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2095
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2096
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2097
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@377
  2098
    } else {
nkeynes@991
  2099
        check_walign32( REG_EAX );
nkeynes@991
  2100
        load_fr( REG_EDX, FRm );
nkeynes@991
  2101
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@377
  2102
    }
nkeynes@417
  2103
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2104
:}
nkeynes@377
  2105
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2106
    COUNT_INST(I_FMOV7);
nkeynes@559
  2107
    check_fpuen();
nkeynes@991
  2108
    load_reg( REG_EAX, Rm );
nkeynes@991
  2109
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2110
    if( sh4_x86.double_size ) {
nkeynes@991
  2111
        check_ralign64( REG_EAX );
nkeynes@991
  2112
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2113
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2114
        load_reg( REG_EAX, Rm );
nkeynes@991
  2115
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2116
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2117
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2118
        store_dr1( REG_EAX, FRn );
nkeynes@377
  2119
    } else {
nkeynes@991
  2120
        check_ralign32( REG_EAX );
nkeynes@991
  2121
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2122
        store_fr( REG_EAX, FRn );
nkeynes@377
  2123
    }
nkeynes@417
  2124
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2125
:}
nkeynes@377
  2126
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2127
    COUNT_INST(I_FLDI0);
nkeynes@377
  2128
    check_fpuen();
nkeynes@901
  2129
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2130
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2131
        store_fr( REG_EAX, FRn );
nkeynes@901
  2132
    }
nkeynes@417
  2133
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2134
:}
nkeynes@377
  2135
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2136
    COUNT_INST(I_FLDI1);
nkeynes@377
  2137
    check_fpuen();
nkeynes@901
  2138
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2139
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2140
        store_fr( REG_EAX, FRn );
nkeynes@901
  2141
    }
nkeynes@377
  2142
:}
nkeynes@377
  2143
nkeynes@377
  2144
FLOAT FPUL, FRn {:  
nkeynes@671
  2145
    COUNT_INST(I_FLOAT);
nkeynes@377
  2146
    check_fpuen();
nkeynes@991
  2147
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2148
    if( sh4_x86.double_prec ) {
nkeynes@901
  2149
        pop_dr( FRn );
nkeynes@901
  2150
    } else {
nkeynes@901
  2151
        pop_fr( FRn );
nkeynes@901
  2152
    }
nkeynes@377
  2153
:}
nkeynes@377
  2154
FTRC FRm, FPUL {:  
nkeynes@671
  2155
    COUNT_INST(I_FTRC);
nkeynes@377
  2156
    check_fpuen();
nkeynes@901
  2157
    if( sh4_x86.double_prec ) {
nkeynes@901
  2158
        push_dr( FRm );
nkeynes@901
  2159
    } else {
nkeynes@901
  2160
        push_fr( FRm );
nkeynes@901
  2161
    }
nkeynes@995
  2162
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2163
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2164
    FCOMIP_st(1);
nkeynes@991
  2165
    JNA_label( sat );
nkeynes@995
  2166
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@995
  2167
    FILD_r32disp( REG_ECX, 0 );
nkeynes@995
  2168
    FCOMIP_st(1);              
nkeynes@995
  2169
    JAE_label( sat2 );            
nkeynes@995
  2170
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2171
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2172
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2173
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2174
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2175
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2176
    JMP_label(end);             
nkeynes@388
  2177
nkeynes@388
  2178
    JMP_TARGET(sat);
nkeynes@388
  2179
    JMP_TARGET(sat2);
nkeynes@991
  2180
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2181
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2182
    FPOP_st();
nkeynes@388
  2183
    JMP_TARGET(end);
nkeynes@417
  2184
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2185
:}
nkeynes@377
  2186
FLDS FRm, FPUL {:  
nkeynes@671
  2187
    COUNT_INST(I_FLDS);
nkeynes@377
  2188
    check_fpuen();
nkeynes@991
  2189
    load_fr( REG_EAX, FRm );
nkeynes@995
  2190
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2191
:}
nkeynes@377
  2192
FSTS FPUL, FRn {:  
nkeynes@671
  2193
    COUNT_INST(I_FSTS);
nkeynes@377
  2194
    check_fpuen();
nkeynes@995
  2195
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2196
    store_fr( REG_EAX, FRn );
nkeynes@377
  2197
:}
nkeynes@377
  2198
FCNVDS FRm, FPUL {:  
nkeynes@671
  2199
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2200
    check_fpuen();
nkeynes@901
  2201
    if( sh4_x86.double_prec ) {
nkeynes@901
  2202
        push_dr( FRm );
nkeynes@901
  2203
        pop_fpul();
nkeynes@901
  2204
    }
nkeynes@377
  2205
:}
nkeynes@377
  2206
FCNVSD FPUL, FRn {:  
nkeynes@671
  2207
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2208
    check_fpuen();
nkeynes@901
  2209
    if( sh4_x86.double_prec ) {
nkeynes@901
  2210
        push_fpul();
nkeynes@901
  2211
        pop_dr( FRn );
nkeynes@901
  2212
    }
nkeynes@377
  2213
:}
nkeynes@375
  2214
nkeynes@359
  2215
/* Floating point instructions */
nkeynes@374
  2216
FABS FRn {:  
nkeynes@671
  2217
    COUNT_INST(I_FABS);
nkeynes@377
  2218
    check_fpuen();
nkeynes@901
  2219
    if( sh4_x86.double_prec ) {
nkeynes@901
  2220
        push_dr(FRn);
nkeynes@901
  2221
        FABS_st0();
nkeynes@901
  2222
        pop_dr(FRn);
nkeynes@901
  2223
    } else {
nkeynes@901
  2224
        push_fr(FRn);
nkeynes@901
  2225
        FABS_st0();
nkeynes@901
  2226
        pop_fr(FRn);
nkeynes@901
  2227
    }
nkeynes@374
  2228
:}
nkeynes@377
  2229
FADD FRm, FRn {:  
nkeynes@671
  2230
    COUNT_INST(I_FADD);
nkeynes@377
  2231
    check_fpuen();
nkeynes@901
  2232
    if( sh4_x86.double_prec ) {
nkeynes@901
  2233
        push_dr(FRm);
nkeynes@901
  2234
        push_dr(FRn);
nkeynes@901
  2235
        FADDP_st(1);
nkeynes@901
  2236
        pop_dr(FRn);
nkeynes@901
  2237
    } else {
nkeynes@901
  2238
        push_fr(FRm);
nkeynes@901
  2239
        push_fr(FRn);
nkeynes@901
  2240
        FADDP_st(1);
nkeynes@901
  2241
        pop_fr(FRn);
nkeynes@901
  2242
    }
nkeynes@375
  2243
:}
nkeynes@377
  2244
FDIV FRm, FRn {:  
nkeynes@671
  2245
    COUNT_INST(I_FDIV);
nkeynes@377
  2246
    check_fpuen();
nkeynes@901
  2247
    if( sh4_x86.double_prec ) {
nkeynes@901
  2248
        push_dr(FRn);
nkeynes@901
  2249
        push_dr(FRm);
nkeynes@901
  2250
        FDIVP_st(1);
nkeynes@901
  2251
        pop_dr(FRn);
nkeynes@901
  2252
    } else {
nkeynes@901
  2253
        push_fr(FRn);
nkeynes@901
  2254
        push_fr(FRm);
nkeynes@901
  2255
        FDIVP_st(1);
nkeynes@901
  2256
        pop_fr(FRn);
nkeynes@901
  2257
    }
nkeynes@375
  2258
:}
nkeynes@375
  2259
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2260
    COUNT_INST(I_FMAC);
nkeynes@377
  2261
    check_fpuen();
nkeynes@901
  2262
    if( sh4_x86.double_prec ) {
nkeynes@901
  2263
        push_dr( 0 );
nkeynes@901
  2264
        push_dr( FRm );
nkeynes@901
  2265
        FMULP_st(1);
nkeynes@901
  2266
        push_dr( FRn );
nkeynes@901
  2267
        FADDP_st(1);
nkeynes@901
  2268
        pop_dr( FRn );
nkeynes@901
  2269
    } else {
nkeynes@901
  2270
        push_fr( 0 );
nkeynes@901
  2271
        push_fr( FRm );
nkeynes@901
  2272
        FMULP_st(1);
nkeynes@901
  2273
        push_fr( FRn );
nkeynes@901
  2274
        FADDP_st(1);
nkeynes@901
  2275
        pop_fr( FRn );
nkeynes@901
  2276
    }
nkeynes@375
  2277
:}
nkeynes@375
  2278
nkeynes@377
  2279
FMUL FRm, FRn {:  
nkeynes@671
  2280
    COUNT_INST(I_FMUL);
nkeynes@377
  2281
    check_fpuen();
nkeynes@901
  2282
    if( sh4_x86.double_prec ) {
nkeynes@901
  2283
        push_dr(FRm);
nkeynes@901
  2284
        push_dr(FRn);
nkeynes@901
  2285
        FMULP_st(1);
nkeynes@901
  2286
        pop_dr(FRn);
nkeynes@901
  2287
    } else {
nkeynes@901
  2288
        push_fr(FRm);
nkeynes@901
  2289
        push_fr(FRn);
nkeynes@901
  2290
        FMULP_st(1);
nkeynes@901
  2291
        pop_fr(FRn);
nkeynes@901
  2292
    }
nkeynes@377
  2293
:}
nkeynes@377
  2294
FNEG FRn {:  
nkeynes@671
  2295
    COUNT_INST(I_FNEG);
nkeynes@377
  2296
    check_fpuen();
nkeynes@901
  2297
    if( sh4_x86.double_prec ) {
nkeynes@901
  2298
        push_dr(FRn);
nkeynes@901
  2299
        FCHS_st0();
nkeynes@901
  2300
        pop_dr(FRn);
nkeynes@901
  2301
    } else {
nkeynes@901
  2302
        push_fr(FRn);
nkeynes@901
  2303
        FCHS_st0();
nkeynes@901
  2304
        pop_fr(FRn);
nkeynes@901
  2305
    }
nkeynes@377
  2306
:}
nkeynes@377
  2307
FSRRA FRn {:  
nkeynes@671
  2308
    COUNT_INST(I_FSRRA);
nkeynes@377
  2309
    check_fpuen();
nkeynes@901
  2310
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2311
        FLD1_st0();
nkeynes@901
  2312
        push_fr(FRn);
nkeynes@901
  2313
        FSQRT_st0();
nkeynes@901
  2314
        FDIVP_st(1);
nkeynes@901
  2315
        pop_fr(FRn);
nkeynes@901
  2316
    }
nkeynes@377
  2317
:}
nkeynes@377
  2318
FSQRT FRn {:  
nkeynes@671
  2319
    COUNT_INST(I_FSQRT);
nkeynes@377
  2320
    check_fpuen();
nkeynes@901
  2321
    if( sh4_x86.double_prec ) {
nkeynes@901
  2322
        push_dr(FRn);
nkeynes@901
  2323
        FSQRT_st0();
nkeynes@901
  2324
        pop_dr(FRn);
nkeynes@901
  2325
    } else {
nkeynes@901
  2326
        push_fr(FRn);
nkeynes@901
  2327
        FSQRT_st0();
nkeynes@901
  2328
        pop_fr(FRn);
nkeynes@901
  2329
    }
nkeynes@377
  2330
:}
nkeynes@377
  2331
FSUB FRm, FRn {:  
nkeynes@671
  2332
    COUNT_INST(I_FSUB);
nkeynes@377
  2333
    check_fpuen();
nkeynes@901
  2334
    if( sh4_x86.double_prec ) {
nkeynes@901
  2335
        push_dr(FRn);
nkeynes@901
  2336
        push_dr(FRm);
nkeynes@901
  2337
        FSUBP_st(1);
nkeynes@901
  2338
        pop_dr(FRn);
nkeynes@901
  2339
    } else {
nkeynes@901
  2340
        push_fr(FRn);
nkeynes@901
  2341
        push_fr(FRm);
nkeynes@901
  2342
        FSUBP_st(1);
nkeynes@901
  2343
        pop_fr(FRn);
nkeynes@901
  2344
    }
nkeynes@377
  2345
:}
nkeynes@377
  2346
nkeynes@377
  2347
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2348
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2349
    check_fpuen();
nkeynes@901
  2350
    if( sh4_x86.double_prec ) {
nkeynes@901
  2351
        push_dr(FRm);
nkeynes@901
  2352
        push_dr(FRn);
nkeynes@901
  2353
    } else {
nkeynes@901
  2354
        push_fr(FRm);
nkeynes@901
  2355
        push_fr(FRn);
nkeynes@901
  2356
    }
nkeynes@377
  2357
    FCOMIP_st(1);
nkeynes@377
  2358
    SETE_t();
nkeynes@377
  2359
    FPOP_st();
nkeynes@901
  2360
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2361
:}
nkeynes@377
  2362
FCMP/GT FRm, FRn {:  
nkeynes@671
  2363
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2364
    check_fpuen();
nkeynes@901
  2365
    if( sh4_x86.double_prec ) {
nkeynes@901
  2366
        push_dr(FRm);
nkeynes@901
  2367
        push_dr(FRn);
nkeynes@901
  2368
    } else {
nkeynes@901
  2369
        push_fr(FRm);
nkeynes@901
  2370
        push_fr(FRn);
nkeynes@901
  2371
    }
nkeynes@377
  2372
    FCOMIP_st(1);
nkeynes@377
  2373
    SETA_t();
nkeynes@377
  2374
    FPOP_st();
nkeynes@901
  2375
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2376
:}
nkeynes@377
  2377
nkeynes@377
  2378
FSCA FPUL, FRn {:  
nkeynes@671
  2379
    COUNT_INST(I_FSCA);
nkeynes@377
  2380
    check_fpuen();
nkeynes@901
  2381
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2382
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2383
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2384
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2385
    }
nkeynes@417
  2386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2387
:}
nkeynes@377
  2388
FIPR FVm, FVn {:  
nkeynes@671
  2389
    COUNT_INST(I_FIPR);
nkeynes@377
  2390
    check_fpuen();
nkeynes@901
  2391
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2392
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2393
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2394
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2395
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2396
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2397
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2398
        } else {
nkeynes@904
  2399
            push_fr( FVm<<2 );
nkeynes@903
  2400
            push_fr( FVn<<2 );
nkeynes@903
  2401
            FMULP_st(1);
nkeynes@903
  2402
            push_fr( (FVm<<2)+1);
nkeynes@903
  2403
            push_fr( (FVn<<2)+1);
nkeynes@903
  2404
            FMULP_st(1);
nkeynes@903
  2405
            FADDP_st(1);
nkeynes@903
  2406
            push_fr( (FVm<<2)+2);
nkeynes@903
  2407
            push_fr( (FVn<<2)+2);
nkeynes@903
  2408
            FMULP_st(1);
nkeynes@903
  2409
            FADDP_st(1);
nkeynes@903
  2410
            push_fr( (FVm<<2)+3);
nkeynes@903
  2411
            push_fr( (FVn<<2)+3);
nkeynes@903
  2412
            FMULP_st(1);
nkeynes@903
  2413
            FADDP_st(1);
nkeynes@903
  2414
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2415
        }
nkeynes@901
  2416
    }
nkeynes@377
  2417
:}
nkeynes@377
  2418
FTRV XMTRX, FVn {:  
nkeynes@671
  2419
    COUNT_INST(I_FTRV);
nkeynes@377
  2420
    check_fpuen();
nkeynes@901
  2421
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2422
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2423
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2424
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2425
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2426
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2427
nkeynes@991
  2428
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2429
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2430
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2431
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2432
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2433
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2434
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2435
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2436
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2437
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2438
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2439
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2440
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2441
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2442
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2443
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2444
        } else {
nkeynes@991
  2445
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@995
  2446
            CALL1_ptr_r32( sh4_ftrv, REG_EAX );
nkeynes@903
  2447
        }
nkeynes@901
  2448
    }
nkeynes@417
  2449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2450
:}
nkeynes@377
  2451
nkeynes@377
  2452
FRCHG {:  
nkeynes@671
  2453
    COUNT_INST(I_FRCHG);
nkeynes@377
  2454
    check_fpuen();
nkeynes@991
  2455
    XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
nkeynes@995
  2456
    CALL_ptr( sh4_switch_fr_banks );
nkeynes@417
  2457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2458
:}
nkeynes@377
  2459
FSCHG {:  
nkeynes@671
  2460
    COUNT_INST(I_FSCHG);
nkeynes@377
  2461
    check_fpuen();
nkeynes@991
  2462
    XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
nkeynes@991
  2463
    XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2465
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2466
:}
nkeynes@359
  2467
nkeynes@359
  2468
/* Processor control instructions */
nkeynes@368
  2469
LDC Rm, SR {:
nkeynes@671
  2470
    COUNT_INST(I_LDCSR);
nkeynes@386
  2471
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2472
	SLOTILLEGAL();
nkeynes@386
  2473
    } else {
nkeynes@386
  2474
	check_priv();
nkeynes@991
  2475
	load_reg( REG_EAX, Rm );
nkeynes@995
  2476
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2477
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2478
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2479
	return 2;
nkeynes@386
  2480
    }
nkeynes@368
  2481
:}
nkeynes@359
  2482
LDC Rm, GBR {: 
nkeynes@671
  2483
    COUNT_INST(I_LDC);
nkeynes@991
  2484
    load_reg( REG_EAX, Rm );
nkeynes@995
  2485
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@359
  2486
:}
nkeynes@359
  2487
LDC Rm, VBR {:  
nkeynes@671
  2488
    COUNT_INST(I_LDC);
nkeynes@386
  2489
    check_priv();
nkeynes@991
  2490
    load_reg( REG_EAX, Rm );
nkeynes@995
  2491
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2492
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2493
:}
nkeynes@359
  2494
LDC Rm, SSR {:  
nkeynes@671
  2495
    COUNT_INST(I_LDC);
nkeynes@386
  2496
    check_priv();
nkeynes@991
  2497
    load_reg( REG_EAX, Rm );
nkeynes@995
  2498
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2499
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2500
:}
nkeynes@359
  2501
LDC Rm, SGR {:  
nkeynes@671
  2502
    COUNT_INST(I_LDC);
nkeynes@386
  2503
    check_priv();
nkeynes@991
  2504
    load_reg( REG_EAX, Rm );
nkeynes@995
  2505
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2507
:}
nkeynes@359
  2508
LDC Rm, SPC {:  
nkeynes@671
  2509
    COUNT_INST(I_LDC);
nkeynes@386
  2510
    check_priv();
nkeynes@991
  2511
    load_reg( REG_EAX, Rm );
nkeynes@995
  2512
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2514
:}
nkeynes@359
  2515
LDC Rm, DBR {:  
nkeynes@671
  2516
    COUNT_INST(I_LDC);
nkeynes@386
  2517
    check_priv();
nkeynes@991
  2518
    load_reg( REG_EAX, Rm );
nkeynes@995
  2519
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2520
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2521
:}
nkeynes@374
  2522
LDC Rm, Rn_BANK {:  
nkeynes@671
  2523
    COUNT_INST(I_LDC);
nkeynes@386
  2524
    check_priv();
nkeynes@991
  2525
    load_reg( REG_EAX, Rm );
nkeynes@995
  2526
    MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2527
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2528
:}
nkeynes@359
  2529
LDC.L @Rm+, GBR {:  
nkeynes@671
  2530
    COUNT_INST(I_LDCM);
nkeynes@991
  2531
    load_reg( REG_EAX, Rm );
nkeynes@991
  2532
    check_ralign32( REG_EAX );
nkeynes@991
  2533
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2534
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2535
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@417
  2536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2537
:}
nkeynes@368
  2538
LDC.L @Rm+, SR {:
nkeynes@671
  2539
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2540
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2541
	SLOTILLEGAL();
nkeynes@386
  2542
    } else {
nkeynes@559
  2543
	check_priv();
nkeynes@991
  2544
	load_reg( REG_EAX, Rm );
nkeynes@991
  2545
	check_ralign32( REG_EAX );
nkeynes@991
  2546
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2547
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2548
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2549
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2550
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2551
	return 2;
nkeynes@386
  2552
    }
nkeynes@359
  2553
:}
nkeynes@359
  2554
LDC.L @Rm+, VBR {:  
nkeynes@671
  2555
    COUNT_INST(I_LDCM);
nkeynes@559
  2556
    check_priv();
nkeynes@991
  2557
    load_reg( REG_EAX, Rm );
nkeynes@991
  2558
    check_ralign32( REG_EAX );
nkeynes@991
  2559
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2560
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2561
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2562
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2563
:}
nkeynes@359
  2564
LDC.L @Rm+, SSR {:
nkeynes@671
  2565
    COUNT_INST(I_LDCM);
nkeynes@559
  2566
    check_priv();
nkeynes@991
  2567
    load_reg( REG_EAX, Rm );
nkeynes@991
  2568
    check_ralign32( REG_EAX );
nkeynes@991
  2569
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2570
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2571
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2573
:}
nkeynes@359
  2574
LDC.L @Rm+, SGR {:  
nkeynes@671
  2575
    COUNT_INST(I_LDCM);
nkeynes@559
  2576
    check_priv();
nkeynes@991
  2577
    load_reg( REG_EAX, Rm );
nkeynes@991
  2578
    check_ralign32( REG_EAX );
nkeynes@991
  2579
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2580
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2581
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2582
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2583
:}
nkeynes@359
  2584
LDC.L @Rm+, SPC {:  
nkeynes@671
  2585
    COUNT_INST(I_LDCM);
nkeynes@559
  2586
    check_priv();
nkeynes@991
  2587
    load_reg( REG_EAX, Rm );
nkeynes@991
  2588
    check_ralign32( REG_EAX );
nkeynes@991
  2589
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2590
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2591
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2592
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2593
:}
nkeynes@359
  2594
LDC.L @Rm+, DBR {:  
nkeynes@671
  2595
    COUNT_INST(I_LDCM);
nkeynes@559
  2596
    check_priv();
nkeynes@991
  2597
    load_reg( REG_EAX, Rm );
nkeynes@991
  2598
    check_ralign32( REG_EAX );
nkeynes@991
  2599
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2600
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2601
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2603
:}
nkeynes@359
  2604
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2605
    COUNT_INST(I_LDCM);
nkeynes@559
  2606
    check_priv();
nkeynes@991
  2607
    load_reg( REG_EAX, Rm );
nkeynes@991
  2608
    check_ralign32( REG_EAX );
nkeynes@991
  2609
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2610
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2611
    MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2613
:}
nkeynes@626
  2614
LDS Rm, FPSCR {:
nkeynes@673
  2615
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2616
    check_fpuen();
nkeynes@991
  2617
    load_reg( REG_EAX, Rm );
nkeynes@995
  2618
    CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2620
    return 2;
nkeynes@359
  2621
:}
nkeynes@359
  2622
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2623
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2624
    check_fpuen();
nkeynes@991
  2625
    load_reg( REG_EAX, Rm );
nkeynes@991
  2626
    check_ralign32( REG_EAX );
nkeynes@991
  2627
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2628
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2629
    CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2630
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2631
    return 2;
nkeynes@359
  2632
:}
nkeynes@359
  2633
LDS Rm, FPUL {:  
nkeynes@671
  2634
    COUNT_INST(I_LDS);
nkeynes@626
  2635
    check_fpuen();
nkeynes@991
  2636
    load_reg( REG_EAX, Rm );
nkeynes@995
  2637
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@359
  2638
:}
nkeynes@359
  2639
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2640
    COUNT_INST(I_LDSM);
nkeynes@626
  2641
    check_fpuen();
nkeynes@991
  2642
    load_reg( REG_EAX, Rm );
nkeynes@991
  2643
    check_ralign32( REG_EAX );
nkeynes@991
  2644
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2645
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2646
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@417
  2647
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2648
:}
nkeynes@359
  2649
LDS Rm, MACH {: 
nkeynes@671
  2650
    COUNT_INST(I_LDS);
nkeynes@991
  2651
    load_reg( REG_EAX, Rm );
nkeynes@995
  2652
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@359
  2653
:}
nkeynes@359
  2654
LDS.L @Rm+, MACH {:  
nkeynes@671
  2655
    COUNT_INST(I_LDSM);
nkeynes@991
  2656
    load_reg( REG_EAX, Rm );
nkeynes@991
  2657
    check_ralign32( REG_EAX );
nkeynes@991
  2658
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2659
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2660
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2661
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2662
:}
nkeynes@359
  2663
LDS Rm, MACL {:  
nkeynes@671
  2664
    COUNT_INST(I_LDS);
nkeynes@991
  2665
    load_reg( REG_EAX, Rm );
nkeynes@995
  2666
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@359
  2667
:}
nkeynes@359
  2668
LDS.L @Rm+, MACL {:  
nkeynes@671
  2669
    COUNT_INST(I_LDSM);
nkeynes@991
  2670
    load_reg( REG_EAX, Rm );
nkeynes@991
  2671
    check_ralign32( REG_EAX );
nkeynes@991
  2672
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2673
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2674
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  2675
    sh4_x86.tstate = TSTATE_NONE;