nkeynes@23 | 1 | /**
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nkeynes@181 | 2 | * $Id: sh4core.c,v 1.29 2006-07-06 08:46:41 nkeynes Exp $
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nkeynes@23 | 3 | *
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nkeynes@23 | 4 | * SH4 emulation core, and parent module for all the SH4 peripheral
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nkeynes@23 | 5 | * modules.
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nkeynes@23 | 6 | *
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nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@23 | 8 | *
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nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@23 | 12 | * (at your option) any later version.
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nkeynes@23 | 13 | *
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nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@23 | 17 | * GNU General Public License for more details.
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nkeynes@23 | 18 | */
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nkeynes@23 | 19 |
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nkeynes@35 | 20 | #define MODULE sh4_module
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nkeynes@1 | 21 | #include <math.h>
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nkeynes@1 | 22 | #include "dream.h"
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nkeynes@84 | 23 | #include "sh4/sh4core.h"
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nkeynes@84 | 24 | #include "sh4/sh4mmio.h"
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nkeynes@84 | 25 | #include "sh4/intc.h"
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nkeynes@1 | 26 | #include "mem.h"
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nkeynes@23 | 27 | #include "clock.h"
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nkeynes@102 | 28 | #include "syscall.h"
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nkeynes@1 | 29 |
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nkeynes@157 | 30 | #define SH4_CALLTRACE 1
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nkeynes@157 | 31 |
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nkeynes@123 | 32 | #define MAX_INT 0x7FFFFFFF
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nkeynes@123 | 33 | #define MIN_INT 0x80000000
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nkeynes@123 | 34 | #define MAX_INTF 2147483647.0
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nkeynes@123 | 35 | #define MIN_INTF -2147483648.0
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nkeynes@123 | 36 |
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nkeynes@27 | 37 | /* CPU-generated exception code/vector pairs */
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nkeynes@27 | 38 | #define EXC_POWER_RESET 0x000 /* vector special */
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nkeynes@27 | 39 | #define EXC_MANUAL_RESET 0x020
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nkeynes@27 | 40 | #define EXC_SLOT_ILLEGAL 0x1A0
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nkeynes@27 | 41 | #define EXC_ILLEGAL 0x180
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nkeynes@27 | 42 | #define EXV_ILLEGAL 0x100
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nkeynes@27 | 43 | #define EXC_TRAP 0x160
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nkeynes@27 | 44 | #define EXV_TRAP 0x100
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nkeynes@27 | 45 | #define EXC_FPDISABLE 0x800
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nkeynes@27 | 46 | #define EXV_FPDISABLE 0x100
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nkeynes@27 | 47 |
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nkeynes@23 | 48 | /********************** SH4 Module Definition ****************************/
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nkeynes@23 | 49 |
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nkeynes@23 | 50 | void sh4_init( void );
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nkeynes@23 | 51 | void sh4_reset( void );
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nkeynes@30 | 52 | uint32_t sh4_run_slice( uint32_t );
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nkeynes@23 | 53 | void sh4_start( void );
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nkeynes@23 | 54 | void sh4_stop( void );
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nkeynes@23 | 55 | void sh4_save_state( FILE *f );
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nkeynes@23 | 56 | int sh4_load_state( FILE *f );
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nkeynes@16 | 57 |
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nkeynes@15 | 58 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
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nkeynes@23 | 59 | NULL, sh4_run_slice, sh4_stop,
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nkeynes@23 | 60 | sh4_save_state, sh4_load_state };
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nkeynes@15 | 61 |
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nkeynes@1 | 62 | struct sh4_registers sh4r;
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nkeynes@1 | 63 |
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nkeynes@1 | 64 | void sh4_init(void)
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nkeynes@1 | 65 | {
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nkeynes@1 | 66 | register_io_regions( mmio_list_sh4mmio );
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nkeynes@10 | 67 | mmu_init();
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nkeynes@27 | 68 | sh4_reset();
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nkeynes@1 | 69 | }
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nkeynes@1 | 70 |
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nkeynes@1 | 71 | void sh4_reset(void)
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nkeynes@1 | 72 | {
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nkeynes@19 | 73 | /* zero everything out, for the sake of having a consistent state. */
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nkeynes@19 | 74 | memset( &sh4r, 0, sizeof(sh4r) );
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nkeynes@27 | 75 |
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nkeynes@27 | 76 | /* Resume running if we were halted */
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nkeynes@27 | 77 | sh4r.sh4_state = SH4_STATE_RUNNING;
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nkeynes@27 | 78 |
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nkeynes@1 | 79 | sh4r.pc = 0xA0000000;
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nkeynes@1 | 80 | sh4r.new_pc= 0xA0000002;
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nkeynes@1 | 81 | sh4r.vbr = 0x00000000;
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nkeynes@1 | 82 | sh4r.fpscr = 0x00040001;
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nkeynes@1 | 83 | sh4r.sr = 0x700000F0;
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nkeynes@27 | 84 |
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nkeynes@27 | 85 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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nkeynes@27 | 86 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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nkeynes@27 | 87 |
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nkeynes@27 | 88 | /* Peripheral modules */
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nkeynes@157 | 89 | INTC_reset();
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nkeynes@157 | 90 | TMU_reset();
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nkeynes@32 | 91 | SCIF_reset();
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nkeynes@1 | 92 | }
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nkeynes@1 | 93 |
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nkeynes@43 | 94 | static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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nkeynes@43 | 95 | static int sh4_breakpoint_count = 0;
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nkeynes@43 | 96 |
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nkeynes@43 | 97 | void sh4_set_breakpoint( uint32_t pc, int type )
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nkeynes@43 | 98 | {
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nkeynes@43 | 99 | sh4_breakpoints[sh4_breakpoint_count].address = pc;
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nkeynes@43 | 100 | sh4_breakpoints[sh4_breakpoint_count].type = type;
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nkeynes@43 | 101 | sh4_breakpoint_count++;
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nkeynes@43 | 102 | }
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nkeynes@43 | 103 |
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nkeynes@43 | 104 | gboolean sh4_clear_breakpoint( uint32_t pc, int type )
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nkeynes@43 | 105 | {
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nkeynes@43 | 106 | int i;
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nkeynes@43 | 107 |
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nkeynes@43 | 108 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@43 | 109 | if( sh4_breakpoints[i].address == pc &&
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nkeynes@43 | 110 | sh4_breakpoints[i].type == type ) {
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nkeynes@43 | 111 | while( ++i < sh4_breakpoint_count ) {
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nkeynes@43 | 112 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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nkeynes@43 | 113 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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nkeynes@43 | 114 | }
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nkeynes@43 | 115 | sh4_breakpoint_count--;
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nkeynes@43 | 116 | return TRUE;
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nkeynes@43 | 117 | }
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nkeynes@43 | 118 | }
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nkeynes@43 | 119 | return FALSE;
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nkeynes@43 | 120 | }
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nkeynes@43 | 121 |
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nkeynes@43 | 122 | int sh4_get_breakpoint( uint32_t pc )
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nkeynes@43 | 123 | {
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nkeynes@43 | 124 | int i;
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nkeynes@43 | 125 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@43 | 126 | if( sh4_breakpoints[i].address == pc )
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nkeynes@43 | 127 | return sh4_breakpoints[i].type;
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nkeynes@43 | 128 | }
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nkeynes@43 | 129 | return 0;
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nkeynes@43 | 130 | }
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nkeynes@43 | 131 |
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nkeynes@30 | 132 | uint32_t sh4_run_slice( uint32_t nanosecs )
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nkeynes@1 | 133 | {
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nkeynes@30 | 134 | int target = sh4r.icount + nanosecs / sh4_cpu_period;
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nkeynes@27 | 135 | int start = sh4r.icount;
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nkeynes@23 | 136 | int i;
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nkeynes@23 | 137 |
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nkeynes@27 | 138 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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nkeynes@27 | 139 | if( sh4r.int_pending != 0 )
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nkeynes@27 | 140 | sh4r.sh4_state = SH4_STATE_RUNNING;;
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nkeynes@23 | 141 | }
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nkeynes@27 | 142 |
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nkeynes@53 | 143 | for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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nkeynes@27 | 144 | if( !sh4_execute_instruction() )
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nkeynes@27 | 145 | break;
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nkeynes@43 | 146 | #ifdef ENABLE_DEBUG_MODE
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nkeynes@43 | 147 | for( i=0; i<sh4_breakpoint_count; i++ ) {
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nkeynes@43 | 148 | if( sh4_breakpoints[i].address == sh4r.pc ) {
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nkeynes@43 | 149 | break;
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nkeynes@43 | 150 | }
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nkeynes@43 | 151 | }
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nkeynes@43 | 152 | if( i != sh4_breakpoint_count ) {
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nkeynes@43 | 153 | dreamcast_stop();
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nkeynes@43 | 154 | if( sh4_breakpoints[i].type == BREAK_ONESHOT )
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nkeynes@43 | 155 | sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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nkeynes@43 | 156 | break;
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nkeynes@43 | 157 | }
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nkeynes@43 | 158 | #endif
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nkeynes@27 | 159 | }
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nkeynes@30 | 160 |
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nkeynes@30 | 161 | /* If we aborted early, but the cpu is still technically running,
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nkeynes@30 | 162 | * we're doing a hard abort - cut the timeslice back to what we
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nkeynes@30 | 163 | * actually executed
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nkeynes@30 | 164 | */
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nkeynes@53 | 165 | if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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nkeynes@53 | 166 | nanosecs = sh4r.slice_cycle;
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nkeynes@27 | 167 | }
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nkeynes@27 | 168 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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nkeynes@30 | 169 | TMU_run_slice( nanosecs );
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nkeynes@30 | 170 | SCIF_run_slice( nanosecs );
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nkeynes@27 | 171 | }
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nkeynes@53 | 172 | sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
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nkeynes@30 | 173 | return nanosecs;
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nkeynes@1 | 174 | }
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nkeynes@1 | 175 |
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nkeynes@1 | 176 | void sh4_stop(void)
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nkeynes@1 | 177 | {
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nkeynes@27 | 178 |
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nkeynes@1 | 179 | }
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nkeynes@1 | 180 |
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nkeynes@23 | 181 | void sh4_save_state( FILE *f )
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nkeynes@16 | 182 | {
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nkeynes@16 | 183 | fwrite( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@157 | 184 | INTC_save_state( f );
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nkeynes@53 | 185 | TMU_save_state( f );
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nkeynes@23 | 186 | SCIF_save_state( f );
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nkeynes@16 | 187 | }
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nkeynes@16 | 188 |
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nkeynes@23 | 189 | int sh4_load_state( FILE * f )
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nkeynes@16 | 190 | {
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nkeynes@18 | 191 | fread( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@157 | 192 | INTC_load_state( f );
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nkeynes@53 | 193 | TMU_load_state( f );
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nkeynes@23 | 194 | return SCIF_load_state( f );
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nkeynes@16 | 195 | }
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nkeynes@16 | 196 |
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nkeynes@23 | 197 | /********************** SH4 emulation core ****************************/
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nkeynes@23 | 198 |
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nkeynes@23 | 199 | void sh4_set_pc( int pc )
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nkeynes@23 | 200 | {
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nkeynes@23 | 201 | sh4r.pc = pc;
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nkeynes@23 | 202 | sh4r.new_pc = pc+2;
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nkeynes@23 | 203 | }
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nkeynes@23 | 204 |
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nkeynes@104 | 205 | #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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nkeynes@27 | 206 | #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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nkeynes@1 | 207 |
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nkeynes@157 | 208 | #if(SH4_CALLTRACE == 1)
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nkeynes@157 | 209 | #define MAX_CALLSTACK 32
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nkeynes@157 | 210 | static struct call_stack {
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nkeynes@157 | 211 | sh4addr_t call_addr;
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nkeynes@157 | 212 | sh4addr_t target_addr;
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nkeynes@157 | 213 | sh4addr_t stack_pointer;
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nkeynes@157 | 214 | } call_stack[MAX_CALLSTACK];
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nkeynes@157 | 215 |
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nkeynes@157 | 216 | static int call_stack_depth = 0;
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nkeynes@157 | 217 | int sh4_call_trace_on = 0;
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nkeynes@157 | 218 |
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nkeynes@157 | 219 | static inline trace_call( sh4addr_t source, sh4addr_t dest )
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nkeynes@157 | 220 | {
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nkeynes@157 | 221 | if( call_stack_depth < MAX_CALLSTACK ) {
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nkeynes@157 | 222 | call_stack[call_stack_depth].call_addr = source;
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nkeynes@157 | 223 | call_stack[call_stack_depth].target_addr = dest;
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nkeynes@157 | 224 | call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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nkeynes@157 | 225 | }
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nkeynes@157 | 226 | call_stack_depth++;
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nkeynes@157 | 227 | }
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nkeynes@157 | 228 |
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nkeynes@157 | 229 | static inline trace_return( sh4addr_t source, sh4addr_t dest )
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nkeynes@157 | 230 | {
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nkeynes@157 | 231 | if( call_stack_depth > 0 ) {
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nkeynes@157 | 232 | call_stack_depth--;
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nkeynes@157 | 233 | }
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nkeynes@157 | 234 | }
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nkeynes@157 | 235 |
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nkeynes@157 | 236 | void fprint_stack_trace( FILE *f )
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nkeynes@157 | 237 | {
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nkeynes@157 | 238 | int i = call_stack_depth -1;
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nkeynes@157 | 239 | if( i >= MAX_CALLSTACK )
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nkeynes@157 | 240 | i = MAX_CALLSTACK - 1;
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nkeynes@157 | 241 | for( ; i >= 0; i-- ) {
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nkeynes@157 | 242 | fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
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nkeynes@157 | 243 | (call_stack_depth - i), call_stack[i].call_addr,
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nkeynes@157 | 244 | call_stack[i].target_addr, call_stack[i].stack_pointer );
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nkeynes@157 | 245 | }
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nkeynes@157 | 246 | }
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nkeynes@157 | 247 |
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nkeynes@157 | 248 | #define TRACE_CALL( source, dest ) trace_call(source, dest)
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nkeynes@157 | 249 | #define TRACE_RETURN( source, dest ) trace_return(source, dest)
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nkeynes@157 | 250 | #else
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nkeynes@157 | 251 | #define TRACE_CALL( dest, rts )
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nkeynes@157 | 252 | #define TRACE_RETURN( source, dest )
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nkeynes@157 | 253 | #endif
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nkeynes@157 | 254 |
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nkeynes@1 | 255 | #define RAISE( x, v ) do{ \
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nkeynes@1 | 256 | if( sh4r.vbr == 0 ) { \
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nkeynes@1 | 257 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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nkeynes@104 | 258 | dreamcast_stop(); return FALSE; \
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nkeynes@1 | 259 | } else { \
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nkeynes@1 | 260 | sh4r.spc = sh4r.pc + 2; \
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nkeynes@1 | 261 | sh4r.ssr = sh4_read_sr(); \
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nkeynes@1 | 262 | sh4r.sgr = sh4r.r[15]; \
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nkeynes@1 | 263 | MMIO_WRITE(MMU,EXPEVT,x); \
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nkeynes@1 | 264 | sh4r.pc = sh4r.vbr + v; \
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nkeynes@1 | 265 | sh4r.new_pc = sh4r.pc + 2; \
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nkeynes@1 | 266 | sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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nkeynes@1 | 267 | } \
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nkeynes@27 | 268 | return TRUE; } while(0)
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nkeynes@1 | 269 |
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nkeynes@10 | 270 | #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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nkeynes@10 | 271 | #define MEM_READ_WORD( addr ) sh4_read_word(addr)
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nkeynes@10 | 272 | #define MEM_READ_LONG( addr ) sh4_read_long(addr)
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nkeynes@10 | 273 | #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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nkeynes@10 | 274 | #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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nkeynes@10 | 275 | #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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nkeynes@1 | 276 |
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nkeynes@1 | 277 | #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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nkeynes@1 | 278 |
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nkeynes@124 | 279 | #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
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nkeynes@84 | 280 |
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nkeynes@124 | 281 | #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
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nkeynes@84 | 282 |
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nkeynes@1 | 283 | #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
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nkeynes@1 | 284 | #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
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nkeynes@1 | 285 | #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
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nkeynes@84 | 286 | #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
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nkeynes@2 | 287 | #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
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nkeynes@1 | 288 |
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nkeynes@1 | 289 | static void sh4_switch_banks( )
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nkeynes@1 | 290 | {
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nkeynes@1 | 291 | uint32_t tmp[8];
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nkeynes@1 | 292 |
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nkeynes@1 | 293 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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nkeynes@1 | 294 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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nkeynes@1 | 295 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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nkeynes@1 | 296 | }
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nkeynes@1 | 297 |
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nkeynes@1 | 298 | static void sh4_load_sr( uint32_t newval )
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nkeynes@1 | 299 | {
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nkeynes@1 | 300 | if( (newval ^ sh4r.sr) & SR_RB )
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nkeynes@1 | 301 | sh4_switch_banks();
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nkeynes@1 | 302 | sh4r.sr = newval;
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nkeynes@1 | 303 | sh4r.t = (newval&SR_T) ? 1 : 0;
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nkeynes@1 | 304 | sh4r.s = (newval&SR_S) ? 1 : 0;
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nkeynes@1 | 305 | sh4r.m = (newval&SR_M) ? 1 : 0;
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nkeynes@1 | 306 | sh4r.q = (newval&SR_Q) ? 1 : 0;
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nkeynes@1 | 307 | intc_mask_changed();
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nkeynes@1 | 308 | }
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nkeynes@1 | 309 |
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nkeynes@124 | 310 | static void sh4_write_float( uint32_t addr, int reg )
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nkeynes@124 | 311 | {
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nkeynes@124 | 312 | if( IS_FPU_DOUBLESIZE() ) {
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nkeynes@124 | 313 | if( reg & 1 ) {
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nkeynes@124 | 314 | sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
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nkeynes@124 | 315 | sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
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nkeynes@124 | 316 | } else {
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nkeynes@124 | 317 | sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
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nkeynes@124 | 318 | sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
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nkeynes@124 | 319 | }
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nkeynes@124 | 320 | } else {
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nkeynes@124 | 321 | sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
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nkeynes@124 | 322 | }
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nkeynes@124 | 323 | }
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nkeynes@124 | 324 |
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nkeynes@124 | 325 | static void sh4_read_float( uint32_t addr, int reg )
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nkeynes@124 | 326 | {
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nkeynes@124 | 327 | if( IS_FPU_DOUBLESIZE() ) {
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nkeynes@124 | 328 | if( reg & 1 ) {
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nkeynes@124 | 329 | *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
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nkeynes@124 | 330 | *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
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nkeynes@124 | 331 | } else {
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nkeynes@124 | 332 | *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
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nkeynes@124 | 333 | *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
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nkeynes@124 | 334 | }
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nkeynes@124 | 335 | } else {
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nkeynes@124 | 336 | *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
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nkeynes@124 | 337 | }
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nkeynes@124 | 338 | }
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nkeynes@124 | 339 |
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nkeynes@1 | 340 | static uint32_t sh4_read_sr( void )
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nkeynes@1 | 341 | {
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nkeynes@1 | 342 | /* synchronize sh4r.sr with the various bitflags */
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nkeynes@1 | 343 | sh4r.sr &= SR_MQSTMASK;
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nkeynes@1 | 344 | if( sh4r.t ) sh4r.sr |= SR_T;
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nkeynes@1 | 345 | if( sh4r.s ) sh4r.sr |= SR_S;
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nkeynes@1 | 346 | if( sh4r.m ) sh4r.sr |= SR_M;
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nkeynes@1 | 347 | if( sh4r.q ) sh4r.sr |= SR_Q;
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nkeynes@1 | 348 | return sh4r.sr;
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nkeynes@1 | 349 | }
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nkeynes@1 | 350 | /* function for external use */
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nkeynes@1 | 351 | void sh4_raise_exception( int code, int vector )
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nkeynes@1 | 352 | {
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nkeynes@1 | 353 | RAISE(code, vector);
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nkeynes@1 | 354 | }
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nkeynes@1 | 355 |
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nkeynes@1 | 356 | static void sh4_accept_interrupt( void )
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nkeynes@1 | 357 | {
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nkeynes@1 | 358 | uint32_t code = intc_accept_interrupt();
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nkeynes@1 | 359 | sh4r.ssr = sh4_read_sr();
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nkeynes@1 | 360 | sh4r.spc = sh4r.pc;
|
nkeynes@1 | 361 | sh4r.sgr = sh4r.r[15];
|
nkeynes@1 | 362 | sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
|
nkeynes@1 | 363 | MMIO_WRITE( MMU, INTEVT, code );
|
nkeynes@1 | 364 | sh4r.pc = sh4r.vbr + 0x600;
|
nkeynes@1 | 365 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@92 | 366 | // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
|
nkeynes@1 | 367 | }
|
nkeynes@1 | 368 |
|
nkeynes@27 | 369 | gboolean sh4_execute_instruction( void )
|
nkeynes@1 | 370 | {
|
nkeynes@84 | 371 | uint32_t pc;
|
nkeynes@2 | 372 | unsigned short ir;
|
nkeynes@1 | 373 | uint32_t tmp;
|
nkeynes@1 | 374 | uint64_t tmpl;
|
nkeynes@123 | 375 | float ftmp;
|
nkeynes@123 | 376 | double dtmp;
|
nkeynes@1 | 377 |
|
nkeynes@1 | 378 | #define R0 sh4r.r[0]
|
nkeynes@84 | 379 | #define FR0 FR(0)
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nkeynes@84 | 380 | #define DR0 DR(0)
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nkeynes@1 | 381 | #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
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nkeynes@1 | 382 | #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
|
nkeynes@1 | 383 | #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
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nkeynes@1 | 384 | #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
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nkeynes@1 | 385 | #define DISP8(ir) (ir&0x00FF)
|
nkeynes@1 | 386 | #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
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nkeynes@1 | 387 | #define IMM8(ir) SIGNEXT8(ir&0x00FF)
|
nkeynes@1 | 388 | #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
|
nkeynes@1 | 389 | #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
|
nkeynes@84 | 390 | #define FRNn(ir) ((ir&0x0F00)>>8)
|
nkeynes@84 | 391 | #define FRMn(ir) ((ir&0x00F0)>>4)
|
nkeynes@84 | 392 | #define DRNn(ir) ((ir&0x0E00)>>9)
|
nkeynes@84 | 393 | #define DRMn(ir) ((ir&0x00E0)>>5)
|
nkeynes@2 | 394 | #define FVN(ir) ((ir&0x0C00)>>8)
|
nkeynes@2 | 395 | #define FVM(ir) ((ir&0x0300)>>6)
|
nkeynes@84 | 396 | #define FRN(ir) FR(FRNn(ir))
|
nkeynes@84 | 397 | #define FRM(ir) FR(FRMn(ir))
|
nkeynes@84 | 398 | #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
|
nkeynes@84 | 399 | #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
|
nkeynes@95 | 400 | #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
|
nkeynes@95 | 401 | #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
|
nkeynes@84 | 402 | #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
|
nkeynes@84 | 403 | #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
|
nkeynes@1 | 404 | #define FPULf *((float *)&sh4r.fpul)
|
nkeynes@1 | 405 | #define FPULi (sh4r.fpul)
|
nkeynes@1 | 406 |
|
nkeynes@2 | 407 | if( SH4_INT_PENDING() )
|
nkeynes@2 | 408 | sh4_accept_interrupt();
|
nkeynes@1 | 409 |
|
nkeynes@2 | 410 | pc = sh4r.pc;
|
nkeynes@84 | 411 | if( pc > 0xFFFFFF00 ) {
|
nkeynes@84 | 412 | /* SYSCALL Magic */
|
nkeynes@102 | 413 | syscall_invoke( pc );
|
nkeynes@104 | 414 | sh4r.in_delay_slot = 0;
|
nkeynes@84 | 415 | pc = sh4r.pc = sh4r.pr;
|
nkeynes@84 | 416 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@84 | 417 | }
|
nkeynes@2 | 418 | ir = MEM_READ_WORD(pc);
|
nkeynes@1 | 419 | sh4r.icount++;
|
nkeynes@1 | 420 |
|
nkeynes@1 | 421 | switch( (ir&0xF000)>>12 ) {
|
nkeynes@1 | 422 | case 0: /* 0000nnnnmmmmxxxx */
|
nkeynes@1 | 423 | switch( ir&0x000F ) {
|
nkeynes@1 | 424 | case 2:
|
nkeynes@1 | 425 | switch( (ir&0x00F0)>>4 ) {
|
nkeynes@1 | 426 | case 0: /* STC SR, Rn */
|
nkeynes@1 | 427 | CHECKPRIV();
|
nkeynes@1 | 428 | RN(ir) = sh4_read_sr();
|
nkeynes@1 | 429 | break;
|
nkeynes@1 | 430 | case 1: /* STC GBR, Rn */
|
nkeynes@1 | 431 | RN(ir) = sh4r.gbr;
|
nkeynes@1 | 432 | break;
|
nkeynes@1 | 433 | case 2: /* STC VBR, Rn */
|
nkeynes@1 | 434 | CHECKPRIV();
|
nkeynes@1 | 435 | RN(ir) = sh4r.vbr;
|
nkeynes@1 | 436 | break;
|
nkeynes@1 | 437 | case 3: /* STC SSR, Rn */
|
nkeynes@1 | 438 | CHECKPRIV();
|
nkeynes@1 | 439 | RN(ir) = sh4r.ssr;
|
nkeynes@1 | 440 | break;
|
nkeynes@1 | 441 | case 4: /* STC SPC, Rn */
|
nkeynes@1 | 442 | CHECKPRIV();
|
nkeynes@1 | 443 | RN(ir) = sh4r.spc;
|
nkeynes@1 | 444 | break;
|
nkeynes@1 | 445 | case 8: case 9: case 10: case 11: case 12: case 13:
|
nkeynes@1 | 446 | case 14: case 15:/* STC Rm_bank, Rn */
|
nkeynes@1 | 447 | CHECKPRIV();
|
nkeynes@1 | 448 | RN(ir) = RN_BANK(ir);
|
nkeynes@1 | 449 | break;
|
nkeynes@1 | 450 | default: UNDEF(ir);
|
nkeynes@1 | 451 | }
|
nkeynes@1 | 452 | break;
|
nkeynes@1 | 453 | case 3:
|
nkeynes@1 | 454 | switch( (ir&0x00F0)>>4 ) {
|
nkeynes@1 | 455 | case 0: /* BSRF Rn */
|
nkeynes@1 | 456 | CHECKDEST( pc + 4 + RN(ir) );
|
nkeynes@2 | 457 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 458 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 459 | sh4r.pr = sh4r.pc + 4;
|
nkeynes@1 | 460 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 461 | sh4r.new_pc = pc + 4 + RN(ir);
|
nkeynes@157 | 462 | TRACE_CALL( pc, sh4r.new_pc );
|
nkeynes@27 | 463 | return TRUE;
|
nkeynes@1 | 464 | case 2: /* BRAF Rn */
|
nkeynes@1 | 465 | CHECKDEST( pc + 4 + RN(ir) );
|
nkeynes@2 | 466 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 467 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 468 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 469 | sh4r.new_pc = pc + 4 + RN(ir);
|
nkeynes@27 | 470 | return TRUE;
|
nkeynes@1 | 471 | case 8: /* PREF [Rn] */
|
nkeynes@2 | 472 | tmp = RN(ir);
|
nkeynes@2 | 473 | if( (tmp & 0xFC000000) == 0xE0000000 ) {
|
nkeynes@2 | 474 | /* Store queue operation */
|
nkeynes@2 | 475 | int queue = (tmp&0x20)>>2;
|
nkeynes@2 | 476 | int32_t *src = &sh4r.store_queue[queue];
|
nkeynes@2 | 477 | uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
|
nkeynes@2 | 478 | uint32_t target = tmp&0x03FFFFE0 | hi;
|
nkeynes@2 | 479 | mem_copy_to_sh4( target, src, 32 );
|
nkeynes@2 | 480 | }
|
nkeynes@2 | 481 | break;
|
nkeynes@1 | 482 | case 9: /* OCBI [Rn] */
|
nkeynes@1 | 483 | case 10:/* OCBP [Rn] */
|
nkeynes@1 | 484 | case 11:/* OCBWB [Rn] */
|
nkeynes@1 | 485 | /* anything? */
|
nkeynes@1 | 486 | break;
|
nkeynes@1 | 487 | case 12:/* MOVCA.L R0, [Rn] */
|
nkeynes@164 | 488 | tmp = RN(ir);
|
nkeynes@164 | 489 | MEM_WRITE_LONG( tmp, R0 );
|
nkeynes@164 | 490 | break;
|
nkeynes@1 | 491 | default: UNDEF(ir);
|
nkeynes@1 | 492 | }
|
nkeynes@1 | 493 | break;
|
nkeynes@1 | 494 | case 4: /* MOV.B Rm, [R0 + Rn] */
|
nkeynes@1 | 495 | MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 496 | break;
|
nkeynes@1 | 497 | case 5: /* MOV.W Rm, [R0 + Rn] */
|
nkeynes@1 | 498 | MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 499 | break;
|
nkeynes@1 | 500 | case 6: /* MOV.L Rm, [R0 + Rn] */
|
nkeynes@1 | 501 | MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 502 | break;
|
nkeynes@1 | 503 | case 7: /* MUL.L Rm, Rn */
|
nkeynes@2 | 504 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 505 | (RM(ir) * RN(ir));
|
nkeynes@1 | 506 | break;
|
nkeynes@1 | 507 | case 8:
|
nkeynes@1 | 508 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 509 | case 0: /* CLRT */
|
nkeynes@1 | 510 | sh4r.t = 0;
|
nkeynes@1 | 511 | break;
|
nkeynes@1 | 512 | case 1: /* SETT */
|
nkeynes@1 | 513 | sh4r.t = 1;
|
nkeynes@1 | 514 | break;
|
nkeynes@1 | 515 | case 2: /* CLRMAC */
|
nkeynes@1 | 516 | sh4r.mac = 0;
|
nkeynes@1 | 517 | break;
|
nkeynes@1 | 518 | case 3: /* LDTLB */
|
nkeynes@1 | 519 | break;
|
nkeynes@1 | 520 | case 4: /* CLRS */
|
nkeynes@1 | 521 | sh4r.s = 0;
|
nkeynes@1 | 522 | break;
|
nkeynes@1 | 523 | case 5: /* SETS */
|
nkeynes@1 | 524 | sh4r.s = 1;
|
nkeynes@1 | 525 | break;
|
nkeynes@1 | 526 | default: UNDEF(ir);
|
nkeynes@1 | 527 | }
|
nkeynes@1 | 528 | break;
|
nkeynes@1 | 529 | case 9:
|
nkeynes@1 | 530 | if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
|
nkeynes@1 | 531 | RN(ir) = sh4r.t;
|
nkeynes@1 | 532 | else if( ir == 0x0019 ) /* DIV0U */
|
nkeynes@1 | 533 | sh4r.m = sh4r.q = sh4r.t = 0;
|
nkeynes@1 | 534 | else if( ir == 0x0009 )
|
nkeynes@1 | 535 | /* NOP */;
|
nkeynes@1 | 536 | else UNDEF(ir);
|
nkeynes@1 | 537 | break;
|
nkeynes@1 | 538 | case 10:
|
nkeynes@1 | 539 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@1 | 540 | case 0: /* STS MACH, Rn */
|
nkeynes@1 | 541 | RN(ir) = sh4r.mac >> 32;
|
nkeynes@1 | 542 | break;
|
nkeynes@1 | 543 | case 1: /* STS MACL, Rn */
|
nkeynes@1 | 544 | RN(ir) = (uint32_t)sh4r.mac;
|
nkeynes@1 | 545 | break;
|
nkeynes@1 | 546 | case 2: /* STS PR, Rn */
|
nkeynes@1 | 547 | RN(ir) = sh4r.pr;
|
nkeynes@1 | 548 | break;
|
nkeynes@1 | 549 | case 3: /* STC SGR, Rn */
|
nkeynes@1 | 550 | CHECKPRIV();
|
nkeynes@1 | 551 | RN(ir) = sh4r.sgr;
|
nkeynes@1 | 552 | break;
|
nkeynes@1 | 553 | case 5:/* STS FPUL, Rn */
|
nkeynes@1 | 554 | RN(ir) = sh4r.fpul;
|
nkeynes@1 | 555 | break;
|
nkeynes@1 | 556 | case 6: /* STS FPSCR, Rn */
|
nkeynes@1 | 557 | RN(ir) = sh4r.fpscr;
|
nkeynes@1 | 558 | break;
|
nkeynes@1 | 559 | case 15:/* STC DBR, Rn */
|
nkeynes@1 | 560 | CHECKPRIV();
|
nkeynes@1 | 561 | RN(ir) = sh4r.dbr;
|
nkeynes@1 | 562 | break;
|
nkeynes@1 | 563 | default: UNDEF(ir);
|
nkeynes@1 | 564 | }
|
nkeynes@1 | 565 | break;
|
nkeynes@1 | 566 | case 11:
|
nkeynes@1 | 567 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 568 | case 0: /* RTS */
|
nkeynes@1 | 569 | CHECKDEST( sh4r.pr );
|
nkeynes@2 | 570 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 571 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 572 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 573 | sh4r.new_pc = sh4r.pr;
|
nkeynes@157 | 574 | TRACE_RETURN( pc, sh4r.new_pc );
|
nkeynes@27 | 575 | return TRUE;
|
nkeynes@1 | 576 | case 1: /* SLEEP */
|
nkeynes@27 | 577 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
|
nkeynes@27 | 578 | sh4r.sh4_state = SH4_STATE_STANDBY;
|
nkeynes@27 | 579 | } else {
|
nkeynes@27 | 580 | sh4r.sh4_state = SH4_STATE_SLEEP;
|
nkeynes@27 | 581 | }
|
nkeynes@27 | 582 | return FALSE; /* Halt CPU */
|
nkeynes@1 | 583 | case 2: /* RTE */
|
nkeynes@1 | 584 | CHECKPRIV();
|
nkeynes@1 | 585 | CHECKDEST( sh4r.spc );
|
nkeynes@2 | 586 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 587 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 588 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 589 | sh4r.new_pc = sh4r.spc;
|
nkeynes@1 | 590 | sh4_load_sr( sh4r.ssr );
|
nkeynes@27 | 591 | return TRUE;
|
nkeynes@1 | 592 | default:UNDEF(ir);
|
nkeynes@1 | 593 | }
|
nkeynes@1 | 594 | break;
|
nkeynes@1 | 595 | case 12:/* MOV.B [R0+R%d], R%d */
|
nkeynes@1 | 596 | RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
|
nkeynes@1 | 597 | break;
|
nkeynes@1 | 598 | case 13:/* MOV.W [R0+R%d], R%d */
|
nkeynes@1 | 599 | RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
|
nkeynes@1 | 600 | break;
|
nkeynes@1 | 601 | case 14:/* MOV.L [R0+R%d], R%d */
|
nkeynes@1 | 602 | RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
|
nkeynes@1 | 603 | break;
|
nkeynes@1 | 604 | case 15:/* MAC.L [Rm++], [Rn++] */
|
nkeynes@1 | 605 | tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
|
nkeynes@1 | 606 | SIGNEXT32(MEM_READ_LONG(RN(ir))) );
|
nkeynes@1 | 607 | if( sh4r.s ) {
|
nkeynes@1 | 608 | /* 48-bit Saturation. Yuch */
|
nkeynes@1 | 609 | tmpl += SIGNEXT48(sh4r.mac);
|
nkeynes@2 | 610 | if( tmpl < 0xFFFF800000000000LL )
|
nkeynes@2 | 611 | tmpl = 0xFFFF800000000000LL;
|
nkeynes@2 | 612 | else if( tmpl > 0x00007FFFFFFFFFFFLL )
|
nkeynes@2 | 613 | tmpl = 0x00007FFFFFFFFFFFLL;
|
nkeynes@2 | 614 | sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
|
nkeynes@2 | 615 | (tmpl&0x0000FFFFFFFFFFFFLL);
|
nkeynes@1 | 616 | } else sh4r.mac = tmpl;
|
nkeynes@1 | 617 |
|
nkeynes@1 | 618 | RM(ir) += 4;
|
nkeynes@1 | 619 | RN(ir) += 4;
|
nkeynes@1 | 620 |
|
nkeynes@1 | 621 | break;
|
nkeynes@1 | 622 | default: UNDEF(ir);
|
nkeynes@1 | 623 | }
|
nkeynes@1 | 624 | break;
|
nkeynes@1 | 625 | case 1: /* 0001nnnnmmmmdddd */
|
nkeynes@1 | 626 | /* MOV.L Rm, [Rn + disp4*4] */
|
nkeynes@1 | 627 | MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
|
nkeynes@1 | 628 | break;
|
nkeynes@1 | 629 | case 2: /* 0010nnnnmmmmxxxx */
|
nkeynes@1 | 630 | switch( ir&0x000F ) {
|
nkeynes@1 | 631 | case 0: /* MOV.B Rm, [Rn] */
|
nkeynes@1 | 632 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 633 | break;
|
nkeynes@1 | 634 | case 1: /* MOV.W Rm, [Rn] */
|
nkeynes@1 | 635 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 636 | break;
|
nkeynes@1 | 637 | case 2: /* MOV.L Rm, [Rn] */
|
nkeynes@1 | 638 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 639 | break;
|
nkeynes@1 | 640 | case 3: UNDEF(ir);
|
nkeynes@1 | 641 | break;
|
nkeynes@1 | 642 | case 4: /* MOV.B Rm, [--Rn] */
|
nkeynes@1 | 643 | RN(ir) --;
|
nkeynes@1 | 644 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 645 | break;
|
nkeynes@1 | 646 | case 5: /* MOV.W Rm, [--Rn] */
|
nkeynes@1 | 647 | RN(ir) -= 2;
|
nkeynes@1 | 648 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 649 | break;
|
nkeynes@1 | 650 | case 6: /* MOV.L Rm, [--Rn] */
|
nkeynes@1 | 651 | RN(ir) -= 4;
|
nkeynes@1 | 652 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 653 | break;
|
nkeynes@1 | 654 | case 7: /* DIV0S Rm, Rn */
|
nkeynes@1 | 655 | sh4r.q = RN(ir)>>31;
|
nkeynes@1 | 656 | sh4r.m = RM(ir)>>31;
|
nkeynes@1 | 657 | sh4r.t = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 658 | break;
|
nkeynes@1 | 659 | case 8: /* TST Rm, Rn */
|
nkeynes@1 | 660 | sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
|
nkeynes@1 | 661 | break;
|
nkeynes@1 | 662 | case 9: /* AND Rm, Rn */
|
nkeynes@1 | 663 | RN(ir) &= RM(ir);
|
nkeynes@1 | 664 | break;
|
nkeynes@1 | 665 | case 10:/* XOR Rm, Rn */
|
nkeynes@1 | 666 | RN(ir) ^= RM(ir);
|
nkeynes@1 | 667 | break;
|
nkeynes@1 | 668 | case 11:/* OR Rm, Rn */
|
nkeynes@1 | 669 | RN(ir) |= RM(ir);
|
nkeynes@1 | 670 | break;
|
nkeynes@1 | 671 | case 12:/* CMP/STR Rm, Rn */
|
nkeynes@1 | 672 | /* set T = 1 if any byte in RM & RN is the same */
|
nkeynes@1 | 673 | tmp = RM(ir) ^ RN(ir);
|
nkeynes@1 | 674 | sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
|
nkeynes@1 | 675 | (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
|
nkeynes@1 | 676 | break;
|
nkeynes@1 | 677 | case 13:/* XTRCT Rm, Rn */
|
nkeynes@1 | 678 | RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 679 | break;
|
nkeynes@1 | 680 | case 14:/* MULU.W Rm, Rn */
|
nkeynes@2 | 681 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 682 | (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
|
nkeynes@1 | 683 | break;
|
nkeynes@1 | 684 | case 15:/* MULS.W Rm, Rn */
|
nkeynes@2 | 685 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 686 | (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
|
nkeynes@1 | 687 | break;
|
nkeynes@1 | 688 | }
|
nkeynes@1 | 689 | break;
|
nkeynes@1 | 690 | case 3: /* 0011nnnnmmmmxxxx */
|
nkeynes@1 | 691 | switch( ir&0x000F ) {
|
nkeynes@1 | 692 | case 0: /* CMP/EQ Rm, Rn */
|
nkeynes@1 | 693 | sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
|
nkeynes@1 | 694 | break;
|
nkeynes@1 | 695 | case 2: /* CMP/HS Rm, Rn */
|
nkeynes@1 | 696 | sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
|
nkeynes@1 | 697 | break;
|
nkeynes@1 | 698 | case 3: /* CMP/GE Rm, Rn */
|
nkeynes@1 | 699 | sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 700 | break;
|
nkeynes@1 | 701 | case 4: { /* DIV1 Rm, Rn */
|
nkeynes@1 | 702 | /* This is just from the sh4p manual with some
|
nkeynes@1 | 703 | * simplifications (someone want to check it's correct? :)
|
nkeynes@1 | 704 | * Why they couldn't just provide a real DIV instruction...
|
nkeynes@1 | 705 | * Please oh please let the translator batch these things
|
nkeynes@1 | 706 | * up into a single DIV... */
|
nkeynes@1 | 707 | uint32_t tmp0, tmp1, tmp2, dir;
|
nkeynes@1 | 708 |
|
nkeynes@1 | 709 | dir = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 710 | sh4r.q = (RN(ir) >> 31);
|
nkeynes@1 | 711 | tmp2 = RM(ir);
|
nkeynes@1 | 712 | RN(ir) = (RN(ir) << 1) | sh4r.t;
|
nkeynes@1 | 713 | tmp0 = RN(ir);
|
nkeynes@1 | 714 | if( dir ) {
|
nkeynes@1 | 715 | RN(ir) += tmp2;
|
nkeynes@1 | 716 | tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
|
nkeynes@1 | 717 | } else {
|
nkeynes@1 | 718 | RN(ir) -= tmp2;
|
nkeynes@1 | 719 | tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
|
nkeynes@1 | 720 | }
|
nkeynes@1 | 721 | sh4r.q ^= sh4r.m ^ tmp1;
|
nkeynes@1 | 722 | sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
|
nkeynes@1 | 723 | break; }
|
nkeynes@1 | 724 | case 5: /* DMULU.L Rm, Rn */
|
nkeynes@1 | 725 | sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
|
nkeynes@1 | 726 | break;
|
nkeynes@1 | 727 | case 6: /* CMP/HI Rm, Rn */
|
nkeynes@1 | 728 | sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
|
nkeynes@1 | 729 | break;
|
nkeynes@1 | 730 | case 7: /* CMP/GT Rm, Rn */
|
nkeynes@1 | 731 | sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 732 | break;
|
nkeynes@1 | 733 | case 8: /* SUB Rm, Rn */
|
nkeynes@1 | 734 | RN(ir) -= RM(ir);
|
nkeynes@1 | 735 | break;
|
nkeynes@1 | 736 | case 10:/* SUBC Rm, Rn */
|
nkeynes@1 | 737 | tmp = RN(ir);
|
nkeynes@1 | 738 | RN(ir) = RN(ir) - RM(ir) - sh4r.t;
|
nkeynes@1 | 739 | sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
|
nkeynes@1 | 740 | break;
|
nkeynes@1 | 741 | case 11:/* SUBV Rm, Rn */
|
nkeynes@1 | 742 | UNIMP(ir);
|
nkeynes@1 | 743 | break;
|
nkeynes@1 | 744 | case 12:/* ADD Rm, Rn */
|
nkeynes@1 | 745 | RN(ir) += RM(ir);
|
nkeynes@1 | 746 | break;
|
nkeynes@1 | 747 | case 13:/* DMULS.L Rm, Rn */
|
nkeynes@1 | 748 | sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
|
nkeynes@1 | 749 | break;
|
nkeynes@1 | 750 | case 14:/* ADDC Rm, Rn */
|
nkeynes@1 | 751 | tmp = RN(ir);
|
nkeynes@1 | 752 | RN(ir) += RM(ir) + sh4r.t;
|
nkeynes@1 | 753 | sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
|
nkeynes@1 | 754 | break;
|
nkeynes@1 | 755 | case 15:/* ADDV Rm, Rn */
|
nkeynes@1 | 756 | UNIMP(ir);
|
nkeynes@1 | 757 | break;
|
nkeynes@1 | 758 | default: UNDEF(ir);
|
nkeynes@1 | 759 | }
|
nkeynes@1 | 760 | break;
|
nkeynes@1 | 761 | case 4: /* 0100nnnnxxxxxxxx */
|
nkeynes@1 | 762 | switch( ir&0x00FF ) {
|
nkeynes@1 | 763 | case 0x00: /* SHLL Rn */
|
nkeynes@1 | 764 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 765 | RN(ir) <<= 1;
|
nkeynes@1 | 766 | break;
|
nkeynes@1 | 767 | case 0x01: /* SHLR Rn */
|
nkeynes@1 | 768 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 769 | RN(ir) >>= 1;
|
nkeynes@1 | 770 | break;
|
nkeynes@1 | 771 | case 0x02: /* STS.L MACH, [--Rn] */
|
nkeynes@1 | 772 | RN(ir) -= 4;
|
nkeynes@1 | 773 | MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
|
nkeynes@1 | 774 | break;
|
nkeynes@1 | 775 | case 0x03: /* STC.L SR, [--Rn] */
|
nkeynes@1 | 776 | CHECKPRIV();
|
nkeynes@1 | 777 | RN(ir) -= 4;
|
nkeynes@1 | 778 | MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
|
nkeynes@1 | 779 | break;
|
nkeynes@1 | 780 | case 0x04: /* ROTL Rn */
|
nkeynes@1 | 781 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 782 | RN(ir) <<= 1;
|
nkeynes@1 | 783 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 784 | break;
|
nkeynes@1 | 785 | case 0x05: /* ROTR Rn */
|
nkeynes@1 | 786 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 787 | RN(ir) >>= 1;
|
nkeynes@1 | 788 | RN(ir) |= (sh4r.t << 31);
|
nkeynes@1 | 789 | break;
|
nkeynes@1 | 790 | case 0x06: /* LDS.L [Rn++], MACH */
|
nkeynes@1 | 791 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 792 | (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
|
nkeynes@1 | 793 | RN(ir) += 4;
|
nkeynes@1 | 794 | break;
|
nkeynes@1 | 795 | case 0x07: /* LDC.L [Rn++], SR */
|
nkeynes@1 | 796 | CHECKPRIV();
|
nkeynes@1 | 797 | sh4_load_sr( MEM_READ_LONG(RN(ir)) );
|
nkeynes@1 | 798 | RN(ir) +=4;
|
nkeynes@1 | 799 | break;
|
nkeynes@1 | 800 | case 0x08: /* SHLL2 Rn */
|
nkeynes@1 | 801 | RN(ir) <<= 2;
|
nkeynes@1 | 802 | break;
|
nkeynes@1 | 803 | case 0x09: /* SHLR2 Rn */
|
nkeynes@1 | 804 | RN(ir) >>= 2;
|
nkeynes@1 | 805 | break;
|
nkeynes@1 | 806 | case 0x0A: /* LDS Rn, MACH */
|
nkeynes@1 | 807 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 808 | (((uint64_t)RN(ir))<<32);
|
nkeynes@1 | 809 | break;
|
nkeynes@1 | 810 | case 0x0B: /* JSR [Rn] */
|
nkeynes@1 | 811 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 812 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 813 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 814 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 815 | sh4r.new_pc = RN(ir);
|
nkeynes@1 | 816 | sh4r.pr = pc + 4;
|
nkeynes@157 | 817 | TRACE_CALL( pc, sh4r.new_pc );
|
nkeynes@27 | 818 | return TRUE;
|
nkeynes@1 | 819 | case 0x0E: /* LDC Rn, SR */
|
nkeynes@1 | 820 | CHECKPRIV();
|
nkeynes@1 | 821 | sh4_load_sr( RN(ir) );
|
nkeynes@1 | 822 | break;
|
nkeynes@1 | 823 | case 0x10: /* DT Rn */
|
nkeynes@1 | 824 | RN(ir) --;
|
nkeynes@1 | 825 | sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
|
nkeynes@1 | 826 | break;
|
nkeynes@1 | 827 | case 0x11: /* CMP/PZ Rn */
|
nkeynes@1 | 828 | sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
|
nkeynes@1 | 829 | break;
|
nkeynes@1 | 830 | case 0x12: /* STS.L MACL, [--Rn] */
|
nkeynes@1 | 831 | RN(ir) -= 4;
|
nkeynes@1 | 832 | MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
|
nkeynes@1 | 833 | break;
|
nkeynes@1 | 834 | case 0x13: /* STC.L GBR, [--Rn] */
|
nkeynes@1 | 835 | RN(ir) -= 4;
|
nkeynes@1 | 836 | MEM_WRITE_LONG( RN(ir), sh4r.gbr );
|
nkeynes@1 | 837 | break;
|
nkeynes@1 | 838 | case 0x15: /* CMP/PL Rn */
|
nkeynes@1 | 839 | sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
|
nkeynes@1 | 840 | break;
|
nkeynes@1 | 841 | case 0x16: /* LDS.L [Rn++], MACL */
|
nkeynes@2 | 842 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 843 | (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
|
nkeynes@1 | 844 | RN(ir) += 4;
|
nkeynes@1 | 845 | break;
|
nkeynes@1 | 846 | case 0x17: /* LDC.L [Rn++], GBR */
|
nkeynes@1 | 847 | sh4r.gbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 848 | RN(ir) +=4;
|
nkeynes@1 | 849 | break;
|
nkeynes@1 | 850 | case 0x18: /* SHLL8 Rn */
|
nkeynes@1 | 851 | RN(ir) <<= 8;
|
nkeynes@1 | 852 | break;
|
nkeynes@1 | 853 | case 0x19: /* SHLR8 Rn */
|
nkeynes@1 | 854 | RN(ir) >>= 8;
|
nkeynes@1 | 855 | break;
|
nkeynes@1 | 856 | case 0x1A: /* LDS Rn, MACL */
|
nkeynes@2 | 857 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 858 | (uint64_t)((uint32_t)(RN(ir)));
|
nkeynes@1 | 859 | break;
|
nkeynes@1 | 860 | case 0x1B: /* TAS.B [Rn] */
|
nkeynes@1 | 861 | tmp = MEM_READ_BYTE( RN(ir) );
|
nkeynes@1 | 862 | sh4r.t = ( tmp == 0 ? 1 : 0 );
|
nkeynes@1 | 863 | MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
|
nkeynes@1 | 864 | break;
|
nkeynes@1 | 865 | case 0x1E: /* LDC Rn, GBR */
|
nkeynes@1 | 866 | sh4r.gbr = RN(ir);
|
nkeynes@1 | 867 | break;
|
nkeynes@1 | 868 | case 0x20: /* SHAL Rn */
|
nkeynes@1 | 869 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 870 | RN(ir) <<= 1;
|
nkeynes@1 | 871 | break;
|
nkeynes@1 | 872 | case 0x21: /* SHAR Rn */
|
nkeynes@1 | 873 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 874 | RN(ir) = ((int32_t)RN(ir)) >> 1;
|
nkeynes@1 | 875 | break;
|
nkeynes@1 | 876 | case 0x22: /* STS.L PR, [--Rn] */
|
nkeynes@1 | 877 | RN(ir) -= 4;
|
nkeynes@1 | 878 | MEM_WRITE_LONG( RN(ir), sh4r.pr );
|
nkeynes@1 | 879 | break;
|
nkeynes@1 | 880 | case 0x23: /* STC.L VBR, [--Rn] */
|
nkeynes@1 | 881 | CHECKPRIV();
|
nkeynes@1 | 882 | RN(ir) -= 4;
|
nkeynes@2 | 883 | MEM_WRITE_LONG( RN(ir), sh4r.vbr );
|
nkeynes@1 | 884 | break;
|
nkeynes@1 | 885 | case 0x24: /* ROTCL Rn */
|
nkeynes@1 | 886 | tmp = RN(ir) >> 31;
|
nkeynes@1 | 887 | RN(ir) <<= 1;
|
nkeynes@1 | 888 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 889 | sh4r.t = tmp;
|
nkeynes@1 | 890 | break;
|
nkeynes@1 | 891 | case 0x25: /* ROTCR Rn */
|
nkeynes@1 | 892 | tmp = RN(ir) & 0x00000001;
|
nkeynes@1 | 893 | RN(ir) >>= 1;
|
nkeynes@1 | 894 | RN(ir) |= (sh4r.t << 31 );
|
nkeynes@1 | 895 | sh4r.t = tmp;
|
nkeynes@1 | 896 | break;
|
nkeynes@1 | 897 | case 0x26: /* LDS.L [Rn++], PR */
|
nkeynes@1 | 898 | sh4r.pr = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 899 | RN(ir) += 4;
|
nkeynes@1 | 900 | break;
|
nkeynes@1 | 901 | case 0x27: /* LDC.L [Rn++], VBR */
|
nkeynes@1 | 902 | CHECKPRIV();
|
nkeynes@1 | 903 | sh4r.vbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 904 | RN(ir) +=4;
|
nkeynes@1 | 905 | break;
|
nkeynes@1 | 906 | case 0x28: /* SHLL16 Rn */
|
nkeynes@1 | 907 | RN(ir) <<= 16;
|
nkeynes@1 | 908 | break;
|
nkeynes@1 | 909 | case 0x29: /* SHLR16 Rn */
|
nkeynes@1 | 910 | RN(ir) >>= 16;
|
nkeynes@1 | 911 | break;
|
nkeynes@1 | 912 | case 0x2A: /* LDS Rn, PR */
|
nkeynes@1 | 913 | sh4r.pr = RN(ir);
|
nkeynes@1 | 914 | break;
|
nkeynes@1 | 915 | case 0x2B: /* JMP [Rn] */
|
nkeynes@1 | 916 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 917 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 918 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 919 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 920 | sh4r.new_pc = RN(ir);
|
nkeynes@27 | 921 | return TRUE;
|
nkeynes@1 | 922 | case 0x2E: /* LDC Rn, VBR */
|
nkeynes@1 | 923 | CHECKPRIV();
|
nkeynes@1 | 924 | sh4r.vbr = RN(ir);
|
nkeynes@1 | 925 | break;
|
nkeynes@1 | 926 | case 0x32: /* STC.L SGR, [--Rn] */
|
nkeynes@1 | 927 | CHECKPRIV();
|
nkeynes@1 | 928 | RN(ir) -= 4;
|
nkeynes@1 | 929 | MEM_WRITE_LONG( RN(ir), sh4r.sgr );
|
nkeynes@1 | 930 | break;
|
nkeynes@1 | 931 | case 0x33: /* STC.L SSR, [--Rn] */
|
nkeynes@1 | 932 | CHECKPRIV();
|
nkeynes@1 | 933 | RN(ir) -= 4;
|
nkeynes@1 | 934 | MEM_WRITE_LONG( RN(ir), sh4r.ssr );
|
nkeynes@1 | 935 | break;
|
nkeynes@1 | 936 | case 0x37: /* LDC.L [Rn++], SSR */
|
nkeynes@1 | 937 | CHECKPRIV();
|
nkeynes@1 | 938 | sh4r.ssr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 939 | RN(ir) +=4;
|
nkeynes@1 | 940 | break;
|
nkeynes@1 | 941 | case 0x3E: /* LDC Rn, SSR */
|
nkeynes@1 | 942 | CHECKPRIV();
|
nkeynes@1 | 943 | sh4r.ssr = RN(ir);
|
nkeynes@1 | 944 | break;
|
nkeynes@1 | 945 | case 0x43: /* STC.L SPC, [--Rn] */
|
nkeynes@1 | 946 | CHECKPRIV();
|
nkeynes@1 | 947 | RN(ir) -= 4;
|
nkeynes@1 | 948 | MEM_WRITE_LONG( RN(ir), sh4r.spc );
|
nkeynes@1 | 949 | break;
|
nkeynes@1 | 950 | case 0x47: /* LDC.L [Rn++], SPC */
|
nkeynes@1 | 951 | CHECKPRIV();
|
nkeynes@1 | 952 | sh4r.spc = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 953 | RN(ir) +=4;
|
nkeynes@1 | 954 | break;
|
nkeynes@1 | 955 | case 0x4E: /* LDC Rn, SPC */
|
nkeynes@1 | 956 | CHECKPRIV();
|
nkeynes@1 | 957 | sh4r.spc = RN(ir);
|
nkeynes@1 | 958 | break;
|
nkeynes@1 | 959 | case 0x52: /* STS.L FPUL, [--Rn] */
|
nkeynes@1 | 960 | RN(ir) -= 4;
|
nkeynes@1 | 961 | MEM_WRITE_LONG( RN(ir), sh4r.fpul );
|
nkeynes@1 | 962 | break;
|
nkeynes@1 | 963 | case 0x56: /* LDS.L [Rn++], FPUL */
|
nkeynes@1 | 964 | sh4r.fpul = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 965 | RN(ir) +=4;
|
nkeynes@1 | 966 | break;
|
nkeynes@1 | 967 | case 0x5A: /* LDS Rn, FPUL */
|
nkeynes@1 | 968 | sh4r.fpul = RN(ir);
|
nkeynes@1 | 969 | break;
|
nkeynes@1 | 970 | case 0x62: /* STS.L FPSCR, [--Rn] */
|
nkeynes@1 | 971 | RN(ir) -= 4;
|
nkeynes@1 | 972 | MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
|
nkeynes@1 | 973 | break;
|
nkeynes@1 | 974 | case 0x66: /* LDS.L [Rn++], FPSCR */
|
nkeynes@1 | 975 | sh4r.fpscr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 976 | RN(ir) +=4;
|
nkeynes@1 | 977 | break;
|
nkeynes@1 | 978 | case 0x6A: /* LDS Rn, FPSCR */
|
nkeynes@1 | 979 | sh4r.fpscr = RN(ir);
|
nkeynes@1 | 980 | break;
|
nkeynes@1 | 981 | case 0xF2: /* STC.L DBR, [--Rn] */
|
nkeynes@1 | 982 | CHECKPRIV();
|
nkeynes@1 | 983 | RN(ir) -= 4;
|
nkeynes@1 | 984 | MEM_WRITE_LONG( RN(ir), sh4r.dbr );
|
nkeynes@1 | 985 | break;
|
nkeynes@1 | 986 | case 0xF6: /* LDC.L [Rn++], DBR */
|
nkeynes@1 | 987 | CHECKPRIV();
|
nkeynes@1 | 988 | sh4r.dbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 989 | RN(ir) +=4;
|
nkeynes@1 | 990 | break;
|
nkeynes@1 | 991 | case 0xFA: /* LDC Rn, DBR */
|
nkeynes@1 | 992 | CHECKPRIV();
|
nkeynes@1 | 993 | sh4r.dbr = RN(ir);
|
nkeynes@1 | 994 | break;
|
nkeynes@1 | 995 | case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
|
nkeynes@1 | 996 | case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
|
nkeynes@1 | 997 | CHECKPRIV();
|
nkeynes@1 | 998 | RN(ir) -= 4;
|
nkeynes@1 | 999 | MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
|
nkeynes@1 | 1000 | break;
|
nkeynes@1 | 1001 | case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
|
nkeynes@1 | 1002 | case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
|
nkeynes@1 | 1003 | CHECKPRIV();
|
nkeynes@1 | 1004 | RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 1005 | RN(ir) += 4;
|
nkeynes@1 | 1006 | break;
|
nkeynes@1 | 1007 | case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
|
nkeynes@1 | 1008 | case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
|
nkeynes@1 | 1009 | CHECKPRIV();
|
nkeynes@1 | 1010 | RN_BANK(ir) = RM(ir);
|
nkeynes@1 | 1011 | break;
|
nkeynes@1 | 1012 | default:
|
nkeynes@1 | 1013 | if( (ir&0x000F) == 0x0F ) {
|
nkeynes@1 | 1014 | /* MAC.W [Rm++], [Rn++] */
|
nkeynes@1 | 1015 | tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
|
nkeynes@1 | 1016 | SIGNEXT16(MEM_READ_WORD(RN(ir)));
|
nkeynes@1 | 1017 | if( sh4r.s ) {
|
nkeynes@1 | 1018 | /* FIXME */
|
nkeynes@1 | 1019 | UNIMP(ir);
|
nkeynes@1 | 1020 | } else sh4r.mac += SIGNEXT32(tmp);
|
nkeynes@1 | 1021 | RM(ir) += 2;
|
nkeynes@1 | 1022 | RN(ir) += 2;
|
nkeynes@1 | 1023 | } else if( (ir&0x000F) == 0x0C ) {
|
nkeynes@1 | 1024 | /* SHAD Rm, Rn */
|
nkeynes@1 | 1025 | tmp = RM(ir);
|
nkeynes@1 | 1026 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@9 | 1027 | else if( (tmp & 0x1F) == 0 )
|
nkeynes@9 | 1028 | RN(ir) = ((int32_t)RN(ir)) >> 31;
|
nkeynes@9 | 1029 | else
|
nkeynes@9 | 1030 | RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
|
nkeynes@1 | 1031 | } else if( (ir&0x000F) == 0x0D ) {
|
nkeynes@1 | 1032 | /* SHLD Rm, Rn */
|
nkeynes@1 | 1033 | tmp = RM(ir);
|
nkeynes@1 | 1034 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@1 | 1035 | else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
|
nkeynes@1 | 1036 | else RN(ir) >>= (((~tmp) & 0x1F)+1);
|
nkeynes@1 | 1037 | } else UNDEF(ir);
|
nkeynes@1 | 1038 | }
|
nkeynes@1 | 1039 | break;
|
nkeynes@1 | 1040 | case 5: /* 0101nnnnmmmmdddd */
|
nkeynes@1 | 1041 | /* MOV.L [Rm + disp4*4], Rn */
|
nkeynes@1 | 1042 | RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
|
nkeynes@1 | 1043 | break;
|
nkeynes@1 | 1044 | case 6: /* 0110xxxxxxxxxxxx */
|
nkeynes@1 | 1045 | switch( ir&0x000f ) {
|
nkeynes@1 | 1046 | case 0: /* MOV.B [Rm], Rn */
|
nkeynes@1 | 1047 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 1048 | break;
|
nkeynes@1 | 1049 | case 1: /* MOV.W [Rm], Rn */
|
nkeynes@1 | 1050 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 1051 | break;
|
nkeynes@1 | 1052 | case 2: /* MOV.L [Rm], Rn */
|
nkeynes@1 | 1053 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 1054 | break;
|
nkeynes@1 | 1055 | case 3: /* MOV Rm, Rn */
|
nkeynes@1 | 1056 | RN(ir) = RM(ir);
|
nkeynes@1 | 1057 | break;
|
nkeynes@1 | 1058 | case 4: /* MOV.B [Rm++], Rn */
|
nkeynes@1 | 1059 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 1060 | RM(ir) ++;
|
nkeynes@1 | 1061 | break;
|
nkeynes@1 | 1062 | case 5: /* MOV.W [Rm++], Rn */
|
nkeynes@1 | 1063 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 1064 | RM(ir) += 2;
|
nkeynes@1 | 1065 | break;
|
nkeynes@1 | 1066 | case 6: /* MOV.L [Rm++], Rn */
|
nkeynes@1 | 1067 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 1068 | RM(ir) += 4;
|
nkeynes@1 | 1069 | break;
|
nkeynes@1 | 1070 | case 7: /* NOT Rm, Rn */
|
nkeynes@1 | 1071 | RN(ir) = ~RM(ir);
|
nkeynes@1 | 1072 | break;
|
nkeynes@1 | 1073 | case 8: /* SWAP.B Rm, Rn */
|
nkeynes@1 | 1074 | RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
|
nkeynes@1 | 1075 | ((RM(ir)&0x000000FF)<<8);
|
nkeynes@1 | 1076 | break;
|
nkeynes@1 | 1077 | case 9: /* SWAP.W Rm, Rn */
|
nkeynes@1 | 1078 | RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 1079 | break;
|
nkeynes@1 | 1080 | case 10:/* NEGC Rm, Rn */
|
nkeynes@1 | 1081 | tmp = 0 - RM(ir);
|
nkeynes@1 | 1082 | RN(ir) = tmp - sh4r.t;
|
nkeynes@1 | 1083 | sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
|
nkeynes@1 | 1084 | break;
|
nkeynes@1 | 1085 | case 11:/* NEG Rm, Rn */
|
nkeynes@1 | 1086 | RN(ir) = 0 - RM(ir);
|
nkeynes@1 | 1087 | break;
|
nkeynes@1 | 1088 | case 12:/* EXTU.B Rm, Rn */
|
nkeynes@1 | 1089 | RN(ir) = RM(ir)&0x000000FF;
|
nkeynes@1 | 1090 | break;
|
nkeynes@1 | 1091 | case 13:/* EXTU.W Rm, Rn */
|
nkeynes@1 | 1092 | RN(ir) = RM(ir)&0x0000FFFF;
|
nkeynes@1 | 1093 | break;
|
nkeynes@1 | 1094 | case 14:/* EXTS.B Rm, Rn */
|
nkeynes@1 | 1095 | RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
|
nkeynes@1 | 1096 | break;
|
nkeynes@1 | 1097 | case 15:/* EXTS.W Rm, Rn */
|
nkeynes@1 | 1098 | RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
|
nkeynes@1 | 1099 | break;
|
nkeynes@1 | 1100 | }
|
nkeynes@1 | 1101 | break;
|
nkeynes@1 | 1102 | case 7: /* 0111nnnniiiiiiii */
|
nkeynes@1 | 1103 | /* ADD imm8, Rn */
|
nkeynes@1 | 1104 | RN(ir) += IMM8(ir);
|
nkeynes@1 | 1105 | break;
|
nkeynes@1 | 1106 | case 8: /* 1000xxxxxxxxxxxx */
|
nkeynes@1 | 1107 | switch( (ir&0x0F00) >> 8 ) {
|
nkeynes@1 | 1108 | case 0: /* MOV.B R0, [Rm + disp4] */
|
nkeynes@1 | 1109 | MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
|
nkeynes@1 | 1110 | break;
|
nkeynes@1 | 1111 | case 1: /* MOV.W R0, [Rm + disp4*2] */
|
nkeynes@1 | 1112 | MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
|
nkeynes@1 | 1113 | break;
|
nkeynes@1 | 1114 | case 4: /* MOV.B [Rm + disp4], R0 */
|
nkeynes@1 | 1115 | R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
|
nkeynes@1 | 1116 | break;
|
nkeynes@1 | 1117 | case 5: /* MOV.W [Rm + disp4*2], R0 */
|
nkeynes@1 | 1118 | R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
|
nkeynes@1 | 1119 | break;
|
nkeynes@1 | 1120 | case 8: /* CMP/EQ imm, R0 */
|
nkeynes@1 | 1121 | sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
|
nkeynes@1 | 1122 | break;
|
nkeynes@1 | 1123 | case 9: /* BT disp8 */
|
nkeynes@2 | 1124 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1125 | if( sh4r.t ) {
|
nkeynes@1 | 1126 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 1127 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 1128 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@27 | 1129 | return TRUE;
|
nkeynes@1 | 1130 | }
|
nkeynes@1 | 1131 | break;
|
nkeynes@1 | 1132 | case 11:/* BF disp8 */
|
nkeynes@2 | 1133 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1134 | if( !sh4r.t ) {
|
nkeynes@1 | 1135 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 1136 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 1137 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@27 | 1138 | return TRUE;
|
nkeynes@1 | 1139 | }
|
nkeynes@1 | 1140 | break;
|
nkeynes@1 | 1141 | case 13:/* BT/S disp8 */
|
nkeynes@2 | 1142 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1143 | if( sh4r.t ) {
|
nkeynes@1 | 1144 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1145 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1146 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1147 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@2 | 1148 | sh4r.in_delay_slot = 1;
|
nkeynes@27 | 1149 | return TRUE;
|
nkeynes@1 | 1150 | }
|
nkeynes@1 | 1151 | break;
|
nkeynes@1 | 1152 | case 15:/* BF/S disp8 */
|
nkeynes@2 | 1153 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1154 | if( !sh4r.t ) {
|
nkeynes@1 | 1155 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1156 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1157 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1158 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@27 | 1159 | return TRUE;
|
nkeynes@1 | 1160 | }
|
nkeynes@1 | 1161 | break;
|
nkeynes@1 | 1162 | default: UNDEF(ir);
|
nkeynes@1 | 1163 | }
|
nkeynes@1 | 1164 | break;
|
nkeynes@1 | 1165 | case 9: /* 1001xxxxxxxxxxxx */
|
nkeynes@1 | 1166 | /* MOV.W [disp8*2 + pc + 4], Rn */
|
nkeynes@1 | 1167 | RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
|
nkeynes@1 | 1168 | break;
|
nkeynes@1 | 1169 | case 10:/* 1010dddddddddddd */
|
nkeynes@1 | 1170 | /* BRA disp12 */
|
nkeynes@2 | 1171 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1172 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1173 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1174 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1175 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@27 | 1176 | return TRUE;
|
nkeynes@1 | 1177 | case 11:/* 1011dddddddddddd */
|
nkeynes@1 | 1178 | /* BSR disp12 */
|
nkeynes@1 | 1179 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1180 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1181 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1182 | sh4r.pr = pc + 4;
|
nkeynes@1 | 1183 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1184 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@157 | 1185 | TRACE_CALL( pc, sh4r.new_pc );
|
nkeynes@27 | 1186 | return TRUE;
|
nkeynes@1 | 1187 | case 12:/* 1100xxxxdddddddd */
|
nkeynes@1 | 1188 | switch( (ir&0x0F00)>>8 ) {
|
nkeynes@1 | 1189 | case 0: /* MOV.B R0, [GBR + disp8] */
|
nkeynes@1 | 1190 | MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
|
nkeynes@1 | 1191 | break;
|
nkeynes@1 | 1192 | case 1: /* MOV.W R0, [GBR + disp8*2] */
|
nkeynes@1 | 1193 | MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
|
nkeynes@1 | 1194 | break;
|
nkeynes@1 | 1195 | case 2: /*MOV.L R0, [GBR + disp8*4] */
|
nkeynes@1 | 1196 | MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
|
nkeynes@1 | 1197 | break;
|
nkeynes@1 | 1198 | case 3: /* TRAPA imm8 */
|
nkeynes@2 | 1199 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1200 | sh4r.in_delay_slot = 1;
|
nkeynes@116 | 1201 | MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
|
nkeynes@1 | 1202 | RAISE( EXC_TRAP, EXV_TRAP );
|
nkeynes@1 | 1203 | break;
|
nkeynes@1 | 1204 | case 4: /* MOV.B [GBR + disp8], R0 */
|
nkeynes@1 | 1205 | R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
|
nkeynes@1 | 1206 | break;
|
nkeynes@1 | 1207 | case 5: /* MOV.W [GBR + disp8*2], R0 */
|
nkeynes@1 | 1208 | R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
|
nkeynes@1 | 1209 | break;
|
nkeynes@1 | 1210 | case 6: /* MOV.L [GBR + disp8*4], R0 */
|
nkeynes@1 | 1211 | R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
|
nkeynes@1 | 1212 | break;
|
nkeynes@1 | 1213 | case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
|
nkeynes@1 | 1214 | R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
|
nkeynes@1 | 1215 | break;
|
nkeynes@1 | 1216 | case 8: /* TST imm8, R0 */
|
nkeynes@1 | 1217 | sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
|
nkeynes@1 | 1218 | break;
|
nkeynes@1 | 1219 | case 9: /* AND imm8, R0 */
|
nkeynes@1 | 1220 | R0 &= UIMM8(ir);
|
nkeynes@1 | 1221 | break;
|
nkeynes@1 | 1222 | case 10:/* XOR imm8, R0 */
|
nkeynes@1 | 1223 | R0 ^= UIMM8(ir);
|
nkeynes@1 | 1224 | break;
|
nkeynes@1 | 1225 | case 11:/* OR imm8, R0 */
|
nkeynes@1 | 1226 | R0 |= UIMM8(ir);
|
nkeynes@1 | 1227 | break;
|
nkeynes@1 | 1228 | case 12:/* TST.B imm8, [R0+GBR] */
|
nkeynes@1 | 1229 | sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
|
nkeynes@1 | 1230 | break;
|
nkeynes@1 | 1231 | case 13:/* AND.B imm8, [R0+GBR] */
|
nkeynes@1 | 1232 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1233 | UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1234 | break;
|
nkeynes@1 | 1235 | case 14:/* XOR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1236 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1237 | UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1238 | break;
|
nkeynes@1 | 1239 | case 15:/* OR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1240 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1241 | UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1242 | break;
|
nkeynes@1 | 1243 | }
|
nkeynes@1 | 1244 | break;
|
nkeynes@1 | 1245 | case 13:/* 1101nnnndddddddd */
|
nkeynes@1 | 1246 | /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
|
nkeynes@1 | 1247 | RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
|
nkeynes@1 | 1248 | break;
|
nkeynes@1 | 1249 | case 14:/* 1110nnnniiiiiiii */
|
nkeynes@1 | 1250 | /* MOV imm8, Rn */
|
nkeynes@1 | 1251 | RN(ir) = IMM8(ir);
|
nkeynes@1 | 1252 | break;
|
nkeynes@1 | 1253 | case 15:/* 1111xxxxxxxxxxxx */
|
nkeynes@1 | 1254 | CHECKFPUEN();
|
nkeynes@84 | 1255 | if( IS_FPU_DOUBLEPREC() ) {
|
nkeynes@84 | 1256 | switch( ir&0x000F ) {
|
nkeynes@84 | 1257 | case 0: /* FADD FRm, FRn */
|
nkeynes@84 | 1258 | DRN(ir) += DRM(ir);
|
nkeynes@84 | 1259 | break;
|
nkeynes@84 | 1260 | case 1: /* FSUB FRm, FRn */
|
nkeynes@84 | 1261 | DRN(ir) -= DRM(ir);
|
nkeynes@84 | 1262 | break;
|
nkeynes@84 | 1263 | case 2: /* FMUL FRm, FRn */
|
nkeynes@84 | 1264 | DRN(ir) = DRN(ir) * DRM(ir);
|
nkeynes@84 | 1265 | break;
|
nkeynes@84 | 1266 | case 3: /* FDIV FRm, FRn */
|
nkeynes@84 | 1267 | DRN(ir) = DRN(ir) / DRM(ir);
|
nkeynes@84 | 1268 | break;
|
nkeynes@84 | 1269 | case 4: /* FCMP/EQ FRm, FRn */
|
nkeynes@84 | 1270 | sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
|
nkeynes@84 | 1271 | break;
|
nkeynes@84 | 1272 | case 5: /* FCMP/GT FRm, FRn */
|
nkeynes@84 | 1273 | sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
|
nkeynes@84 | 1274 | break;
|
nkeynes@84 | 1275 | case 6: /* FMOV.S [Rm+R0], FRn */
|
nkeynes@84 | 1276 | MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
|
nkeynes@84 | 1277 | break;
|
nkeynes@84 | 1278 | case 7: /* FMOV.S FRm, [Rn+R0] */
|
nkeynes@84 | 1279 | MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
|
nkeynes@84 | 1280 | break;
|
nkeynes@84 | 1281 | case 8: /* FMOV.S [Rm], FRn */
|
nkeynes@84 | 1282 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@84 | 1283 | break;
|
nkeynes@84 | 1284 | case 9: /* FMOV.S [Rm++], FRn */
|
nkeynes@84 | 1285 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@84 | 1286 | RM(ir) += FP_WIDTH;
|
nkeynes@84 | 1287 | break;
|
nkeynes@84 | 1288 | case 10:/* FMOV.S FRm, [Rn] */
|
nkeynes@84 | 1289 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@84 | 1290 | break;
|
nkeynes@84 | 1291 | case 11:/* FMOV.S FRm, [--Rn] */
|
nkeynes@84 | 1292 | RN(ir) -= FP_WIDTH;
|
nkeynes@84 | 1293 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@84 | 1294 | break;
|
nkeynes@84 | 1295 | case 12:/* FMOV FRm, FRn */
|
nkeynes@84 | 1296 | if( IS_FPU_DOUBLESIZE() )
|
nkeynes@84 | 1297 | DRN(ir) = DRM(ir);
|
nkeynes@84 | 1298 | else
|
nkeynes@84 | 1299 | FRN(ir) = FRM(ir);
|
nkeynes@84 | 1300 | break;
|
nkeynes@84 | 1301 | case 13:
|
nkeynes@84 | 1302 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@84 | 1303 | case 0: /* FSTS FPUL, FRn */
|
nkeynes@84 | 1304 | FRN(ir) = FPULf;
|
nkeynes@84 | 1305 | break;
|
nkeynes@84 | 1306 | case 1: /* FLDS FRn,FPUL */
|
nkeynes@84 | 1307 | FPULf = FRN(ir);
|
nkeynes@84 | 1308 | break;
|
nkeynes@84 | 1309 | case 2: /* FLOAT FPUL, FRn */
|
nkeynes@84 | 1310 | DRN(ir) = (float)FPULi;
|
nkeynes@84 | 1311 | break;
|
nkeynes@84 | 1312 | case 3: /* FTRC FRn, FPUL */
|
nkeynes@123 | 1313 | dtmp = DRN(ir);
|
nkeynes@123 | 1314 | if( dtmp >= MAX_INTF )
|
nkeynes@123 | 1315 | FPULi = MAX_INT;
|
nkeynes@123 | 1316 | else if( dtmp <= MIN_INTF )
|
nkeynes@123 | 1317 | FPULi = MIN_INT;
|
nkeynes@123 | 1318 | else
|
nkeynes@123 | 1319 | FPULi = (int32_t)dtmp;
|
nkeynes@84 | 1320 | break;
|
nkeynes@84 | 1321 | case 4: /* FNEG FRn */
|
nkeynes@84 | 1322 | DRN(ir) = -DRN(ir);
|
nkeynes@84 | 1323 | break;
|
nkeynes@84 | 1324 | case 5: /* FABS FRn */
|
nkeynes@84 | 1325 | DRN(ir) = fabs(DRN(ir));
|
nkeynes@84 | 1326 | break;
|
nkeynes@84 | 1327 | case 6: /* FSQRT FRn */
|
nkeynes@84 | 1328 | DRN(ir) = sqrt(DRN(ir));
|
nkeynes@84 | 1329 | break;
|
nkeynes@84 | 1330 | case 7: /* FSRRA FRn */
|
nkeynes@181 | 1331 | /* NO-OP when PR=1 */
|
nkeynes@84 | 1332 | break;
|
nkeynes@84 | 1333 | case 8: /* FLDI0 FRn */
|
nkeynes@84 | 1334 | DRN(ir) = 0.0;
|
nkeynes@84 | 1335 | break;
|
nkeynes@84 | 1336 | case 9: /* FLDI1 FRn */
|
nkeynes@84 | 1337 | DRN(ir) = 1.0;
|
nkeynes@84 | 1338 | break;
|
nkeynes@84 | 1339 | case 10: /* FCNVSD FPUL, DRn */
|
nkeynes@181 | 1340 | if( ! IS_FPU_DOUBLESIZE() )
|
nkeynes@181 | 1341 | DRN(ir) = (double)FPULf;
|
nkeynes@84 | 1342 | break;
|
nkeynes@84 | 1343 | case 11: /* FCNVDS DRn, FPUL */
|
nkeynes@181 | 1344 | if( ! IS_FPU_DOUBLESIZE() )
|
nkeynes@181 | 1345 | FPULf = (float)DRN(ir);
|
nkeynes@84 | 1346 | break;
|
nkeynes@84 | 1347 | case 14:/* FIPR FVm, FVn */
|
nkeynes@181 | 1348 | /* NO-OP when PR=1 */
|
nkeynes@84 | 1349 | break;
|
nkeynes@84 | 1350 | case 15:
|
nkeynes@84 | 1351 | if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
|
nkeynes@181 | 1352 | /* NO-OP when PR=1 */
|
nkeynes@84 | 1353 | break;
|
nkeynes@84 | 1354 | }
|
nkeynes@181 | 1355 | else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
|
nkeynes@181 | 1356 | /* NO-OP when PR=1 */
|
nkeynes@84 | 1357 | break;
|
nkeynes@84 | 1358 | }
|
nkeynes@84 | 1359 | else if( ir == 0xFBFD ) {
|
nkeynes@84 | 1360 | /* FRCHG */
|
nkeynes@84 | 1361 | sh4r.fpscr ^= FPSCR_FR;
|
nkeynes@84 | 1362 | break;
|
nkeynes@84 | 1363 | }
|
nkeynes@84 | 1364 | else if( ir == 0xF3FD ) {
|
nkeynes@84 | 1365 | /* FSCHG */
|
nkeynes@84 | 1366 | sh4r.fpscr ^= FPSCR_SZ;
|
nkeynes@84 | 1367 | break;
|
nkeynes@84 | 1368 | }
|
nkeynes@84 | 1369 | default: UNDEF(ir);
|
nkeynes@84 | 1370 | }
|
nkeynes@84 | 1371 | break;
|
nkeynes@84 | 1372 | case 14:/* FMAC FR0, FRm, FRn */
|
nkeynes@84 | 1373 | DRN(ir) += DRM(ir)*DR0;
|
nkeynes@84 | 1374 | break;
|
nkeynes@84 | 1375 | default: UNDEF(ir);
|
nkeynes@84 | 1376 | }
|
nkeynes@122 | 1377 | } else { /* Single precision */
|
nkeynes@84 | 1378 | switch( ir&0x000F ) {
|
nkeynes@1 | 1379 | case 0: /* FADD FRm, FRn */
|
nkeynes@1 | 1380 | FRN(ir) += FRM(ir);
|
nkeynes@1 | 1381 | break;
|
nkeynes@1 | 1382 | case 1: /* FSUB FRm, FRn */
|
nkeynes@1 | 1383 | FRN(ir) -= FRM(ir);
|
nkeynes@1 | 1384 | break;
|
nkeynes@1 | 1385 | case 2: /* FMUL FRm, FRn */
|
nkeynes@1 | 1386 | FRN(ir) = FRN(ir) * FRM(ir);
|
nkeynes@1 | 1387 | break;
|
nkeynes@1 | 1388 | case 3: /* FDIV FRm, FRn */
|
nkeynes@1 | 1389 | FRN(ir) = FRN(ir) / FRM(ir);
|
nkeynes@1 | 1390 | break;
|
nkeynes@1 | 1391 | case 4: /* FCMP/EQ FRm, FRn */
|
nkeynes@1 | 1392 | sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1393 | break;
|
nkeynes@1 | 1394 | case 5: /* FCMP/GT FRm, FRn */
|
nkeynes@1 | 1395 | sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1396 | break;
|
nkeynes@1 | 1397 | case 6: /* FMOV.S [Rm+R0], FRn */
|
nkeynes@1 | 1398 | MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
|
nkeynes@1 | 1399 | break;
|
nkeynes@1 | 1400 | case 7: /* FMOV.S FRm, [Rn+R0] */
|
nkeynes@1 | 1401 | MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
|
nkeynes@1 | 1402 | break;
|
nkeynes@1 | 1403 | case 8: /* FMOV.S [Rm], FRn */
|
nkeynes@1 | 1404 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1405 | break;
|
nkeynes@1 | 1406 | case 9: /* FMOV.S [Rm++], FRn */
|
nkeynes@1 | 1407 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1408 | RM(ir) += FP_WIDTH;
|
nkeynes@1 | 1409 | break;
|
nkeynes@1 | 1410 | case 10:/* FMOV.S FRm, [Rn] */
|
nkeynes@1 | 1411 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1412 | break;
|
nkeynes@1 | 1413 | case 11:/* FMOV.S FRm, [--Rn] */
|
nkeynes@1 | 1414 | RN(ir) -= FP_WIDTH;
|
nkeynes@1 | 1415 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1416 | break;
|
nkeynes@1 | 1417 | case 12:/* FMOV FRm, FRn */
|
nkeynes@84 | 1418 | if( IS_FPU_DOUBLESIZE() )
|
nkeynes@84 | 1419 | DRN(ir) = DRM(ir);
|
nkeynes@84 | 1420 | else
|
nkeynes@84 | 1421 | FRN(ir) = FRM(ir);
|
nkeynes@1 | 1422 | break;
|
nkeynes@1 | 1423 | case 13:
|
nkeynes@1 | 1424 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@84 | 1425 | case 0: /* FSTS FPUL, FRn */
|
nkeynes@84 | 1426 | FRN(ir) = FPULf;
|
nkeynes@84 | 1427 | break;
|
nkeynes@84 | 1428 | case 1: /* FLDS FRn,FPUL */
|
nkeynes@84 | 1429 | FPULf = FRN(ir);
|
nkeynes@84 | 1430 | break;
|
nkeynes@84 | 1431 | case 2: /* FLOAT FPUL, FRn */
|
nkeynes@84 | 1432 | FRN(ir) = (float)FPULi;
|
nkeynes@84 | 1433 | break;
|
nkeynes@84 | 1434 | case 3: /* FTRC FRn, FPUL */
|
nkeynes@123 | 1435 | ftmp = FRN(ir);
|
nkeynes@123 | 1436 | if( ftmp >= MAX_INTF )
|
nkeynes@123 | 1437 | FPULi = MAX_INT;
|
nkeynes@123 | 1438 | else if( ftmp <= MIN_INTF )
|
nkeynes@123 | 1439 | FPULi = MIN_INT;
|
nkeynes@123 | 1440 | else
|
nkeynes@123 | 1441 | FPULi = (int32_t)ftmp;
|
nkeynes@84 | 1442 | break;
|
nkeynes@84 | 1443 | case 4: /* FNEG FRn */
|
nkeynes@84 | 1444 | FRN(ir) = -FRN(ir);
|
nkeynes@84 | 1445 | break;
|
nkeynes@84 | 1446 | case 5: /* FABS FRn */
|
nkeynes@84 | 1447 | FRN(ir) = fabsf(FRN(ir));
|
nkeynes@84 | 1448 | break;
|
nkeynes@84 | 1449 | case 6: /* FSQRT FRn */
|
nkeynes@84 | 1450 | FRN(ir) = sqrtf(FRN(ir));
|
nkeynes@84 | 1451 | break;
|
nkeynes@84 | 1452 | case 7: /* FSRRA FRn */
|
nkeynes@84 | 1453 | FRN(ir) = 1.0/sqrtf(FRN(ir));
|
nkeynes@84 | 1454 | break;
|
nkeynes@84 | 1455 | case 8: /* FLDI0 FRn */
|
nkeynes@84 | 1456 | FRN(ir) = 0.0;
|
nkeynes@84 | 1457 | break;
|
nkeynes@84 | 1458 | case 9: /* FLDI1 FRn */
|
nkeynes@84 | 1459 | FRN(ir) = 1.0;
|
nkeynes@84 | 1460 | break;
|
nkeynes@84 | 1461 | case 10: /* FCNVSD FPUL, DRn */
|
nkeynes@84 | 1462 | break;
|
nkeynes@84 | 1463 | case 11: /* FCNVDS DRn, FPUL */
|
nkeynes@84 | 1464 | break;
|
nkeynes@84 | 1465 | case 14:/* FIPR FVm, FVn */
|
nkeynes@2 | 1466 | /* FIXME: This is not going to be entirely accurate
|
nkeynes@2 | 1467 | * as the SH4 instruction is less precise. Also
|
nkeynes@2 | 1468 | * need to check for 0s and infinities.
|
nkeynes@2 | 1469 | */
|
nkeynes@2 | 1470 | {
|
nkeynes@2 | 1471 | int tmp2 = FVN(ir);
|
nkeynes@2 | 1472 | tmp = FVM(ir);
|
nkeynes@84 | 1473 | FR(tmp2+3) = FR(tmp)*FR(tmp2) +
|
nkeynes@84 | 1474 | FR(tmp+1)*FR(tmp2+1) +
|
nkeynes@84 | 1475 | FR(tmp+2)*FR(tmp2+2) +
|
nkeynes@84 | 1476 | FR(tmp+3)*FR(tmp2+3);
|
nkeynes@1 | 1477 | break;
|
nkeynes@2 | 1478 | }
|
nkeynes@84 | 1479 | case 15:
|
nkeynes@84 | 1480 | if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
|
nkeynes@84 | 1481 | tmp = FVN(ir);
|
nkeynes@84 | 1482 | float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
|
nkeynes@84 | 1483 | FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
|
nkeynes@84 | 1484 | XF(8)*fv[2] + XF(12)*fv[3];
|
nkeynes@84 | 1485 | FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
|
nkeynes@84 | 1486 | XF(9)*fv[2] + XF(13)*fv[3];
|
nkeynes@84 | 1487 | FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
|
nkeynes@84 | 1488 | XF(10)*fv[2] + XF(14)*fv[3];
|
nkeynes@84 | 1489 | FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
|
nkeynes@84 | 1490 | XF(11)*fv[2] + XF(15)*fv[3];
|
nkeynes@84 | 1491 | break;
|
nkeynes@84 | 1492 | }
|
nkeynes@84 | 1493 | else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
|
nkeynes@84 | 1494 | float angle = (((float)(short)(FPULi>>16)) +
|
nkeynes@122 | 1495 | (((float)(FPULi&0xFFFF))/65536.0)) *
|
nkeynes@84 | 1496 | 2 * M_PI;
|
nkeynes@84 | 1497 | int reg = FRNn(ir);
|
nkeynes@84 | 1498 | FR(reg) = sinf(angle);
|
nkeynes@84 | 1499 | FR(reg+1) = cosf(angle);
|
nkeynes@84 | 1500 | break;
|
nkeynes@84 | 1501 | }
|
nkeynes@84 | 1502 | else if( ir == 0xFBFD ) {
|
nkeynes@84 | 1503 | /* FRCHG */
|
nkeynes@84 | 1504 | sh4r.fpscr ^= FPSCR_FR;
|
nkeynes@84 | 1505 | break;
|
nkeynes@84 | 1506 | }
|
nkeynes@84 | 1507 | else if( ir == 0xF3FD ) {
|
nkeynes@84 | 1508 | /* FSCHG */
|
nkeynes@84 | 1509 | sh4r.fpscr ^= FPSCR_SZ;
|
nkeynes@84 | 1510 | break;
|
nkeynes@84 | 1511 | }
|
nkeynes@84 | 1512 | default: UNDEF(ir);
|
nkeynes@1 | 1513 | }
|
nkeynes@1 | 1514 | break;
|
nkeynes@1 | 1515 | case 14:/* FMAC FR0, FRm, FRn */
|
nkeynes@1 | 1516 | FRN(ir) += FRM(ir)*FR0;
|
nkeynes@1 | 1517 | break;
|
nkeynes@1 | 1518 | default: UNDEF(ir);
|
nkeynes@84 | 1519 | }
|
nkeynes@84 | 1520 | }
|
nkeynes@84 | 1521 | break;
|
nkeynes@1 | 1522 | }
|
nkeynes@1 | 1523 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1524 | sh4r.new_pc += 2;
|
nkeynes@2 | 1525 | sh4r.in_delay_slot = 0;
|
nkeynes@1 | 1526 | }
|