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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 417:bd927df302a9
prev416:714df603c869
next502:c4ecae2b1b5e
author nkeynes
date Thu Oct 04 08:47:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Suppress redundant T flag loads
Tweak run_slice for performance
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.18 2007-10-04 08:47:27 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	precheck();\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exit( EXIT_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exit( EXIT_ILLEGAL );\
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	}\
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    }\
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static void check_priv_no_precheck()
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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#define check_fpuen( ) \
nkeynes@416
   351
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   352
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   353
	precheck();\
nkeynes@416
   354
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   355
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   356
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   357
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
nkeynes@416
   358
	} else {\
nkeynes@416
   359
	    JNE_exit(EXIT_FPU_DISABLED);\
nkeynes@416
   360
	}\
nkeynes@416
   361
    }
nkeynes@416
   362
nkeynes@416
   363
static void check_fpuen_no_precheck()
nkeynes@368
   364
{
nkeynes@368
   365
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   366
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   367
	load_spreg( R_EAX, R_SR );
nkeynes@368
   368
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   369
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   370
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   371
	} else {
nkeynes@368
   372
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   373
	}
nkeynes@368
   374
    }
nkeynes@416
   375
nkeynes@368
   376
}
nkeynes@368
   377
nkeynes@368
   378
static void check_ralign16( int x86reg )
nkeynes@368
   379
{
nkeynes@368
   380
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   381
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   382
}
nkeynes@368
   383
nkeynes@368
   384
static void check_walign16( int x86reg )
nkeynes@368
   385
{
nkeynes@368
   386
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   387
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   388
}
nkeynes@368
   389
nkeynes@368
   390
static void check_ralign32( int x86reg )
nkeynes@368
   391
{
nkeynes@368
   392
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   393
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   394
}
nkeynes@368
   395
static void check_walign32( int x86reg )
nkeynes@368
   396
{
nkeynes@368
   397
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   398
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   399
}
nkeynes@368
   400
nkeynes@361
   401
#define UNDEF()
nkeynes@361
   402
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   403
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   404
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   405
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   406
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   407
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   408
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   409
nkeynes@416
   410
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   411
nkeynes@368
   412
nkeynes@359
   413
nkeynes@359
   414
/**
nkeynes@359
   415
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   416
 * SI/DI as required
nkeynes@359
   417
 */
nkeynes@408
   418
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   419
{
nkeynes@368
   420
    PUSH_r32(R_EBP);
nkeynes@359
   421
    /* mov &sh4r, ebp */
nkeynes@359
   422
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@368
   423
    
nkeynes@368
   424
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   425
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   426
    sh4_x86.fpuen_checked = FALSE;
nkeynes@409
   427
    sh4_x86.branch_taken = FALSE;
nkeynes@368
   428
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   429
    sh4_x86.block_start_pc = pc;
nkeynes@417
   430
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
   431
}
nkeynes@359
   432
nkeynes@368
   433
/**
nkeynes@408
   434
 * Exit the block to an absolute PC
nkeynes@416
   435
 * Bytes: 29
nkeynes@368
   436
 */
nkeynes@408
   437
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@368
   438
{
nkeynes@408
   439
    load_imm32( R_ECX, pc );                            // 5
nkeynes@408
   440
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@408
   441
    MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
nkeynes@408
   442
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@408
   443
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   444
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@374
   445
    POP_r32(R_EBP);
nkeynes@368
   446
    RET();
nkeynes@359
   447
}
nkeynes@359
   448
nkeynes@359
   449
/**
nkeynes@408
   450
 * Exit the block with sh4r.pc already written
nkeynes@416
   451
 * Bytes: 15
nkeynes@408
   452
 */
nkeynes@408
   453
void exit_block_pcset( pc )
nkeynes@408
   454
{
nkeynes@408
   455
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   456
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@417
   457
    load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   458
    call_func1(xlat_get_code,R_EAX);
nkeynes@408
   459
    POP_r32(R_EBP);
nkeynes@408
   460
    RET();
nkeynes@408
   461
}
nkeynes@408
   462
nkeynes@408
   463
/**
nkeynes@408
   464
 * Write the block trailer (exception handling block)
nkeynes@359
   465
 */
nkeynes@359
   466
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@409
   467
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@409
   468
	// Didn't exit unconditionally already, so write the termination here
nkeynes@409
   469
	exit_block( pc, pc );
nkeynes@409
   470
    }
nkeynes@388
   471
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   472
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   473
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   474
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   475
	JMP_rel8( 33, target1 );
nkeynes@388
   476
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   477
	JMP_rel8( 26, target2 );
nkeynes@388
   478
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   479
	JMP_rel8( 19, target3 );
nkeynes@388
   480
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   481
	JMP_rel8( 12, target4 );
nkeynes@388
   482
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   483
	JMP_rel8( 5, target5 );
nkeynes@388
   484
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   485
	// target
nkeynes@388
   486
	JMP_TARGET(target1);
nkeynes@388
   487
	JMP_TARGET(target2);
nkeynes@388
   488
	JMP_TARGET(target3);
nkeynes@388
   489
	JMP_TARGET(target4);
nkeynes@388
   490
	JMP_TARGET(target5);
nkeynes@417
   491
	// Raise exception
nkeynes@388
   492
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@416
   493
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@416
   494
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@388
   495
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   496
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@416
   497
	MUL_r32( R_EDX );
nkeynes@417
   498
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@388
   499
	
nkeynes@388
   500
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   501
	CALL_r32( R_EAX ); // 2
nkeynes@388
   502
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
   503
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   504
	call_func1(xlat_get_code,R_EAX);
nkeynes@388
   505
	POP_r32(R_EBP);
nkeynes@388
   506
	RET();
nkeynes@368
   507
nkeynes@388
   508
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   509
    }
nkeynes@368
   510
nkeynes@359
   511
}
nkeynes@359
   512
nkeynes@388
   513
nkeynes@388
   514
extern uint16_t *sh4_icache;
nkeynes@388
   515
extern uint32_t sh4_icache_addr;
nkeynes@388
   516
nkeynes@359
   517
/**
nkeynes@359
   518
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   519
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   520
 * 
nkeynes@359
   521
 *
nkeynes@359
   522
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   523
 * (eg a branch or 
nkeynes@359
   524
 */
nkeynes@408
   525
uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
nkeynes@359
   526
{
nkeynes@388
   527
    uint32_t ir;
nkeynes@388
   528
    /* Read instruction */
nkeynes@388
   529
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   530
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   531
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   532
    } else {
nkeynes@388
   533
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   534
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   535
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   536
	     * region, fallback on the full-blown memory read
nkeynes@388
   537
	     */
nkeynes@388
   538
	    sh4_icache = NULL;
nkeynes@388
   539
	    ir = sh4_read_word(pc);
nkeynes@388
   540
	} else {
nkeynes@388
   541
	    sh4_icache_addr = pageaddr;
nkeynes@388
   542
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   543
	}
nkeynes@388
   544
    }
nkeynes@388
   545
nkeynes@359
   546
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   547
            case 0x0:
nkeynes@359
   548
                switch( ir&0xF ) {
nkeynes@359
   549
                    case 0x2:
nkeynes@359
   550
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   551
                            case 0x0:
nkeynes@359
   552
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   553
                                    case 0x0:
nkeynes@359
   554
                                        { /* STC SR, Rn */
nkeynes@359
   555
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   556
                                        check_priv();
nkeynes@374
   557
                                        call_func0(sh4_read_sr);
nkeynes@368
   558
                                        store_reg( R_EAX, Rn );
nkeynes@417
   559
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   560
                                        }
nkeynes@359
   561
                                        break;
nkeynes@359
   562
                                    case 0x1:
nkeynes@359
   563
                                        { /* STC GBR, Rn */
nkeynes@359
   564
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   565
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   566
                                        store_reg( R_EAX, Rn );
nkeynes@359
   567
                                        }
nkeynes@359
   568
                                        break;
nkeynes@359
   569
                                    case 0x2:
nkeynes@359
   570
                                        { /* STC VBR, Rn */
nkeynes@359
   571
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   572
                                        check_priv();
nkeynes@359
   573
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   574
                                        store_reg( R_EAX, Rn );
nkeynes@417
   575
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   576
                                        }
nkeynes@359
   577
                                        break;
nkeynes@359
   578
                                    case 0x3:
nkeynes@359
   579
                                        { /* STC SSR, Rn */
nkeynes@359
   580
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   581
                                        check_priv();
nkeynes@359
   582
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   583
                                        store_reg( R_EAX, Rn );
nkeynes@417
   584
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   585
                                        }
nkeynes@359
   586
                                        break;
nkeynes@359
   587
                                    case 0x4:
nkeynes@359
   588
                                        { /* STC SPC, Rn */
nkeynes@359
   589
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   590
                                        check_priv();
nkeynes@359
   591
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   592
                                        store_reg( R_EAX, Rn );
nkeynes@417
   593
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   594
                                        }
nkeynes@359
   595
                                        break;
nkeynes@359
   596
                                    default:
nkeynes@359
   597
                                        UNDEF();
nkeynes@359
   598
                                        break;
nkeynes@359
   599
                                }
nkeynes@359
   600
                                break;
nkeynes@359
   601
                            case 0x1:
nkeynes@359
   602
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   603
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   604
                                check_priv();
nkeynes@374
   605
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   606
                                store_reg( R_EAX, Rn );
nkeynes@417
   607
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   608
                                }
nkeynes@359
   609
                                break;
nkeynes@359
   610
                        }
nkeynes@359
   611
                        break;
nkeynes@359
   612
                    case 0x3:
nkeynes@359
   613
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   614
                            case 0x0:
nkeynes@359
   615
                                { /* BSRF Rn */
nkeynes@359
   616
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   617
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   618
                            	SLOTILLEGAL();
nkeynes@374
   619
                                } else {
nkeynes@408
   620
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   621
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   622
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   623
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   624
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   625
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
   626
                            	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
   627
                            	exit_block_pcset(pc+2);
nkeynes@409
   628
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   629
                            	return 4;
nkeynes@374
   630
                                }
nkeynes@359
   631
                                }
nkeynes@359
   632
                                break;
nkeynes@359
   633
                            case 0x2:
nkeynes@359
   634
                                { /* BRAF Rn */
nkeynes@359
   635
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   636
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   637
                            	SLOTILLEGAL();
nkeynes@374
   638
                                } else {
nkeynes@408
   639
                            	load_reg( R_EAX, Rn );
nkeynes@408
   640
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   641
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   642
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   643
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
   644
                            	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
   645
                            	exit_block_pcset(pc+2);
nkeynes@409
   646
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   647
                            	return 4;
nkeynes@374
   648
                                }
nkeynes@359
   649
                                }
nkeynes@359
   650
                                break;
nkeynes@359
   651
                            case 0x8:
nkeynes@359
   652
                                { /* PREF @Rn */
nkeynes@359
   653
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   654
                                load_reg( R_EAX, Rn );
nkeynes@374
   655
                                PUSH_r32( R_EAX );
nkeynes@374
   656
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   657
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
   658
                                JNE_rel8(7, end);
nkeynes@374
   659
                                call_func0( sh4_flush_store_queue );
nkeynes@380
   660
                                JMP_TARGET(end);
nkeynes@377
   661
                                ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
   662
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   663
                                }
nkeynes@359
   664
                                break;
nkeynes@359
   665
                            case 0x9:
nkeynes@359
   666
                                { /* OCBI @Rn */
nkeynes@359
   667
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   668
                                }
nkeynes@359
   669
                                break;
nkeynes@359
   670
                            case 0xA:
nkeynes@359
   671
                                { /* OCBP @Rn */
nkeynes@359
   672
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   673
                                }
nkeynes@359
   674
                                break;
nkeynes@359
   675
                            case 0xB:
nkeynes@359
   676
                                { /* OCBWB @Rn */
nkeynes@359
   677
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   678
                                }
nkeynes@359
   679
                                break;
nkeynes@359
   680
                            case 0xC:
nkeynes@359
   681
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   682
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   683
                                load_reg( R_EAX, 0 );
nkeynes@361
   684
                                load_reg( R_ECX, Rn );
nkeynes@416
   685
                                precheck();
nkeynes@374
   686
                                check_walign32( R_ECX );
nkeynes@361
   687
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   688
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   689
                                }
nkeynes@359
   690
                                break;
nkeynes@359
   691
                            default:
nkeynes@359
   692
                                UNDEF();
nkeynes@359
   693
                                break;
nkeynes@359
   694
                        }
nkeynes@359
   695
                        break;
nkeynes@359
   696
                    case 0x4:
nkeynes@359
   697
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   698
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   699
                        load_reg( R_EAX, 0 );
nkeynes@359
   700
                        load_reg( R_ECX, Rn );
nkeynes@359
   701
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   702
                        load_reg( R_EAX, Rm );
nkeynes@359
   703
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   704
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   705
                        }
nkeynes@359
   706
                        break;
nkeynes@359
   707
                    case 0x5:
nkeynes@359
   708
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   709
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   710
                        load_reg( R_EAX, 0 );
nkeynes@361
   711
                        load_reg( R_ECX, Rn );
nkeynes@361
   712
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   713
                        precheck();
nkeynes@374
   714
                        check_walign16( R_ECX );
nkeynes@361
   715
                        load_reg( R_EAX, Rm );
nkeynes@361
   716
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   717
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   718
                        }
nkeynes@359
   719
                        break;
nkeynes@359
   720
                    case 0x6:
nkeynes@359
   721
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   722
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   723
                        load_reg( R_EAX, 0 );
nkeynes@361
   724
                        load_reg( R_ECX, Rn );
nkeynes@361
   725
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   726
                        precheck();
nkeynes@374
   727
                        check_walign32( R_ECX );
nkeynes@361
   728
                        load_reg( R_EAX, Rm );
nkeynes@361
   729
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   730
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   731
                        }
nkeynes@359
   732
                        break;
nkeynes@359
   733
                    case 0x7:
nkeynes@359
   734
                        { /* MUL.L Rm, Rn */
nkeynes@359
   735
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   736
                        load_reg( R_EAX, Rm );
nkeynes@361
   737
                        load_reg( R_ECX, Rn );
nkeynes@361
   738
                        MUL_r32( R_ECX );
nkeynes@361
   739
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   740
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   741
                        }
nkeynes@359
   742
                        break;
nkeynes@359
   743
                    case 0x8:
nkeynes@359
   744
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   745
                            case 0x0:
nkeynes@359
   746
                                { /* CLRT */
nkeynes@374
   747
                                CLC();
nkeynes@374
   748
                                SETC_t();
nkeynes@417
   749
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   750
                                }
nkeynes@359
   751
                                break;
nkeynes@359
   752
                            case 0x1:
nkeynes@359
   753
                                { /* SETT */
nkeynes@374
   754
                                STC();
nkeynes@374
   755
                                SETC_t();
nkeynes@417
   756
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   757
                                }
nkeynes@359
   758
                                break;
nkeynes@359
   759
                            case 0x2:
nkeynes@359
   760
                                { /* CLRMAC */
nkeynes@374
   761
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   762
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   763
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   764
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   765
                                }
nkeynes@359
   766
                                break;
nkeynes@359
   767
                            case 0x3:
nkeynes@359
   768
                                { /* LDTLB */
nkeynes@359
   769
                                }
nkeynes@359
   770
                                break;
nkeynes@359
   771
                            case 0x4:
nkeynes@359
   772
                                { /* CLRS */
nkeynes@374
   773
                                CLC();
nkeynes@374
   774
                                SETC_sh4r(R_S);
nkeynes@417
   775
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   776
                                }
nkeynes@359
   777
                                break;
nkeynes@359
   778
                            case 0x5:
nkeynes@359
   779
                                { /* SETS */
nkeynes@374
   780
                                STC();
nkeynes@374
   781
                                SETC_sh4r(R_S);
nkeynes@417
   782
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   783
                                }
nkeynes@359
   784
                                break;
nkeynes@359
   785
                            default:
nkeynes@359
   786
                                UNDEF();
nkeynes@359
   787
                                break;
nkeynes@359
   788
                        }
nkeynes@359
   789
                        break;
nkeynes@359
   790
                    case 0x9:
nkeynes@359
   791
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   792
                            case 0x0:
nkeynes@359
   793
                                { /* NOP */
nkeynes@359
   794
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   795
                                }
nkeynes@359
   796
                                break;
nkeynes@359
   797
                            case 0x1:
nkeynes@359
   798
                                { /* DIV0U */
nkeynes@361
   799
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   800
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   801
                                store_spreg( R_EAX, R_M );
nkeynes@361
   802
                                store_spreg( R_EAX, R_T );
nkeynes@417
   803
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   804
                                }
nkeynes@359
   805
                                break;
nkeynes@359
   806
                            case 0x2:
nkeynes@359
   807
                                { /* MOVT Rn */
nkeynes@359
   808
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   809
                                load_spreg( R_EAX, R_T );
nkeynes@359
   810
                                store_reg( R_EAX, Rn );
nkeynes@359
   811
                                }
nkeynes@359
   812
                                break;
nkeynes@359
   813
                            default:
nkeynes@359
   814
                                UNDEF();
nkeynes@359
   815
                                break;
nkeynes@359
   816
                        }
nkeynes@359
   817
                        break;
nkeynes@359
   818
                    case 0xA:
nkeynes@359
   819
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   820
                            case 0x0:
nkeynes@359
   821
                                { /* STS MACH, Rn */
nkeynes@359
   822
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   823
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   824
                                store_reg( R_EAX, Rn );
nkeynes@359
   825
                                }
nkeynes@359
   826
                                break;
nkeynes@359
   827
                            case 0x1:
nkeynes@359
   828
                                { /* STS MACL, Rn */
nkeynes@359
   829
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   830
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   831
                                store_reg( R_EAX, Rn );
nkeynes@359
   832
                                }
nkeynes@359
   833
                                break;
nkeynes@359
   834
                            case 0x2:
nkeynes@359
   835
                                { /* STS PR, Rn */
nkeynes@359
   836
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   837
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   838
                                store_reg( R_EAX, Rn );
nkeynes@359
   839
                                }
nkeynes@359
   840
                                break;
nkeynes@359
   841
                            case 0x3:
nkeynes@359
   842
                                { /* STC SGR, Rn */
nkeynes@359
   843
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   844
                                check_priv();
nkeynes@359
   845
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   846
                                store_reg( R_EAX, Rn );
nkeynes@417
   847
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   848
                                }
nkeynes@359
   849
                                break;
nkeynes@359
   850
                            case 0x5:
nkeynes@359
   851
                                { /* STS FPUL, Rn */
nkeynes@359
   852
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   853
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   854
                                store_reg( R_EAX, Rn );
nkeynes@359
   855
                                }
nkeynes@359
   856
                                break;
nkeynes@359
   857
                            case 0x6:
nkeynes@359
   858
                                { /* STS FPSCR, Rn */
nkeynes@359
   859
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   860
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   861
                                store_reg( R_EAX, Rn );
nkeynes@359
   862
                                }
nkeynes@359
   863
                                break;
nkeynes@359
   864
                            case 0xF:
nkeynes@359
   865
                                { /* STC DBR, Rn */
nkeynes@359
   866
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   867
                                check_priv();
nkeynes@359
   868
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   869
                                store_reg( R_EAX, Rn );
nkeynes@417
   870
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   871
                                }
nkeynes@359
   872
                                break;
nkeynes@359
   873
                            default:
nkeynes@359
   874
                                UNDEF();
nkeynes@359
   875
                                break;
nkeynes@359
   876
                        }
nkeynes@359
   877
                        break;
nkeynes@359
   878
                    case 0xB:
nkeynes@359
   879
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   880
                            case 0x0:
nkeynes@359
   881
                                { /* RTS */
nkeynes@374
   882
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   883
                            	SLOTILLEGAL();
nkeynes@374
   884
                                } else {
nkeynes@408
   885
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
   886
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   887
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
   888
                            	sh4_x86_translate_instruction(pc+2);
nkeynes@408
   889
                            	exit_block_pcset(pc+2);
nkeynes@409
   890
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   891
                            	return 4;
nkeynes@374
   892
                                }
nkeynes@359
   893
                                }
nkeynes@359
   894
                                break;
nkeynes@359
   895
                            case 0x1:
nkeynes@359
   896
                                { /* SLEEP */
nkeynes@388
   897
                                check_priv();
nkeynes@388
   898
                                call_func0( sh4_sleep );
nkeynes@417
   899
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
   900
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
   901
                                return 2;
nkeynes@359
   902
                                }
nkeynes@359
   903
                                break;
nkeynes@359
   904
                            case 0x2:
nkeynes@359
   905
                                { /* RTE */
nkeynes@374
   906
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   907
                            	SLOTILLEGAL();
nkeynes@374
   908
                                } else {
nkeynes@408
   909
                            	check_priv();
nkeynes@408
   910
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
   911
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   912
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   913
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   914
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   915
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   916
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   917
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
   918
                            	sh4_x86_translate_instruction(pc+2);
nkeynes@408
   919
                            	exit_block_pcset(pc+2);
nkeynes@409
   920
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   921
                            	return 4;
nkeynes@374
   922
                                }
nkeynes@359
   923
                                }
nkeynes@359
   924
                                break;
nkeynes@359
   925
                            default:
nkeynes@359
   926
                                UNDEF();
nkeynes@359
   927
                                break;
nkeynes@359
   928
                        }
nkeynes@359
   929
                        break;
nkeynes@359
   930
                    case 0xC:
nkeynes@359
   931
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   932
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   933
                        load_reg( R_EAX, 0 );
nkeynes@359
   934
                        load_reg( R_ECX, Rm );
nkeynes@359
   935
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   936
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   937
                        store_reg( R_EAX, Rn );
nkeynes@417
   938
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   939
                        }
nkeynes@359
   940
                        break;
nkeynes@359
   941
                    case 0xD:
nkeynes@359
   942
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   943
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   944
                        load_reg( R_EAX, 0 );
nkeynes@361
   945
                        load_reg( R_ECX, Rm );
nkeynes@361
   946
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   947
                        precheck();
nkeynes@374
   948
                        check_ralign16( R_ECX );
nkeynes@361
   949
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   950
                        store_reg( R_EAX, Rn );
nkeynes@417
   951
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   952
                        }
nkeynes@359
   953
                        break;
nkeynes@359
   954
                    case 0xE:
nkeynes@359
   955
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   956
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   957
                        load_reg( R_EAX, 0 );
nkeynes@361
   958
                        load_reg( R_ECX, Rm );
nkeynes@361
   959
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   960
                        precheck();
nkeynes@374
   961
                        check_ralign32( R_ECX );
nkeynes@361
   962
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   963
                        store_reg( R_EAX, Rn );
nkeynes@417
   964
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
                        }
nkeynes@359
   966
                        break;
nkeynes@359
   967
                    case 0xF:
nkeynes@359
   968
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   969
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   970
                        load_reg( R_ECX, Rm );
nkeynes@416
   971
                        precheck();
nkeynes@386
   972
                        check_ralign32( R_ECX );
nkeynes@386
   973
                        load_reg( R_ECX, Rn );
nkeynes@386
   974
                        check_ralign32( R_ECX );
nkeynes@386
   975
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   976
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   977
                        PUSH_r32( R_EAX );
nkeynes@386
   978
                        load_reg( R_ECX, Rm );
nkeynes@386
   979
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   980
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   981
                        POP_r32( R_ECX );
nkeynes@386
   982
                        IMUL_r32( R_ECX );
nkeynes@386
   983
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   984
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   985
                    
nkeynes@386
   986
                        load_spreg( R_ECX, R_S );
nkeynes@386
   987
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   988
                        JE_rel8( 7, nosat );
nkeynes@386
   989
                        call_func0( signsat48 );
nkeynes@386
   990
                        JMP_TARGET( nosat );
nkeynes@417
   991
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   992
                        }
nkeynes@359
   993
                        break;
nkeynes@359
   994
                    default:
nkeynes@359
   995
                        UNDEF();
nkeynes@359
   996
                        break;
nkeynes@359
   997
                }
nkeynes@359
   998
                break;
nkeynes@359
   999
            case 0x1:
nkeynes@359
  1000
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
  1001
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1002
                load_reg( R_ECX, Rn );
nkeynes@361
  1003
                load_reg( R_EAX, Rm );
nkeynes@361
  1004
                ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1005
                precheck();
nkeynes@374
  1006
                check_walign32( R_ECX );
nkeynes@361
  1007
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1008
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1009
                }
nkeynes@359
  1010
                break;
nkeynes@359
  1011
            case 0x2:
nkeynes@359
  1012
                switch( ir&0xF ) {
nkeynes@359
  1013
                    case 0x0:
nkeynes@359
  1014
                        { /* MOV.B Rm, @Rn */
nkeynes@359
  1015
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1016
                        load_reg( R_EAX, Rm );
nkeynes@359
  1017
                        load_reg( R_ECX, Rn );
nkeynes@359
  1018
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1019
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1020
                        }
nkeynes@359
  1021
                        break;
nkeynes@359
  1022
                    case 0x1:
nkeynes@359
  1023
                        { /* MOV.W Rm, @Rn */
nkeynes@359
  1024
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1025
                        load_reg( R_ECX, Rn );
nkeynes@416
  1026
                        precheck();
nkeynes@374
  1027
                        check_walign16( R_ECX );
nkeynes@386
  1028
                        load_reg( R_EAX, Rm );
nkeynes@386
  1029
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1030
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1031
                        }
nkeynes@359
  1032
                        break;
nkeynes@359
  1033
                    case 0x2:
nkeynes@359
  1034
                        { /* MOV.L Rm, @Rn */
nkeynes@359
  1035
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1036
                        load_reg( R_EAX, Rm );
nkeynes@361
  1037
                        load_reg( R_ECX, Rn );
nkeynes@416
  1038
                        precheck();
nkeynes@374
  1039
                        check_walign32(R_ECX);
nkeynes@361
  1040
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1041
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1042
                        }
nkeynes@359
  1043
                        break;
nkeynes@359
  1044
                    case 0x4:
nkeynes@359
  1045
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
  1046
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1047
                        load_reg( R_EAX, Rm );
nkeynes@359
  1048
                        load_reg( R_ECX, Rn );
nkeynes@386
  1049
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1050
                        store_reg( R_ECX, Rn );
nkeynes@359
  1051
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1052
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1053
                        }
nkeynes@359
  1054
                        break;
nkeynes@359
  1055
                    case 0x5:
nkeynes@359
  1056
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
  1057
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1058
                        load_reg( R_ECX, Rn );
nkeynes@416
  1059
                        precheck();
nkeynes@374
  1060
                        check_walign16( R_ECX );
nkeynes@361
  1061
                        load_reg( R_EAX, Rm );
nkeynes@361
  1062
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
  1063
                        store_reg( R_ECX, Rn );
nkeynes@361
  1064
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1065
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1066
                        }
nkeynes@359
  1067
                        break;
nkeynes@359
  1068
                    case 0x6:
nkeynes@359
  1069
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
  1070
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1071
                        load_reg( R_EAX, Rm );
nkeynes@361
  1072
                        load_reg( R_ECX, Rn );
nkeynes@416
  1073
                        precheck();
nkeynes@374
  1074
                        check_walign32( R_ECX );
nkeynes@361
  1075
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1076
                        store_reg( R_ECX, Rn );
nkeynes@361
  1077
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1078
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1079
                        }
nkeynes@359
  1080
                        break;
nkeynes@359
  1081
                    case 0x7:
nkeynes@359
  1082
                        { /* DIV0S Rm, Rn */
nkeynes@359
  1083
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1084
                        load_reg( R_EAX, Rm );
nkeynes@386
  1085
                        load_reg( R_ECX, Rn );
nkeynes@361
  1086
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
  1087
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
  1088
                        store_spreg( R_EAX, R_M );
nkeynes@361
  1089
                        store_spreg( R_ECX, R_Q );
nkeynes@361
  1090
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1091
                        SETNE_t();
nkeynes@417
  1092
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
  1093
                        }
nkeynes@359
  1094
                        break;
nkeynes@359
  1095
                    case 0x8:
nkeynes@359
  1096
                        { /* TST Rm, Rn */
nkeynes@359
  1097
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1098
                        load_reg( R_EAX, Rm );
nkeynes@361
  1099
                        load_reg( R_ECX, Rn );
nkeynes@361
  1100
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1101
                        SETE_t();
nkeynes@417
  1102
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1103
                        }
nkeynes@359
  1104
                        break;
nkeynes@359
  1105
                    case 0x9:
nkeynes@359
  1106
                        { /* AND Rm, Rn */
nkeynes@359
  1107
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1108
                        load_reg( R_EAX, Rm );
nkeynes@359
  1109
                        load_reg( R_ECX, Rn );
nkeynes@359
  1110
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1111
                        store_reg( R_ECX, Rn );
nkeynes@417
  1112
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1113
                        }
nkeynes@359
  1114
                        break;
nkeynes@359
  1115
                    case 0xA:
nkeynes@359
  1116
                        { /* XOR Rm, Rn */
nkeynes@359
  1117
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1118
                        load_reg( R_EAX, Rm );
nkeynes@359
  1119
                        load_reg( R_ECX, Rn );
nkeynes@359
  1120
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1121
                        store_reg( R_ECX, Rn );
nkeynes@417
  1122
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1123
                        }
nkeynes@359
  1124
                        break;
nkeynes@359
  1125
                    case 0xB:
nkeynes@359
  1126
                        { /* OR Rm, Rn */
nkeynes@359
  1127
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1128
                        load_reg( R_EAX, Rm );
nkeynes@359
  1129
                        load_reg( R_ECX, Rn );
nkeynes@359
  1130
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1131
                        store_reg( R_ECX, Rn );
nkeynes@417
  1132
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1133
                        }
nkeynes@359
  1134
                        break;
nkeynes@359
  1135
                    case 0xC:
nkeynes@359
  1136
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1137
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1138
                        load_reg( R_EAX, Rm );
nkeynes@368
  1139
                        load_reg( R_ECX, Rn );
nkeynes@368
  1140
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1141
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1142
                        JE_rel8(13, target1);
nkeynes@368
  1143
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1144
                        JE_rel8(9, target2);
nkeynes@368
  1145
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1146
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1147
                        JE_rel8(2, target3);
nkeynes@368
  1148
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1149
                        JMP_TARGET(target1);
nkeynes@380
  1150
                        JMP_TARGET(target2);
nkeynes@380
  1151
                        JMP_TARGET(target3);
nkeynes@368
  1152
                        SETE_t();
nkeynes@417
  1153
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1154
                        }
nkeynes@359
  1155
                        break;
nkeynes@359
  1156
                    case 0xD:
nkeynes@359
  1157
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1158
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1159
                        load_reg( R_EAX, Rm );
nkeynes@394
  1160
                        load_reg( R_ECX, Rn );
nkeynes@394
  1161
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1162
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1163
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1164
                        store_reg( R_ECX, Rn );
nkeynes@417
  1165
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1166
                        }
nkeynes@359
  1167
                        break;
nkeynes@359
  1168
                    case 0xE:
nkeynes@359
  1169
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1170
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1171
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1172
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1173
                        MUL_r32( R_ECX );
nkeynes@374
  1174
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1175
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1176
                        }
nkeynes@359
  1177
                        break;
nkeynes@359
  1178
                    case 0xF:
nkeynes@359
  1179
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1180
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1181
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1182
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1183
                        MUL_r32( R_ECX );
nkeynes@374
  1184
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1185
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1186
                        }
nkeynes@359
  1187
                        break;
nkeynes@359
  1188
                    default:
nkeynes@359
  1189
                        UNDEF();
nkeynes@359
  1190
                        break;
nkeynes@359
  1191
                }
nkeynes@359
  1192
                break;
nkeynes@359
  1193
            case 0x3:
nkeynes@359
  1194
                switch( ir&0xF ) {
nkeynes@359
  1195
                    case 0x0:
nkeynes@359
  1196
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1197
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1198
                        load_reg( R_EAX, Rm );
nkeynes@359
  1199
                        load_reg( R_ECX, Rn );
nkeynes@359
  1200
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1201
                        SETE_t();
nkeynes@417
  1202
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1203
                        }
nkeynes@359
  1204
                        break;
nkeynes@359
  1205
                    case 0x2:
nkeynes@359
  1206
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1207
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1208
                        load_reg( R_EAX, Rm );
nkeynes@359
  1209
                        load_reg( R_ECX, Rn );
nkeynes@359
  1210
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1211
                        SETAE_t();
nkeynes@417
  1212
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1213
                        }
nkeynes@359
  1214
                        break;
nkeynes@359
  1215
                    case 0x3:
nkeynes@359
  1216
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1217
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1218
                        load_reg( R_EAX, Rm );
nkeynes@359
  1219
                        load_reg( R_ECX, Rn );
nkeynes@359
  1220
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1221
                        SETGE_t();
nkeynes@417
  1222
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1223
                        }
nkeynes@359
  1224
                        break;
nkeynes@359
  1225
                    case 0x4:
nkeynes@359
  1226
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1227
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1228
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1229
                        load_reg( R_EAX, Rn );
nkeynes@417
  1230
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1231
                    	LDC_t();
nkeynes@417
  1232
                        }
nkeynes@386
  1233
                        RCL1_r32( R_EAX );
nkeynes@386
  1234
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1235
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1236
                        JE_rel8(5, mqequal);
nkeynes@386
  1237
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1238
                        JMP_rel8(3, end);
nkeynes@380
  1239
                        JMP_TARGET(mqequal);
nkeynes@386
  1240
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1241
                        JMP_TARGET(end);
nkeynes@386
  1242
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1243
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1244
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1245
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1246
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1247
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1248
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1249
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1250
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1251
                        }
nkeynes@359
  1252
                        break;
nkeynes@359
  1253
                    case 0x5:
nkeynes@359
  1254
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1255
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1256
                        load_reg( R_EAX, Rm );
nkeynes@361
  1257
                        load_reg( R_ECX, Rn );
nkeynes@361
  1258
                        MUL_r32(R_ECX);
nkeynes@361
  1259
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1260
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1261
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1262
                        }
nkeynes@359
  1263
                        break;
nkeynes@359
  1264
                    case 0x6:
nkeynes@359
  1265
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1266
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1267
                        load_reg( R_EAX, Rm );
nkeynes@359
  1268
                        load_reg( R_ECX, Rn );
nkeynes@359
  1269
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1270
                        SETA_t();
nkeynes@417
  1271
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1272
                        }
nkeynes@359
  1273
                        break;
nkeynes@359
  1274
                    case 0x7:
nkeynes@359
  1275
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1276
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1277
                        load_reg( R_EAX, Rm );
nkeynes@359
  1278
                        load_reg( R_ECX, Rn );
nkeynes@359
  1279
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1280
                        SETG_t();
nkeynes@417
  1281
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1282
                        }
nkeynes@359
  1283
                        break;
nkeynes@359
  1284
                    case 0x8:
nkeynes@359
  1285
                        { /* SUB Rm, Rn */
nkeynes@359
  1286
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1287
                        load_reg( R_EAX, Rm );
nkeynes@359
  1288
                        load_reg( R_ECX, Rn );
nkeynes@359
  1289
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1290
                        store_reg( R_ECX, Rn );
nkeynes@417
  1291
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1292
                        }
nkeynes@359
  1293
                        break;
nkeynes@359
  1294
                    case 0xA:
nkeynes@359
  1295
                        { /* SUBC Rm, Rn */
nkeynes@359
  1296
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1297
                        load_reg( R_EAX, Rm );
nkeynes@359
  1298
                        load_reg( R_ECX, Rn );
nkeynes@417
  1299
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1300
                    	LDC_t();
nkeynes@417
  1301
                        }
nkeynes@359
  1302
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1303
                        store_reg( R_ECX, Rn );
nkeynes@394
  1304
                        SETC_t();
nkeynes@417
  1305
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1306
                        }
nkeynes@359
  1307
                        break;
nkeynes@359
  1308
                    case 0xB:
nkeynes@359
  1309
                        { /* SUBV Rm, Rn */
nkeynes@359
  1310
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1311
                        load_reg( R_EAX, Rm );
nkeynes@359
  1312
                        load_reg( R_ECX, Rn );
nkeynes@359
  1313
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1314
                        store_reg( R_ECX, Rn );
nkeynes@359
  1315
                        SETO_t();
nkeynes@417
  1316
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1317
                        }
nkeynes@359
  1318
                        break;
nkeynes@359
  1319
                    case 0xC:
nkeynes@359
  1320
                        { /* ADD Rm, Rn */
nkeynes@359
  1321
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1322
                        load_reg( R_EAX, Rm );
nkeynes@359
  1323
                        load_reg( R_ECX, Rn );
nkeynes@359
  1324
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1325
                        store_reg( R_ECX, Rn );
nkeynes@417
  1326
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1327
                        }
nkeynes@359
  1328
                        break;
nkeynes@359
  1329
                    case 0xD:
nkeynes@359
  1330
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1331
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1332
                        load_reg( R_EAX, Rm );
nkeynes@361
  1333
                        load_reg( R_ECX, Rn );
nkeynes@361
  1334
                        IMUL_r32(R_ECX);
nkeynes@361
  1335
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1336
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1337
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1338
                        }
nkeynes@359
  1339
                        break;
nkeynes@359
  1340
                    case 0xE:
nkeynes@359
  1341
                        { /* ADDC Rm, Rn */
nkeynes@359
  1342
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1343
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1344
                    	LDC_t();
nkeynes@417
  1345
                        }
nkeynes@359
  1346
                        load_reg( R_EAX, Rm );
nkeynes@359
  1347
                        load_reg( R_ECX, Rn );
nkeynes@359
  1348
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1349
                        store_reg( R_ECX, Rn );
nkeynes@359
  1350
                        SETC_t();
nkeynes@417
  1351
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1352
                        }
nkeynes@359
  1353
                        break;
nkeynes@359
  1354
                    case 0xF:
nkeynes@359
  1355
                        { /* ADDV Rm, Rn */
nkeynes@359
  1356
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1357
                        load_reg( R_EAX, Rm );
nkeynes@359
  1358
                        load_reg( R_ECX, Rn );
nkeynes@359
  1359
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1360
                        store_reg( R_ECX, Rn );
nkeynes@359
  1361
                        SETO_t();
nkeynes@417
  1362
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1363
                        }
nkeynes@359
  1364
                        break;
nkeynes@359
  1365
                    default:
nkeynes@359
  1366
                        UNDEF();
nkeynes@359
  1367
                        break;
nkeynes@359
  1368
                }
nkeynes@359
  1369
                break;
nkeynes@359
  1370
            case 0x4:
nkeynes@359
  1371
                switch( ir&0xF ) {
nkeynes@359
  1372
                    case 0x0:
nkeynes@359
  1373
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1374
                            case 0x0:
nkeynes@359
  1375
                                { /* SHLL Rn */
nkeynes@359
  1376
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1377
                                load_reg( R_EAX, Rn );
nkeynes@359
  1378
                                SHL1_r32( R_EAX );
nkeynes@397
  1379
                                SETC_t();
nkeynes@359
  1380
                                store_reg( R_EAX, Rn );
nkeynes@417
  1381
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1382
                                }
nkeynes@359
  1383
                                break;
nkeynes@359
  1384
                            case 0x1:
nkeynes@359
  1385
                                { /* DT Rn */
nkeynes@359
  1386
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1387
                                load_reg( R_EAX, Rn );
nkeynes@386
  1388
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1389
                                store_reg( R_EAX, Rn );
nkeynes@359
  1390
                                SETE_t();
nkeynes@417
  1391
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1392
                                }
nkeynes@359
  1393
                                break;
nkeynes@359
  1394
                            case 0x2:
nkeynes@359
  1395
                                { /* SHAL Rn */
nkeynes@359
  1396
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1397
                                load_reg( R_EAX, Rn );
nkeynes@359
  1398
                                SHL1_r32( R_EAX );
nkeynes@397
  1399
                                SETC_t();
nkeynes@359
  1400
                                store_reg( R_EAX, Rn );
nkeynes@417
  1401
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1402
                                }
nkeynes@359
  1403
                                break;
nkeynes@359
  1404
                            default:
nkeynes@359
  1405
                                UNDEF();
nkeynes@359
  1406
                                break;
nkeynes@359
  1407
                        }
nkeynes@359
  1408
                        break;
nkeynes@359
  1409
                    case 0x1:
nkeynes@359
  1410
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1411
                            case 0x0:
nkeynes@359
  1412
                                { /* SHLR Rn */
nkeynes@359
  1413
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1414
                                load_reg( R_EAX, Rn );
nkeynes@359
  1415
                                SHR1_r32( R_EAX );
nkeynes@397
  1416
                                SETC_t();
nkeynes@359
  1417
                                store_reg( R_EAX, Rn );
nkeynes@417
  1418
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1419
                                }
nkeynes@359
  1420
                                break;
nkeynes@359
  1421
                            case 0x1:
nkeynes@359
  1422
                                { /* CMP/PZ Rn */
nkeynes@359
  1423
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1424
                                load_reg( R_EAX, Rn );
nkeynes@359
  1425
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1426
                                SETGE_t();
nkeynes@417
  1427
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1428
                                }
nkeynes@359
  1429
                                break;
nkeynes@359
  1430
                            case 0x2:
nkeynes@359
  1431
                                { /* SHAR Rn */
nkeynes@359
  1432
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1433
                                load_reg( R_EAX, Rn );
nkeynes@359
  1434
                                SAR1_r32( R_EAX );
nkeynes@397
  1435
                                SETC_t();
nkeynes@359
  1436
                                store_reg( R_EAX, Rn );
nkeynes@417
  1437
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1438
                                }
nkeynes@359
  1439
                                break;
nkeynes@359
  1440
                            default:
nkeynes@359
  1441
                                UNDEF();
nkeynes@359
  1442
                                break;
nkeynes@359
  1443
                        }
nkeynes@359
  1444
                        break;
nkeynes@359
  1445
                    case 0x2:
nkeynes@359
  1446
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1447
                            case 0x0:
nkeynes@359
  1448
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1449
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1450
                                load_reg( R_ECX, Rn );
nkeynes@416
  1451
                                precheck();
nkeynes@395
  1452
                                check_walign32( R_ECX );
nkeynes@386
  1453
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1454
                                store_reg( R_ECX, Rn );
nkeynes@359
  1455
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1456
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1457
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1458
                                }
nkeynes@359
  1459
                                break;
nkeynes@359
  1460
                            case 0x1:
nkeynes@359
  1461
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1462
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1463
                                load_reg( R_ECX, Rn );
nkeynes@416
  1464
                                precheck();
nkeynes@395
  1465
                                check_walign32( R_ECX );
nkeynes@386
  1466
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1467
                                store_reg( R_ECX, Rn );
nkeynes@359
  1468
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1469
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1470
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1471
                                }
nkeynes@359
  1472
                                break;
nkeynes@359
  1473
                            case 0x2:
nkeynes@359
  1474
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1475
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1476
                                load_reg( R_ECX, Rn );
nkeynes@416
  1477
                                precheck();
nkeynes@395
  1478
                                check_walign32( R_ECX );
nkeynes@386
  1479
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1480
                                store_reg( R_ECX, Rn );
nkeynes@359
  1481
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1482
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1483
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1484
                                }
nkeynes@359
  1485
                                break;
nkeynes@359
  1486
                            case 0x3:
nkeynes@359
  1487
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1488
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1489
                                precheck();
nkeynes@416
  1490
                                check_priv_no_precheck();
nkeynes@359
  1491
                                load_reg( R_ECX, Rn );
nkeynes@395
  1492
                                check_walign32( R_ECX );
nkeynes@386
  1493
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1494
                                store_reg( R_ECX, Rn );
nkeynes@359
  1495
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1496
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1497
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1498
                                }
nkeynes@359
  1499
                                break;
nkeynes@359
  1500
                            case 0x5:
nkeynes@359
  1501
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1502
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1503
                                load_reg( R_ECX, Rn );
nkeynes@416
  1504
                                precheck();
nkeynes@395
  1505
                                check_walign32( R_ECX );
nkeynes@386
  1506
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1507
                                store_reg( R_ECX, Rn );
nkeynes@359
  1508
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1509
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1510
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1511
                                }
nkeynes@359
  1512
                                break;
nkeynes@359
  1513
                            case 0x6:
nkeynes@359
  1514
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1515
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1516
                                load_reg( R_ECX, Rn );
nkeynes@416
  1517
                                precheck();
nkeynes@395
  1518
                                check_walign32( R_ECX );
nkeynes@386
  1519
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1520
                                store_reg( R_ECX, Rn );
nkeynes@359
  1521
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1522
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1523
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1524
                                }
nkeynes@359
  1525
                                break;
nkeynes@359
  1526
                            case 0xF:
nkeynes@359
  1527
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1528
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1529
                                precheck();
nkeynes@416
  1530
                                check_priv_no_precheck();
nkeynes@359
  1531
                                load_reg( R_ECX, Rn );
nkeynes@395
  1532
                                check_walign32( R_ECX );
nkeynes@386
  1533
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1534
                                store_reg( R_ECX, Rn );
nkeynes@359
  1535
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1536
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1537
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1538
                                }
nkeynes@359
  1539
                                break;
nkeynes@359
  1540
                            default:
nkeynes@359
  1541
                                UNDEF();
nkeynes@359
  1542
                                break;
nkeynes@359
  1543
                        }
nkeynes@359
  1544
                        break;
nkeynes@359
  1545
                    case 0x3:
nkeynes@359
  1546
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1547
                            case 0x0:
nkeynes@359
  1548
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1549
                                    case 0x0:
nkeynes@359
  1550
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1551
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1552
                                        precheck();
nkeynes@416
  1553
                                        check_priv_no_precheck();
nkeynes@395
  1554
                                        call_func0( sh4_read_sr );
nkeynes@374
  1555
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1556
                                        check_walign32( R_ECX );
nkeynes@386
  1557
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1558
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1559
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1560
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1561
                                        }
nkeynes@359
  1562
                                        break;
nkeynes@359
  1563
                                    case 0x1:
nkeynes@359
  1564
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1565
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1566
                                        load_reg( R_ECX, Rn );
nkeynes@416
  1567
                                        precheck();
nkeynes@395
  1568
                                        check_walign32( R_ECX );
nkeynes@386
  1569
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1570
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1571
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1572
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1573
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1574
                                        }
nkeynes@359
  1575
                                        break;
nkeynes@359
  1576
                                    case 0x2:
nkeynes@359
  1577
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1578
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1579
                                        precheck();
nkeynes@416
  1580
                                        check_priv_no_precheck();
nkeynes@359
  1581
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1582
                                        check_walign32( R_ECX );
nkeynes@386
  1583
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1584
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1585
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1586
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1587
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1588
                                        }
nkeynes@359
  1589
                                        break;
nkeynes@359
  1590
                                    case 0x3:
nkeynes@359
  1591
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1592
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1593
                                        precheck();
nkeynes@416
  1594
                                        check_priv_no_precheck();
nkeynes@359
  1595
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1596
                                        check_walign32( R_ECX );
nkeynes@386
  1597
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1598
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1599
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1600
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1601
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1602
                                        }
nkeynes@359
  1603
                                        break;
nkeynes@359
  1604
                                    case 0x4:
nkeynes@359
  1605
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1606
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1607
                                        precheck();
nkeynes@416
  1608
                                        check_priv_no_precheck();
nkeynes@359
  1609
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1610
                                        check_walign32( R_ECX );
nkeynes@386
  1611
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1612
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1613
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1614
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1615
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1616
                                        }
nkeynes@359
  1617
                                        break;
nkeynes@359
  1618
                                    default:
nkeynes@359
  1619
                                        UNDEF();
nkeynes@359
  1620
                                        break;
nkeynes@359
  1621
                                }
nkeynes@359
  1622
                                break;
nkeynes@359
  1623
                            case 0x1:
nkeynes@359
  1624
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1625
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@416
  1626
                                precheck();
nkeynes@416
  1627
                                check_priv_no_precheck();
nkeynes@374
  1628
                                load_reg( R_ECX, Rn );
nkeynes@395
  1629
                                check_walign32( R_ECX );
nkeynes@386
  1630
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1631
                                store_reg( R_ECX, Rn );
nkeynes@374
  1632
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1633
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1634
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1635
                                }
nkeynes@359
  1636
                                break;
nkeynes@359
  1637
                        }
nkeynes@359
  1638
                        break;
nkeynes@359
  1639
                    case 0x4:
nkeynes@359
  1640
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1641
                            case 0x0:
nkeynes@359
  1642
                                { /* ROTL Rn */
nkeynes@359
  1643
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1644
                                load_reg( R_EAX, Rn );
nkeynes@359
  1645
                                ROL1_r32( R_EAX );
nkeynes@359
  1646
                                store_reg( R_EAX, Rn );
nkeynes@359
  1647
                                SETC_t();
nkeynes@417
  1648
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1649
                                }
nkeynes@359
  1650
                                break;
nkeynes@359
  1651
                            case 0x2:
nkeynes@359
  1652
                                { /* ROTCL Rn */
nkeynes@359
  1653
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1654
                                load_reg( R_EAX, Rn );
nkeynes@417
  1655
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1656
                            	LDC_t();
nkeynes@417
  1657
                                }
nkeynes@359
  1658
                                RCL1_r32( R_EAX );
nkeynes@359
  1659
                                store_reg( R_EAX, Rn );
nkeynes@359
  1660
                                SETC_t();
nkeynes@417
  1661
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1662
                                }
nkeynes@359
  1663
                                break;
nkeynes@359
  1664
                            default:
nkeynes@359
  1665
                                UNDEF();
nkeynes@359
  1666
                                break;
nkeynes@359
  1667
                        }
nkeynes@359
  1668
                        break;
nkeynes@359
  1669
                    case 0x5:
nkeynes@359
  1670
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1671
                            case 0x0:
nkeynes@359
  1672
                                { /* ROTR Rn */
nkeynes@359
  1673
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1674
                                load_reg( R_EAX, Rn );
nkeynes@359
  1675
                                ROR1_r32( R_EAX );
nkeynes@359
  1676
                                store_reg( R_EAX, Rn );
nkeynes@359
  1677
                                SETC_t();
nkeynes@417
  1678
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1679
                                }
nkeynes@359
  1680
                                break;
nkeynes@359
  1681
                            case 0x1:
nkeynes@359
  1682
                                { /* CMP/PL Rn */
nkeynes@359
  1683
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1684
                                load_reg( R_EAX, Rn );
nkeynes@359
  1685
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1686
                                SETG_t();
nkeynes@417
  1687
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1688
                                }
nkeynes@359
  1689
                                break;
nkeynes@359
  1690
                            case 0x2:
nkeynes@359
  1691
                                { /* ROTCR Rn */
nkeynes@359
  1692
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1693
                                load_reg( R_EAX, Rn );
nkeynes@417
  1694
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1695
                            	LDC_t();
nkeynes@417
  1696
                                }
nkeynes@359
  1697
                                RCR1_r32( R_EAX );
nkeynes@359
  1698
                                store_reg( R_EAX, Rn );
nkeynes@359
  1699
                                SETC_t();
nkeynes@417
  1700
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1701
                                }
nkeynes@359
  1702
                                break;
nkeynes@359
  1703
                            default:
nkeynes@359
  1704
                                UNDEF();
nkeynes@359
  1705
                                break;
nkeynes@359
  1706
                        }
nkeynes@359
  1707
                        break;
nkeynes@359
  1708
                    case 0x6:
nkeynes@359
  1709
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1710
                            case 0x0:
nkeynes@359
  1711
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1712
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1713
                                load_reg( R_EAX, Rm );
nkeynes@416
  1714
                                precheck();
nkeynes@395
  1715
                                check_ralign32( R_EAX );
nkeynes@359
  1716
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1717
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1718
                                store_reg( R_EAX, Rm );
nkeynes@359
  1719
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1720
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1721
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1722
                                }
nkeynes@359
  1723
                                break;
nkeynes@359
  1724
                            case 0x1:
nkeynes@359
  1725
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1726
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1727
                                load_reg( R_EAX, Rm );
nkeynes@416
  1728
                                precheck();
nkeynes@395
  1729
                                check_ralign32( R_EAX );
nkeynes@359
  1730
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1731
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1732
                                store_reg( R_EAX, Rm );
nkeynes@359
  1733
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1734
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1735
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1736
                                }
nkeynes@359
  1737
                                break;
nkeynes@359
  1738
                            case 0x2:
nkeynes@359
  1739
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1740
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1741
                                load_reg( R_EAX, Rm );
nkeynes@416
  1742
                                precheck();
nkeynes@395
  1743
                                check_ralign32( R_EAX );
nkeynes@359
  1744
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1745
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1746
                                store_reg( R_EAX, Rm );
nkeynes@359
  1747
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1748
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1749
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1750
                                }
nkeynes@359
  1751
                                break;
nkeynes@359
  1752
                            case 0x3:
nkeynes@359
  1753
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1754
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1755
                                precheck();
nkeynes@416
  1756
                                check_priv_no_precheck();
nkeynes@359
  1757
                                load_reg( R_EAX, Rm );
nkeynes@395
  1758
                                check_ralign32( R_EAX );
nkeynes@359
  1759
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1760
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1761
                                store_reg( R_EAX, Rm );
nkeynes@359
  1762
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1763
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1764
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1765
                                }
nkeynes@359
  1766
                                break;
nkeynes@359
  1767
                            case 0x5:
nkeynes@359
  1768
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1769
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1770
                                load_reg( R_EAX, Rm );
nkeynes@416
  1771
                                precheck();
nkeynes@395
  1772
                                check_ralign32( R_EAX );
nkeynes@359
  1773
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1774
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1775
                                store_reg( R_EAX, Rm );
nkeynes@359
  1776
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1777
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1778
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1779
                                }
nkeynes@359
  1780
                                break;
nkeynes@359
  1781
                            case 0x6:
nkeynes@359
  1782
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1783
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1784
                                load_reg( R_EAX, Rm );
nkeynes@416
  1785
                                precheck();
nkeynes@395
  1786
                                check_ralign32( R_EAX );
nkeynes@359
  1787
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1788
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1789
                                store_reg( R_EAX, Rm );
nkeynes@359
  1790
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1791
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1792
                                update_fr_bank( R_EAX );
nkeynes@417
  1793
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1794
                                }
nkeynes@359
  1795
                                break;
nkeynes@359
  1796
                            case 0xF:
nkeynes@359
  1797
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1798
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1799
                                precheck();
nkeynes@416
  1800
                                check_priv_no_precheck();
nkeynes@359
  1801
                                load_reg( R_EAX, Rm );
nkeynes@395
  1802
                                check_ralign32( R_EAX );
nkeynes@359
  1803
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1804
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1805
                                store_reg( R_EAX, Rm );
nkeynes@359
  1806
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1807
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1808
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1809
                                }
nkeynes@359
  1810
                                break;
nkeynes@359
  1811
                            default:
nkeynes@359
  1812
                                UNDEF();
nkeynes@359
  1813
                                break;
nkeynes@359
  1814
                        }
nkeynes@359
  1815
                        break;
nkeynes@359
  1816
                    case 0x7:
nkeynes@359
  1817
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1818
                            case 0x0:
nkeynes@359
  1819
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1820
                                    case 0x0:
nkeynes@359
  1821
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1822
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1823
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1824
                                    	SLOTILLEGAL();
nkeynes@386
  1825
                                        } else {
nkeynes@416
  1826
                                    	precheck();
nkeynes@416
  1827
                                    	check_priv_no_precheck();
nkeynes@386
  1828
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1829
                                    	check_ralign32( R_EAX );
nkeynes@386
  1830
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1831
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1832
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1833
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1834
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1835
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1836
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1837
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1838
                                        }
nkeynes@359
  1839
                                        }
nkeynes@359
  1840
                                        break;
nkeynes@359
  1841
                                    case 0x1:
nkeynes@359
  1842
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1843
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1844
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1845
                                        precheck();
nkeynes@395
  1846
                                        check_ralign32( R_EAX );
nkeynes@359
  1847
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1848
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1849
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1850
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1851
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1852
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1853
                                        }
nkeynes@359
  1854
                                        break;
nkeynes@359
  1855
                                    case 0x2:
nkeynes@359
  1856
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1857
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1858
                                        precheck();
nkeynes@416
  1859
                                        check_priv_no_precheck();
nkeynes@359
  1860
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1861
                                        check_ralign32( R_EAX );
nkeynes@359
  1862
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1863
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1864
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1865
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1866
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1867
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1868
                                        }
nkeynes@359
  1869
                                        break;
nkeynes@359
  1870
                                    case 0x3:
nkeynes@359
  1871
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1872
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1873
                                        precheck();
nkeynes@416
  1874
                                        check_priv_no_precheck();
nkeynes@359
  1875
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1876
                                        check_ralign32( R_EAX );
nkeynes@359
  1877
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1878
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1879
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1880
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1881
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1882
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1883
                                        }
nkeynes@359
  1884
                                        break;
nkeynes@359
  1885
                                    case 0x4:
nkeynes@359
  1886
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1887
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1888
                                        precheck();
nkeynes@416
  1889
                                        check_priv_no_precheck();
nkeynes@359
  1890
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1891
                                        check_ralign32( R_EAX );
nkeynes@359
  1892
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1893
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1894
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1895
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1896
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1897
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1898
                                        }
nkeynes@359
  1899
                                        break;
nkeynes@359
  1900
                                    default:
nkeynes@359
  1901
                                        UNDEF();
nkeynes@359
  1902
                                        break;
nkeynes@359
  1903
                                }
nkeynes@359
  1904
                                break;
nkeynes@359
  1905
                            case 0x1:
nkeynes@359
  1906
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1907
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@416
  1908
                                precheck();
nkeynes@416
  1909
                                check_priv_no_precheck();
nkeynes@374
  1910
                                load_reg( R_EAX, Rm );
nkeynes@395
  1911
                                check_ralign32( R_EAX );
nkeynes@374
  1912
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1913
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1914
                                store_reg( R_EAX, Rm );
nkeynes@374
  1915
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1916
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1917
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1918
                                }
nkeynes@359
  1919
                                break;
nkeynes@359
  1920
                        }
nkeynes@359
  1921
                        break;
nkeynes@359
  1922
                    case 0x8:
nkeynes@359
  1923
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1924
                            case 0x0:
nkeynes@359
  1925
                                { /* SHLL2 Rn */
nkeynes@359
  1926
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1927
                                load_reg( R_EAX, Rn );
nkeynes@359
  1928
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1929
                                store_reg( R_EAX, Rn );
nkeynes@417
  1930
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1931
                                }
nkeynes@359
  1932
                                break;
nkeynes@359
  1933
                            case 0x1:
nkeynes@359
  1934
                                { /* SHLL8 Rn */
nkeynes@359
  1935
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1936
                                load_reg( R_EAX, Rn );
nkeynes@359
  1937
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1938
                                store_reg( R_EAX, Rn );
nkeynes@417
  1939
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1940
                                }
nkeynes@359
  1941
                                break;
nkeynes@359
  1942
                            case 0x2:
nkeynes@359
  1943
                                { /* SHLL16 Rn */
nkeynes@359
  1944
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1945
                                load_reg( R_EAX, Rn );
nkeynes@359
  1946
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1947
                                store_reg( R_EAX, Rn );
nkeynes@417
  1948
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1949
                                }
nkeynes@359
  1950
                                break;
nkeynes@359
  1951
                            default:
nkeynes@359
  1952
                                UNDEF();
nkeynes@359
  1953
                                break;
nkeynes@359
  1954
                        }
nkeynes@359
  1955
                        break;
nkeynes@359
  1956
                    case 0x9:
nkeynes@359
  1957
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1958
                            case 0x0:
nkeynes@359
  1959
                                { /* SHLR2 Rn */
nkeynes@359
  1960
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1961
                                load_reg( R_EAX, Rn );
nkeynes@359
  1962
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1963
                                store_reg( R_EAX, Rn );
nkeynes@417
  1964
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1965
                                }
nkeynes@359
  1966
                                break;
nkeynes@359
  1967
                            case 0x1:
nkeynes@359
  1968
                                { /* SHLR8 Rn */
nkeynes@359
  1969
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1970
                                load_reg( R_EAX, Rn );
nkeynes@359
  1971
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1972
                                store_reg( R_EAX, Rn );
nkeynes@417
  1973
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1974
                                }
nkeynes@359
  1975
                                break;
nkeynes@359
  1976
                            case 0x2:
nkeynes@359
  1977
                                { /* SHLR16 Rn */
nkeynes@359
  1978
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1979
                                load_reg( R_EAX, Rn );
nkeynes@359
  1980
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1981
                                store_reg( R_EAX, Rn );
nkeynes@417
  1982
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1983
                                }
nkeynes@359
  1984
                                break;
nkeynes@359
  1985
                            default:
nkeynes@359
  1986
                                UNDEF();
nkeynes@359
  1987
                                break;
nkeynes@359
  1988
                        }
nkeynes@359
  1989
                        break;
nkeynes@359
  1990
                    case 0xA:
nkeynes@359
  1991
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1992
                            case 0x0:
nkeynes@359
  1993
                                { /* LDS Rm, MACH */
nkeynes@359
  1994
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1995
                                load_reg( R_EAX, Rm );
nkeynes@359
  1996
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1997
                                }
nkeynes@359
  1998
                                break;
nkeynes@359
  1999
                            case 0x1:
nkeynes@359
  2000
                                { /* LDS Rm, MACL */
nkeynes@359
  2001
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2002
                                load_reg( R_EAX, Rm );
nkeynes@359
  2003
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  2004
                                }
nkeynes@359
  2005
                                break;
nkeynes@359
  2006
                            case 0x2:
nkeynes@359
  2007
                                { /* LDS Rm, PR */
nkeynes@359
  2008
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2009
                                load_reg( R_EAX, Rm );
nkeynes@359
  2010
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  2011
                                }
nkeynes@359
  2012
                                break;
nkeynes@359
  2013
                            case 0x3:
nkeynes@359
  2014
                                { /* LDC Rm, SGR */
nkeynes@359
  2015
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2016
                                check_priv();
nkeynes@359
  2017
                                load_reg( R_EAX, Rm );
nkeynes@359
  2018
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  2019
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2020
                                }
nkeynes@359
  2021
                                break;
nkeynes@359
  2022
                            case 0x5:
nkeynes@359
  2023
                                { /* LDS Rm, FPUL */
nkeynes@359
  2024
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2025
                                load_reg( R_EAX, Rm );
nkeynes@359
  2026
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2027
                                }
nkeynes@359
  2028
                                break;
nkeynes@359
  2029
                            case 0x6:
nkeynes@359
  2030
                                { /* LDS Rm, FPSCR */
nkeynes@359
  2031
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2032
                                load_reg( R_EAX, Rm );
nkeynes@359
  2033
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2034
                                update_fr_bank( R_EAX );
nkeynes@417
  2035
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2036
                                }
nkeynes@359
  2037
                                break;
nkeynes@359
  2038
                            case 0xF:
nkeynes@359
  2039
                                { /* LDC Rm, DBR */
nkeynes@359
  2040
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2041
                                check_priv();
nkeynes@359
  2042
                                load_reg( R_EAX, Rm );
nkeynes@359
  2043
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  2044
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2045
                                }
nkeynes@359
  2046
                                break;
nkeynes@359
  2047
                            default:
nkeynes@359
  2048
                                UNDEF();
nkeynes@359
  2049
                                break;
nkeynes@359
  2050
                        }
nkeynes@359
  2051
                        break;
nkeynes@359
  2052
                    case 0xB:
nkeynes@359
  2053
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2054
                            case 0x0:
nkeynes@359
  2055
                                { /* JSR @Rn */
nkeynes@359
  2056
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  2057
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2058
                            	SLOTILLEGAL();
nkeynes@374
  2059
                                } else {
nkeynes@374
  2060
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2061
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  2062
                            	load_reg( R_ECX, Rn );
nkeynes@408
  2063
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  2064
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  2065
                            	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2066
                            	exit_block_pcset(pc+2);
nkeynes@409
  2067
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2068
                            	return 4;
nkeynes@374
  2069
                                }
nkeynes@359
  2070
                                }
nkeynes@359
  2071
                                break;
nkeynes@359
  2072
                            case 0x1:
nkeynes@359
  2073
                                { /* TAS.B @Rn */
nkeynes@359
  2074
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  2075
                                load_reg( R_ECX, Rn );
nkeynes@361
  2076
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  2077
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  2078
                                SETE_t();
nkeynes@361
  2079
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  2080
                                load_reg( R_ECX, Rn );
nkeynes@361
  2081
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2082
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2083
                                }
nkeynes@359
  2084
                                break;
nkeynes@359
  2085
                            case 0x2:
nkeynes@359
  2086
                                { /* JMP @Rn */
nkeynes@359
  2087
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  2088
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2089
                            	SLOTILLEGAL();
nkeynes@374
  2090
                                } else {
nkeynes@408
  2091
                            	load_reg( R_ECX, Rn );
nkeynes@408
  2092
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  2093
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  2094
                            	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2095
                            	exit_block_pcset(pc+2);
nkeynes@409
  2096
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2097
                            	return 4;
nkeynes@374
  2098
                                }
nkeynes@359
  2099
                                }
nkeynes@359
  2100
                                break;
nkeynes@359
  2101
                            default:
nkeynes@359
  2102
                                UNDEF();
nkeynes@359
  2103
                                break;
nkeynes@359
  2104
                        }
nkeynes@359
  2105
                        break;
nkeynes@359
  2106
                    case 0xC:
nkeynes@359
  2107
                        { /* SHAD Rm, Rn */
nkeynes@359
  2108
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2109
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  2110
                        load_reg( R_EAX, Rn );
nkeynes@361
  2111
                        load_reg( R_ECX, Rm );
nkeynes@361
  2112
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2113
                        JGE_rel8(16, doshl);
nkeynes@361
  2114
                                        
nkeynes@361
  2115
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  2116
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2117
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  2118
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  2119
                        JMP_rel8(10, end);          // 2
nkeynes@386
  2120
                    
nkeynes@386
  2121
                        JMP_TARGET(emptysar);
nkeynes@386
  2122
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  2123
                        JMP_rel8(5, end2);
nkeynes@386
  2124
                    
nkeynes@380
  2125
                        JMP_TARGET(doshl);
nkeynes@361
  2126
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2127
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2128
                        JMP_TARGET(end);
nkeynes@386
  2129
                        JMP_TARGET(end2);
nkeynes@361
  2130
                        store_reg( R_EAX, Rn );
nkeynes@417
  2131
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2132
                        }
nkeynes@359
  2133
                        break;
nkeynes@359
  2134
                    case 0xD:
nkeynes@359
  2135
                        { /* SHLD Rm, Rn */
nkeynes@359
  2136
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2137
                        load_reg( R_EAX, Rn );
nkeynes@368
  2138
                        load_reg( R_ECX, Rm );
nkeynes@386
  2139
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2140
                        JGE_rel8(15, doshl);
nkeynes@368
  2141
                    
nkeynes@386
  2142
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2143
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2144
                        JE_rel8( 4, emptyshr );
nkeynes@386
  2145
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  2146
                        JMP_rel8(9, end);          // 2
nkeynes@386
  2147
                    
nkeynes@386
  2148
                        JMP_TARGET(emptyshr);
nkeynes@386
  2149
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  2150
                        JMP_rel8(5, end2);
nkeynes@386
  2151
                    
nkeynes@386
  2152
                        JMP_TARGET(doshl);
nkeynes@386
  2153
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2154
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2155
                        JMP_TARGET(end);
nkeynes@386
  2156
                        JMP_TARGET(end2);
nkeynes@368
  2157
                        store_reg( R_EAX, Rn );
nkeynes@417
  2158
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2159
                        }
nkeynes@359
  2160
                        break;
nkeynes@359
  2161
                    case 0xE:
nkeynes@359
  2162
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2163
                            case 0x0:
nkeynes@359
  2164
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2165
                                    case 0x0:
nkeynes@359
  2166
                                        { /* LDC Rm, SR */
nkeynes@359
  2167
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2168
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2169
                                    	SLOTILLEGAL();
nkeynes@386
  2170
                                        } else {
nkeynes@386
  2171
                                    	check_priv();
nkeynes@386
  2172
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2173
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2174
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2175
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2176
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2177
                                        }
nkeynes@359
  2178
                                        }
nkeynes@359
  2179
                                        break;
nkeynes@359
  2180
                                    case 0x1:
nkeynes@359
  2181
                                        { /* LDC Rm, GBR */
nkeynes@359
  2182
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2183
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2184
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2185
                                        }
nkeynes@359
  2186
                                        break;
nkeynes@359
  2187
                                    case 0x2:
nkeynes@359
  2188
                                        { /* LDC Rm, VBR */
nkeynes@359
  2189
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2190
                                        check_priv();
nkeynes@359
  2191
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2192
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2193
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2194
                                        }
nkeynes@359
  2195
                                        break;
nkeynes@359
  2196
                                    case 0x3:
nkeynes@359
  2197
                                        { /* LDC Rm, SSR */
nkeynes@359
  2198
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2199
                                        check_priv();
nkeynes@359
  2200
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2201
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2202
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2203
                                        }
nkeynes@359
  2204
                                        break;
nkeynes@359
  2205
                                    case 0x4:
nkeynes@359
  2206
                                        { /* LDC Rm, SPC */
nkeynes@359
  2207
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2208
                                        check_priv();
nkeynes@359
  2209
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2210
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2211
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2212
                                        }
nkeynes@359
  2213
                                        break;
nkeynes@359
  2214
                                    default:
nkeynes@359
  2215
                                        UNDEF();
nkeynes@359
  2216
                                        break;
nkeynes@359
  2217
                                }
nkeynes@359
  2218
                                break;
nkeynes@359
  2219
                            case 0x1:
nkeynes@359
  2220
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2221
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2222
                                check_priv();
nkeynes@374
  2223
                                load_reg( R_EAX, Rm );
nkeynes@374
  2224
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2225
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2226
                                }
nkeynes@359
  2227
                                break;
nkeynes@359
  2228
                        }
nkeynes@359
  2229
                        break;
nkeynes@359
  2230
                    case 0xF:
nkeynes@359
  2231
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2232
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  2233
                        load_reg( R_ECX, Rm );
nkeynes@416
  2234
                        precheck();
nkeynes@386
  2235
                        check_ralign16( R_ECX );
nkeynes@386
  2236
                        load_reg( R_ECX, Rn );
nkeynes@386
  2237
                        check_ralign16( R_ECX );
nkeynes@386
  2238
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  2239
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  2240
                        PUSH_r32( R_EAX );
nkeynes@386
  2241
                        load_reg( R_ECX, Rm );
nkeynes@386
  2242
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  2243
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  2244
                        POP_r32( R_ECX );
nkeynes@386
  2245
                        IMUL_r32( R_ECX );
nkeynes@386
  2246
                    
nkeynes@386
  2247
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2248
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2249
                        JE_rel8( 47, nosat );
nkeynes@386
  2250
                    
nkeynes@386
  2251
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2252
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2253
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2254
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2255
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2256
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2257
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2258
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2259
                    
nkeynes@386
  2260
                        JMP_TARGET(positive);
nkeynes@386
  2261
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2262
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2263
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2264
                    
nkeynes@386
  2265
                        JMP_TARGET(nosat);
nkeynes@386
  2266
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2267
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2268
                        JMP_TARGET(end);
nkeynes@386
  2269
                        JMP_TARGET(end2);
nkeynes@386
  2270
                        JMP_TARGET(end3);
nkeynes@417
  2271
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2272
                        }
nkeynes@359
  2273
                        break;
nkeynes@359
  2274
                }
nkeynes@359
  2275
                break;
nkeynes@359
  2276
            case 0x5:
nkeynes@359
  2277
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2278
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2279
                load_reg( R_ECX, Rm );
nkeynes@361
  2280
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  2281
                precheck();
nkeynes@374
  2282
                check_ralign32( R_ECX );
nkeynes@361
  2283
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2284
                store_reg( R_EAX, Rn );
nkeynes@417
  2285
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2286
                }
nkeynes@359
  2287
                break;
nkeynes@359
  2288
            case 0x6:
nkeynes@359
  2289
                switch( ir&0xF ) {
nkeynes@359
  2290
                    case 0x0:
nkeynes@359
  2291
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2292
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2293
                        load_reg( R_ECX, Rm );
nkeynes@359
  2294
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2295
                        store_reg( R_EAX, Rn );
nkeynes@417
  2296
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2297
                        }
nkeynes@359
  2298
                        break;
nkeynes@359
  2299
                    case 0x1:
nkeynes@359
  2300
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2301
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2302
                        load_reg( R_ECX, Rm );
nkeynes@416
  2303
                        precheck();
nkeynes@374
  2304
                        check_ralign16( R_ECX );
nkeynes@361
  2305
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2306
                        store_reg( R_EAX, Rn );
nkeynes@417
  2307
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
                        }
nkeynes@359
  2309
                        break;
nkeynes@359
  2310
                    case 0x2:
nkeynes@359
  2311
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2312
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2313
                        load_reg( R_ECX, Rm );
nkeynes@416
  2314
                        precheck();
nkeynes@374
  2315
                        check_ralign32( R_ECX );
nkeynes@361
  2316
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2317
                        store_reg( R_EAX, Rn );
nkeynes@417
  2318
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2319
                        }
nkeynes@359
  2320
                        break;
nkeynes@359
  2321
                    case 0x3:
nkeynes@359
  2322
                        { /* MOV Rm, Rn */
nkeynes@359
  2323
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2324
                        load_reg( R_EAX, Rm );
nkeynes@359
  2325
                        store_reg( R_EAX, Rn );
nkeynes@359
  2326
                        }
nkeynes@359
  2327
                        break;
nkeynes@359
  2328
                    case 0x4:
nkeynes@359
  2329
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2330
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2331
                        load_reg( R_ECX, Rm );
nkeynes@359
  2332
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2333
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2334
                        store_reg( R_EAX, Rm );
nkeynes@359
  2335
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2336
                        store_reg( R_EAX, Rn );
nkeynes@417
  2337
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2338
                        }
nkeynes@359
  2339
                        break;
nkeynes@359
  2340
                    case 0x5:
nkeynes@359
  2341
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2342
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2343
                        load_reg( R_EAX, Rm );
nkeynes@416
  2344
                        precheck();
nkeynes@374
  2345
                        check_ralign16( R_EAX );
nkeynes@361
  2346
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2347
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2348
                        store_reg( R_EAX, Rm );
nkeynes@361
  2349
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2350
                        store_reg( R_EAX, Rn );
nkeynes@417
  2351
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2352
                        }
nkeynes@359
  2353
                        break;
nkeynes@359
  2354
                    case 0x6:
nkeynes@359
  2355
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2356
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2357
                        load_reg( R_EAX, Rm );
nkeynes@416
  2358
                        precheck();
nkeynes@386
  2359
                        check_ralign32( R_EAX );
nkeynes@361
  2360
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2361
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2362
                        store_reg( R_EAX, Rm );
nkeynes@361
  2363
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2364
                        store_reg( R_EAX, Rn );
nkeynes@417
  2365
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2366
                        }
nkeynes@359
  2367
                        break;
nkeynes@359
  2368
                    case 0x7:
nkeynes@359
  2369
                        { /* NOT Rm, Rn */
nkeynes@359
  2370
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2371
                        load_reg( R_EAX, Rm );
nkeynes@359
  2372
                        NOT_r32( R_EAX );
nkeynes@359
  2373
                        store_reg( R_EAX, Rn );
nkeynes@417
  2374
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2375
                        }
nkeynes@359
  2376
                        break;
nkeynes@359
  2377
                    case 0x8:
nkeynes@359
  2378
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2379
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2380
                        load_reg( R_EAX, Rm );
nkeynes@359
  2381
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2382
                        store_reg( R_EAX, Rn );
nkeynes@359
  2383
                        }
nkeynes@359
  2384
                        break;
nkeynes@359
  2385
                    case 0x9:
nkeynes@359
  2386
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2387
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2388
                        load_reg( R_EAX, Rm );
nkeynes@359
  2389
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2390
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2391
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2392
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2393
                        store_reg( R_ECX, Rn );
nkeynes@417
  2394
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2395
                        }
nkeynes@359
  2396
                        break;
nkeynes@359
  2397
                    case 0xA:
nkeynes@359
  2398
                        { /* NEGC Rm, Rn */
nkeynes@359
  2399
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2400
                        load_reg( R_EAX, Rm );
nkeynes@359
  2401
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2402
                        LDC_t();
nkeynes@359
  2403
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2404
                        store_reg( R_ECX, Rn );
nkeynes@359
  2405
                        SETC_t();
nkeynes@417
  2406
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2407
                        }
nkeynes@359
  2408
                        break;
nkeynes@359
  2409
                    case 0xB:
nkeynes@359
  2410
                        { /* NEG Rm, Rn */
nkeynes@359
  2411
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2412
                        load_reg( R_EAX, Rm );
nkeynes@359
  2413
                        NEG_r32( R_EAX );
nkeynes@359
  2414
                        store_reg( R_EAX, Rn );
nkeynes@417
  2415
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2416
                        }
nkeynes@359
  2417
                        break;
nkeynes@359
  2418
                    case 0xC:
nkeynes@359
  2419
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2420
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2421
                        load_reg( R_EAX, Rm );
nkeynes@361
  2422
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2423
                        store_reg( R_EAX, Rn );
nkeynes@359
  2424
                        }
nkeynes@359
  2425
                        break;
nkeynes@359
  2426
                    case 0xD:
nkeynes@359
  2427
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2428
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2429
                        load_reg( R_EAX, Rm );
nkeynes@361
  2430
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2431
                        store_reg( R_EAX, Rn );
nkeynes@359
  2432
                        }
nkeynes@359
  2433
                        break;
nkeynes@359
  2434
                    case 0xE:
nkeynes@359
  2435
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2436
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2437
                        load_reg( R_EAX, Rm );
nkeynes@359
  2438
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2439
                        store_reg( R_EAX, Rn );
nkeynes@359
  2440
                        }
nkeynes@359
  2441
                        break;
nkeynes@359
  2442
                    case 0xF:
nkeynes@359
  2443
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2444
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2445
                        load_reg( R_EAX, Rm );
nkeynes@361
  2446
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2447
                        store_reg( R_EAX, Rn );
nkeynes@359
  2448
                        }
nkeynes@359
  2449
                        break;
nkeynes@359
  2450
                }
nkeynes@359
  2451
                break;
nkeynes@359
  2452
            case 0x7:
nkeynes@359
  2453
                { /* ADD #imm, Rn */
nkeynes@359
  2454
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2455
                load_reg( R_EAX, Rn );
nkeynes@359
  2456
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2457
                store_reg( R_EAX, Rn );
nkeynes@417
  2458
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2459
                }
nkeynes@359
  2460
                break;
nkeynes@359
  2461
            case 0x8:
nkeynes@359
  2462
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2463
                    case 0x0:
nkeynes@359
  2464
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2465
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2466
                        load_reg( R_EAX, 0 );
nkeynes@359
  2467
                        load_reg( R_ECX, Rn );
nkeynes@359
  2468
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2469
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2470
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2471
                        }
nkeynes@359
  2472
                        break;
nkeynes@359
  2473
                    case 0x1:
nkeynes@359
  2474
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2475
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2476
                        load_reg( R_ECX, Rn );
nkeynes@361
  2477
                        load_reg( R_EAX, 0 );
nkeynes@361
  2478
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2479
                        precheck();
nkeynes@374
  2480
                        check_walign16( R_ECX );
nkeynes@361
  2481
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2482
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2483
                        }
nkeynes@359
  2484
                        break;
nkeynes@359
  2485
                    case 0x4:
nkeynes@359
  2486
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2487
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2488
                        load_reg( R_ECX, Rm );
nkeynes@359
  2489
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2490
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2491
                        store_reg( R_EAX, 0 );
nkeynes@417
  2492
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2493
                        }
nkeynes@359
  2494
                        break;
nkeynes@359
  2495
                    case 0x5:
nkeynes@359
  2496
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2497
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2498
                        load_reg( R_ECX, Rm );
nkeynes@361
  2499
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2500
                        precheck();
nkeynes@374
  2501
                        check_ralign16( R_ECX );
nkeynes@361
  2502
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2503
                        store_reg( R_EAX, 0 );
nkeynes@417
  2504
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2505
                        }
nkeynes@359
  2506
                        break;
nkeynes@359
  2507
                    case 0x8:
nkeynes@359
  2508
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2509
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2510
                        load_reg( R_EAX, 0 );
nkeynes@359
  2511
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2512
                        SETE_t();
nkeynes@417
  2513
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2514
                        }
nkeynes@359
  2515
                        break;
nkeynes@359
  2516
                    case 0x9:
nkeynes@359
  2517
                        { /* BT disp */
nkeynes@359
  2518
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2519
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2520
                    	SLOTILLEGAL();
nkeynes@374
  2521
                        } else {
nkeynes@417
  2522
                    	JF_rel8( 29, nottaken );
nkeynes@408
  2523
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2524
                    	JMP_TARGET(nottaken);
nkeynes@408
  2525
                    	return 2;
nkeynes@374
  2526
                        }
nkeynes@359
  2527
                        }
nkeynes@359
  2528
                        break;
nkeynes@359
  2529
                    case 0xB:
nkeynes@359
  2530
                        { /* BF disp */
nkeynes@359
  2531
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2532
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2533
                    	SLOTILLEGAL();
nkeynes@374
  2534
                        } else {
nkeynes@417
  2535
                    	JT_rel8( 29, nottaken );
nkeynes@408
  2536
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2537
                    	JMP_TARGET(nottaken);
nkeynes@408
  2538
                    	return 2;
nkeynes@374
  2539
                        }
nkeynes@359
  2540
                        }
nkeynes@359
  2541
                        break;
nkeynes@359
  2542
                    case 0xD:
nkeynes@359
  2543
                        { /* BT/S disp */
nkeynes@359
  2544
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2545
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2546
                    	SLOTILLEGAL();
nkeynes@374
  2547
                        } else {
nkeynes@408
  2548
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2549
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2550
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2551
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2552
                    	}
nkeynes@417
  2553
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@408
  2554
                    	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2555
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2556
                    	// not taken
nkeynes@408
  2557
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  2558
                    	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2559
                    	return 4;
nkeynes@374
  2560
                        }
nkeynes@359
  2561
                        }
nkeynes@359
  2562
                        break;
nkeynes@359
  2563
                    case 0xF:
nkeynes@359
  2564
                        { /* BF/S disp */
nkeynes@359
  2565
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2566
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2567
                    	SLOTILLEGAL();
nkeynes@374
  2568
                        } else {
nkeynes@408
  2569
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2570
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2571
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2572
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2573
                    	}
nkeynes@417
  2574
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@408
  2575
                    	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2576
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2577
                    	// not taken
nkeynes@408
  2578
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  2579
                    	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  2580
                    	return 4;
nkeynes@374
  2581
                        }
nkeynes@359
  2582
                        }
nkeynes@359
  2583
                        break;
nkeynes@359
  2584
                    default:
nkeynes@359
  2585
                        UNDEF();
nkeynes@359
  2586
                        break;
nkeynes@359
  2587
                }
nkeynes@359
  2588
                break;
nkeynes@359
  2589
            case 0x9:
nkeynes@359
  2590
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2591
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2592
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2593
            	SLOTILLEGAL();
nkeynes@374
  2594
                } else {
nkeynes@374
  2595
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2596
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2597
            	store_reg( R_EAX, Rn );
nkeynes@417
  2598
            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2599
                }
nkeynes@359
  2600
                }
nkeynes@359
  2601
                break;
nkeynes@359
  2602
            case 0xA:
nkeynes@359
  2603
                { /* BRA disp */
nkeynes@359
  2604
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2605
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2606
            	SLOTILLEGAL();
nkeynes@374
  2607
                } else {
nkeynes@374
  2608
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  2609
            	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  2610
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2611
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2612
            	return 4;
nkeynes@374
  2613
                }
nkeynes@359
  2614
                }
nkeynes@359
  2615
                break;
nkeynes@359
  2616
            case 0xB:
nkeynes@359
  2617
                { /* BSR disp */
nkeynes@359
  2618
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2619
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2620
            	SLOTILLEGAL();
nkeynes@374
  2621
                } else {
nkeynes@374
  2622
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2623
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2624
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  2625
            	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  2626
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2627
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2628
            	return 4;
nkeynes@374
  2629
                }
nkeynes@359
  2630
                }
nkeynes@359
  2631
                break;
nkeynes@359
  2632
            case 0xC:
nkeynes@359
  2633
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2634
                    case 0x0:
nkeynes@359
  2635
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2636
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2637
                        load_reg( R_EAX, 0 );
nkeynes@359
  2638
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2639
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2640
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2641
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2642
                        }
nkeynes@359
  2643
                        break;
nkeynes@359
  2644
                    case 0x1:
nkeynes@359
  2645
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2646
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2647
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2648
                        load_reg( R_EAX, 0 );
nkeynes@361
  2649
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2650
                        precheck();
nkeynes@374
  2651
                        check_walign16( R_ECX );
nkeynes@361
  2652
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2653
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2654
                        }
nkeynes@359
  2655
                        break;
nkeynes@359
  2656
                    case 0x2:
nkeynes@359
  2657
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2658
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2659
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2660
                        load_reg( R_EAX, 0 );
nkeynes@361
  2661
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2662
                        precheck();
nkeynes@374
  2663
                        check_walign32( R_ECX );
nkeynes@361
  2664
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2665
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2666
                        }
nkeynes@359
  2667
                        break;
nkeynes@359
  2668
                    case 0x3:
nkeynes@359
  2669
                        { /* TRAPA #imm */
nkeynes@359
  2670
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2671
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2672
                    	SLOTILLEGAL();
nkeynes@374
  2673
                        } else {
nkeynes@388
  2674
                    	PUSH_imm32( imm );
nkeynes@388
  2675
                    	call_func0( sh4_raise_trap );
nkeynes@388
  2676
                    	ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
  2677
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2678
                    	exit_block_pcset(pc);
nkeynes@409
  2679
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2680
                    	return 2;
nkeynes@374
  2681
                        }
nkeynes@359
  2682
                        }
nkeynes@359
  2683
                        break;
nkeynes@359
  2684
                    case 0x4:
nkeynes@359
  2685
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2686
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2687
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2688
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2689
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2690
                        store_reg( R_EAX, 0 );
nkeynes@417
  2691
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2692
                        }
nkeynes@359
  2693
                        break;
nkeynes@359
  2694
                    case 0x5:
nkeynes@359
  2695
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2696
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2697
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2698
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2699
                        precheck();
nkeynes@374
  2700
                        check_ralign16( R_ECX );
nkeynes@361
  2701
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2702
                        store_reg( R_EAX, 0 );
nkeynes@417
  2703
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2704
                        }
nkeynes@359
  2705
                        break;
nkeynes@359
  2706
                    case 0x6:
nkeynes@359
  2707
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2708
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2709
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2710
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2711
                        precheck();