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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 417:bd927df302a9
prev416:714df603c869
next502:c4ecae2b1b5e
author nkeynes
date Thu Oct 04 08:47:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Suppress redundant T flag loads
Tweak run_slice for performance
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.19 2007-10-04 08:47:27 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	precheck();\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exit( EXIT_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exit( EXIT_ILLEGAL );\
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	}\
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    }\
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static void check_priv_no_precheck()
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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#define check_fpuen( ) \
nkeynes@416
   351
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   352
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   353
	precheck();\
nkeynes@416
   354
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   355
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   356
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   357
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
nkeynes@416
   358
	} else {\
nkeynes@416
   359
	    JNE_exit(EXIT_FPU_DISABLED);\
nkeynes@416
   360
	}\
nkeynes@416
   361
    }
nkeynes@416
   362
nkeynes@416
   363
static void check_fpuen_no_precheck()
nkeynes@368
   364
{
nkeynes@368
   365
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   366
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   367
	load_spreg( R_EAX, R_SR );
nkeynes@368
   368
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   369
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   370
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   371
	} else {
nkeynes@368
   372
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   373
	}
nkeynes@368
   374
    }
nkeynes@416
   375
nkeynes@368
   376
}
nkeynes@368
   377
nkeynes@368
   378
static void check_ralign16( int x86reg )
nkeynes@368
   379
{
nkeynes@368
   380
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   381
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   382
}
nkeynes@368
   383
nkeynes@368
   384
static void check_walign16( int x86reg )
nkeynes@368
   385
{
nkeynes@368
   386
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   387
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   388
}
nkeynes@368
   389
nkeynes@368
   390
static void check_ralign32( int x86reg )
nkeynes@368
   391
{
nkeynes@368
   392
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   393
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   394
}
nkeynes@368
   395
static void check_walign32( int x86reg )
nkeynes@368
   396
{
nkeynes@368
   397
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   398
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   399
}
nkeynes@368
   400
nkeynes@361
   401
#define UNDEF()
nkeynes@361
   402
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   403
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   404
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   405
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   406
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   407
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   408
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   409
nkeynes@416
   410
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   411
nkeynes@368
   412
nkeynes@359
   413
nkeynes@359
   414
/**
nkeynes@359
   415
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   416
 * SI/DI as required
nkeynes@359
   417
 */
nkeynes@408
   418
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   419
{
nkeynes@368
   420
    PUSH_r32(R_EBP);
nkeynes@359
   421
    /* mov &sh4r, ebp */
nkeynes@359
   422
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@368
   423
    
nkeynes@368
   424
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   425
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   426
    sh4_x86.fpuen_checked = FALSE;
nkeynes@409
   427
    sh4_x86.branch_taken = FALSE;
nkeynes@368
   428
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   429
    sh4_x86.block_start_pc = pc;
nkeynes@417
   430
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
   431
}
nkeynes@359
   432
nkeynes@368
   433
/**
nkeynes@408
   434
 * Exit the block to an absolute PC
nkeynes@416
   435
 * Bytes: 29
nkeynes@368
   436
 */
nkeynes@408
   437
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@368
   438
{
nkeynes@408
   439
    load_imm32( R_ECX, pc );                            // 5
nkeynes@408
   440
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@408
   441
    MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
nkeynes@408
   442
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@408
   443
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   444
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@374
   445
    POP_r32(R_EBP);
nkeynes@368
   446
    RET();
nkeynes@359
   447
}
nkeynes@359
   448
nkeynes@359
   449
/**
nkeynes@408
   450
 * Exit the block with sh4r.pc already written
nkeynes@416
   451
 * Bytes: 15
nkeynes@408
   452
 */
nkeynes@408
   453
void exit_block_pcset( pc )
nkeynes@408
   454
{
nkeynes@408
   455
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   456
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@417
   457
    load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   458
    call_func1(xlat_get_code,R_EAX);
nkeynes@408
   459
    POP_r32(R_EBP);
nkeynes@408
   460
    RET();
nkeynes@408
   461
}
nkeynes@408
   462
nkeynes@408
   463
/**
nkeynes@408
   464
 * Write the block trailer (exception handling block)
nkeynes@359
   465
 */
nkeynes@359
   466
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@409
   467
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@409
   468
	// Didn't exit unconditionally already, so write the termination here
nkeynes@409
   469
	exit_block( pc, pc );
nkeynes@409
   470
    }
nkeynes@388
   471
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   472
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   473
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   474
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   475
	JMP_rel8( 33, target1 );
nkeynes@388
   476
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   477
	JMP_rel8( 26, target2 );
nkeynes@388
   478
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   479
	JMP_rel8( 19, target3 );
nkeynes@388
   480
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   481
	JMP_rel8( 12, target4 );
nkeynes@388
   482
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   483
	JMP_rel8( 5, target5 );
nkeynes@388
   484
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   485
	// target
nkeynes@388
   486
	JMP_TARGET(target1);
nkeynes@388
   487
	JMP_TARGET(target2);
nkeynes@388
   488
	JMP_TARGET(target3);
nkeynes@388
   489
	JMP_TARGET(target4);
nkeynes@388
   490
	JMP_TARGET(target5);
nkeynes@417
   491
	// Raise exception
nkeynes@388
   492
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@416
   493
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@416
   494
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@388
   495
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   496
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@416
   497
	MUL_r32( R_EDX );
nkeynes@417
   498
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@388
   499
	
nkeynes@388
   500
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   501
	CALL_r32( R_EAX ); // 2
nkeynes@388
   502
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
   503
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   504
	call_func1(xlat_get_code,R_EAX);
nkeynes@388
   505
	POP_r32(R_EBP);
nkeynes@388
   506
	RET();
nkeynes@368
   507
nkeynes@388
   508
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   509
    }
nkeynes@368
   510
nkeynes@359
   511
}
nkeynes@359
   512
nkeynes@388
   513
nkeynes@388
   514
extern uint16_t *sh4_icache;
nkeynes@388
   515
extern uint32_t sh4_icache_addr;
nkeynes@388
   516
nkeynes@359
   517
/**
nkeynes@359
   518
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   519
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   520
 * 
nkeynes@359
   521
 *
nkeynes@359
   522
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   523
 * (eg a branch or 
nkeynes@359
   524
 */
nkeynes@408
   525
uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
nkeynes@359
   526
{
nkeynes@388
   527
    uint32_t ir;
nkeynes@388
   528
    /* Read instruction */
nkeynes@388
   529
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   530
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   531
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   532
    } else {
nkeynes@388
   533
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   534
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   535
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   536
	     * region, fallback on the full-blown memory read
nkeynes@388
   537
	     */
nkeynes@388
   538
	    sh4_icache = NULL;
nkeynes@388
   539
	    ir = sh4_read_word(pc);
nkeynes@388
   540
	} else {
nkeynes@388
   541
	    sh4_icache_addr = pageaddr;
nkeynes@388
   542
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   543
	}
nkeynes@388
   544
    }
nkeynes@388
   545
nkeynes@359
   546
%%
nkeynes@359
   547
/* ALU operations */
nkeynes@359
   548
ADD Rm, Rn {:
nkeynes@359
   549
    load_reg( R_EAX, Rm );
nkeynes@359
   550
    load_reg( R_ECX, Rn );
nkeynes@359
   551
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   552
    store_reg( R_ECX, Rn );
nkeynes@417
   553
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   554
:}
nkeynes@359
   555
ADD #imm, Rn {:  
nkeynes@359
   556
    load_reg( R_EAX, Rn );
nkeynes@359
   557
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   558
    store_reg( R_EAX, Rn );
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   560
:}
nkeynes@359
   561
ADDC Rm, Rn {:
nkeynes@417
   562
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   563
	LDC_t();
nkeynes@417
   564
    }
nkeynes@359
   565
    load_reg( R_EAX, Rm );
nkeynes@359
   566
    load_reg( R_ECX, Rn );
nkeynes@359
   567
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   568
    store_reg( R_ECX, Rn );
nkeynes@359
   569
    SETC_t();
nkeynes@417
   570
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   571
:}
nkeynes@359
   572
ADDV Rm, Rn {:
nkeynes@359
   573
    load_reg( R_EAX, Rm );
nkeynes@359
   574
    load_reg( R_ECX, Rn );
nkeynes@359
   575
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   576
    store_reg( R_ECX, Rn );
nkeynes@359
   577
    SETO_t();
nkeynes@417
   578
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   579
:}
nkeynes@359
   580
AND Rm, Rn {:
nkeynes@359
   581
    load_reg( R_EAX, Rm );
nkeynes@359
   582
    load_reg( R_ECX, Rn );
nkeynes@359
   583
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   584
    store_reg( R_ECX, Rn );
nkeynes@417
   585
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   586
:}
nkeynes@359
   587
AND #imm, R0 {:  
nkeynes@359
   588
    load_reg( R_EAX, 0 );
nkeynes@359
   589
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   590
    store_reg( R_EAX, 0 );
nkeynes@417
   591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   592
:}
nkeynes@359
   593
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   594
    load_reg( R_EAX, 0 );
nkeynes@359
   595
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   596
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   597
    PUSH_r32(R_ECX);
nkeynes@386
   598
    call_func0(sh4_read_byte);
nkeynes@386
   599
    POP_r32(R_ECX);
nkeynes@386
   600
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   601
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   603
:}
nkeynes@359
   604
CMP/EQ Rm, Rn {:  
nkeynes@359
   605
    load_reg( R_EAX, Rm );
nkeynes@359
   606
    load_reg( R_ECX, Rn );
nkeynes@359
   607
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   608
    SETE_t();
nkeynes@417
   609
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   610
:}
nkeynes@359
   611
CMP/EQ #imm, R0 {:  
nkeynes@359
   612
    load_reg( R_EAX, 0 );
nkeynes@359
   613
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   614
    SETE_t();
nkeynes@417
   615
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   616
:}
nkeynes@359
   617
CMP/GE Rm, Rn {:  
nkeynes@359
   618
    load_reg( R_EAX, Rm );
nkeynes@359
   619
    load_reg( R_ECX, Rn );
nkeynes@359
   620
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   621
    SETGE_t();
nkeynes@417
   622
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   623
:}
nkeynes@359
   624
CMP/GT Rm, Rn {: 
nkeynes@359
   625
    load_reg( R_EAX, Rm );
nkeynes@359
   626
    load_reg( R_ECX, Rn );
nkeynes@359
   627
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   628
    SETG_t();
nkeynes@417
   629
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   630
:}
nkeynes@359
   631
CMP/HI Rm, Rn {:  
nkeynes@359
   632
    load_reg( R_EAX, Rm );
nkeynes@359
   633
    load_reg( R_ECX, Rn );
nkeynes@359
   634
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   635
    SETA_t();
nkeynes@417
   636
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   637
:}
nkeynes@359
   638
CMP/HS Rm, Rn {: 
nkeynes@359
   639
    load_reg( R_EAX, Rm );
nkeynes@359
   640
    load_reg( R_ECX, Rn );
nkeynes@359
   641
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   642
    SETAE_t();
nkeynes@417
   643
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   644
 :}
nkeynes@359
   645
CMP/PL Rn {: 
nkeynes@359
   646
    load_reg( R_EAX, Rn );
nkeynes@359
   647
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   648
    SETG_t();
nkeynes@417
   649
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   650
:}
nkeynes@359
   651
CMP/PZ Rn {:  
nkeynes@359
   652
    load_reg( R_EAX, Rn );
nkeynes@359
   653
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   654
    SETGE_t();
nkeynes@417
   655
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   656
:}
nkeynes@361
   657
CMP/STR Rm, Rn {:  
nkeynes@368
   658
    load_reg( R_EAX, Rm );
nkeynes@368
   659
    load_reg( R_ECX, Rn );
nkeynes@368
   660
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   661
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   662
    JE_rel8(13, target1);
nkeynes@368
   663
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   664
    JE_rel8(9, target2);
nkeynes@368
   665
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   666
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   667
    JE_rel8(2, target3);
nkeynes@368
   668
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   669
    JMP_TARGET(target1);
nkeynes@380
   670
    JMP_TARGET(target2);
nkeynes@380
   671
    JMP_TARGET(target3);
nkeynes@368
   672
    SETE_t();
nkeynes@417
   673
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   674
:}
nkeynes@361
   675
DIV0S Rm, Rn {:
nkeynes@361
   676
    load_reg( R_EAX, Rm );
nkeynes@386
   677
    load_reg( R_ECX, Rn );
nkeynes@361
   678
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   679
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   680
    store_spreg( R_EAX, R_M );
nkeynes@361
   681
    store_spreg( R_ECX, R_Q );
nkeynes@361
   682
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   683
    SETNE_t();
nkeynes@417
   684
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   685
:}
nkeynes@361
   686
DIV0U {:  
nkeynes@361
   687
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   688
    store_spreg( R_EAX, R_Q );
nkeynes@361
   689
    store_spreg( R_EAX, R_M );
nkeynes@361
   690
    store_spreg( R_EAX, R_T );
nkeynes@417
   691
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   692
:}
nkeynes@386
   693
DIV1 Rm, Rn {:
nkeynes@386
   694
    load_spreg( R_ECX, R_M );
nkeynes@386
   695
    load_reg( R_EAX, Rn );
nkeynes@417
   696
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   697
	LDC_t();
nkeynes@417
   698
    }
nkeynes@386
   699
    RCL1_r32( R_EAX );
nkeynes@386
   700
    SETC_r8( R_DL ); // Q'
nkeynes@386
   701
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   702
    JE_rel8(5, mqequal);
nkeynes@386
   703
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   704
    JMP_rel8(3, end);
nkeynes@380
   705
    JMP_TARGET(mqequal);
nkeynes@386
   706
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   707
    JMP_TARGET(end);
nkeynes@386
   708
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   709
    SETC_r8(R_AL); // tmp1
nkeynes@386
   710
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   711
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   712
    store_spreg( R_ECX, R_Q );
nkeynes@386
   713
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   714
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   715
    store_spreg( R_EAX, R_T );
nkeynes@417
   716
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   717
:}
nkeynes@361
   718
DMULS.L Rm, Rn {:  
nkeynes@361
   719
    load_reg( R_EAX, Rm );
nkeynes@361
   720
    load_reg( R_ECX, Rn );
nkeynes@361
   721
    IMUL_r32(R_ECX);
nkeynes@361
   722
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   723
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   724
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   725
:}
nkeynes@361
   726
DMULU.L Rm, Rn {:  
nkeynes@361
   727
    load_reg( R_EAX, Rm );
nkeynes@361
   728
    load_reg( R_ECX, Rn );
nkeynes@361
   729
    MUL_r32(R_ECX);
nkeynes@361
   730
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   731
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   732
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   733
:}
nkeynes@359
   734
DT Rn {:  
nkeynes@359
   735
    load_reg( R_EAX, Rn );
nkeynes@382
   736
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   737
    store_reg( R_EAX, Rn );
nkeynes@359
   738
    SETE_t();
nkeynes@417
   739
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   740
:}
nkeynes@359
   741
EXTS.B Rm, Rn {:  
nkeynes@359
   742
    load_reg( R_EAX, Rm );
nkeynes@359
   743
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   744
    store_reg( R_EAX, Rn );
nkeynes@359
   745
:}
nkeynes@361
   746
EXTS.W Rm, Rn {:  
nkeynes@361
   747
    load_reg( R_EAX, Rm );
nkeynes@361
   748
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   749
    store_reg( R_EAX, Rn );
nkeynes@361
   750
:}
nkeynes@361
   751
EXTU.B Rm, Rn {:  
nkeynes@361
   752
    load_reg( R_EAX, Rm );
nkeynes@361
   753
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   754
    store_reg( R_EAX, Rn );
nkeynes@361
   755
:}
nkeynes@361
   756
EXTU.W Rm, Rn {:  
nkeynes@361
   757
    load_reg( R_EAX, Rm );
nkeynes@361
   758
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   759
    store_reg( R_EAX, Rn );
nkeynes@361
   760
:}
nkeynes@386
   761
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   762
    load_reg( R_ECX, Rm );
nkeynes@416
   763
    precheck();
nkeynes@386
   764
    check_ralign32( R_ECX );
nkeynes@386
   765
    load_reg( R_ECX, Rn );
nkeynes@386
   766
    check_ralign32( R_ECX );
nkeynes@386
   767
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   768
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   769
    PUSH_r32( R_EAX );
nkeynes@386
   770
    load_reg( R_ECX, Rm );
nkeynes@386
   771
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   772
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   773
    POP_r32( R_ECX );
nkeynes@386
   774
    IMUL_r32( R_ECX );
nkeynes@386
   775
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   776
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   777
nkeynes@386
   778
    load_spreg( R_ECX, R_S );
nkeynes@386
   779
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   780
    JE_rel8( 7, nosat );
nkeynes@386
   781
    call_func0( signsat48 );
nkeynes@386
   782
    JMP_TARGET( nosat );
nkeynes@417
   783
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   784
:}
nkeynes@386
   785
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   786
    load_reg( R_ECX, Rm );
nkeynes@416
   787
    precheck();
nkeynes@386
   788
    check_ralign16( R_ECX );
nkeynes@386
   789
    load_reg( R_ECX, Rn );
nkeynes@386
   790
    check_ralign16( R_ECX );
nkeynes@386
   791
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   792
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   793
    PUSH_r32( R_EAX );
nkeynes@386
   794
    load_reg( R_ECX, Rm );
nkeynes@386
   795
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   796
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   797
    POP_r32( R_ECX );
nkeynes@386
   798
    IMUL_r32( R_ECX );
nkeynes@386
   799
nkeynes@386
   800
    load_spreg( R_ECX, R_S );
nkeynes@386
   801
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   802
    JE_rel8( 47, nosat );
nkeynes@386
   803
nkeynes@386
   804
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   805
    JNO_rel8( 51, end );            // 2
nkeynes@386
   806
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   807
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   808
    JS_rel8( 13, positive );        // 2
nkeynes@386
   809
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   810
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   811
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   812
nkeynes@386
   813
    JMP_TARGET(positive);
nkeynes@386
   814
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   815
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   816
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   817
nkeynes@386
   818
    JMP_TARGET(nosat);
nkeynes@386
   819
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   820
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   821
    JMP_TARGET(end);
nkeynes@386
   822
    JMP_TARGET(end2);
nkeynes@386
   823
    JMP_TARGET(end3);
nkeynes@417
   824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   825
:}
nkeynes@359
   826
MOVT Rn {:  
nkeynes@359
   827
    load_spreg( R_EAX, R_T );
nkeynes@359
   828
    store_reg( R_EAX, Rn );
nkeynes@359
   829
:}
nkeynes@361
   830
MUL.L Rm, Rn {:  
nkeynes@361
   831
    load_reg( R_EAX, Rm );
nkeynes@361
   832
    load_reg( R_ECX, Rn );
nkeynes@361
   833
    MUL_r32( R_ECX );
nkeynes@361
   834
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   835
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   836
:}
nkeynes@374
   837
MULS.W Rm, Rn {:
nkeynes@374
   838
    load_reg16s( R_EAX, Rm );
nkeynes@374
   839
    load_reg16s( R_ECX, Rn );
nkeynes@374
   840
    MUL_r32( R_ECX );
nkeynes@374
   841
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   842
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   843
:}
nkeynes@374
   844
MULU.W Rm, Rn {:  
nkeynes@374
   845
    load_reg16u( R_EAX, Rm );
nkeynes@374
   846
    load_reg16u( R_ECX, Rn );
nkeynes@374
   847
    MUL_r32( R_ECX );
nkeynes@374
   848
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   849
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   850
:}
nkeynes@359
   851
NEG Rm, Rn {:
nkeynes@359
   852
    load_reg( R_EAX, Rm );
nkeynes@359
   853
    NEG_r32( R_EAX );
nkeynes@359
   854
    store_reg( R_EAX, Rn );
nkeynes@417
   855
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   856
:}
nkeynes@359
   857
NEGC Rm, Rn {:  
nkeynes@359
   858
    load_reg( R_EAX, Rm );
nkeynes@359
   859
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   860
    LDC_t();
nkeynes@359
   861
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   862
    store_reg( R_ECX, Rn );
nkeynes@359
   863
    SETC_t();
nkeynes@417
   864
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   865
:}
nkeynes@359
   866
NOT Rm, Rn {:  
nkeynes@359
   867
    load_reg( R_EAX, Rm );
nkeynes@359
   868
    NOT_r32( R_EAX );
nkeynes@359
   869
    store_reg( R_EAX, Rn );
nkeynes@417
   870
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   871
:}
nkeynes@359
   872
OR Rm, Rn {:  
nkeynes@359
   873
    load_reg( R_EAX, Rm );
nkeynes@359
   874
    load_reg( R_ECX, Rn );
nkeynes@359
   875
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   876
    store_reg( R_ECX, Rn );
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   878
:}
nkeynes@359
   879
OR #imm, R0 {:
nkeynes@359
   880
    load_reg( R_EAX, 0 );
nkeynes@359
   881
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   882
    store_reg( R_EAX, 0 );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@374
   885
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   886
    load_reg( R_EAX, 0 );
nkeynes@374
   887
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   888
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   889
    PUSH_r32(R_ECX);
nkeynes@386
   890
    call_func0(sh4_read_byte);
nkeynes@386
   891
    POP_r32(R_ECX);
nkeynes@386
   892
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   893
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   895
:}
nkeynes@359
   896
ROTCL Rn {:
nkeynes@359
   897
    load_reg( R_EAX, Rn );
nkeynes@417
   898
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   899
	LDC_t();
nkeynes@417
   900
    }
nkeynes@359
   901
    RCL1_r32( R_EAX );
nkeynes@359
   902
    store_reg( R_EAX, Rn );
nkeynes@359
   903
    SETC_t();
nkeynes@417
   904
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   905
:}
nkeynes@359
   906
ROTCR Rn {:  
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@417
   908
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   909
	LDC_t();
nkeynes@417
   910
    }
nkeynes@359
   911
    RCR1_r32( R_EAX );
nkeynes@359
   912
    store_reg( R_EAX, Rn );
nkeynes@359
   913
    SETC_t();
nkeynes@417
   914
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   915
:}
nkeynes@359
   916
ROTL Rn {:  
nkeynes@359
   917
    load_reg( R_EAX, Rn );
nkeynes@359
   918
    ROL1_r32( R_EAX );
nkeynes@359
   919
    store_reg( R_EAX, Rn );
nkeynes@359
   920
    SETC_t();
nkeynes@417
   921
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   922
:}
nkeynes@359
   923
ROTR Rn {:  
nkeynes@359
   924
    load_reg( R_EAX, Rn );
nkeynes@359
   925
    ROR1_r32( R_EAX );
nkeynes@359
   926
    store_reg( R_EAX, Rn );
nkeynes@359
   927
    SETC_t();
nkeynes@417
   928
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   929
:}
nkeynes@359
   930
SHAD Rm, Rn {:
nkeynes@359
   931
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   932
    load_reg( R_EAX, Rn );
nkeynes@361
   933
    load_reg( R_ECX, Rm );
nkeynes@361
   934
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   935
    JGE_rel8(16, doshl);
nkeynes@361
   936
                    
nkeynes@361
   937
    NEG_r32( R_ECX );      // 2
nkeynes@361
   938
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   939
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   940
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   941
    JMP_rel8(10, end);          // 2
nkeynes@386
   942
nkeynes@386
   943
    JMP_TARGET(emptysar);
nkeynes@386
   944
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   945
    JMP_rel8(5, end2);
nkeynes@382
   946
nkeynes@380
   947
    JMP_TARGET(doshl);
nkeynes@361
   948
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   949
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   950
    JMP_TARGET(end);
nkeynes@386
   951
    JMP_TARGET(end2);
nkeynes@361
   952
    store_reg( R_EAX, Rn );
nkeynes@417
   953
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   954
:}
nkeynes@359
   955
SHLD Rm, Rn {:  
nkeynes@368
   956
    load_reg( R_EAX, Rn );
nkeynes@368
   957
    load_reg( R_ECX, Rm );
nkeynes@382
   958
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   959
    JGE_rel8(15, doshl);
nkeynes@368
   960
nkeynes@382
   961
    NEG_r32( R_ECX );      // 2
nkeynes@382
   962
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   963
    JE_rel8( 4, emptyshr );
nkeynes@382
   964
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   965
    JMP_rel8(9, end);          // 2
nkeynes@386
   966
nkeynes@386
   967
    JMP_TARGET(emptyshr);
nkeynes@386
   968
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   969
    JMP_rel8(5, end2);
nkeynes@382
   970
nkeynes@382
   971
    JMP_TARGET(doshl);
nkeynes@382
   972
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   973
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   974
    JMP_TARGET(end);
nkeynes@386
   975
    JMP_TARGET(end2);
nkeynes@368
   976
    store_reg( R_EAX, Rn );
nkeynes@417
   977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   978
:}
nkeynes@359
   979
SHAL Rn {: 
nkeynes@359
   980
    load_reg( R_EAX, Rn );
nkeynes@359
   981
    SHL1_r32( R_EAX );
nkeynes@397
   982
    SETC_t();
nkeynes@359
   983
    store_reg( R_EAX, Rn );
nkeynes@417
   984
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   985
:}
nkeynes@359
   986
SHAR Rn {:  
nkeynes@359
   987
    load_reg( R_EAX, Rn );
nkeynes@359
   988
    SAR1_r32( R_EAX );
nkeynes@397
   989
    SETC_t();
nkeynes@359
   990
    store_reg( R_EAX, Rn );
nkeynes@417
   991
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   992
:}
nkeynes@359
   993
SHLL Rn {:  
nkeynes@359
   994
    load_reg( R_EAX, Rn );
nkeynes@359
   995
    SHL1_r32( R_EAX );
nkeynes@397
   996
    SETC_t();
nkeynes@359
   997
    store_reg( R_EAX, Rn );
nkeynes@417
   998
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   999
:}
nkeynes@359
  1000
SHLL2 Rn {:
nkeynes@359
  1001
    load_reg( R_EAX, Rn );
nkeynes@359
  1002
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1003
    store_reg( R_EAX, Rn );
nkeynes@417
  1004
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1005
:}
nkeynes@359
  1006
SHLL8 Rn {:  
nkeynes@359
  1007
    load_reg( R_EAX, Rn );
nkeynes@359
  1008
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1009
    store_reg( R_EAX, Rn );
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1011
:}
nkeynes@359
  1012
SHLL16 Rn {:  
nkeynes@359
  1013
    load_reg( R_EAX, Rn );
nkeynes@359
  1014
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1015
    store_reg( R_EAX, Rn );
nkeynes@417
  1016
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1017
:}
nkeynes@359
  1018
SHLR Rn {:  
nkeynes@359
  1019
    load_reg( R_EAX, Rn );
nkeynes@359
  1020
    SHR1_r32( R_EAX );
nkeynes@397
  1021
    SETC_t();
nkeynes@359
  1022
    store_reg( R_EAX, Rn );
nkeynes@417
  1023
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1024
:}
nkeynes@359
  1025
SHLR2 Rn {:  
nkeynes@359
  1026
    load_reg( R_EAX, Rn );
nkeynes@359
  1027
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1028
    store_reg( R_EAX, Rn );
nkeynes@417
  1029
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1030
:}
nkeynes@359
  1031
SHLR8 Rn {:  
nkeynes@359
  1032
    load_reg( R_EAX, Rn );
nkeynes@359
  1033
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1034
    store_reg( R_EAX, Rn );
nkeynes@417
  1035
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1036
:}
nkeynes@359
  1037
SHLR16 Rn {:  
nkeynes@359
  1038
    load_reg( R_EAX, Rn );
nkeynes@359
  1039
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1040
    store_reg( R_EAX, Rn );
nkeynes@417
  1041
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1042
:}
nkeynes@359
  1043
SUB Rm, Rn {:  
nkeynes@359
  1044
    load_reg( R_EAX, Rm );
nkeynes@359
  1045
    load_reg( R_ECX, Rn );
nkeynes@359
  1046
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1047
    store_reg( R_ECX, Rn );
nkeynes@417
  1048
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1049
:}
nkeynes@359
  1050
SUBC Rm, Rn {:  
nkeynes@359
  1051
    load_reg( R_EAX, Rm );
nkeynes@359
  1052
    load_reg( R_ECX, Rn );
nkeynes@417
  1053
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1054
	LDC_t();
nkeynes@417
  1055
    }
nkeynes@359
  1056
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1057
    store_reg( R_ECX, Rn );
nkeynes@394
  1058
    SETC_t();
nkeynes@417
  1059
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1060
:}
nkeynes@359
  1061
SUBV Rm, Rn {:  
nkeynes@359
  1062
    load_reg( R_EAX, Rm );
nkeynes@359
  1063
    load_reg( R_ECX, Rn );
nkeynes@359
  1064
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1065
    store_reg( R_ECX, Rn );
nkeynes@359
  1066
    SETO_t();
nkeynes@417
  1067
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1068
:}
nkeynes@359
  1069
SWAP.B Rm, Rn {:  
nkeynes@359
  1070
    load_reg( R_EAX, Rm );
nkeynes@359
  1071
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1072
    store_reg( R_EAX, Rn );
nkeynes@359
  1073
:}
nkeynes@359
  1074
SWAP.W Rm, Rn {:  
nkeynes@359
  1075
    load_reg( R_EAX, Rm );
nkeynes@359
  1076
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1077
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1078
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1079
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1080
    store_reg( R_ECX, Rn );
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1082
:}
nkeynes@361
  1083
TAS.B @Rn {:  
nkeynes@361
  1084
    load_reg( R_ECX, Rn );
nkeynes@361
  1085
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1086
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1087
    SETE_t();
nkeynes@361
  1088
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1089
    load_reg( R_ECX, Rn );
nkeynes@361
  1090
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1091
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1092
:}
nkeynes@361
  1093
TST Rm, Rn {:  
nkeynes@361
  1094
    load_reg( R_EAX, Rm );
nkeynes@361
  1095
    load_reg( R_ECX, Rn );
nkeynes@361
  1096
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1097
    SETE_t();
nkeynes@417
  1098
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1099
:}
nkeynes@368
  1100
TST #imm, R0 {:  
nkeynes@368
  1101
    load_reg( R_EAX, 0 );
nkeynes@368
  1102
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1103
    SETE_t();
nkeynes@417
  1104
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1105
:}
nkeynes@368
  1106
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1107
    load_reg( R_EAX, 0);
nkeynes@368
  1108
    load_reg( R_ECX, R_GBR);
nkeynes@368
  1109
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1110
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  1111
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1112
    SETE_t();
nkeynes@417
  1113
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1114
:}
nkeynes@359
  1115
XOR Rm, Rn {:  
nkeynes@359
  1116
    load_reg( R_EAX, Rm );
nkeynes@359
  1117
    load_reg( R_ECX, Rn );
nkeynes@359
  1118
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1119
    store_reg( R_ECX, Rn );
nkeynes@417
  1120
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1121
:}
nkeynes@359
  1122
XOR #imm, R0 {:  
nkeynes@359
  1123
    load_reg( R_EAX, 0 );
nkeynes@359
  1124
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1125
    store_reg( R_EAX, 0 );
nkeynes@417
  1126
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1127
:}
nkeynes@359
  1128
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1129
    load_reg( R_EAX, 0 );
nkeynes@359
  1130
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1131
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1132
    PUSH_r32(R_ECX);
nkeynes@386
  1133
    call_func0(sh4_read_byte);
nkeynes@386
  1134
    POP_r32(R_ECX);
nkeynes@359
  1135
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1136
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1138
:}
nkeynes@361
  1139
XTRCT Rm, Rn {:
nkeynes@361
  1140
    load_reg( R_EAX, Rm );
nkeynes@394
  1141
    load_reg( R_ECX, Rn );
nkeynes@394
  1142
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1143
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1144
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1145
    store_reg( R_ECX, Rn );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
:}
nkeynes@359
  1148
nkeynes@359
  1149
/* Data move instructions */
nkeynes@359
  1150
MOV Rm, Rn {:  
nkeynes@359
  1151
    load_reg( R_EAX, Rm );
nkeynes@359
  1152
    store_reg( R_EAX, Rn );
nkeynes@359
  1153
:}
nkeynes@359
  1154
MOV #imm, Rn {:  
nkeynes@359
  1155
    load_imm32( R_EAX, imm );
nkeynes@359
  1156
    store_reg( R_EAX, Rn );
nkeynes@359
  1157
:}
nkeynes@359
  1158
MOV.B Rm, @Rn {:  
nkeynes@359
  1159
    load_reg( R_EAX, Rm );
nkeynes@359
  1160
    load_reg( R_ECX, Rn );
nkeynes@359
  1161
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1163
:}
nkeynes@359
  1164
MOV.B Rm, @-Rn {:  
nkeynes@359
  1165
    load_reg( R_EAX, Rm );
nkeynes@359
  1166
    load_reg( R_ECX, Rn );
nkeynes@382
  1167
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1168
    store_reg( R_ECX, Rn );
nkeynes@359
  1169
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1171
:}
nkeynes@359
  1172
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1173
    load_reg( R_EAX, 0 );
nkeynes@359
  1174
    load_reg( R_ECX, Rn );
nkeynes@359
  1175
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1176
    load_reg( R_EAX, Rm );
nkeynes@359
  1177
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1179
:}
nkeynes@359
  1180
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1181
    load_reg( R_EAX, 0 );
nkeynes@359
  1182
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1183
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1184
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1186
:}
nkeynes@359
  1187
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1188
    load_reg( R_EAX, 0 );
nkeynes@359
  1189
    load_reg( R_ECX, Rn );
nkeynes@359
  1190
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1191
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1193
:}
nkeynes@359
  1194
MOV.B @Rm, Rn {:  
nkeynes@359
  1195
    load_reg( R_ECX, Rm );
nkeynes@359
  1196
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1197
    store_reg( R_EAX, Rn );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1199
:}
nkeynes@359
  1200
MOV.B @Rm+, Rn {:  
nkeynes@359
  1201
    load_reg( R_ECX, Rm );
nkeynes@359
  1202
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1203
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1204
    store_reg( R_EAX, Rm );
nkeynes@359
  1205
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1206
    store_reg( R_EAX, Rn );
nkeynes@417
  1207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1208
:}
nkeynes@359
  1209
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1210
    load_reg( R_EAX, 0 );
nkeynes@359
  1211
    load_reg( R_ECX, Rm );
nkeynes@359
  1212
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1213
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1214
    store_reg( R_EAX, Rn );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1216
:}
nkeynes@359
  1217
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1218
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1219
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1220
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1221
    store_reg( R_EAX, 0 );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@359
  1224
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1225
    load_reg( R_ECX, Rm );
nkeynes@359
  1226
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1227
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1228
    store_reg( R_EAX, 0 );
nkeynes@417
  1229
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1230
:}
nkeynes@374
  1231
MOV.L Rm, @Rn {:
nkeynes@361
  1232
    load_reg( R_EAX, Rm );
nkeynes@361
  1233
    load_reg( R_ECX, Rn );
nkeynes@416
  1234
    precheck();
nkeynes@374
  1235
    check_walign32(R_ECX);
nkeynes@361
  1236
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1237
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1238
:}
nkeynes@361
  1239
MOV.L Rm, @-Rn {:  
nkeynes@361
  1240
    load_reg( R_EAX, Rm );
nkeynes@361
  1241
    load_reg( R_ECX, Rn );
nkeynes@416
  1242
    precheck();
nkeynes@374
  1243
    check_walign32( R_ECX );
nkeynes@361
  1244
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1245
    store_reg( R_ECX, Rn );
nkeynes@361
  1246
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1248
:}
nkeynes@361
  1249
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1250
    load_reg( R_EAX, 0 );
nkeynes@361
  1251
    load_reg( R_ECX, Rn );
nkeynes@361
  1252
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1253
    precheck();
nkeynes@374
  1254
    check_walign32( R_ECX );
nkeynes@361
  1255
    load_reg( R_EAX, Rm );
nkeynes@361
  1256
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1257
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1258
:}
nkeynes@361
  1259
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1260
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1261
    load_reg( R_EAX, 0 );
nkeynes@361
  1262
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1263
    precheck();
nkeynes@374
  1264
    check_walign32( R_ECX );
nkeynes@361
  1265
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1266
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1267
:}
nkeynes@361
  1268
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1269
    load_reg( R_ECX, Rn );
nkeynes@361
  1270
    load_reg( R_EAX, Rm );
nkeynes@361
  1271
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1272
    precheck();
nkeynes@374
  1273
    check_walign32( R_ECX );
nkeynes@361
  1274
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1275
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1276
:}
nkeynes@361
  1277
MOV.L @Rm, Rn {:  
nkeynes@361
  1278
    load_reg( R_ECX, Rm );
nkeynes@416
  1279
    precheck();
nkeynes@374
  1280
    check_ralign32( R_ECX );
nkeynes@361
  1281
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1282
    store_reg( R_EAX, Rn );
nkeynes@417
  1283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1284
:}
nkeynes@361
  1285
MOV.L @Rm+, Rn {:  
nkeynes@361
  1286
    load_reg( R_EAX, Rm );
nkeynes@416
  1287
    precheck();
nkeynes@382
  1288
    check_ralign32( R_EAX );
nkeynes@361
  1289
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1290
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1291
    store_reg( R_EAX, Rm );
nkeynes@361
  1292
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1293
    store_reg( R_EAX, Rn );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1295
:}
nkeynes@361
  1296
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1297
    load_reg( R_EAX, 0 );
nkeynes@361
  1298
    load_reg( R_ECX, Rm );
nkeynes@361
  1299
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1300
    precheck();
nkeynes@374
  1301
    check_ralign32( R_ECX );
nkeynes@361
  1302
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1303
    store_reg( R_EAX, Rn );
nkeynes@417
  1304
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1305
:}
nkeynes@361
  1306
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1307
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1308
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1309
    precheck();
nkeynes@374
  1310
    check_ralign32( R_ECX );
nkeynes@361
  1311
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1312
    store_reg( R_EAX, 0 );
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1314
:}
nkeynes@361
  1315
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1316
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1317
	SLOTILLEGAL();
nkeynes@374
  1318
    } else {
nkeynes@388
  1319
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  1320
	char *ptr = mem_get_region(target);
nkeynes@388
  1321
	if( ptr != NULL ) {
nkeynes@388
  1322
	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  1323
	} else {
nkeynes@388
  1324
	    load_imm32( R_ECX, target );
nkeynes@388
  1325
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1326
	}
nkeynes@382
  1327
	store_reg( R_EAX, Rn );
nkeynes@417
  1328
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1329
    }
nkeynes@361
  1330
:}
nkeynes@361
  1331
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1332
    load_reg( R_ECX, Rm );
nkeynes@361
  1333
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  1334
    precheck();
nkeynes@374
  1335
    check_ralign32( R_ECX );
nkeynes@361
  1336
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1337
    store_reg( R_EAX, Rn );
nkeynes@417
  1338
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1339
:}
nkeynes@361
  1340
MOV.W Rm, @Rn {:  
nkeynes@361
  1341
    load_reg( R_ECX, Rn );
nkeynes@416
  1342
    precheck();
nkeynes@374
  1343
    check_walign16( R_ECX );
nkeynes@382
  1344
    load_reg( R_EAX, Rm );
nkeynes@382
  1345
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1347
:}
nkeynes@361
  1348
MOV.W Rm, @-Rn {:  
nkeynes@361
  1349
    load_reg( R_ECX, Rn );
nkeynes@416
  1350
    precheck();
nkeynes@374
  1351
    check_walign16( R_ECX );
nkeynes@361
  1352
    load_reg( R_EAX, Rm );
nkeynes@361
  1353
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1354
    store_reg( R_ECX, Rn );
nkeynes@361
  1355
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1356
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1357
:}
nkeynes@361
  1358
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1359
    load_reg( R_EAX, 0 );
nkeynes@361
  1360
    load_reg( R_ECX, Rn );
nkeynes@361
  1361
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1362
    precheck();
nkeynes@374
  1363
    check_walign16( R_ECX );
nkeynes@361
  1364
    load_reg( R_EAX, Rm );
nkeynes@361
  1365
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1366
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1367
:}
nkeynes@361
  1368
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1369
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1370
    load_reg( R_EAX, 0 );
nkeynes@361
  1371
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1372
    precheck();
nkeynes@374
  1373
    check_walign16( R_ECX );
nkeynes@361
  1374
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1375
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1376
:}
nkeynes@361
  1377
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1378
    load_reg( R_ECX, Rn );
nkeynes@361
  1379
    load_reg( R_EAX, 0 );
nkeynes@361
  1380
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1381
    precheck();
nkeynes@374
  1382
    check_walign16( R_ECX );
nkeynes@361
  1383
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1385
:}
nkeynes@361
  1386
MOV.W @Rm, Rn {:  
nkeynes@361
  1387
    load_reg( R_ECX, Rm );
nkeynes@416
  1388
    precheck();
nkeynes@374
  1389
    check_ralign16( R_ECX );
nkeynes@361
  1390
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1391
    store_reg( R_EAX, Rn );
nkeynes@417
  1392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1393
:}
nkeynes@361
  1394
MOV.W @Rm+, Rn {:  
nkeynes@361
  1395
    load_reg( R_EAX, Rm );
nkeynes@416
  1396
    precheck();
nkeynes@374
  1397
    check_ralign16( R_EAX );
nkeynes@361
  1398
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1399
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1400
    store_reg( R_EAX, Rm );
nkeynes@361
  1401
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1402
    store_reg( R_EAX, Rn );
nkeynes@417
  1403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1404
:}
nkeynes@361
  1405
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1406
    load_reg( R_EAX, 0 );
nkeynes@361
  1407
    load_reg( R_ECX, Rm );
nkeynes@361
  1408
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1409
    precheck();
nkeynes@374
  1410
    check_ralign16( R_ECX );
nkeynes@361
  1411
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1412
    store_reg( R_EAX, Rn );
nkeynes@417
  1413
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1414
:}
nkeynes@361
  1415
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1416
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1417
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1418
    precheck();
nkeynes@374
  1419
    check_ralign16( R_ECX );
nkeynes@361
  1420
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1421
    store_reg( R_EAX, 0 );
nkeynes@417
  1422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1423
:}
nkeynes@361
  1424
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1425
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1426
	SLOTILLEGAL();
nkeynes@374
  1427
    } else {
nkeynes@374
  1428
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1429
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1430
	store_reg( R_EAX, Rn );
nkeynes@417
  1431
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1432
    }
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1435
    load_reg( R_ECX, Rm );
nkeynes@361
  1436
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1437
    precheck();
nkeynes@374
  1438
    check_ralign16( R_ECX );
nkeynes@361
  1439
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1440
    store_reg( R_EAX, 0 );
nkeynes@417
  1441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1442
:}
nkeynes@361
  1443
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1444
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1445
	SLOTILLEGAL();
nkeynes@374
  1446
    } else {
nkeynes@374
  1447
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1448
	store_reg( R_ECX, 0 );
nkeynes@374
  1449
    }
nkeynes@361
  1450
:}
nkeynes@361
  1451
MOVCA.L R0, @Rn {:  
nkeynes@361
  1452
    load_reg( R_EAX, 0 );
nkeynes@361
  1453
    load_reg( R_ECX, Rn );
nkeynes@416
  1454
    precheck();
nkeynes@374
  1455
    check_walign32( R_ECX );
nkeynes@361
  1456
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1458
:}
nkeynes@359
  1459
nkeynes@359
  1460
/* Control transfer instructions */
nkeynes@374
  1461
BF disp {:
nkeynes@374
  1462
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1463
	SLOTILLEGAL();
nkeynes@374
  1464
    } else {
nkeynes@417
  1465
	JT_rel8( 29, nottaken );
nkeynes@408
  1466
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1467
	JMP_TARGET(nottaken);
nkeynes@408
  1468
	return 2;
nkeynes@374
  1469
    }
nkeynes@374
  1470
:}
nkeynes@374
  1471
BF/S disp {:
nkeynes@374
  1472
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1473
	SLOTILLEGAL();
nkeynes@374
  1474
    } else {
nkeynes@408
  1475
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1476
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1477
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1478
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1479
	}
nkeynes@417
  1480
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@408
  1481
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1482
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1483
	// not taken
nkeynes@408
  1484
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1485
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1486
	return 4;
nkeynes@374
  1487
    }
nkeynes@374
  1488
:}
nkeynes@374
  1489
BRA disp {:  
nkeynes@374
  1490
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1491
	SLOTILLEGAL();
nkeynes@374
  1492
    } else {
nkeynes@374
  1493
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1494
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1495
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1496
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1497
	return 4;
nkeynes@374
  1498
    }
nkeynes@374
  1499
:}
nkeynes@374
  1500
BRAF Rn {:  
nkeynes@374
  1501
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1502
	SLOTILLEGAL();
nkeynes@374
  1503
    } else {
nkeynes@408
  1504
	load_reg( R_EAX, Rn );
nkeynes@408
  1505
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1506
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1507
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1508
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1509
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1510
	exit_block_pcset(pc+2);
nkeynes@409
  1511
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1512
	return 4;
nkeynes@374
  1513
    }
nkeynes@374
  1514
:}
nkeynes@374
  1515
BSR disp {:  
nkeynes@374
  1516
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1517
	SLOTILLEGAL();
nkeynes@374
  1518
    } else {
nkeynes@374
  1519
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1520
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1521
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1522
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1523
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1524
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1525
	return 4;
nkeynes@374
  1526
    }
nkeynes@374
  1527
:}
nkeynes@374
  1528
BSRF Rn {:  
nkeynes@374
  1529
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1530
	SLOTILLEGAL();
nkeynes@374
  1531
    } else {
nkeynes@408
  1532
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1533
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1534
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1535
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1536
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1537
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1538
	sh4_x86_translate_instruction( pc + 2 );
nkeynes@408
  1539
	exit_block_pcset(pc+2);
nkeynes@409
  1540
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1541
	return 4;
nkeynes@374
  1542
    }
nkeynes@374
  1543
:}
nkeynes@374
  1544
BT disp {:
nkeynes@374
  1545
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1546
	SLOTILLEGAL();
nkeynes@374
  1547
    } else {
nkeynes@417
  1548
	JF_rel8( 29, nottaken );
nkeynes@408
  1549
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1550
	JMP_TARGET(nottaken);
nkeynes@408
  1551
	return 2;
nkeynes@374
  1552
    }
nkeynes@374
  1553
:}
nkeynes@374
  1554
BT/S disp {:
nkeynes@374
  1555
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1556
	SLOTILLEGAL();
nkeynes@374
  1557
    } else {
nkeynes@408
  1558
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1559
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1560
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1561
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1562
	}
nkeynes@417
  1563
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@408
  1564
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1565
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1566
	// not taken
nkeynes@408
  1567
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@408
  1568
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1569
	return 4;
nkeynes@374
  1570
    }
nkeynes@374
  1571
:}
nkeynes@374
  1572
JMP @Rn {:  
nkeynes@374
  1573
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1574
	SLOTILLEGAL();
nkeynes@374
  1575
    } else {
nkeynes@408
  1576
	load_reg( R_ECX, Rn );
nkeynes@408
  1577
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1578
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1579
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1580
	exit_block_pcset(pc+2);
nkeynes@409
  1581
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1582
	return 4;
nkeynes@374
  1583
    }
nkeynes@374
  1584
:}
nkeynes@374
  1585
JSR @Rn {:  
nkeynes@374
  1586
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1587
	SLOTILLEGAL();
nkeynes@374
  1588
    } else {
nkeynes@374
  1589
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1590
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1591
	load_reg( R_ECX, Rn );
nkeynes@408
  1592
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1593
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1594
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1595
	exit_block_pcset(pc+2);
nkeynes@409
  1596
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1597
	return 4;
nkeynes@374
  1598
    }
nkeynes@374
  1599
:}
nkeynes@374
  1600
RTE {:  
nkeynes@374
  1601
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1602
	SLOTILLEGAL();
nkeynes@374
  1603
    } else {
nkeynes@408
  1604
	check_priv();
nkeynes@408
  1605
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1606
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1607
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1608
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1609
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1610
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1611
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1612
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1613
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1614
	exit_block_pcset(pc+2);
nkeynes@409
  1615
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1616
	return 4;
nkeynes@374
  1617
    }
nkeynes@374
  1618
:}
nkeynes@374
  1619
RTS {:  
nkeynes@374
  1620
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1621
	SLOTILLEGAL();
nkeynes@374
  1622
    } else {
nkeynes@408
  1623
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1624
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1625
	sh4_x86.in_delay_slot = TRUE;
nkeynes@408
  1626
	sh4_x86_translate_instruction(pc+2);
nkeynes@408
  1627
	exit_block_pcset(pc+2);
nkeynes@409
  1628
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1629
	return 4;
nkeynes@374
  1630
    }
nkeynes@374
  1631
:}
nkeynes@374
  1632
TRAPA #imm {:  
nkeynes@374
  1633
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1634
	SLOTILLEGAL();
nkeynes@374
  1635
    } else {
nkeynes@388
  1636
	PUSH_imm32( imm );
nkeynes@388
  1637
	call_func0( sh4_raise_trap );
nkeynes@388
  1638
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
  1639
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1640
	exit_block_pcset(pc);
nkeynes@409
  1641
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1642
	return 2;
nkeynes@374
  1643
    }
nkeynes@374
  1644
:}
nkeynes@374
  1645
UNDEF {:  
nkeynes@374
  1646
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1647
	SLOTILLEGAL();
nkeynes@374
  1648
    } else {
nkeynes@416
  1649
	precheck();
nkeynes@386
  1650
	JMP_exit(EXIT_ILLEGAL);
nkeynes@408
  1651
	return 2;
nkeynes@374
  1652
    }
nkeynes@368
  1653
:}
nkeynes@374
  1654
nkeynes@374
  1655
CLRMAC {:  
nkeynes@374
  1656
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1657
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1658
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1659
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1660
:}
nkeynes@374
  1661
CLRS {:
nkeynes@374
  1662
    CLC();
nkeynes@374
  1663
    SETC_sh4r(R_S);
nkeynes@417
  1664
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1665
:}
nkeynes@374
  1666
CLRT {:  
nkeynes@374
  1667
    CLC();
nkeynes@374
  1668
    SETC_t();
nkeynes@417
  1669
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1670
:}
nkeynes@374
  1671
SETS {:  
nkeynes@374
  1672
    STC();
nkeynes@374
  1673
    SETC_sh4r(R_S);
nkeynes@417
  1674
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1675
:}
nkeynes@374
  1676
SETT {:  
nkeynes@374
  1677
    STC();
nkeynes@374
  1678
    SETC_t();
nkeynes@417
  1679
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1680
:}
nkeynes@359
  1681
nkeynes@375
  1682
/* Floating point moves */
nkeynes@375
  1683
FMOV FRm, FRn {:  
nkeynes@375
  1684
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1685
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1686
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1687
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1688
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1689
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1690
     */
nkeynes@377
  1691
    check_fpuen();
nkeynes@375
  1692
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1693
    load_fr_bank( R_EDX );
nkeynes@375
  1694
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1695
    JNE_rel8(8, doublesize);
nkeynes@375
  1696
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1697
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1698
    if( FRm&1 ) {
nkeynes@386
  1699
	JMP_rel8(24, end);
nkeynes@380
  1700
	JMP_TARGET(doublesize);
nkeynes@375
  1701
	load_xf_bank( R_ECX ); 
nkeynes@375
  1702
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1703
	if( FRn&1 ) {
nkeynes@375
  1704
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1705
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1706
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1707
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1708
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1709
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1710
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1711
	}
nkeynes@380
  1712
	JMP_TARGET(end);
nkeynes@375
  1713
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1714
	if( FRn&1 ) {
nkeynes@386
  1715
	    JMP_rel8(24, end);
nkeynes@375
  1716
	    load_xf_bank( R_ECX );
nkeynes@375
  1717
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1718
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1719
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1720
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1721
	    JMP_TARGET(end);
nkeynes@375
  1722
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1723
	    JMP_rel8(12, end);
nkeynes@375
  1724
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1725
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1726
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1727
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1728
	    JMP_TARGET(end);
nkeynes@375
  1729
	}
nkeynes@375
  1730
    }
nkeynes@417
  1731
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1732
:}
nkeynes@416
  1733
FMOV FRm, @Rn {: 
nkeynes@416
  1734
    precheck();
nkeynes@416
  1735
    check_fpuen_no_precheck();
nkeynes@416
  1736
    load_reg( R_ECX, Rn );
nkeynes@416
  1737
    check_walign32( R_ECX );
nkeynes@416
  1738
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1739
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1740
    JNE_rel8(20, doublesize);
nkeynes@416
  1741
    load_fr_bank( R_EDX );
nkeynes@416
  1742
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1743
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1744
    if( FRm&1 ) {
nkeynes@386
  1745
	JMP_rel8( 48, end );
nkeynes@380
  1746
	JMP_TARGET(doublesize);
nkeynes@416
  1747
	load_xf_bank( R_EDX );
nkeynes@416
  1748
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1749
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1750
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1751
	JMP_TARGET(end);
nkeynes@375
  1752
    } else {
nkeynes@380
  1753
	JMP_rel8( 39, end );
nkeynes@380
  1754
	JMP_TARGET(doublesize);
nkeynes@416
  1755
	load_fr_bank( R_EDX );
nkeynes@416
  1756
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1757
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1758
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1759
	JMP_TARGET(end);
nkeynes@375
  1760
    }
nkeynes@417
  1761
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1762
:}
nkeynes@375
  1763
FMOV @Rm, FRn {:  
nkeynes@416
  1764
    precheck();
nkeynes@416
  1765
    check_fpuen_no_precheck();
nkeynes@416
  1766
    load_reg( R_ECX, Rm );
nkeynes@416
  1767
    check_ralign32( R_ECX );
nkeynes@416
  1768
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1769
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1770
    JNE_rel8(19, doublesize);
nkeynes@416
  1771
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1772
    load_fr_bank( R_EDX );
nkeynes@416
  1773
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1774
    if( FRn&1 ) {
nkeynes@386
  1775
	JMP_rel8(48, end);
nkeynes@380
  1776
	JMP_TARGET(doublesize);
nkeynes@416
  1777
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1778
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1779
	load_xf_bank( R_EDX );
nkeynes@416
  1780
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1781
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1782
	JMP_TARGET(end);
nkeynes@375
  1783
    } else {
nkeynes@380
  1784
	JMP_rel8(36, end);
nkeynes@380
  1785
	JMP_TARGET(doublesize);
nkeynes@416
  1786
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1787
	load_fr_bank( R_EDX );
nkeynes@416
  1788
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1789
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1790
	JMP_TARGET(end);
nkeynes@375
  1791
    }
nkeynes@417
  1792
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1793
:}
nkeynes@377
  1794
FMOV FRm, @-Rn {:  
nkeynes@416
  1795
    precheck();
nkeynes@416
  1796
    check_fpuen_no_precheck();
nkeynes@416
  1797
    load_reg( R_ECX, Rn );
nkeynes@416
  1798
    check_walign32( R_ECX );
nkeynes@416
  1799
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1800
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@382
  1801
    JNE_rel8(26, doublesize);
nkeynes@416
  1802
    load_fr_bank( R_EDX );
nkeynes@416
  1803
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1804
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1805
    store_reg( R_ECX, Rn );
nkeynes@416
  1806
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1807
    if( FRm&1 ) {
nkeynes@386
  1808
	JMP_rel8( 54, end );
nkeynes@380
  1809
	JMP_TARGET(doublesize);
nkeynes@416
  1810
	load_xf_bank( R_EDX );
nkeynes@416
  1811
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1812
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1813
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1814
	store_reg( R_ECX, Rn );
nkeynes@416
  1815
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1816
	JMP_TARGET(end);
nkeynes@377
  1817
    } else {
nkeynes@382
  1818
	JMP_rel8( 45, end );
nkeynes@380
  1819
	JMP_TARGET(doublesize);
nkeynes@416
  1820
	load_fr_bank( R_EDX );
nkeynes@416
  1821
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1822
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1823
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1824
	store_reg( R_ECX, Rn );
nkeynes@416
  1825
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1826
	JMP_TARGET(end);
nkeynes@377
  1827
    }
nkeynes@417
  1828
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1829
:}
nkeynes@416
  1830
FMOV @Rm+, FRn {:
nkeynes@416
  1831
    precheck();
nkeynes@416
  1832
    check_fpuen_no_precheck();
nkeynes@416
  1833
    load_reg( R_ECX, Rm );
nkeynes@416
  1834
    check_ralign32( R_ECX );
nkeynes@416
  1835
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1836
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1837
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1838
    JNE_rel8(25, doublesize);
nkeynes@377
  1839
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1840
    store_reg( R_EAX, Rm );
nkeynes@416
  1841
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1842
    load_fr_bank( R_EDX );
nkeynes@416
  1843
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1844
    if( FRn&1 ) {
nkeynes@386
  1845
	JMP_rel8(54, end);
nkeynes@380
  1846
	JMP_TARGET(doublesize);
nkeynes@377
  1847
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1848
	store_reg(R_EAX, Rm);
nkeynes@416
  1849
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1850
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1851
	load_xf_bank( R_EDX );
nkeynes@416
  1852
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1853
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1854
	JMP_TARGET(end);
nkeynes@377
  1855
    } else {
nkeynes@380
  1856
	JMP_rel8(42, end);
nkeynes@377
  1857
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1858
	store_reg(R_EAX, Rm);
nkeynes@416
  1859
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1860
	load_fr_bank( R_EDX );
nkeynes@416
  1861
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1862
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1863
	JMP_TARGET(end);
nkeynes@377
  1864
    }
nkeynes@417
  1865
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1866
:}
nkeynes@377
  1867
FMOV FRm, @(R0, Rn) {:  
nkeynes@416
  1868
    precheck();
nkeynes@416
  1869
    check_fpuen_no_precheck();
nkeynes@416
  1870
    load_reg( R_ECX, Rn );
nkeynes@416
  1871
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1872
    check_walign32( R_ECX );
nkeynes@416
  1873
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1874
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1875
    JNE_rel8(20, doublesize);
nkeynes@416
  1876
    load_fr_bank( R_EDX );
nkeynes@416
  1877
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1878
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1879
    if( FRm&1 ) {
nkeynes@386
  1880
	JMP_rel8( 48, end );
nkeynes@380
  1881
	JMP_TARGET(doublesize);
nkeynes@416
  1882
	load_xf_bank( R_EDX );
nkeynes@416
  1883
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1884
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1885
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1886
	JMP_TARGET(end);
nkeynes@377
  1887
    } else {
nkeynes@380
  1888
	JMP_rel8( 39, end );
nkeynes@380
  1889
	JMP_TARGET(doublesize);
nkeynes@416
  1890
	load_fr_bank( R_EDX );
nkeynes@416
  1891
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1892
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1893
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1894
	JMP_TARGET(end);
nkeynes@377
  1895
    }
nkeynes@417
  1896
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1897
:}
nkeynes@377
  1898
FMOV @(R0, Rm), FRn {:  
nkeynes@416
  1899
    precheck();
nkeynes@416
  1900
    check_fpuen_no_precheck();
nkeynes@416
  1901
    load_reg( R_ECX, Rm );
nkeynes@416
  1902
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1903
    check_ralign32( R_ECX );
nkeynes@416
  1904
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1905
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@380
  1906
    JNE_rel8(19, doublesize);
nkeynes@416
  1907
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1908
    load_fr_bank( R_EDX );
nkeynes@416
  1909
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1910
    if( FRn&1 ) {
nkeynes@386
  1911
	JMP_rel8(48, end);
nkeynes@380
  1912
	JMP_TARGET(doublesize);
nkeynes@416
  1913
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1914
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1915
	load_xf_bank( R_EDX );
nkeynes@416
  1916
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1917
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1918
	JMP_TARGET(end);
nkeynes@377
  1919
    } else {
nkeynes@380
  1920
	JMP_rel8(36, end);
nkeynes@380
  1921
	JMP_TARGET(doublesize);
nkeynes@416
  1922
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1923
	load_fr_bank( R_EDX );
nkeynes@416
  1924
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1925
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1926
	JMP_TARGET(end);
nkeynes@377
  1927
    }
nkeynes@417
  1928
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1929
:}
nkeynes@377
  1930
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1931
    check_fpuen();
nkeynes@377
  1932
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1933
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1934
    JNE_rel8(8, end);
nkeynes@377
  1935
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1936
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1937
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1938
    JMP_TARGET(end);
nkeynes@417
  1939
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1940
:}
nkeynes@377
  1941
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1942
    check_fpuen();
nkeynes@377
  1943
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1944
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1945
    JNE_rel8(11, end);
nkeynes@377
  1946
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1947
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1948
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1949
    JMP_TARGET(end);
nkeynes@417
  1950
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1951
:}
nkeynes@377
  1952
nkeynes@377
  1953
FLOAT FPUL, FRn {:  
nkeynes@377
  1954
    check_fpuen();
nkeynes@377
  1955
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1956
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1957
    FILD_sh4r(R_FPUL);
nkeynes@377
  1958
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1959
    JNE_rel8(5, doubleprec);
nkeynes@377
  1960
    pop_fr( R_EDX, FRn );
nkeynes@380
  1961
    JMP_rel8(3, end);
nkeynes@380
  1962
    JMP_TARGET(doubleprec);
nkeynes@377
  1963
    pop_dr( R_EDX, FRn );
nkeynes@380
  1964
    JMP_TARGET(end);
nkeynes@417
  1965
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1966
:}
nkeynes@377
  1967
FTRC FRm, FPUL {:  
nkeynes@377
  1968
    check_fpuen();
nkeynes@388
  1969
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1970
    load_fr_bank( R_EDX );
nkeynes@388
  1971
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1972
    JNE_rel8(5, doubleprec);
nkeynes@388
  1973
    push_fr( R_EDX, FRm );
nkeynes@388
  1974
    JMP_rel8(3, doop);
nkeynes@388
  1975
    JMP_TARGET(doubleprec);
nkeynes@388
  1976
    push_dr( R_EDX, FRm );
nkeynes@388
  1977
    JMP_TARGET( doop );
nkeynes@388
  1978
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1979
    FILD_r32ind( R_ECX );
nkeynes@388
  1980
    FCOMIP_st(1);
nkeynes@394
  1981
    JNA_rel8( 32, sat );
nkeynes@388
  1982
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1983
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1984
    FCOMIP_st(1);                   // 2
nkeynes@394
  1985
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1986
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1987
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1988
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1989
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1990
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1991
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1992
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1993
nkeynes@388
  1994
    JMP_TARGET(sat);
nkeynes@388
  1995
    JMP_TARGET(sat2);
nkeynes@388
  1996
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1997
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1998
    FPOP_st();
nkeynes@388
  1999
    JMP_TARGET(end);
nkeynes@417
  2000
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2001
:}
nkeynes@377
  2002
FLDS FRm, FPUL {:  
nkeynes@377
  2003
    check_fpuen();
nkeynes@377
  2004
    load_fr_bank( R_ECX );
nkeynes@377
  2005
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2006
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2008
:}
nkeynes@377
  2009
FSTS FPUL, FRn {:  
nkeynes@377
  2010
    check_fpuen();
nkeynes@377
  2011
    load_fr_bank( R_ECX );
nkeynes@377
  2012
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  2013
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  2014
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2015
:}
nkeynes@377
  2016
FCNVDS FRm, FPUL {:  
nkeynes@377
  2017
    check_fpuen();
nkeynes@377
  2018
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2019
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2020
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2021
    load_fr_bank( R_ECX );
nkeynes@377
  2022
    push_dr( R_ECX, FRm );
nkeynes@377
  2023
    pop_fpul();
nkeynes@380
  2024
    JMP_TARGET(end);
nkeynes@417
  2025
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2026
:}
nkeynes@377
  2027
FCNVSD FPUL, FRn {:  
nkeynes@377
  2028
    check_fpuen();
nkeynes@377
  2029
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2030
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2031
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2032
    load_fr_bank( R_ECX );
nkeynes@377
  2033
    push_fpul();
nkeynes@377
  2034
    pop_dr( R_ECX, FRn );
nkeynes@380
  2035
    JMP_TARGET(end);
nkeynes@417
  2036
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2037
:}
nkeynes@375
  2038
nkeynes@359
  2039
/* Floating point instructions */
nkeynes@374
  2040
FABS FRn {:  
nkeynes@377
  2041
    check_fpuen();
nkeynes@374
  2042
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2043
    load_fr_bank( R_EDX );
nkeynes@374
  2044
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2045
    JNE_rel8(10, doubleprec);
nkeynes@374
  2046
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  2047
    FABS_st0(); // 2
nkeynes@374
  2048
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2049
    JMP_rel8(8,end); // 2
nkeynes@380
  2050
    JMP_TARGET(doubleprec);
nkeynes@374
  2051
    push_dr(R_EDX, FRn);
nkeynes@374
  2052
    FABS_st0();
nkeynes@374
  2053
    pop_dr(R_EDX, FRn);
nkeynes@380
  2054
    JMP_TARGET(end);
nkeynes@417
  2055
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2056
:}
nkeynes@377
  2057
FADD FRm, FRn {:  
nkeynes@377
  2058
    check_fpuen();
nkeynes@375
  2059
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2060
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2061
    load_fr_bank( R_EDX );
nkeynes@380
  2062
    JNE_rel8(13,doubleprec);
nkeynes@377
  2063
    push_fr(R_EDX, FRm);
nkeynes@377
  2064
    push_fr(R_EDX, FRn);
nkeynes@377
  2065
    FADDP_st(1);
nkeynes@377
  2066
    pop_fr(R_EDX, FRn);
nkeynes@380
  2067
    JMP_rel8(11,end);
nkeynes@380
  2068
    JMP_TARGET(doubleprec);
nkeynes@377
  2069
    push_dr(R_EDX, FRm);
nkeynes@377
  2070
    push_dr(R_EDX, FRn);
nkeynes@377
  2071
    FADDP_st(1);
nkeynes@377
  2072
    pop_dr(R_EDX, FRn);
nkeynes@380
  2073
    JMP_TARGET(end);
nkeynes@417
  2074
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2075
:}
nkeynes@377
  2076
FDIV FRm, FRn {:  
nkeynes@377
  2077
    check_fpuen();
nkeynes@375
  2078
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2079
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2080
    load_fr_bank( R_EDX );
nkeynes@380
  2081
    JNE_rel8(13, doubleprec);
nkeynes@377
  2082
    push_fr(R_EDX, FRn);
nkeynes@377
  2083
    push_fr(R_EDX, FRm);
nkeynes@377
  2084
    FDIVP_st(1);
nkeynes@377
  2085
    pop_fr(R_EDX, FRn);
nkeynes@380
  2086
    JMP_rel8(11, end);
nkeynes@380
  2087
    JMP_TARGET(doubleprec);
nkeynes@377
  2088
    push_dr(R_EDX, FRn);
nkeynes@377
  2089
    push_dr(R_EDX, FRm);
nkeynes@377
  2090
    FDIVP_st(1);
nkeynes@377
  2091
    pop_dr(R_EDX, FRn);
nkeynes@380
  2092
    JMP_TARGET(end);
nkeynes@417
  2093
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2094
:}
nkeynes@375
  2095
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2096
    check_fpuen();
nkeynes@375
  2097
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2098
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2099
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2100
    JNE_rel8(18, doubleprec);
nkeynes@375
  2101
    push_fr( R_EDX, 0 );
nkeynes@375
  2102
    push_fr( R_EDX, FRm );
nkeynes@375
  2103
    FMULP_st(1);
nkeynes@375
  2104
    push_fr( R_EDX, FRn );
nkeynes@375
  2105
    FADDP_st(1);
nkeynes@375
  2106
    pop_fr( R_EDX, FRn );
nkeynes@380
  2107
    JMP_rel8(16, end);
nkeynes@380
  2108
    JMP_TARGET(doubleprec);
nkeynes@375
  2109
    push_dr( R_EDX, 0 );
nkeynes@375
  2110
    push_dr( R_EDX, FRm );
nkeynes@375
  2111
    FMULP_st(1);
nkeynes@375
  2112
    push_dr( R_EDX, FRn );
nkeynes@375
  2113
    FADDP_st(1);
nkeynes@375
  2114
    pop_dr( R_EDX, FRn );
nkeynes@380
  2115
    JMP_TARGET(end);
nkeynes@417
  2116
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2117
:}
nkeynes@375
  2118
nkeynes@377
  2119
FMUL FRm, FRn {:  
nkeynes@377
  2120
    check_fpuen();
nkeynes@377
  2121
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2122
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2123
    load_fr_bank( R_EDX );
nkeynes@380
  2124
    JNE_rel8(13, doubleprec);
nkeynes@377
  2125
    push_fr(R_EDX, FRm);
nkeynes@377
  2126
    push_fr(R_EDX, FRn);
nkeynes@377
  2127
    FMULP_st(1);
nkeynes@377
  2128
    pop_fr(R_EDX, FRn);
nkeynes@380
  2129
    JMP_rel8(11, end);
nkeynes@380
  2130
    JMP_TARGET(doubleprec);
nkeynes@377
  2131
    push_dr(R_EDX, FRm);
nkeynes@377
  2132
    push_dr(R_EDX, FRn);
nkeynes@377
  2133
    FMULP_st(1);
nkeynes@377
  2134
    pop_dr(R_EDX, FRn);
nkeynes@380
  2135
    JMP_TARGET(end);
nkeynes@417
  2136
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2137
:}
nkeynes@377
  2138
FNEG FRn {:  
nkeynes@377
  2139
    check_fpuen();
nkeynes@377
  2140
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2141
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2142
    load_fr_bank( R_EDX );
nkeynes@380
  2143
    JNE_rel8(10, doubleprec);
nkeynes@377
  2144
    push_fr(R_EDX, FRn);
nkeynes@377
  2145
    FCHS_st0();
nkeynes@377
  2146
    pop_fr(R_EDX, FRn);
nkeynes@380
  2147
    JMP_rel8(8, end);
nkeynes@380
  2148
    JMP_TARGET(doubleprec);
nkeynes@377
  2149
    push_dr(R_EDX, FRn);
nkeynes@377
  2150
    FCHS_st0();
nkeynes@377
  2151
    pop_dr(R_EDX, FRn);
nkeynes@380
  2152
    JMP_TARGET(end);
nkeynes@417
  2153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2154
:}
nkeynes@377
  2155
FSRRA FRn {:  
nkeynes@377
  2156
    check_fpuen();
nkeynes@377
  2157
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2158
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2159
    load_fr_bank( R_EDX );
nkeynes@380
  2160
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2161
    FLD1_st0();
nkeynes@377
  2162
    push_fr(R_EDX, FRn);
nkeynes@377
  2163
    FSQRT_st0();
nkeynes@377
  2164
    FDIVP_st(1);
nkeynes@377
  2165
    pop_fr(R_EDX, FRn);
nkeynes@380
  2166
    JMP_TARGET(end);
nkeynes@417
  2167
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2168
:}
nkeynes@377
  2169
FSQRT FRn {:  
nkeynes@377
  2170
    check_fpuen();
nkeynes@377
  2171
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2172
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2173
    load_fr_bank( R_EDX );
nkeynes@380
  2174
    JNE_rel8(10, doubleprec);
nkeynes@377
  2175
    push_fr(R_EDX, FRn);
nkeynes@377
  2176
    FSQRT_st0();
nkeynes@377
  2177
    pop_fr(R_EDX, FRn);
nkeynes@380
  2178
    JMP_rel8(8, end);
nkeynes@380
  2179
    JMP_TARGET(doubleprec);
nkeynes@377
  2180
    push_dr(R_EDX, FRn);
nkeynes@377
  2181
    FSQRT_st0();
nkeynes@377
  2182
    pop_dr(R_EDX, FRn);
nkeynes@380
  2183
    JMP_TARGET(end);
nkeynes@417
  2184
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2185
:}
nkeynes@377
  2186
FSUB FRm, FRn {:  
nkeynes@377
  2187
    check_fpuen();
nkeynes@377
  2188
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2189
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2190
    load_fr_bank( R_EDX );
nkeynes@380
  2191
    JNE_rel8(13, doubleprec);
nkeynes@377
  2192
    push_fr(R_EDX, FRn);
nkeynes@377
  2193
    push_fr(R_EDX, FRm);
nkeynes@388
  2194
    FSUBP_st(1);
nkeynes@377
  2195
    pop_fr(R_EDX, FRn);
nkeynes@380
  2196
    JMP_rel8(11, end);
nkeynes@380
  2197
    JMP_TARGET(doubleprec);
nkeynes@377
  2198
    push_dr(R_EDX, FRn);
nkeynes@377
  2199
    push_dr(R_EDX, FRm);
nkeynes@388
  2200
    FSUBP_st(1);
nkeynes@377
  2201
    pop_dr(R_EDX, FRn);
nkeynes@380
  2202
    JMP_TARGET(end);
nkeynes@417
  2203
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2204
:}
nkeynes@377
  2205
nkeynes@377
  2206
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2207
    check_fpuen();
nkeynes@377
  2208
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2209
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2210
    load_fr_bank( R_EDX );
nkeynes@380
  2211
    JNE_rel8(8, doubleprec);
nkeynes@377
  2212
    push_fr(R_EDX, FRm);
nkeynes@377
  2213
    push_fr(R_EDX, FRn);
nkeynes@380
  2214
    JMP_rel8(6, end);
nkeynes@380
  2215
    JMP_TARGET(doubleprec);
nkeynes@377
  2216
    push_dr(R_EDX, FRm);
nkeynes@377
  2217
    push_dr(R_EDX, FRn);
nkeynes@382
  2218
    JMP_TARGET(end);
nkeynes@377
  2219
    FCOMIP_st(1);
nkeynes@377
  2220
    SETE_t();
nkeynes@377
  2221
    FPOP_st();
nkeynes@417
  2222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2223
:}
nkeynes@377
  2224
FCMP/GT FRm, FRn {:  
nkeynes@377
  2225
    check_fpuen();
nkeynes@377
  2226
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2227
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2228
    load_fr_bank( R_EDX );
nkeynes@380
  2229
    JNE_rel8(8, doubleprec);
nkeynes@377
  2230
    push_fr(R_EDX, FRm);
nkeynes@377
  2231
    push_fr(R_EDX, FRn);
nkeynes@380
  2232
    JMP_rel8(6, end);
nkeynes@380
  2233
    JMP_TARGET(doubleprec);
nkeynes@377
  2234
    push_dr(R_EDX, FRm);
nkeynes@377
  2235
    push_dr(R_EDX, FRn);
nkeynes@380
  2236
    JMP_TARGET(end);
nkeynes@377
  2237
    FCOMIP_st(1);
nkeynes@377
  2238
    SETA_t();
nkeynes@377
  2239
    FPOP_st();
nkeynes@417
  2240
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2241
:}
nkeynes@377
  2242
nkeynes@377
  2243
FSCA FPUL, FRn {:  
nkeynes@377
  2244
    check_fpuen();
nkeynes@388
  2245
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2246
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2247
    JNE_rel8( 21, doubleprec );
nkeynes@388
  2248
    load_fr_bank( R_ECX );
nkeynes@388
  2249
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2250
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2251
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2252
    JMP_TARGET(doubleprec);
nkeynes@417
  2253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2254
:}
nkeynes@377
  2255
FIPR FVm, FVn {:  
nkeynes@377
  2256
    check_fpuen();
nkeynes@388
  2257
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2258
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2259
    JNE_rel8(44, doubleprec);
nkeynes@388
  2260
    
nkeynes@388
  2261
    load_fr_bank( R_ECX );
nkeynes@388
  2262
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2263
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2264
    FMULP_st(1);
nkeynes@388
  2265
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2266
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2267
    FMULP_st(1);
nkeynes@388
  2268
    FADDP_st(1);
nkeynes@388
  2269
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2270
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2271
    FMULP_st(1);
nkeynes@388
  2272
    FADDP_st(1);
nkeynes@388
  2273
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2274
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2275
    FMULP_st(1);
nkeynes@388
  2276
    FADDP_st(1);
nkeynes@388
  2277
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2278
    JMP_TARGET(doubleprec);
nkeynes@417
  2279
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2280
:}
nkeynes@377
  2281
FTRV XMTRX, FVn {:  
nkeynes@377
  2282
    check_fpuen();
nkeynes@388
  2283
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2284
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2285
    JNE_rel8( 30, doubleprec );
nkeynes@388
  2286
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2287
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2288
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2289
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2290
    JMP_TARGET(doubleprec);
nkeynes@417
  2291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2292
:}
nkeynes@377
  2293
nkeynes@377
  2294
FRCHG {:  
nkeynes@377
  2295
    check_fpuen();
nkeynes@377
  2296
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2297
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2298
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2299
    update_fr_bank( R_ECX );
nkeynes@417
  2300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2301
:}
nkeynes@377
  2302
FSCHG {:  
nkeynes@377
  2303
    check_fpuen();
nkeynes@377
  2304
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2305
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2306
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2307
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2308
:}
nkeynes@359
  2309
nkeynes@359
  2310
/* Processor control instructions */
nkeynes@368
  2311
LDC Rm, SR {:
nkeynes@386
  2312
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2313
	SLOTILLEGAL();
nkeynes@386
  2314
    } else {
nkeynes@386
  2315
	check_priv();
nkeynes@386
  2316
	load_reg( R_EAX, Rm );
nkeynes@386
  2317
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2318
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2319
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2320
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2321
    }
nkeynes@368
  2322
:}
nkeynes@359
  2323
LDC Rm, GBR {: 
nkeynes@359
  2324
    load_reg( R_EAX, Rm );
nkeynes@359
  2325
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2326
:}
nkeynes@359
  2327
LDC Rm, VBR {:  
nkeynes@386
  2328
    check_priv();
nkeynes@359
  2329
    load_reg( R_EAX, Rm );
nkeynes@359
  2330
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2331
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2332
:}
nkeynes@359
  2333
LDC Rm, SSR {:  
nkeynes@386
  2334
    check_priv();
nkeynes@359
  2335
    load_reg( R_EAX, Rm );
nkeynes@359
  2336
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2337
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDC Rm, SGR {:  
nkeynes@386
  2340
    check_priv();
nkeynes@359
  2341
    load_reg( R_EAX, Rm );
nkeynes@359
  2342
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2343
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2344
:}
nkeynes@359
  2345
LDC Rm, SPC {:  
nkeynes@386
  2346
    check_priv();
nkeynes@359
  2347
    load_reg( R_EAX, Rm );
nkeynes@359
  2348
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2350
:}
nkeynes@359
  2351
LDC Rm, DBR {:  
nkeynes@386
  2352
    check_priv();
nkeynes@359
  2353
    load_reg( R_EAX, Rm );
nkeynes@359
  2354
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2356
:}
nkeynes@374
  2357
LDC Rm, Rn_BANK {:  
nkeynes@386
  2358
    check_priv();
nkeynes@374
  2359
    load_reg( R_EAX, Rm );
nkeynes@374
  2360
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2361
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2362
:}
nkeynes@359
  2363
LDC.L @Rm+, GBR {:  
nkeynes@359
  2364
    load_reg( R_EAX, Rm );
nkeynes@416
  2365
    precheck();
nkeynes@395
  2366
    check_ralign32( R_EAX );
nkeynes@359
  2367
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2368
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2369
    store_reg( R_EAX, Rm );
nkeynes@359
  2370
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2371
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2373
:}
nkeynes@368
  2374
LDC.L @Rm+, SR {:
nkeynes@386
  2375
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2376
	SLOTILLEGAL();
nkeynes@386
  2377
    } else {
nkeynes@416
  2378
	precheck();
nkeynes@416
  2379
	check_priv_no_precheck();
nkeynes@386
  2380
	load_reg( R_EAX, Rm );
nkeynes@395
  2381
	check_ralign32( R_EAX );
nkeynes@386
  2382
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2383
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2384
	store_reg( R_EAX, Rm );
nkeynes@386
  2385
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2386
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2387
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2388
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2389
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2390
    }
nkeynes@359
  2391
:}
nkeynes@359
  2392
LDC.L @Rm+, VBR {:  
nkeynes@416
  2393
    precheck();
nkeynes@416
  2394
    check_priv_no_precheck();
nkeynes@359
  2395
    load_reg( R_EAX, Rm );
nkeynes@395
  2396
    check_ralign32( R_EAX );
nkeynes@359
  2397
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2398
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2399
    store_reg( R_EAX, Rm );
nkeynes@359
  2400
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2401
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2403
:}
nkeynes@359
  2404
LDC.L @Rm+, SSR {:
nkeynes@416
  2405
    precheck();
nkeynes@416
  2406
    check_priv_no_precheck();
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@416
  2408
    check_ralign32( R_EAX );
nkeynes@359
  2409
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2410
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2411
    store_reg( R_EAX, Rm );
nkeynes@359
  2412
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2413
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2415
:}
nkeynes@359
  2416
LDC.L @Rm+, SGR {:  
nkeynes@416
  2417
    precheck();
nkeynes@416
  2418
    check_priv_no_precheck();
nkeynes@359
  2419
    load_reg( R_EAX, Rm );
nkeynes@395
  2420
    check_ralign32( R_EAX );
nkeynes@359
  2421
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2422
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2423
    store_reg( R_EAX, Rm );
nkeynes@359
  2424
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2425
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2427
:}
nkeynes@359
  2428
LDC.L @Rm+, SPC {:  
nkeynes@416
  2429
    precheck();
nkeynes@416
  2430
    check_priv_no_precheck();
nkeynes@359
  2431
    load_reg( R_EAX, Rm );
nkeynes@395
  2432
    check_ralign32( R_EAX );
nkeynes@359
  2433
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2434
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2435
    store_reg( R_EAX, Rm );
nkeynes@359
  2436
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2437
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2439
:}
nkeynes@359
  2440
LDC.L @Rm+, DBR {:  
nkeynes@416
  2441
    precheck();
nkeynes@416
  2442
    check_priv_no_precheck();
nkeynes@359
  2443
    load_reg( R_EAX, Rm );
nkeynes@395
  2444
    check_ralign32( R_EAX );
nkeynes@359
  2445
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2446
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2447
    store_reg( R_EAX, Rm );
nkeynes@359
  2448
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2449
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2451
:}
nkeynes@359
  2452
LDC.L @Rm+, Rn_BANK {:  
nkeynes@416
  2453
    precheck();
nkeynes@416
  2454
    check_priv_no_precheck();
nkeynes@374
  2455
    load_reg( R_EAX, Rm );
nkeynes@395
  2456
    check_ralign32( R_EAX );
nkeynes@374
  2457
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2458
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2459
    store_reg( R_EAX, Rm );
nkeynes@374
  2460
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2461
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2463
:}
nkeynes@359
  2464
LDS Rm, FPSCR {:  
nkeynes@359
  2465
    load_reg( R_EAX, Rm );
nkeynes@359
  2466
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2467
    update_fr_bank( R_EAX );
nkeynes@417
  2468
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2469
:}
nkeynes@359
  2470
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2471
    load_reg( R_EAX, Rm );
nkeynes@416
  2472
    precheck();
nkeynes@395
  2473
    check_ralign32( R_EAX );
nkeynes@359
  2474
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2475
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2476
    store_reg( R_EAX, Rm );
nkeynes@359
  2477
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2478
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2479
    update_fr_bank( R_EAX );
nkeynes@417
  2480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2481
:}
nkeynes@359
  2482
LDS Rm, FPUL {:  
nkeynes@359
  2483
    load_reg( R_EAX, Rm );
nkeynes@359
  2484
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2485
:}
nkeynes@359
  2486
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2487
    load_reg( R_EAX, Rm );
nkeynes@416
  2488
    precheck();
nkeynes@395
  2489
    check_ralign32( R_EAX );
nkeynes@359
  2490
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2491
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2492
    store_reg( R_EAX, Rm );
nkeynes@359
  2493
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2494
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2496
:}
nkeynes@359
  2497
LDS Rm, MACH {: 
nkeynes@359
  2498
    load_reg( R_EAX, Rm );
nkeynes@359
  2499
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2500
:}
nkeynes@359
  2501
LDS.L @Rm+, MACH {:  
nkeynes@359
  2502
    load_reg( R_EAX, Rm );
nkeynes@416
  2503
    precheck();
nkeynes@395
  2504
    check_ralign32( R_EAX );
nkeynes@359
  2505
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2506
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2507
    store_reg( R_EAX, Rm );
nkeynes@359
  2508
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2509
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2510
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2511
:}
nkeynes@359
  2512
LDS Rm, MACL {:  
nkeynes@359
  2513
    load_reg( R_EAX, Rm );
nkeynes@359
  2514
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2515
:}
nkeynes@359
  2516
LDS.L @Rm+, MACL {:  
nkeynes@359
  2517
    load_reg( R_EAX, Rm );
nkeynes@416
  2518
    precheck();
nkeynes@395
  2519
    check_ralign32( R_EAX );
nkeynes@359
  2520
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2521
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2522
    store_reg( R_EAX, Rm );
nkeynes@359
  2523
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2524
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
LDS Rm, PR {:  
nkeynes@359
  2528
    load_reg( R_EAX, Rm );
nkeynes@359
  2529
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2530
:}
nkeynes@359
  2531
LDS.L @Rm+, PR {:  
nkeynes@359
  2532
    load_reg( R_EAX, Rm );
nkeynes@416
  2533
    precheck();
nkeynes@395
  2534
    check_ralign32( R_EAX );
nkeynes@359
  2535
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2536
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2537
    store_reg( R_EAX, Rm );
nkeynes@359
  2538
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2539
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2540
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2541
:}
nkeynes@359
  2542
LDTLB {:  :}
nkeynes@359
  2543
OCBI @Rn {:  :}
nkeynes@359
  2544
OCBP @Rn {:  :}
nkeynes@359
  2545
OCBWB @Rn {:  :}
nkeynes@374
  2546
PREF @Rn {:
nkeynes@374
  2547
    load_reg( R_EAX, Rn );
nkeynes@374
  2548
    PUSH_r32( R_EAX );
nkeynes@374
  2549
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2550
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2551
    JNE_rel8(7, end);
nkeynes@374
  2552
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2553
    JMP_TARGET(end);
nkeynes@377
  2554
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
  2555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2556
:}
nkeynes@388
  2557
SLEEP {: 
nkeynes@388
  2558
    check_priv();
nkeynes@388
  2559
    call_func0( sh4_sleep );
nkeynes@417
  2560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2561
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2562
    return 2;
nkeynes@388
  2563
:}
nkeynes@386
  2564
STC SR, Rn {:
nkeynes@386
  2565
    check_priv();
nkeynes@386
  2566
    call_func0(sh4_read_sr);
nkeynes@386
  2567
    store_reg( R_EAX, Rn );
nkeynes@417
  2568
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2569
:}
nkeynes@359
  2570
STC GBR, Rn {:  
nkeynes@359
  2571
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2572
    store_reg( R_EAX, Rn );
nkeynes@359
  2573
:}
nkeynes@359
  2574
STC VBR, Rn {:  
nkeynes@386
  2575
    check_priv();
nkeynes@359
  2576
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2577
    store_reg( R_EAX, Rn );
nkeynes@417
  2578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2579
:}
nkeynes@359
  2580
STC SSR, Rn {:  
nkeynes@386
  2581
    check_priv();
nkeynes@359
  2582
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2583
    store_reg( R_EAX, Rn );
nkeynes@417
  2584
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2585
:}
nkeynes@359
  2586
STC SPC, Rn {:  
nkeynes@386
  2587
    check_priv();
nkeynes@359
  2588
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2589
    store_reg( R_EAX, Rn );
nkeynes@417
  2590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2591
:}
nkeynes@359
  2592
STC SGR, Rn {:  
nkeynes@386
  2593
    check_priv();
nkeynes@359
  2594
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2595
    store_reg( R_EAX, Rn );
nkeynes@417
  2596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2597
:}
nkeynes@359
  2598
STC DBR, Rn {:  
nkeynes@386
  2599
    check_priv();
nkeynes@359
  2600
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2601
    store_reg( R_EAX, Rn );
nkeynes@417
  2602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2603
:}
nkeynes@374
  2604
STC Rm_BANK, Rn {:
nkeynes@386
  2605
    check_priv();
nkeynes@374
  2606
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2607
    store_reg( R_EAX, Rn );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2609
:}
nkeynes@374
  2610
STC.L SR, @-Rn {:
nkeynes@416
  2611
    precheck();
nkeynes@416
  2612
    check_priv_no_precheck();
nkeynes@395
  2613
    call_func0( sh4_read_sr );
nkeynes@368
  2614
    load_reg( R_ECX, Rn );
nkeynes@395
  2615
    check_walign32( R_ECX );
nkeynes@382
  2616
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2617
    store_reg( R_ECX, Rn );
nkeynes@368
  2618
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2620
:}
nkeynes@359
  2621
STC.L VBR, @-Rn {:  
nkeynes@416
  2622
    precheck();
nkeynes@416
  2623
    check_priv_no_precheck();
nkeynes@359
  2624
    load_reg( R_ECX, Rn );
nkeynes@395
  2625
    check_walign32( R_ECX );
nkeynes@382
  2626
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2627
    store_reg( R_ECX, Rn );
nkeynes@359
  2628
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2629
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2630
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2631
:}
nkeynes@359
  2632
STC.L SSR, @-Rn {:  
nkeynes@416
  2633
    precheck();
nkeynes@416
  2634
    check_priv_no_precheck();
nkeynes@359
  2635
    load_reg( R_ECX, Rn );
nkeynes@395
  2636
    check_walign32( R_ECX );
nkeynes@382
  2637
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2638
    store_reg( R_ECX, Rn );
nkeynes@359
  2639
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2640
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2641
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2642
:}
nkeynes@416
  2643
STC.L SPC, @-Rn {:
nkeynes@416
  2644
    precheck();
nkeynes@416
  2645
    check_priv_no_precheck();
nkeynes@359
  2646
    load_reg( R_ECX, Rn );
nkeynes@395
  2647
    check_walign32( R_ECX );
nkeynes@382
  2648
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2649
    store_reg( R_ECX, Rn );
nkeynes@359
  2650
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2651
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2653
:}
nkeynes@359
  2654
STC.L SGR, @-Rn {:  
nkeynes@416
  2655
    precheck();
nkeynes@416
  2656
    check_priv_no_precheck();
nkeynes@359
  2657
    load_reg( R_ECX, Rn );
nkeynes@395
  2658
    check_walign32( R_ECX );
nkeynes@382
  2659
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2660
    store_reg( R_ECX, Rn );
nkeynes@359
  2661
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2662
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2663
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2664
:}
nkeynes@359
  2665
STC.L DBR, @-Rn {:  
nkeynes@416
  2666
    precheck();
nkeynes@416
  2667
    check_priv_no_precheck();
nkeynes@359
  2668
    load_reg( R_ECX, Rn );
nkeynes@395
  2669
    check_walign32( R_ECX );
nkeynes@382
  2670
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2671
    store_reg( R_ECX, Rn );
nkeynes@359
  2672
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2673
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2674
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2675
:}
nkeynes@374
  2676
STC.L Rm_BANK, @-Rn {:  
nkeynes@416
  2677
    precheck();
nkeynes@416
  2678
    check_priv_no_precheck();
nkeynes@374
  2679
    load_reg( R_ECX, Rn );
nkeynes@395
  2680
    check_walign32( R_ECX );
nkeynes@382
  2681
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2682
    store_reg( R_ECX, Rn );
nkeynes@374
  2683
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2684
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2686
:}
nkeynes@359
  2687
STC.L GBR, @-Rn {:  
nkeynes@359
  2688
    load_reg( R_ECX, Rn );
nkeynes@416
  2689
    precheck();
nkeynes@395
  2690
    check_walign32( R_ECX );
nkeynes@382
  2691
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2692
    store_reg( R_ECX, Rn );
nkeynes@359
  2693
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2694
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2696
:}
nkeynes@359
  2697
STS FPSCR, Rn {:  
nkeynes@359
  2698
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2699
    store_reg( R_EAX, Rn );
nkeynes@359
  2700
:}
nkeynes@359
  2701
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2702
    load_reg( R_ECX, Rn );
nkeynes@416
  2703
    precheck();
nkeynes@395
  2704
    check_walign32( R_ECX );
nkeynes@382
  2705
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2706
    store_reg( R_ECX, Rn );
nkeynes@359
  2707
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2708
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2709
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2710
:}
nkeynes@359
  2711
STS FPUL, Rn {:  
nkeynes@359
  2712
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2713
    store_reg( R_EAX, Rn );
nkeynes@359
  2714
:}
nkeynes@359
  2715
STS.L FPUL, @-Rn {:  
nkeynes@359
  2716
    load_reg( R_ECX, Rn );
nkeynes@416
  2717
    precheck();
nkeynes@395
  2718
    check_walign32( R_ECX );
nkeynes@382
  2719
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2720
    store_reg( R_ECX, Rn );
nkeynes@359
  2721
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2722
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2723
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2724
:}
nkeynes@359
  2725
STS MACH, Rn {:  
nkeynes@359
  2726
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2727
    store_reg( R_EAX, Rn );
nkeynes@359
  2728
:}
nkeynes@359
  2729
STS.L MACH, @-Rn {:  
nkeynes@359
  2730
    load_reg( R_ECX, Rn );
nkeynes@416
  2731
    precheck();
nkeynes@395
  2732
    check_walign32( R_ECX );
nkeynes@382
  2733
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2734
    store_reg( R_ECX, Rn );
nkeynes@359
  2735
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2736
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2738
:}
nkeynes@359
  2739
STS MACL, Rn {:  
nkeynes@359
  2740
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2741
    store_reg( R_EAX, Rn );
nkeynes@359
  2742
:}
nkeynes@359
  2743
STS.L MACL, @-Rn {:  
nkeynes@359
  2744
    load_reg( R_ECX, Rn );
nkeynes@416
  2745
    precheck();
nkeynes@395
  2746
    check_walign32( R_ECX );
nkeynes@382
  2747
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2748
    store_reg( R_ECX, Rn );
nkeynes@359
  2749
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2750
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2751
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2752
:}
nkeynes@359
  2753
STS PR, Rn {:  
nkeynes@359
  2754
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2755
    store_reg( R_EAX, Rn );
nkeynes@359
  2756
:}
nkeynes@359
  2757
STS.L PR, @-Rn {:  
nkeynes@359
  2758
    load_reg( R_ECX, Rn );
nkeynes@416
  2759
    precheck();
nkeynes@395
  2760
    check_walign32( R_ECX );
nkeynes@382
  2761
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2762
    store_reg( R_ECX, Rn );
nkeynes@359
  2763
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2764
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2765
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2766
:}
nkeynes@359
  2767
nkeynes@359
  2768
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2769
%%
nkeynes@416
  2770
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2771
    return 0;
nkeynes@359
  2772
}
.