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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 361:be3de4ecd954
prev359:c588dce7ebde
next368:36fac4c42322
author nkeynes
date Tue Aug 28 08:46:14 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Translator WIP: fill out and correct another batch of instructions
file annotate diff log raw
nkeynes@359
     1
/**
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 * $Id: sh4x86.in,v 1.2 2007-08-28 08:46:14 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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    19
 */
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#include "sh4core.h"
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#include "sh4trans.h"
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#include "x86op.h"
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_spreg( int x86reg, int regoffset )
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    37
{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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    42
}
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    43
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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    52
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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    67
}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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    72
 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    OP(0xFF);
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    MODRM_rm32_r32(R_EAX, 2);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() {
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    /* push ebp */
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    *xlat_output++ = 0x50 + R_EBP;
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    /* load carry from SR */
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}
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/**
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 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
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 */
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void sh4_translate_end_block( sh4addr_t pc ) {
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    /* pop ebp */
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    *xlat_output++ = 0x58 + R_EBP;
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    /* ret */
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    *xlat_output++ = 0xC3;
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}
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/**
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 * Translate a single instruction. Delayed branches are handled specially
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 * by translating both branch and delayed instruction as a single unit (as
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 * 
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 *
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 * @return true if the instruction marks the end of a basic block
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 * (eg a branch or 
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 */
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uint32_t sh4_x86_translate_instruction( uint32_t pc )
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{
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    uint16_t ir = sh4_read_word( pc );
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%%
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/* ALU operations */
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ADD Rm, Rn {:
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_reg( R_ECX, Rn );
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:}
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ADD #imm, Rn {:  
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    load_reg( R_EAX, Rn );
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    ADD_imm8s_r32( imm, R_EAX );
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    store_reg( R_EAX, Rn );
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:}
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ADDC Rm, Rn {:
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    LDC_t();
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    ADC_r32_r32( R_EAX, R_ECX );
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    store_reg( R_ECX, Rn );
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    SETC_t();
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:}
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ADDV Rm, Rn {:
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_reg( R_ECX, Rn );
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    SETO_t();
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:}
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AND Rm, Rn {:
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    AND_r32_r32( R_EAX, R_ECX );
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    store_reg( R_ECX, Rn );
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:}
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AND #imm, R0 {:  
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    load_reg( R_EAX, 0 );
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    AND_imm32_r32(imm, R_EAX); 
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    store_reg( R_EAX, 0 );
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:}
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AND.B #imm, @(R0, GBR) {: 
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    load_reg( R_EAX, 0 );
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    load_spreg( R_ECX, R_GBR );
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    ADD_r32_r32( R_EAX, R_EBX );
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    MEM_READ_BYTE( R_ECX, R_EAX );
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    AND_imm32_r32(imm, R_ECX );
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    MEM_WRITE_BYTE( R_ECX, R_EAX );
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:}
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CMP/EQ Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETE_t();
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:}
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CMP/EQ #imm, R0 {:  
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    load_reg( R_EAX, 0 );
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    CMP_imm8s_r32(imm, R_EAX);
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    SETE_t();
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:}
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CMP/GE Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETGE_t();
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:}
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CMP/GT Rm, Rn {: 
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETG_t();
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:}
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CMP/HI Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETA_t();
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:}
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CMP/HS Rm, Rn {: 
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETAE_t();
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 :}
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CMP/PL Rn {: 
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    load_reg( R_EAX, Rn );
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    CMP_imm8s_r32( 0, R_EAX );
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    SETG_t();
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:}
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CMP/PZ Rn {:  
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    load_reg( R_EAX, Rn );
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    CMP_imm8s_r32( 0, R_EAX );
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    SETGE_t();
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:}
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CMP/STR Rm, Rn {:  
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:}
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DIV0S Rm, Rn {:
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rm );
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    SHR_imm8_r32( 31, R_EAX );
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    SHR_imm8_r32( 31, R_ECX );
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    store_spreg( R_EAX, R_M );
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    store_spreg( R_ECX, R_Q );
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    CMP_r32_r32( R_EAX, R_ECX );
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    SETE_t();
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:}
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   246
DIV0U {:  
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    XOR_r32_r32( R_EAX, R_EAX );
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    store_spreg( R_EAX, R_Q );
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   249
    store_spreg( R_EAX, R_M );
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    store_spreg( R_EAX, R_T );
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:}
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   252
DIV1 Rm, Rn {:  :}
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DMULS.L Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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   256
    IMUL_r32(R_ECX);
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    store_spreg( R_EDX, R_MACH );
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   258
    store_spreg( R_EAX, R_MACL );
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:}
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   260
DMULU.L Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    load_reg( R_ECX, Rn );
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   263
    MUL_r32(R_ECX);
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    store_spreg( R_EDX, R_MACH );
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   265
    store_spreg( R_EAX, R_MACL );    
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:}
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   267
DT Rn {:  
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    load_reg( R_EAX, Rn );
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    ADD_imm8s_r32( -1, Rn );
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    store_reg( R_EAX, Rn );
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    SETE_t();
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:}
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   273
EXTS.B Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    MOVSX_r8_r32( R_EAX, R_EAX );
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    store_reg( R_EAX, Rn );
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:}
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   278
EXTS.W Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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   280
    MOVSX_r16_r32( R_EAX, R_EAX );
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    store_reg( R_EAX, Rn );
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:}
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   283
EXTU.B Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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    MOVZX_r8_r32( R_EAX, R_EAX );
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    store_reg( R_EAX, Rn );
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:}
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   288
EXTU.W Rm, Rn {:  
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   289
    load_reg( R_EAX, Rm );
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   290
    MOVZX_r16_r32( R_EAX, R_EAX );
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   291
    store_reg( R_EAX, Rn );
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:}
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   293
MAC.L @Rm+, @Rn+ {:  :}
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   294
MAC.W @Rm+, @Rn+ {:  :}
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   295
MOVT Rn {:  
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   296
    load_spreg( R_EAX, R_T );
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   297
    store_reg( R_EAX, Rn );
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   298
:}
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   299
MUL.L Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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   301
    load_reg( R_ECX, Rn );
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   302
    MUL_r32( R_ECX );
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   303
    store_spreg( R_EAX, R_MACL );
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   304
:}
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   305
MULS.W Rm, Rn {:  
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:}
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   307
MULU.W Rm, Rn {:  :}
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   308
NEG Rm, Rn {:
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   309
    load_reg( R_EAX, Rm );
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   310
    NEG_r32( R_EAX );
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    store_reg( R_EAX, Rn );
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   312
:}
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   313
NEGC Rm, Rn {:  
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    load_reg( R_EAX, Rm );
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   315
    XOR_r32_r32( R_ECX, R_ECX );
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   316
    LDC_t();
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   317
    SBB_r32_r32( R_EAX, R_ECX );
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   318
    store_reg( R_ECX, Rn );
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   319
    SETC_t();
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:}
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   321
NOT Rm, Rn {:  
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   322
    load_reg( R_EAX, Rm );
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   323
    NOT_r32( R_EAX );
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   324
    store_reg( R_EAX, Rn );
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   325
:}
nkeynes@359
   326
OR Rm, Rn {:  
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   327
    load_reg( R_EAX, Rm );
nkeynes@359
   328
    load_reg( R_ECX, Rn );
nkeynes@359
   329
    OR_r32_r32( R_EAX, R_ECX );
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   330
    store_reg( R_ECX, Rn );
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   331
:}
nkeynes@359
   332
OR #imm, R0 {:
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   333
    load_reg( R_EAX, 0 );
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   334
    OR_imm32_r32(imm, R_EAX);
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   335
    store_reg( R_EAX, 0 );
nkeynes@359
   336
:}
nkeynes@359
   337
OR.B #imm, @(R0, GBR) {:  :}
nkeynes@359
   338
ROTCL Rn {:
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   339
    load_reg( R_EAX, Rn );
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   340
    LDC_t();
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   341
    RCL1_r32( R_EAX );
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   342
    store_reg( R_EAX, Rn );
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   343
    SETC_t();
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   344
:}
nkeynes@359
   345
ROTCR Rn {:  
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   346
    load_reg( R_EAX, Rn );
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   347
    LDC_t();
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   348
    RCR1_r32( R_EAX );
nkeynes@359
   349
    store_reg( R_EAX, Rn );
nkeynes@359
   350
    SETC_t();
nkeynes@359
   351
:}
nkeynes@359
   352
ROTL Rn {:  
nkeynes@359
   353
    load_reg( R_EAX, Rn );
nkeynes@359
   354
    ROL1_r32( R_EAX );
nkeynes@359
   355
    store_reg( R_EAX, Rn );
nkeynes@359
   356
    SETC_t();
nkeynes@359
   357
:}
nkeynes@359
   358
ROTR Rn {:  
nkeynes@359
   359
    load_reg( R_EAX, Rn );
nkeynes@359
   360
    ROR1_r32( R_EAX );
nkeynes@359
   361
    store_reg( R_EAX, Rn );
nkeynes@359
   362
    SETC_t();
nkeynes@359
   363
:}
nkeynes@359
   364
SHAD Rm, Rn {:
nkeynes@359
   365
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   366
    load_reg( R_EAX, Rn );
nkeynes@361
   367
    load_reg( R_ECX, Rm );
nkeynes@361
   368
    CMP_imm32_r32( 0, R_ECX );
nkeynes@361
   369
    JAE_rel8(9);
nkeynes@361
   370
                    
nkeynes@361
   371
    NEG_r32( R_ECX );      // 2
nkeynes@361
   372
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   373
    SAR_r32_CL( R_EAX );       // 2
nkeynes@361
   374
    JMP_rel8(5);               // 2
nkeynes@361
   375
    
nkeynes@361
   376
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   377
    SHL_r32_CL( R_EAX );       // 2
nkeynes@361
   378
                    
nkeynes@361
   379
    store_reg( R_EAX, Rn );
nkeynes@359
   380
:}
nkeynes@359
   381
SHLD Rm, Rn {:  
nkeynes@359
   382
:}
nkeynes@359
   383
SHAL Rn {: 
nkeynes@359
   384
    load_reg( R_EAX, Rn );
nkeynes@359
   385
    SHL1_r32( R_EAX );
nkeynes@359
   386
    store_reg( R_EAX, Rn );
nkeynes@359
   387
:}
nkeynes@359
   388
SHAR Rn {:  
nkeynes@359
   389
    load_reg( R_EAX, Rn );
nkeynes@359
   390
    SAR1_r32( R_EAX );
nkeynes@359
   391
    store_reg( R_EAX, Rn );
nkeynes@359
   392
:}
nkeynes@359
   393
SHLL Rn {:  
nkeynes@359
   394
    load_reg( R_EAX, Rn );
nkeynes@359
   395
    SHL1_r32( R_EAX );
nkeynes@359
   396
    store_reg( R_EAX, Rn );
nkeynes@359
   397
:}
nkeynes@359
   398
SHLL2 Rn {:
nkeynes@359
   399
    load_reg( R_EAX, Rn );
nkeynes@359
   400
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   401
    store_reg( R_EAX, Rn );
nkeynes@359
   402
:}
nkeynes@359
   403
SHLL8 Rn {:  
nkeynes@359
   404
    load_reg( R_EAX, Rn );
nkeynes@359
   405
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   406
    store_reg( R_EAX, Rn );
nkeynes@359
   407
:}
nkeynes@359
   408
SHLL16 Rn {:  
nkeynes@359
   409
    load_reg( R_EAX, Rn );
nkeynes@359
   410
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   411
    store_reg( R_EAX, Rn );
nkeynes@359
   412
:}
nkeynes@359
   413
SHLR Rn {:  
nkeynes@359
   414
    load_reg( R_EAX, Rn );
nkeynes@359
   415
    SHR1_r32( R_EAX );
nkeynes@359
   416
    store_reg( R_EAX, Rn );
nkeynes@359
   417
:}
nkeynes@359
   418
SHLR2 Rn {:  
nkeynes@359
   419
    load_reg( R_EAX, Rn );
nkeynes@359
   420
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   421
    store_reg( R_EAX, Rn );
nkeynes@359
   422
:}
nkeynes@359
   423
SHLR8 Rn {:  
nkeynes@359
   424
    load_reg( R_EAX, Rn );
nkeynes@359
   425
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   426
    store_reg( R_EAX, Rn );
nkeynes@359
   427
:}
nkeynes@359
   428
SHLR16 Rn {:  
nkeynes@359
   429
    load_reg( R_EAX, Rn );
nkeynes@359
   430
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   431
    store_reg( R_EAX, Rn );
nkeynes@359
   432
:}
nkeynes@359
   433
SUB Rm, Rn {:  
nkeynes@359
   434
    load_reg( R_EAX, Rm );
nkeynes@359
   435
    load_reg( R_ECX, Rn );
nkeynes@359
   436
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   437
    store_reg( R_ECX, Rn );
nkeynes@359
   438
:}
nkeynes@359
   439
SUBC Rm, Rn {:  
nkeynes@359
   440
    load_reg( R_EAX, Rm );
nkeynes@359
   441
    load_reg( R_ECX, Rn );
nkeynes@359
   442
    LDC_t();
nkeynes@359
   443
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   444
    store_reg( R_ECX, Rn );
nkeynes@359
   445
:}
nkeynes@359
   446
SUBV Rm, Rn {:  
nkeynes@359
   447
    load_reg( R_EAX, Rm );
nkeynes@359
   448
    load_reg( R_ECX, Rn );
nkeynes@359
   449
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   450
    store_reg( R_ECX, Rn );
nkeynes@359
   451
    SETO_t();
nkeynes@359
   452
:}
nkeynes@359
   453
SWAP.B Rm, Rn {:  
nkeynes@359
   454
    load_reg( R_EAX, Rm );
nkeynes@359
   455
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   456
    store_reg( R_EAX, Rn );
nkeynes@359
   457
:}
nkeynes@359
   458
SWAP.W Rm, Rn {:  
nkeynes@359
   459
    load_reg( R_EAX, Rm );
nkeynes@359
   460
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   461
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   462
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   463
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   464
    store_reg( R_ECX, Rn );
nkeynes@359
   465
:}
nkeynes@361
   466
TAS.B @Rn {:  
nkeynes@361
   467
    load_reg( R_ECX, Rn );
nkeynes@361
   468
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   469
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   470
    SETE_t();
nkeynes@361
   471
    OR_imm8_r8( 0x80, R_AL );
nkeynes@361
   472
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   473
:}
nkeynes@361
   474
TST Rm, Rn {:  
nkeynes@361
   475
    load_reg( R_EAX, Rm );
nkeynes@361
   476
    load_reg( R_ECX, Rn );
nkeynes@361
   477
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   478
    SETE_t();
nkeynes@361
   479
:}
nkeynes@359
   480
TST #imm, R0 {:  :}
nkeynes@359
   481
TST.B #imm, @(R0, GBR) {:  :}
nkeynes@359
   482
XOR Rm, Rn {:  
nkeynes@359
   483
    load_reg( R_EAX, Rm );
nkeynes@359
   484
    load_reg( R_ECX, Rn );
nkeynes@359
   485
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   486
    store_reg( R_ECX, Rn );
nkeynes@359
   487
:}
nkeynes@359
   488
XOR #imm, R0 {:  
nkeynes@359
   489
    load_reg( R_EAX, 0 );
nkeynes@359
   490
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   491
    store_reg( R_EAX, 0 );
nkeynes@359
   492
:}
nkeynes@359
   493
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   494
    load_reg( R_EAX, 0 );
nkeynes@359
   495
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   496
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   497
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   498
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   499
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   500
:}
nkeynes@361
   501
XTRCT Rm, Rn {:
nkeynes@361
   502
    load_reg( R_EAX, Rm );
nkeynes@361
   503
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   504
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   505
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   506
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   507
    store_reg( R_ECX, Rn );
nkeynes@359
   508
:}
nkeynes@359
   509
nkeynes@359
   510
/* Data move instructions */
nkeynes@359
   511
MOV Rm, Rn {:  
nkeynes@359
   512
    load_reg( R_EAX, Rm );
nkeynes@359
   513
    store_reg( R_EAX, Rn );
nkeynes@359
   514
:}
nkeynes@359
   515
MOV #imm, Rn {:  
nkeynes@359
   516
    load_imm32( R_EAX, imm );
nkeynes@359
   517
    store_reg( R_EAX, Rn );
nkeynes@359
   518
:}
nkeynes@359
   519
MOV.B Rm, @Rn {:  
nkeynes@359
   520
    load_reg( R_EAX, Rm );
nkeynes@359
   521
    load_reg( R_ECX, Rn );
nkeynes@359
   522
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   523
:}
nkeynes@359
   524
MOV.B Rm, @-Rn {:  
nkeynes@359
   525
    load_reg( R_EAX, Rm );
nkeynes@359
   526
    load_reg( R_ECX, Rn );
nkeynes@359
   527
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   528
    store_reg( R_ECX, Rn );
nkeynes@359
   529
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   530
:}
nkeynes@359
   531
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   532
    load_reg( R_EAX, 0 );
nkeynes@359
   533
    load_reg( R_ECX, Rn );
nkeynes@359
   534
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   535
    load_reg( R_EAX, Rm );
nkeynes@359
   536
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   537
:}
nkeynes@359
   538
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   539
    load_reg( R_EAX, 0 );
nkeynes@359
   540
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   541
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   542
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   543
:}
nkeynes@359
   544
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   545
    load_reg( R_EAX, 0 );
nkeynes@359
   546
    load_reg( R_ECX, Rn );
nkeynes@359
   547
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   548
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   549
:}
nkeynes@359
   550
MOV.B @Rm, Rn {:  
nkeynes@359
   551
    load_reg( R_ECX, Rm );
nkeynes@359
   552
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   553
    store_reg( R_ECX, Rn );
nkeynes@359
   554
:}
nkeynes@359
   555
MOV.B @Rm+, Rn {:  
nkeynes@359
   556
    load_reg( R_ECX, Rm );
nkeynes@359
   557
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
   558
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
   559
    store_reg( R_EAX, Rm );
nkeynes@359
   560
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   561
    store_reg( R_EAX, Rn );
nkeynes@359
   562
:}
nkeynes@359
   563
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
   564
    load_reg( R_EAX, 0 );
nkeynes@359
   565
    load_reg( R_ECX, Rm );
nkeynes@359
   566
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   567
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   568
    store_reg( R_EAX, Rn );
nkeynes@359
   569
:}
nkeynes@359
   570
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
   571
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   572
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   573
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   574
    store_reg( R_EAX, 0 );
nkeynes@359
   575
:}
nkeynes@359
   576
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
   577
    load_reg( R_ECX, Rm );
nkeynes@359
   578
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   579
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   580
    store_reg( R_EAX, 0 );
nkeynes@359
   581
:}
nkeynes@361
   582
MOV.L Rm, @Rn {:  
nkeynes@361
   583
    load_reg( R_EAX, Rm );
nkeynes@361
   584
    load_reg( R_ECX, Rn );
nkeynes@361
   585
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   586
:}
nkeynes@361
   587
MOV.L Rm, @-Rn {:  
nkeynes@361
   588
    load_reg( R_EAX, Rm );
nkeynes@361
   589
    load_reg( R_ECX, Rn );
nkeynes@361
   590
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   591
    store_reg( R_ECX, Rn );
nkeynes@361
   592
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   593
:}
nkeynes@361
   594
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
   595
    load_reg( R_EAX, 0 );
nkeynes@361
   596
    load_reg( R_ECX, Rn );
nkeynes@361
   597
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   598
    load_reg( R_EAX, Rm );
nkeynes@361
   599
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   600
:}
nkeynes@361
   601
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
   602
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   603
    load_reg( R_EAX, 0 );
nkeynes@361
   604
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   605
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   606
:}
nkeynes@361
   607
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
   608
    load_reg( R_ECX, Rn );
nkeynes@361
   609
    load_reg( R_EAX, Rm );
nkeynes@361
   610
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   611
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   612
:}
nkeynes@361
   613
MOV.L @Rm, Rn {:  
nkeynes@361
   614
    load_reg( R_ECX, Rm );
nkeynes@361
   615
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   616
    store_reg( R_EAX, Rn );
nkeynes@361
   617
:}
nkeynes@361
   618
MOV.L @Rm+, Rn {:  
nkeynes@361
   619
    load_reg( R_EAX, Rm );
nkeynes@361
   620
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   621
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
   622
    store_reg( R_EAX, Rm );
nkeynes@361
   623
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   624
    store_reg( R_EAX, Rn );
nkeynes@361
   625
:}
nkeynes@361
   626
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
   627
    load_reg( R_EAX, 0 );
nkeynes@361
   628
    load_reg( R_ECX, Rm );
nkeynes@361
   629
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   630
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   631
    store_reg( R_EAX, Rn );
nkeynes@361
   632
:}
nkeynes@361
   633
MOV.L @(disp, GBR), R0 {:
nkeynes@361
   634
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   635
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   636
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   637
    store_reg( R_EAX, 0 );
nkeynes@361
   638
:}
nkeynes@361
   639
MOV.L @(disp, PC), Rn {:  
nkeynes@361
   640
    load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
   641
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   642
    store_reg( R_EAX, 0 );
nkeynes@361
   643
:}
nkeynes@361
   644
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
   645
    load_reg( R_ECX, Rm );
nkeynes@361
   646
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@361
   647
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   648
    store_reg( R_EAX, Rn );
nkeynes@361
   649
:}
nkeynes@361
   650
MOV.W Rm, @Rn {:  
nkeynes@361
   651
    load_reg( R_ECX, Rn );
nkeynes@361
   652
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   653
    store_reg( R_EAX, Rn );
nkeynes@361
   654
:}
nkeynes@361
   655
MOV.W Rm, @-Rn {:  
nkeynes@361
   656
    load_reg( R_ECX, Rn );
nkeynes@361
   657
    load_reg( R_EAX, Rm );
nkeynes@361
   658
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   659
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   660
:}
nkeynes@361
   661
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
   662
    load_reg( R_EAX, 0 );
nkeynes@361
   663
    load_reg( R_ECX, Rn );
nkeynes@361
   664
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   665
    load_reg( R_EAX, Rm );
nkeynes@361
   666
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   667
:}
nkeynes@361
   668
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
   669
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   670
    load_reg( R_EAX, 0 );
nkeynes@361
   671
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   672
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   673
:}
nkeynes@361
   674
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
   675
    load_reg( R_ECX, Rn );
nkeynes@361
   676
    load_reg( R_EAX, 0 );
nkeynes@361
   677
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   678
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
   679
:}
nkeynes@361
   680
MOV.W @Rm, Rn {:  
nkeynes@361
   681
    load_reg( R_ECX, Rm );
nkeynes@361
   682
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   683
    store_reg( R_EAX, Rn );
nkeynes@361
   684
:}
nkeynes@361
   685
MOV.W @Rm+, Rn {:  
nkeynes@361
   686
    load_reg( R_EAX, Rm );
nkeynes@361
   687
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   688
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
   689
    store_reg( R_EAX, Rm );
nkeynes@361
   690
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   691
    store_reg( R_EAX, Rn );
nkeynes@361
   692
:}
nkeynes@361
   693
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
   694
    load_reg( R_EAX, 0 );
nkeynes@361
   695
    load_reg( R_ECX, Rm );
nkeynes@361
   696
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   697
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   698
    store_reg( R_EAX, Rn );
nkeynes@361
   699
:}
nkeynes@361
   700
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
   701
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   702
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   703
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   704
    store_reg( R_EAX, 0 );
nkeynes@361
   705
:}
nkeynes@361
   706
MOV.W @(disp, PC), Rn {:  
nkeynes@361
   707
    load_imm32( R_ECX, pc + disp + 4 );
nkeynes@361
   708
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   709
    store_reg( R_EAX, Rn );
nkeynes@361
   710
:}
nkeynes@361
   711
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
   712
    load_reg( R_ECX, Rm );
nkeynes@361
   713
    ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   714
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   715
    store_reg( R_EAX, 0 );
nkeynes@361
   716
:}
nkeynes@361
   717
MOVA @(disp, PC), R0 {:  
nkeynes@361
   718
    load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
   719
    store_reg( R_ECX, 0 );
nkeynes@361
   720
:}
nkeynes@361
   721
MOVCA.L R0, @Rn {:  
nkeynes@361
   722
    load_reg( R_EAX, 0 );
nkeynes@361
   723
    load_reg( R_ECX, Rn );
nkeynes@361
   724
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   725
:}
nkeynes@359
   726
nkeynes@359
   727
/* Control transfer instructions */
nkeynes@359
   728
BF disp {:  :}
nkeynes@359
   729
BF/S disp {:  :}
nkeynes@359
   730
BRA disp {:  :}
nkeynes@359
   731
BRAF Rn {:  :}
nkeynes@359
   732
BSR disp {:  :}
nkeynes@359
   733
BSRF Rn {:  :}
nkeynes@359
   734
BT disp {:  /* If true, result PC += 4 + disp. else result PC = pc+2 */
nkeynes@359
   735
    return pc + 2;
nkeynes@359
   736
:}
nkeynes@359
   737
BT/S disp {:
nkeynes@359
   738
nkeynes@359
   739
    return pc + 4;
nkeynes@359
   740
:}
nkeynes@359
   741
JMP @Rn {:  :}
nkeynes@359
   742
JSR @Rn {:  :}
nkeynes@359
   743
RTE {:  :}
nkeynes@359
   744
RTS {:  :}
nkeynes@359
   745
TRAPA #imm {:  :}
nkeynes@359
   746
UNDEF {:  :}
nkeynes@359
   747
nkeynes@359
   748
CLRMAC {:  :}
nkeynes@359
   749
CLRS {:  :}
nkeynes@359
   750
CLRT {:  :}
nkeynes@359
   751
SETS {:  :}
nkeynes@359
   752
SETT {:  :}
nkeynes@359
   753
nkeynes@359
   754
/* Floating point instructions */
nkeynes@359
   755
FABS FRn {:  :}
nkeynes@359
   756
FADD FRm, FRn {:  :}
nkeynes@359
   757
FCMP/EQ FRm, FRn {:  :}
nkeynes@359
   758
FCMP/GT FRm, FRn {:  :}
nkeynes@359
   759
FCNVDS FRm, FPUL {:  :}
nkeynes@359
   760
FCNVSD FPUL, FRn {:  :}
nkeynes@359
   761
FDIV FRm, FRn {:  :}
nkeynes@359
   762
FIPR FVm, FVn {:  :}
nkeynes@359
   763
FLDS FRm, FPUL {:  :}
nkeynes@359
   764
FLDI0 FRn {:  :}
nkeynes@359
   765
FLDI1 FRn {:  :}
nkeynes@359
   766
FLOAT FPUL, FRn {:  :}
nkeynes@359
   767
FMAC FR0, FRm, FRn {:  :}
nkeynes@359
   768
FMOV FRm, FRn {:  :}
nkeynes@359
   769
FMOV FRm, @Rn {:  :}
nkeynes@359
   770
FMOV FRm, @-Rn {:  :}
nkeynes@359
   771
FMOV FRm, @(R0, Rn) {:  :}
nkeynes@359
   772
FMOV @Rm, FRn {:  :}
nkeynes@359
   773
FMOV @Rm+, FRn {:  :}
nkeynes@359
   774
FMOV @(R0, Rm), FRn {:  :}
nkeynes@359
   775
FMUL FRm, FRn {:  :}
nkeynes@359
   776
FNEG FRn {:  :}
nkeynes@359
   777
FRCHG {:  :}
nkeynes@359
   778
FSCA FPUL, FRn {:  :}
nkeynes@359
   779
FSCHG {:  :}
nkeynes@359
   780
FSQRT FRn {:  :}
nkeynes@359
   781
FSRRA FRn {:  :}
nkeynes@359
   782
FSTS FPUL, FRn {:  :}
nkeynes@359
   783
FSUB FRm, FRn {:  :}
nkeynes@359
   784
FTRC FRm, FPUL {:  :}
nkeynes@359
   785
FTRV XMTRX, FVn {:  :}
nkeynes@359
   786
nkeynes@359
   787
/* Processor control instructions */
nkeynes@359
   788
LDC Rm, SR {: /* We need to be a little careful about SR */ :}
nkeynes@359
   789
LDC Rm, GBR {: 
nkeynes@359
   790
    load_reg( R_EAX, Rm );
nkeynes@359
   791
    store_spreg( R_EAX, R_GBR );
nkeynes@359
   792
:}
nkeynes@359
   793
LDC Rm, VBR {:  
nkeynes@359
   794
    load_reg( R_EAX, Rm );
nkeynes@359
   795
    store_spreg( R_EAX, R_VBR );
nkeynes@359
   796
:}
nkeynes@359
   797
LDC Rm, SSR {:  
nkeynes@359
   798
    load_reg( R_EAX, Rm );
nkeynes@359
   799
    store_spreg( R_EAX, R_SSR );
nkeynes@359
   800
:}
nkeynes@359
   801
LDC Rm, SGR {:  
nkeynes@359
   802
    load_reg( R_EAX, Rm );
nkeynes@359
   803
    store_spreg( R_EAX, R_SGR );
nkeynes@359
   804
:}
nkeynes@359
   805
LDC Rm, SPC {:  
nkeynes@359
   806
    load_reg( R_EAX, Rm );
nkeynes@359
   807
    store_spreg( R_EAX, R_SPC );
nkeynes@359
   808
:}
nkeynes@359
   809
LDC Rm, DBR {:  
nkeynes@359
   810
    load_reg( R_EAX, Rm );
nkeynes@359
   811
    store_spreg( R_EAX, R_DBR );
nkeynes@359
   812
:}
nkeynes@359
   813
LDC Rm, Rn_BANK {:  :}
nkeynes@359
   814
LDC.L @Rm+, GBR {:  
nkeynes@359
   815
    load_reg( R_EAX, Rm );
nkeynes@359
   816
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   817
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   818
    store_reg( R_EAX, Rm );
nkeynes@359
   819
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   820
    store_spreg( R_EAX, R_GBR );
nkeynes@359
   821
:}
nkeynes@359
   822
LDC.L @Rm+, SR {:  
nkeynes@359
   823
:}
nkeynes@359
   824
LDC.L @Rm+, VBR {:  
nkeynes@359
   825
    load_reg( R_EAX, Rm );
nkeynes@359
   826
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   827
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   828
    store_reg( R_EAX, Rm );
nkeynes@359
   829
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   830
    store_spreg( R_EAX, R_VBR );
nkeynes@359
   831
:}
nkeynes@359
   832
LDC.L @Rm+, SSR {:
nkeynes@359
   833
    load_reg( R_EAX, Rm );
nkeynes@359
   834
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   835
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   836
    store_reg( R_EAX, Rm );
nkeynes@359
   837
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   838
    store_spreg( R_EAX, R_SSR );
nkeynes@359
   839
:}
nkeynes@359
   840
LDC.L @Rm+, SGR {:  
nkeynes@359
   841
    load_reg( R_EAX, Rm );
nkeynes@359
   842
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   843
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   844
    store_reg( R_EAX, Rm );
nkeynes@359
   845
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   846
    store_spreg( R_EAX, R_SGR );
nkeynes@359
   847
:}
nkeynes@359
   848
LDC.L @Rm+, SPC {:  
nkeynes@359
   849
    load_reg( R_EAX, Rm );
nkeynes@359
   850
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   851
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   852
    store_reg( R_EAX, Rm );
nkeynes@359
   853
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   854
    store_spreg( R_EAX, R_SPC );
nkeynes@359
   855
:}
nkeynes@359
   856
LDC.L @Rm+, DBR {:  
nkeynes@359
   857
    load_reg( R_EAX, Rm );
nkeynes@359
   858
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   859
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   860
    store_reg( R_EAX, Rm );
nkeynes@359
   861
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   862
    store_spreg( R_EAX, R_DBR );
nkeynes@359
   863
:}
nkeynes@359
   864
LDC.L @Rm+, Rn_BANK {:  
nkeynes@359
   865
:}
nkeynes@359
   866
LDS Rm, FPSCR {:  
nkeynes@359
   867
    load_reg( R_EAX, Rm );
nkeynes@359
   868
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
   869
:}
nkeynes@359
   870
LDS.L @Rm+, FPSCR {:  
nkeynes@359
   871
    load_reg( R_EAX, Rm );
nkeynes@359
   872
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   873
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   874
    store_reg( R_EAX, Rm );
nkeynes@359
   875
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   876
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
   877
:}
nkeynes@359
   878
LDS Rm, FPUL {:  
nkeynes@359
   879
    load_reg( R_EAX, Rm );
nkeynes@359
   880
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
   881
:}
nkeynes@359
   882
LDS.L @Rm+, FPUL {:  
nkeynes@359
   883
    load_reg( R_EAX, Rm );
nkeynes@359
   884
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   885
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   886
    store_reg( R_EAX, Rm );
nkeynes@359
   887
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   888
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
   889
:}
nkeynes@359
   890
LDS Rm, MACH {: 
nkeynes@359
   891
    load_reg( R_EAX, Rm );
nkeynes@359
   892
    store_spreg( R_EAX, R_MACH );
nkeynes@359
   893
:}
nkeynes@359
   894
LDS.L @Rm+, MACH {:  
nkeynes@359
   895
    load_reg( R_EAX, Rm );
nkeynes@359
   896
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   897
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   898
    store_reg( R_EAX, Rm );
nkeynes@359
   899
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   900
    store_spreg( R_EAX, R_MACH );
nkeynes@359
   901
:}
nkeynes@359
   902
LDS Rm, MACL {:  
nkeynes@359
   903
    load_reg( R_EAX, Rm );
nkeynes@359
   904
    store_spreg( R_EAX, R_MACL );
nkeynes@359
   905
:}
nkeynes@359
   906
LDS.L @Rm+, MACL {:  
nkeynes@359
   907
    load_reg( R_EAX, Rm );
nkeynes@359
   908
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   909
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   910
    store_reg( R_EAX, Rm );
nkeynes@359
   911
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   912
    store_spreg( R_EAX, R_MACL );
nkeynes@359
   913
:}
nkeynes@359
   914
LDS Rm, PR {:  
nkeynes@359
   915
    load_reg( R_EAX, Rm );
nkeynes@359
   916
    store_spreg( R_EAX, R_PR );
nkeynes@359
   917
:}
nkeynes@359
   918
LDS.L @Rm+, PR {:  
nkeynes@359
   919
    load_reg( R_EAX, Rm );
nkeynes@359
   920
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   921
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   922
    store_reg( R_EAX, Rm );
nkeynes@359
   923
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   924
    store_spreg( R_EAX, R_PR );
nkeynes@359
   925
:}
nkeynes@359
   926
LDTLB {:  :}
nkeynes@359
   927
OCBI @Rn {:  :}
nkeynes@359
   928
OCBP @Rn {:  :}
nkeynes@359
   929
OCBWB @Rn {:  :}
nkeynes@359
   930
PREF @Rn {:  :}
nkeynes@359
   931
SLEEP {:  :}
nkeynes@359
   932
 STC SR, Rn {:  /* TODO */
nkeynes@359
   933
:}
nkeynes@359
   934
STC GBR, Rn {:  
nkeynes@359
   935
    load_spreg( R_EAX, R_GBR );
nkeynes@359
   936
    store_reg( R_EAX, Rn );
nkeynes@359
   937
:}
nkeynes@359
   938
STC VBR, Rn {:  
nkeynes@359
   939
    load_spreg( R_EAX, R_VBR );
nkeynes@359
   940
    store_reg( R_EAX, Rn );
nkeynes@359
   941
:}
nkeynes@359
   942
STC SSR, Rn {:  
nkeynes@359
   943
    load_spreg( R_EAX, R_SSR );
nkeynes@359
   944
    store_reg( R_EAX, Rn );
nkeynes@359
   945
:}
nkeynes@359
   946
STC SPC, Rn {:  
nkeynes@359
   947
    load_spreg( R_EAX, R_SPC );
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@359
   949
:}
nkeynes@359
   950
STC SGR, Rn {:  
nkeynes@359
   951
    load_spreg( R_EAX, R_SGR );
nkeynes@359
   952
    store_reg( R_EAX, Rn );
nkeynes@359
   953
:}
nkeynes@359
   954
STC DBR, Rn {:  
nkeynes@359
   955
    load_spreg( R_EAX, R_DBR );
nkeynes@359
   956
    store_reg( R_EAX, Rn );
nkeynes@359
   957
:}
nkeynes@359
   958
 STC Rm_BANK, Rn {: /* TODO */ 
nkeynes@359
   959
:}
nkeynes@359
   960
 STC.L SR, @-Rn {:  /* TODO */
nkeynes@359
   961
:}
nkeynes@359
   962
STC.L VBR, @-Rn {:  
nkeynes@359
   963
    load_reg( R_ECX, Rn );
nkeynes@359
   964
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
   965
    store_reg( R_ECX, Rn );
nkeynes@359
   966
    load_spreg( R_EAX, R_VBR );
nkeynes@359
   967
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   968
:}
nkeynes@359
   969
STC.L SSR, @-Rn {:  
nkeynes@359
   970
    load_reg( R_ECX, Rn );
nkeynes@359
   971
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
   972
    store_reg( R_ECX, Rn );
nkeynes@359
   973
    load_spreg( R_EAX, R_SSR );
nkeynes@359
   974
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   975
:}
nkeynes@359
   976
STC.L SPC, @-Rn {:  
nkeynes@359
   977
    load_reg( R_ECX, Rn );
nkeynes@359
   978
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
   979
    store_reg( R_ECX, Rn );
nkeynes@359
   980
    load_spreg( R_EAX, R_SPC );
nkeynes@359
   981
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   982
:}
nkeynes@359
   983
STC.L SGR, @-Rn {:  
nkeynes@359
   984
    load_reg( R_ECX, Rn );
nkeynes@359
   985
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
   986
    store_reg( R_ECX, Rn );
nkeynes@359
   987
    load_spreg( R_EAX, R_SGR );
nkeynes@359
   988
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   989
:}
nkeynes@359
   990
STC.L DBR, @-Rn {:  
nkeynes@359
   991
    load_reg( R_ECX, Rn );
nkeynes@359
   992
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
   993
    store_reg( R_ECX, Rn );
nkeynes@359
   994
    load_spreg( R_EAX, R_DBR );
nkeynes@359
   995
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   996
:}
nkeynes@359
   997
STC.L Rm_BANK, @-Rn {:  :}
nkeynes@359
   998
STC.L GBR, @-Rn {:  
nkeynes@359
   999
    load_reg( R_ECX, Rn );
nkeynes@359
  1000
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1001
    store_reg( R_ECX, Rn );
nkeynes@359
  1002
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  1003
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1004
:}
nkeynes@359
  1005
STS FPSCR, Rn {:  
nkeynes@359
  1006
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1007
    store_reg( R_EAX, Rn );
nkeynes@359
  1008
:}
nkeynes@359
  1009
STS.L FPSCR, @-Rn {:  
nkeynes@359
  1010
    load_reg( R_ECX, Rn );
nkeynes@359
  1011
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1012
    store_reg( R_ECX, Rn );
nkeynes@359
  1013
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1014
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1015
:}
nkeynes@359
  1016
STS FPUL, Rn {:  
nkeynes@359
  1017
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1018
    store_reg( R_EAX, Rn );
nkeynes@359
  1019
:}
nkeynes@359
  1020
STS.L FPUL, @-Rn {:  
nkeynes@359
  1021
    load_reg( R_ECX, Rn );
nkeynes@359
  1022
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1023
    store_reg( R_ECX, Rn );
nkeynes@359
  1024
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1025
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1026
:}
nkeynes@359
  1027
STS MACH, Rn {:  
nkeynes@359
  1028
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  1029
    store_reg( R_EAX, Rn );
nkeynes@359
  1030
:}
nkeynes@359
  1031
STS.L MACH, @-Rn {:  
nkeynes@359
  1032
    load_reg( R_ECX, Rn );
nkeynes@359
  1033
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1034
    store_reg( R_ECX, Rn );
nkeynes@359
  1035
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  1036
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1037
:}
nkeynes@359
  1038
STS MACL, Rn {:  
nkeynes@359
  1039
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  1040
    store_reg( R_EAX, Rn );
nkeynes@359
  1041
:}
nkeynes@359
  1042
STS.L MACL, @-Rn {:  
nkeynes@359
  1043
    load_reg( R_ECX, Rn );
nkeynes@359
  1044
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1045
    store_reg( R_ECX, Rn );
nkeynes@359
  1046
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  1047
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1048
:}
nkeynes@359
  1049
STS PR, Rn {:  
nkeynes@359
  1050
    load_spreg( R_EAX, R_PR );
nkeynes@359
  1051
    store_reg( R_EAX, Rn );
nkeynes@359
  1052
:}
nkeynes@359
  1053
STS.L PR, @-Rn {:  
nkeynes@359
  1054
    load_reg( R_ECX, Rn );
nkeynes@359
  1055
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1056
    store_reg( R_ECX, Rn );
nkeynes@359
  1057
    load_spreg( R_EAX, R_PR );
nkeynes@359
  1058
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1059
:}
nkeynes@359
  1060
nkeynes@359
  1061
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  1062
%%
nkeynes@359
  1063
nkeynes@359
  1064
    return 0;
nkeynes@359
  1065
}
.