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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 155:be61d1a20937
prev137:41907543d890
next158:a0a82246b44e
author nkeynes
date Wed May 24 11:50:19 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add load/save/reset state, and general tidy up
file annotate diff log raw
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/**
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 * $Id: asic.c,v 1.15 2006-05-24 11:50:19 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
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					NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 8
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#define G2_BIT4_TICKS 16
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#define G2_BIT0_ON_TICKS 24
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#define G2_BIT0_OFF_TICKS 24
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struct asic_g2_state {
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    unsigned int bit5_off_timer;
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    unsigned int bit4_on_timer;
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    unsigned int bit4_off_timer;
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    unsigned int bit0_on_timer;
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    unsigned int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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	return 1;
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    else
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	return 0;
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}
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/* FIXME: Handle rollover */
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void asic_g2_write_word()
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{
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    g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
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    if( g2_state.bit4_off_timer < sh4r.icount )
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	g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
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    g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
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    if( g2_state.bit0_off_timer < sh4r.icount ) {
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	g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
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	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_read_status()
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( g2_state.bit5_off_timer <= sh4r.icount )
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	val = val & (~0x20);
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    if( g2_state.bit4_off_timer <= sh4r.icount )
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	val = val & (~0x10);
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    else if( g2_state.bit4_on_timer <= sh4r.icount )
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	val = val | 0x10;
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    if( g2_state.bit0_off_timer <= sh4r.icount )
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	val = val & (~0x01);
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    else if( g2_state.bit0_on_timer <= sh4r.icount )
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	val = val | 0x01;
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    return val | 0x0E;
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}   
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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void asic_ide_dma_transfer( )
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{	
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    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 &&
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	MMIO_READ( EXTDMA, IDEDMACTL1 ) == 0 ) {
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	uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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	uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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	int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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	uint32_t xfer = ide_read_data_dma( addr, length );
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	if( xfer != 0 ) {
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	    MMIO_WRITE( EXTDMA, IDEDMASH4, addr + xfer );
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	    MMIO_WRITE( EXTDMA, IDEDMASIZ, length - xfer );
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	    if( xfer == length ) {
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		MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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		asic_event( EVENT_IDE_DMA );
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	    }
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	}
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    }
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}
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void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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{
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    switch( reg ) {
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    case PIRQ1:
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	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
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	/* fallthrough */
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    case PIRQ0:
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    case PIRQ2:
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	/* Clear any interrupts */
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	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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	asic_check_cleared_events();
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	break;
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    case MAPLE_STATE:
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	MMIO_WRITE( ASIC, reg, val );
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	if( val & 1 ) {
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	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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	    // WARN( "Maple request initiated at %08X, halting", maple_addr );
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	    maple_handle_buffer( maple_addr );
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	    MMIO_WRITE( ASIC, reg, 0 );
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	}
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	break;
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    case PVRDMACTL: /* Initiate PVR DMA transfer */
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	MMIO_WRITE( ASIC, reg, val );
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	if( val & 1 ) {
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	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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	    char *data = alloca( count );
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	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
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	    if( rcount != count )
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		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
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	    mem_copy_to_sh4( dest_addr, data, rcount );
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	    asic_event( EVENT_PVR_DMA );
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	}
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	break;
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    default:
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	MMIO_WRITE( ASIC, reg, val );
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	WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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	      reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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    }
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}
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int32_t mmio_region_ASIC_read( uint32_t reg )
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{
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    int32_t val;
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    switch( reg ) {
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        /*
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        case 0x89C:
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            sh4_stop();
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            return 0x000000B;
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        */     
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    case PIRQ0:
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    case PIRQ1:
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    case PIRQ2:
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    case IRQA0:
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    case IRQA1:
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    case IRQA2:
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    case IRQB0:
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    case IRQB1:
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    case IRQB2:
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    case IRQC0:
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    case IRQC1:
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    case IRQC2:
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	val = MMIO_READ(ASIC, reg);
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	//            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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	//                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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	return val;            
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    case G2STATUS:
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	return g2_read_status();
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    default:
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	val = MMIO_READ(ASIC, reg);
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	WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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	      reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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	return val;
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    }
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}
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MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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{
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    WARN( "EXTDMA write %08X <= %08X", reg, val );
nkeynes@125
   270
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    switch( reg ) {
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    case IDEALTSTATUS: /* Device control */
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   273
	ide_write_control( val );
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   274
	break;
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   275
    case IDEDATA:
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	ide_write_data_pio( val );
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	break;
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    case IDEFEAT:
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	if( ide_can_write_regs() )
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	    idereg.feature = (uint8_t)val;
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	break;
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   282
    case IDECOUNT:
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   283
	if( ide_can_write_regs() )
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	    idereg.count = (uint8_t)val;
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   285
	break;
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   286
    case IDELBA0:
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   287
	if( ide_can_write_regs() )
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   288
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   289
	break;
nkeynes@125
   290
    case IDELBA1:
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   291
	if( ide_can_write_regs() )
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   292
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   293
	break;
nkeynes@125
   294
    case IDELBA2:
nkeynes@125
   295
	if( ide_can_write_regs() )
nkeynes@125
   296
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   297
	break;
nkeynes@125
   298
    case IDEDEV:
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   299
	if( ide_can_write_regs() )
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   300
	    idereg.device = (uint8_t)val;
nkeynes@125
   301
	break;
nkeynes@125
   302
    case IDECMD:
nkeynes@125
   303
	if( ide_can_write_regs() ) {
nkeynes@125
   304
	    ide_write_command( (uint8_t)val );
nkeynes@125
   305
	}
nkeynes@125
   306
	break;
nkeynes@125
   307
    case IDEDMACTL1:
nkeynes@155
   308
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@125
   309
    case IDEDMACTL2:
nkeynes@125
   310
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@155
   311
	asic_ide_dma_transfer( );
nkeynes@125
   312
	break;
nkeynes@125
   313
    default:
nkeynes@2
   314
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   315
    }
nkeynes@1
   316
}
nkeynes@1
   317
nkeynes@1
   318
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   319
{
nkeynes@56
   320
    uint32_t val;
nkeynes@1
   321
    switch( reg ) {
nkeynes@2
   322
        case IDEALTSTATUS: return idereg.status;
nkeynes@2
   323
        case IDEDATA: return ide_read_data_pio( );
nkeynes@2
   324
        case IDEFEAT: return idereg.error;
nkeynes@2
   325
        case IDECOUNT:return idereg.count;
nkeynes@2
   326
        case IDELBA0: return idereg.disc;
nkeynes@2
   327
        case IDELBA1: return idereg.lba1;
nkeynes@2
   328
        case IDELBA2: return idereg.lba2;
nkeynes@2
   329
        case IDEDEV: return idereg.device;
nkeynes@2
   330
        case IDECMD:
nkeynes@125
   331
	    return ide_read_status();
nkeynes@1
   332
        default:
nkeynes@56
   333
	    val = MMIO_READ( EXTDMA, reg );
nkeynes@94
   334
	    //DEBUG( "EXTDMA read %08X => %08X", reg, val );
nkeynes@56
   335
	    return val;
nkeynes@1
   336
    }
nkeynes@1
   337
}
nkeynes@1
   338
.