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lxdream.org :: lxdream/src/asic.h
lxdream 0.9.1
released Jun 29
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filename src/asic.h
changeset 155:be61d1a20937
prev147:82478590bfa7
next158:a0a82246b44e
author nkeynes
date Wed May 24 11:50:19 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add load/save/reset state, and general tidy up
file annotate diff log raw
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/**
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 * $Id: asic.h,v 1.9 2006-05-24 11:50:19 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions, 
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 * although some functions (maple, ide) are implemented elsewhere.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include "mmio.h"
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/**
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 * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines.
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 * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9.
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 */
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MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" )
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    LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
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    LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
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    LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
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    LONG_PORT( 0x810, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1 - host address?>" )
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    LONG_PORT( 0x814, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2 - host address?>" )
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    LONG_PORT( 0x818, ASICUNK3, PORT_MRW, 0, "ASIC <unknown3>" )
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    LONG_PORT( 0x81C, ASICUNK4, PORT_MRW, 0, "ASIC <unknown4>" )
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    LONG_PORT( 0x820, ASICUNKF, PORT_MRW, 0, "ASIC <unknownF>" )
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    LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
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    LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
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    LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )
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    LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
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    LONG_PORT( 0x884, ASICUNK9, PORT_MRW, 0, "ASIC <unknown9>" )
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    LONG_PORT( 0x888, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )
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    LONG_PORT( 0x88C, G2STATUS, PORT_MR, 0, "G2 Bus status" )
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    LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )
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    LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC <unknownC>" )
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    LONG_PORT( 0x8A4, ASICUNKD, PORT_MRW, 0, "ASIC <unknownD>" )
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    LONG_PORT( 0x8AC, ASICUNKE, PORT_MRW, 0, "ASIC <unknownE>" )
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    LONG_PORT( 0x900, PIRQ0, PORT_MRW, 0, "Pending interrupts 0" )
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    LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
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    LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
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    LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" )
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    LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" )
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    LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" )
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    LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" )
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    LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" )
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    LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" )
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    LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" )
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    LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" )
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    LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" )
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    LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" )
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    LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" )
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    LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" )
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    LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" )
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/* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff
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 * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff.
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 * The whole region 800..8ff is long-readable, but since I so far have no idea
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 * what any of it means (nor have I seen any of it accessed), they're not
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 * listed above.
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 */
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    LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" )
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    LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" )
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    LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" )
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    LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" )
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    LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" )
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    LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" )
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    LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" )
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    LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" )
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    LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" )
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    LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" )
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    LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" )
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    LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" )
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    LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" )
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    LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" )
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    LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" )
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/* Note: Maple registers repeat at 0xD00..0xDFF,
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 * 0xE00..0xEFF and 0xF00..0xFFF */
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MMIO_REGION_END
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MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" )
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    BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */
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    BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" )
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    WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" )
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    BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" )
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    BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" )
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    BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */
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    BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */
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    BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */
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    BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" )
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    BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" )
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    LONG_PORT( 0x404, IDEDMASH4, PORT_MRW, 0, "IDE DMA SH4 address" )
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    LONG_PORT( 0x408, IDEDMASIZ, PORT_MRW, 0, "IDE DMA Size" )
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    LONG_PORT( 0x40C, IDEDMADIR, PORT_MRW, 0, "IDE DMA Direction" )
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    LONG_PORT( 0x414, IDEDMACTL1, PORT_MRW, 0, "IDE DMA Control 1" )
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    LONG_PORT( 0x418, IDEDMACTL2, PORT_MRW, 0, "IDE DMA Control 2" )
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    WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" )
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    LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" )
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    LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" )
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    LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA <unknown3>" )
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    LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA <unknown4>" )
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    LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA <unknown5>" )
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    LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" )
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    LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" )
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    LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" )
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    LONG_PORT( 0x4B8, EXTDMAUNK9, PORT_MRW, 0, "Ext DMA <unknown9>" )
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    LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )
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    LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" )
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    LONG_PORT( 0x804, SPUDMA0SH4, PORT_MRW, 0, "SPU DMA0 SH4-based address" )
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    LONG_PORT( 0x808, SPUDMA0SIZ, PORT_MRW, 0, "SPU DMA0 Size" )
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    LONG_PORT( 0x80C, SPUDMA0DIR, PORT_MRW, 0, "SPU DMA0 Direction" )
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    LONG_PORT( 0x810, SPUDMA0MOD, PORT_MRW, 0, "SPU DMA0 Mode" )
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    LONG_PORT( 0x814, SPUDMA0CTL1, PORT_MRW, 0, "SPU DMA0 Control 1" )
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    LONG_PORT( 0x818, SPUDMA0CTL2, PORT_MRW, 0, "SPU DMA0 Control 2" )
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    LONG_PORT( 0x81C, SPUDMA0UN1, PORT_MRW, 0, "SPU DMA0 <unknown1>" )
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    LONG_PORT( 0x820, SPUDMA1EXT, PORT_MRW, 0, "SPU DMA1 External address" )
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    LONG_PORT( 0x824, SPUDMA1SH4, PORT_MRW, 0, "SPU DMA1 SH4-based address" )
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    LONG_PORT( 0x828, SPUDMA1SIZ, PORT_MRW, 0, "SPU DMA1 Size" )
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    LONG_PORT( 0x82C, SPUDMA1DIR, PORT_MRW, 0, "SPU DMA1 Direction" )
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    LONG_PORT( 0x830, SPUDMA1MOD, PORT_MRW, 0, "SPU DMA1 Mode" )
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    LONG_PORT( 0x834, SPUDMA1CTL1, PORT_MRW, 0, "SPU DMA1 Control 1" )
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    LONG_PORT( 0x838, SPUDMA1CTL2, PORT_MRW, 0, "SPU DMA1 Control 2" )
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    LONG_PORT( 0x83C, SPUDMA1UN1, PORT_MRW, 0, "SPU DMA1 <unknown1>" )
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    LONG_PORT( 0x840, SPUDMA2EXT, PORT_MRW, 0, "SPU DMA2 External address" )
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    LONG_PORT( 0x844, SPUDMA2SH4, PORT_MRW, 0, "SPU DMA2 SH4-based address" )
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    LONG_PORT( 0x848, SPUDMA2SIZ, PORT_MRW, 0, "SPU DMA2 Size" )
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    LONG_PORT( 0x84C, SPUDMA2DIR, PORT_MRW, 0, "SPU DMA2 Direction" )
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    LONG_PORT( 0x850, SPUDMA2MOD, PORT_MRW, 0, "SPU DMA2 Mode" )
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    LONG_PORT( 0x854, SPUDMA2CTL1, PORT_MRW, 0, "SPU DMA2 Control 1" )
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    LONG_PORT( 0x858, SPUDMA2CTL2, PORT_MRW, 0, "SPU DMA2 Control 2" )
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    LONG_PORT( 0x85C, SPUDMA2UN1, PORT_MRW, 0, "SPU DMA2 <unknown1>" )
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    LONG_PORT( 0x860, SPUDMA3EXT, PORT_MRW, 0, "SPU DMA3 External address" )
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    LONG_PORT( 0x864, SPUDMA3SH4, PORT_MRW, 0, "SPU DMA3 SH4-based address" )
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    LONG_PORT( 0x868, SPUDMA3SIZ, PORT_MRW, 0, "SPU DMA3 Size" )
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    LONG_PORT( 0x86C, SPUDMA3DIR, PORT_MRW, 0, "SPU DMA3 Direction" )
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    LONG_PORT( 0x870, SPUDMA3MOD, PORT_MRW, 0, "SPU DMA3 Mode" )
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    LONG_PORT( 0x874, SPUDMA3CTL1, PORT_MRW, 0, "SPU DMA3 Control 1" )
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    LONG_PORT( 0x878, SPUDMA3CTL2, PORT_MRW, 0, "SPU DMA3 Control 2" )
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    LONG_PORT( 0x87C, SPUDMA3UN1, PORT_MRW, 0, "SPU DMA3 <unknown1>" )
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    LONG_PORT( 0x890, SPUDMAWAIT, PORT_MRW, 0, "SPU DMA wait states (?)" )
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    LONG_PORT( 0x894, SPUDMAUN1, PORT_MRW, 0, "SPU DMA <unknown1>" )
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    LONG_PORT( 0x898, SPUDMAUN2, PORT_MRW, 0, "SPU DMA <unknown2>" )
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    LONG_PORT( 0x89C, SPUDMAUN3, PORT_MRW, 0, "SPU DMA <unknown3>" )
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    LONG_PORT( 0x8A0, SPUDMAUN4, PORT_MRW, 0, "SPU DMA <unknown4>" )
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    LONG_PORT( 0x8A4, SPUDMAUN5, PORT_MRW, 0, "SPU DMA <unknown5>" )
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    LONG_PORT( 0x8A8, SPUDMAUN6, PORT_MRW, 0, "SPU DMA <unknown6>" )
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    LONG_PORT( 0x8AC, SPUDMAUN7, PORT_MRW, 0, "SPU DMA <unknown7>" )
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    LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA <unknown8>" )
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    LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" )
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    LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" )
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    LONG_PORT( 0x8BC, SPUDMAUN11, PORT_MRW, 0, "SPU DMA <unknown11>" )
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    LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
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    LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
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   164
    LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
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    LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" )
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   166
    LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
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   167
    LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
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   168
    LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
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   169
    LONG_PORT( 0xC80, PVRDMA2UN1, PORT_MRW, 0, "PVR DMA <unknown1>" )
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MMIO_REGION_END
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#define EVENT_PVR_RENDER_DONE 2
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#define EVENT_SCANLINE1 3
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#define EVENT_SCANLINE2 4
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#define EVENT_RETRACE   5
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#define EVENT_PVR_UNK 6
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#define EVENT_PVR_OPAQUE_DONE 7
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#define EVENT_PVR_OPAQUEMOD_DONE 8
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#define EVENT_PVR_TRANS_DONE 9
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#define EVENT_PVR_TRANSMOD_DONE 10
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#define EVENT_MAPLE_DMA 12
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#define EVENT_MAPLE_ERR 13 /* ??? */
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#define EVENT_IDE_DMA 14
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#define EVENT_SPU_DMA0  15
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#define EVENT_SPU_DMA1  16
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#define EVENT_SPU_DMA2  17
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#define EVENT_SPU_DMA3  18
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#define EVENT_PVR_DMA   19
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#define EVENT_PVR_PUNCHOUT_DONE 21
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#define EVENT_IDE       32
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   193
#define EVENT_AICA      33
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/**
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 * Raise an ASIC event 
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 */
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void asic_event( int event );
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/**
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 * Clear an ASIC event. Currently only the IDE controller is known to use
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 * this functionality.
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 */
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void asic_clear_event( int event );
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void asic_g2_write_word( );
.