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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 502:c4ecae2b1b5e
prev428:338966c8aed0
next550:a27e31340147
author nkeynes
date Thu Nov 08 11:54:16 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add sh4ptr_t type, start converting bare pointer refs to it
file annotate diff log raw
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/**
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 * $Id: sh4mmio.c,v 1.15 2007-11-08 11:54:16 nkeynes Exp $
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 * 
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 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
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 * responsible for including the IMPL side of the SH4 MMIO pages.
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 * Most of these will eventually be split off into their own files.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include "dream.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "clock.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#define MMIO_IMPL
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#include "sh4/sh4mmio.h"
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/********************************* MMU *************************************/
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MMIO_REGION_READ_DEFFN( MMU )
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#define OCRAM_START (0x1C000000>>PAGE_BITS)
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#define OCRAM_END   (0x20000000>>PAGE_BITS)
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static sh4ptr_t cache = NULL;
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    switch(reg) {
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    case MMUCR:
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	if( val & MMUCR_AT ) {
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	    ERROR( "MMU Address translation not implemented!" );
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	    dreamcast_stop();
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	}
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	break;
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    case CCR:
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	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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	break;
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    default:
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	break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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	return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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        case MEM_OC_INDEX0: /* OIX=0 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
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            break;
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        case MEM_OC_INDEX1: /* OIX=1 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
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            break;
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        default: /* disabled */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = NULL;
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            break;
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    }
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}
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/********************************* BSC *************************************/
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uint32_t bsc_input = 0x0300;
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uint16_t bsc_read_pdtra()
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{
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    int i;
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    uint32_t pctra = MMIO_READ( BSC, PCTRA );
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    uint16_t output = MMIO_READ( BSC, PDTRA );
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    uint16_t input_mask = 0, output_mask = 0;
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    for( i=0; i<16; i++ ) {
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	int bits = (pctra >> (i<<1)) & 0x03;
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	if( bits == 2 ) input_mask |= (1<<i);
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	else if( bits != 0 ) output_mask |= (1<<i);
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    }
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    /* ??? */
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    if( ((output | (~output_mask)) & 0x03) == 3 ) {
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        output |= 0x03;
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    } else {
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        output &= ~0x03;
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    }
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    return (bsc_input & input_mask) | output;
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}
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uint32_t bsc_read_pdtrb()
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{
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    int i;
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    uint32_t pctrb = MMIO_READ( BSC, PCTRB );
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    uint16_t output = MMIO_READ( BSC, PDTRB );
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    uint16_t input_mask = 0, output_mask = 0;
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    for( i=0; i<4; i++ ) {
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	int bits = (pctrb >> (i<<1)) & 0x03;
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	if( bits == 2 ) input_mask |= (1<<i);
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	else if( bits != 0 ) output_mask |= (1<<i);
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    }
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    return ((bsc_input>>16) & input_mask) | output;
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}
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MMIO_REGION_WRITE_DEFFN(BSC)
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int32_t mmio_region_BSC_read( uint32_t reg )
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{
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    int32_t val;
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    switch( reg ) {
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        case PDTRA:
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	    val = bsc_read_pdtra();
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	    break;
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        case PDTRB:
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	    val = bsc_read_pdtrb();
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	    break;
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        default:
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            val = MMIO_READ( BSC, reg );
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    }
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    return val;
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}
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/********************************* UBC *************************************/
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MMIO_REGION_STUBFNS( UBC )
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/********************************** SCI *************************************/
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MMIO_REGION_STUBFNS( SCI )
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.