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lxdream.org :: lxdream/src/sh4/sh4.def
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.def
changeset 359:c588dce7ebde
author nkeynes
date Thu Aug 23 12:33:27 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Commit decoder generator
Translator work in progress
Fix mac.l, mac.w in emu core
file annotate diff log raw
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##
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## Instruction file for the SH4 - from the SH4 manual.
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##   line ::= bitpattern WHITESPACE result NEWLINE
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##   bitpattern ::= { '0' | '1' | '(' operand ')' }
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##   operand ::= IDENTIFIER ':' NUMBER signspec
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##   signspec ::= 'u' | 's' |
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##   result ::= { IDENTIFIER | NON-IDENT-CHAR }
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registers {
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   uint32    Rm, Rn = r0..r15
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   uint32    Rm_BANK, Rn_BANK = r8_bank..r15_bank
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   float     Frm, Frn = fr0..fr15
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   float     XFm, XFn = xf0..xf15
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   double    Drm, Drn = dr0..dr8 overlaps fr0..fr15 swapped
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   double    XDm, XDn = xd0..xd8 overlaps xf0..xf15 swapped
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   float[4]  FVm, FVn = fv0..fv3 overlaps fr0..fr15
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   float[16] XMTRX = xmtrx overlaps xf0..xf15
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## Special registers
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   uint32 GBR, SR, VBR, SSR, SGR SPC, DBR
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   uint32 FPSCR, FPUL, MACH, MACL, PR, PC
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}
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0011(Rn:4)(Rm:4)1100 ADD Rm, Rn
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0111(Rn:4)(imm:8s)   ADD #imm, Rn
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0011(Rn:4)(Rm:4)1110 ADDC Rm, Rn
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0011(Rn:4)(Rm:4)1111 ADDV Rm, Rn
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0010(Rn:4)(Rm:4)1001 AND Rm, Rn
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11001001(imm:8u)     AND #imm, R0
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11001101(imm:8u)     AND.B #imm, @(R0, GBR)
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10001011(disp:8s<<1)    BF disp
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10001111(disp:8s<<1)    BF/S disp
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1010(disp:12s<<1)       BRA disp
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0000(Rn:4)00100011   BRAF Rn
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1011(disp:12s<<1)       BSR disp
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0000(Rn:4)00000011   BSRF Rn
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10001001(disp:8s<<1)    BT disp
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10001101(disp:8s<<1)    BT/S disp
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0000000000101000     CLRMAC
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0000000001001000     CLRS
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0000000000001000     CLRT
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0011(Rn:4)(Rm:4)0000 CMP/EQ Rm, Rn
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10001000(imm:8s)     CMP/EQ #imm, R0
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0011(Rn:4)(Rm:4)0011 CMP/GE Rm, Rn
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0011(Rn:4)(Rm:4)0111 CMP/GT Rm, Rn
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0011(Rn:4)(Rm:4)0110 CMP/HI Rm, Rn
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0011(Rn:4)(Rm:4)0010 CMP/HS Rm, Rn
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0100(Rn:4)00010101   CMP/PL Rn
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0100(Rn:4)00010001   CMP/PZ Rn
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0010(Rn:4)(Rm:4)1100 CMP/STR Rm, Rn
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0010(Rn:4)(Rm:4)0111 DIV0S Rm, Rn
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0000000000011001     DIV0U
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0011(Rn:4)(Rm:4)0100 DIV1 Rm, Rn
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0011(Rn:4)(Rm:4)1101 DMULS.L Rm, Rn
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0011(Rn:4)(Rm:4)0101 DMULU.L Rm, Rn
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0100(Rn:4)00010000   DT Rn
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0110(Rn:4)(Rm:4)1110 EXTS.B Rm, Rn
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0110(Rn:4)(Rm:4)1111 EXTS.W Rm, Rn
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0110(Rn:4)(Rm:4)1100 EXTU.B Rm, Rn
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0110(Rn:4)(Rm:4)1101 EXTU.W Rm, Rn
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1111(FRn:4)01011101    FABS FRn
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1111(FRn:4)(FRm:4)0000 FADD FRm, FRn
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1111(FRn:4)(FRm:4)0100 FCMP/EQ FRm, FRn
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1111(FRn:4)(FRm:4)0101 FCMP/GT FRm, FRn
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1111(FRm:4)10111101    FCNVDS FRm, FPUL
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1111(FRn:4)10101101    FCNVSD FPUL, FRn
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1111(FRn:4)(FRm:4)0011 FDIV FRm, FRn
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1111(FVn:2)(FVm:2)11101101 FIPR FVm, FVn
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1111(FRm:4)00011101    FLDS FRm, FPUL
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1111(FRn:4)10001101    FLDI0 FRn
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1111(FRn:4)10011101    FLDI1 FRn
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1111(FRn:4)00101101    FLOAT FPUL, FRn
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1111(FRn:4)(FRm:4)1110 FMAC FR0, FRm, FRn
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1111(FRn:4)(FRm:4)1100 FMOV FRm, FRn
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1111(Rn:4)(FRm:4)1010  FMOV FRm, @Rn
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1111(Rn:4)(FRm:4)1011  FMOV FRm, @-Rn
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1111(Rn:4)(FRm:4)0111  FMOV FRm, @(R0, Rn)
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1111(FRn:4)(Rm:4)1000  FMOV @Rm, FRn
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1111(FRn:4)(Rm:4)1001  FMOV @Rm+, FRn
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1111(FRn:4)(Rm:4)0110  FMOV @(R0, Rm), FRn
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1111(FRn:4)(FRm:4)0010 FMUL FRm, FRn
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1111(FRn:4)01001101    FNEG FRn
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1111101111111101       FRCHG
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1111(FRn:3<<1)011111101   FSCA FPUL, FRn
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1111001111111101       FSCHG
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1111(FRn:4)01101101    FSQRT FRn
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1111(FRn:4)01111101    FSRRA FRn
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1111(FRn:4)00001101    FSTS FPUL, FRn
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1111(FRn:4)(FRm:4)0001 FSUB FRm, FRn
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1111(FRm:4)00111101    FTRC FRm, FPUL
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1111(FVn:2)0111111101  FTRV XMTRX, FVn
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0100(Rn:4)00101011   JMP @Rn
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0100(Rn:4)00001011   JSR @Rn
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0100(Rm:4)00011110   LDC Rm, GBR
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0100(Rm:4)00001110   LDC Rm, SR
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0100(Rm:4)00101110   LDC Rm, VBR
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0100(Rm:4)00111110   LDC Rm, SSR
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0100(Rm:4)00111010   LDC Rm, SGR
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0100(Rm:4)01001110   LDC Rm, SPC
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0100(Rm:4)11111010   LDC Rm, DBR
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0100(Rm:4)1(Rn_BANK:3)1110 LDC Rm, Rn_BANK
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0100(Rm:4)00010111   LDC.L @Rm+, GBR
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0100(Rm:4)00000111   LDC.L @Rm+, SR
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0100(Rm:4)00100111   LDC.L @Rm+, VBR
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0100(Rm:4)00110111   LDC.L @Rm+, SSR
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0100(Rm:4)00110110   LDC.L @Rm+, SGR
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0100(Rm:4)01000111   LDC.L @Rm+, SPC
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0100(Rm:4)11110110   LDC.L @Rm+, DBR
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0100(Rm:4)1(Rn_BANK:3)0111 LDC.L @Rm+, Rn_BANK
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0100(Rm:4)01101010   LDS Rm, FPSCR
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0100(Rm:4)01100110   LDS.L @Rm+, FPSCR
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0100(Rm:4)01011010   LDS Rm, FPUL
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0100(Rm:4)01010110   LDS.L @Rm+, FPUL
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0100(Rm:4)00001010   LDS Rm, MACH
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0100(Rm:4)00000110   LDS.L @Rm+, MACH
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0100(Rm:4)00011010   LDS Rm, MACL
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0100(Rm:4)00010110   LDS.L @Rm+, MACL
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0100(Rm:4)00101010   LDS Rm, PR
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0100(Rm:4)00100110   LDS.L @Rm+, PR
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0000000000111000     LDTLB
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0000(Rn:4)(Rm:4)1111 MAC.L @Rm+, @Rn+
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0100(Rn:4)(Rm:4)1111 MAC.W @Rm+, @Rn+
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0110(Rn:4)(Rm:4)0011 MOV Rm, Rn
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1110(Rn:4)(imm:8s)   MOV #imm, Rn
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0010(Rn:4)(Rm:4)0000 MOV.B Rm, @Rn
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0010(Rn:4)(Rm:4)0100 MOV.B Rm, @-Rn
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0000(Rn:4)(Rm:4)0100 MOV.B Rm, @(R0, Rn)
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11000000(disp:8)     MOV.B R0, @(disp, GBR)
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10000000(Rn:4)(disp:4) MOV.B R0, @(disp, Rn)
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0110(Rn:4)(Rm:4)0000 MOV.B @Rm, Rn
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0110(Rn:4)(Rm:4)0100 MOV.B @Rm+, Rn
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0000(Rn:4)(Rm:4)1100 MOV.B @(R0, Rm), Rn
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11000100(disp:8)     MOV.B @(disp, GBR), R0
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10000100(Rm:4)(disp:4) MOV.B @(disp, Rm), R0
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0010(Rn:4)(Rm:4)0010 MOV.L Rm, @Rn
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0010(Rn:4)(Rm:4)0110 MOV.L Rm, @-Rn
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0000(Rn:4)(Rm:4)0110 MOV.L Rm, @(R0, Rn)
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11000010(disp:8<<2)     MOV.L R0, @(disp, GBR)
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0001(Rn:4)(Rm:4)(disp:4<<2) MOV.L Rm, @(disp, Rn)
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0110(Rn:4)(Rm:4)0010 MOV.L @Rm, Rn
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0110(Rn:4)(Rm:4)0110 MOV.L @Rm+, Rn
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0000(Rn:4)(Rm:4)1110 MOV.L @(R0, Rm), Rn
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11000110(disp:8<<2)     MOV.L @(disp, GBR), R0
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1101(Rn:4)(disp:8<<2)   MOV.L @(disp, PC), Rn
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0101(Rn:4)(Rm:4)(disp:4<<2) MOV.L @(disp, Rm), Rn
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0010(Rn:4)(Rm:4)0001 MOV.W Rm, @Rn
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0010(Rn:4)(Rm:4)0101 MOV.W Rm, @-Rn
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0000(Rn:4)(Rm:4)0101 MOV.W Rm, @(R0, Rn)
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11000001(disp:8<<1)     MOV.W R0, @(disp, GBR)
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10000001(Rn:4)(disp:4<<1) MOV.W R0, @(disp, Rn)
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0110(Rn:4)(Rm:4)0001 MOV.W @Rm, Rn
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0110(Rn:4)(Rm:4)0101 MOV.W @Rm+, Rn
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0000(Rn:4)(Rm:4)1101 MOV.W @(R0, Rm), Rn
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11000101(disp:8<<1)     MOV.W @(disp, GBR), R0
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1001(Rn:4)(disp:8<<1)   MOV.W @(disp, PC), Rn
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10000101(Rm:4)(disp:4<<1) MOV.W @(disp, Rm), R0
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11000111(disp:8<<2)     MOVA @(disp, PC), R0
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0000(Rn:4)11000011   MOVCA.L R0, @Rn
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0000(Rn:4)00101001   MOVT Rn
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0000(Rn:4)(Rm:4)0111 MUL.L Rm, Rn
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0010(Rn:4)(Rm:4)1111 MULS.W Rm, Rn
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0010(Rn:4)(Rm:4)1110 MULU.W Rm, Rn
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0110(Rn:4)(Rm:4)1011 NEG Rm, Rn
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0110(Rn:4)(Rm:4)1010 NEGC Rm, Rn
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0000000000001001     NOP
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0110(Rn:4)(Rm:4)0111 NOT Rm, Rn
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0000(Rn:4)10010011   OCBI @Rn
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0000(Rn:4)10100011   OCBP @Rn
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0000(Rn:4)10110011   OCBWB @Rn
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0010(Rn:4)(Rm:4)1011 OR Rm, Rn
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11001011(imm:8)      OR #imm, R0
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11001111(imm:8)      OR.B #imm, @(R0, GBR)
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0000(Rn:4)10000011   PREF @Rn
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0100(Rn:4)00100100   ROTCL Rn
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0100(Rn:4)00100101   ROTCR Rn
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0100(Rn:4)00000100   ROTL Rn
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0100(Rn:4)00000101   ROTR Rn
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0000000000101011     RTE
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0000000000001011     RTS
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0000000001011000     SETS
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0000000000011000     SETT
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0100(Rn:4)(Rm:4)1100 SHAD Rm, Rn
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0100(Rn:4)00100000   SHAL Rn
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0100(Rn:4)00100001   SHAR Rn
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0100(Rn:4)(Rm:4)1101 SHLD Rm, Rn
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0100(Rn:4)00000000   SHLL Rn
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0100(Rn:4)00001000   SHLL2 Rn
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0100(Rn:4)00011000   SHLL8 Rn
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0100(Rn:4)00101000   SHLL16 Rn
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0100(Rn:4)00000001   SHLR Rn
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0100(Rn:4)00001001   SHLR2 Rn
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0100(Rn:4)00011001   SHLR8 Rn
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0100(Rn:4)00101001   SHLR16 Rn
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0000000000011011     SLEEP
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0000(Rn:4)00000010   STC SR, Rn
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0000(Rn:4)00010010   STC GBR, Rn
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0000(Rn:4)00100010   STC VBR, Rn
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0000(Rn:4)00110010   STC SSR, Rn
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0000(Rn:4)01000010   STC SPC, Rn
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0000(Rn:4)00111010   STC SGR, Rn
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0000(Rn:4)11111010   STC DBR, Rn
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0000(Rn:4)1(Rm_BANK:3)0010 STC Rm_BANK, Rn
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0100(Rn:4)00000011   STC.L SR, @-Rn
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0100(Rn:4)00100011   STC.L VBR, @-Rn
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0100(Rn:4)00110011   STC.L SSR, @-Rn
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0100(Rn:4)01000011   STC.L SPC, @-Rn
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0100(Rn:4)00110010   STC.L SGR, @-Rn
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0100(Rn:4)11110010   STC.L DBR, @-Rn
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0100(Rn:4)1(Rm_BANK:3)0011 STC.L Rm_BANK, @-Rn
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0100(Rn:4)00010011   STC.L GBR, @-Rn
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0000(Rn:4)01101010   STS FPSCR, Rn
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0100(Rn:4)01100010   STS.L FPSCR, @-Rn
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0000(Rn:4)01011010   STS FPUL, Rn
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0100(Rn:4)01010010   STS.L FPUL, @-Rn
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0000(Rn:4)00001010   STS MACH, Rn
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0100(Rn:4)00000010   STS.L MACH, @-Rn
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0000(Rn:4)00011010   STS MACL, Rn
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0100(Rn:4)00010010   STS.L MACL, @-Rn
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0000(Rn:4)00101010   STS PR, Rn
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0100(Rn:4)00100010   STS.L PR, @-Rn
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0011(Rn:4)(Rm:4)1000 SUB Rm, Rn
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0011(Rn:4)(Rm:4)1010 SUBC Rm, Rn
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0011(Rn:4)(Rm:4)1011 SUBV Rm, Rn
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0110(Rn:4)(Rm:4)1000 SWAP.B Rm, Rn
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0110(Rn:4)(Rm:4)1001 SWAP.W Rm, Rn
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0100(Rn:4)00011011   TAS.B @Rn
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11000011(imm:8)      TRAPA #imm
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0010(Rn:4)(Rm:4)1000 TST Rm, Rn
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11001000(imm:8)      TST #imm, R0
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11001100(imm:8)      TST.B #imm, @(R0, GBR)
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0010(Rn:4)(Rm:4)1010 XOR Rm, Rn
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11001010(imm:8)      XOR #imm, R0
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11001110(imm:8)      XOR.B #imm, @(R0, GBR)
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0010(Rn:4)(Rm:4)1101 XTRCT Rm, Rn
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1111111111111101     UNDEF
.