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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 359:c588dce7ebde
next361:be3de4ecd954
author nkeynes
date Thu Aug 23 12:33:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Commit decoder generator
Translator work in progress
Fix mac.l, mac.w in emu core
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@359
     2
 * $Id: sh4x86.c,v 1.1 2007-08-23 12:33:27 nkeynes Exp $
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@359
    21
#include "sh4core.h"
nkeynes@359
    22
#include "sh4trans.h"
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    23
#include "x86op.h"
nkeynes@359
    24
nkeynes@359
    25
/**
nkeynes@359
    26
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
    27
 */
nkeynes@359
    28
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
    29
{
nkeynes@359
    30
    /* mov [bp+n], reg */
nkeynes@359
    31
    OP(0x89);
nkeynes@359
    32
    OP(0x45 + x86reg<<3);
nkeynes@359
    33
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
    34
}
nkeynes@359
    35
nkeynes@359
    36
static inline void load_spreg( int x86reg, int regoffset )
nkeynes@359
    37
{
nkeynes@359
    38
    /* mov [bp+n], reg */
nkeynes@359
    39
    OP(0x89);
nkeynes@359
    40
    OP(0x45 + x86reg<<3);
nkeynes@359
    41
    OP(regoffset);
nkeynes@359
    42
}
nkeynes@359
    43
nkeynes@359
    44
#define UNDEF()
nkeynes@359
    45
#define MEM_READ_BYTE( addr_reg, value_reg )
nkeynes@359
    46
#define MEM_READ_WORD( addr_reg, value_reg )
nkeynes@359
    47
#define MEM_READ_LONG( addr_reg, value_reg )
nkeynes@359
    48
#define MEM_WRITE_BYTE( addr_reg, value_reg )
nkeynes@359
    49
#define MEM_WRITE_WORD( addr_reg, value_reg )
nkeynes@359
    50
#define MEM_WRITE_LONG( addr_reg, value_reg )
nkeynes@359
    51
nkeynes@359
    52
/**
nkeynes@359
    53
 * Emit an instruction to load an immediate value into a register
nkeynes@359
    54
 */
nkeynes@359
    55
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
    56
    /* mov #value, reg */
nkeynes@359
    57
    OP(0xB8 + x86reg);
nkeynes@359
    58
    OP32(value);
nkeynes@359
    59
}
nkeynes@359
    60
nkeynes@359
    61
/**
nkeynes@359
    62
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
    63
 */
nkeynes@359
    64
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
    65
    /* mov reg, [bp+n] */
nkeynes@359
    66
    OP(0x8B);
nkeynes@359
    67
    OP(0x45 + x86reg<<3);
nkeynes@359
    68
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
    69
}
nkeynes@359
    70
void static inline store_spreg( int x86reg, int regoffset ) {
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    71
    /* mov reg, [bp+n] */
nkeynes@359
    72
    OP(0x8B);
nkeynes@359
    73
    OP(0x45 + x86reg<<3);
nkeynes@359
    74
    OP(regoffset);
nkeynes@359
    75
}
nkeynes@359
    76
nkeynes@359
    77
nkeynes@359
    78
/**
nkeynes@359
    79
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
    80
 * SI/DI as required
nkeynes@359
    81
 */
nkeynes@359
    82
void sh4_translate_begin_block() {
nkeynes@359
    83
    /* push ebp */
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    84
    *xlat_output++ = 0x50 + R_EBP;
nkeynes@359
    85
nkeynes@359
    86
    /* mov &sh4r, ebp */
nkeynes@359
    87
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@359
    88
nkeynes@359
    89
    /* load carry from SR */
nkeynes@359
    90
}
nkeynes@359
    91
nkeynes@359
    92
/**
nkeynes@359
    93
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
    94
 */
nkeynes@359
    95
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@359
    96
    /* pop ebp */
nkeynes@359
    97
    *xlat_output++ = 0x58 + R_EBP;
nkeynes@359
    98
nkeynes@359
    99
    /* ret */
nkeynes@359
   100
    *xlat_output++ = 0xC3;
nkeynes@359
   101
}
nkeynes@359
   102
nkeynes@359
   103
/**
nkeynes@359
   104
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   105
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   106
 * 
nkeynes@359
   107
 *
nkeynes@359
   108
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   109
 * (eg a branch or 
nkeynes@359
   110
 */
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   111
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   112
{
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   113
    uint16_t ir = 0;
nkeynes@359
   114
nkeynes@359
   115
        switch( (ir&0xF000) >> 12 ) {
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   116
            case 0x0:
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   117
                switch( ir&0xF ) {
nkeynes@359
   118
                    case 0x2:
nkeynes@359
   119
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   120
                            case 0x0:
nkeynes@359
   121
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   122
                                    case 0x0:
nkeynes@359
   123
                                        { /* STC SR, Rn */
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   124
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   125
                                        /* TODO */
nkeynes@359
   126
                                        }
nkeynes@359
   127
                                        break;
nkeynes@359
   128
                                    case 0x1:
nkeynes@359
   129
                                        { /* STC GBR, Rn */
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   130
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   131
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   132
                                        store_reg( R_EAX, Rn );
nkeynes@359
   133
                                        }
nkeynes@359
   134
                                        break;
nkeynes@359
   135
                                    case 0x2:
nkeynes@359
   136
                                        { /* STC VBR, Rn */
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   137
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   138
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   139
                                        store_reg( R_EAX, Rn );
nkeynes@359
   140
                                        }
nkeynes@359
   141
                                        break;
nkeynes@359
   142
                                    case 0x3:
nkeynes@359
   143
                                        { /* STC SSR, Rn */
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   144
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   145
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   146
                                        store_reg( R_EAX, Rn );
nkeynes@359
   147
                                        }
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   148
                                        break;
nkeynes@359
   149
                                    case 0x4:
nkeynes@359
   150
                                        { /* STC SPC, Rn */
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   151
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   152
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   153
                                        store_reg( R_EAX, Rn );
nkeynes@359
   154
                                        }
nkeynes@359
   155
                                        break;
nkeynes@359
   156
                                    default:
nkeynes@359
   157
                                        UNDEF();
nkeynes@359
   158
                                        break;
nkeynes@359
   159
                                }
nkeynes@359
   160
                                break;
nkeynes@359
   161
                            case 0x1:
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   162
                                { /* STC Rm_BANK, Rn */
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   163
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
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   164
                                /* TODO */
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   165
                                }
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   166
                                break;
nkeynes@359
   167
                        }
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   168
                        break;
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   169
                    case 0x3:
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   170
                        switch( (ir&0xF0) >> 4 ) {
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   171
                            case 0x0:
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   172
                                { /* BSRF Rn */
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   173
                                uint32_t Rn = ((ir>>8)&0xF); 
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   174
                                }
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   175
                                break;
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   176
                            case 0x2:
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   177
                                { /* BRAF Rn */
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   178
                                uint32_t Rn = ((ir>>8)&0xF); 
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   179
                                }
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   180
                                break;
nkeynes@359
   181
                            case 0x8:
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   182
                                { /* PREF @Rn */
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   183
                                uint32_t Rn = ((ir>>8)&0xF); 
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   184
                                }
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   185
                                break;
nkeynes@359
   186
                            case 0x9:
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   187
                                { /* OCBI @Rn */
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   188
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   189
                                }
nkeynes@359
   190
                                break;
nkeynes@359
   191
                            case 0xA:
nkeynes@359
   192
                                { /* OCBP @Rn */
nkeynes@359
   193
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   194
                                }
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   195
                                break;
nkeynes@359
   196
                            case 0xB:
nkeynes@359
   197
                                { /* OCBWB @Rn */
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   198
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   199
                                }
nkeynes@359
   200
                                break;
nkeynes@359
   201
                            case 0xC:
nkeynes@359
   202
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   203
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   204
                                }
nkeynes@359
   205
                                break;
nkeynes@359
   206
                            default:
nkeynes@359
   207
                                UNDEF();
nkeynes@359
   208
                                break;
nkeynes@359
   209
                        }
nkeynes@359
   210
                        break;
nkeynes@359
   211
                    case 0x4:
nkeynes@359
   212
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   213
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   214
                        load_reg( R_EAX, 0 );
nkeynes@359
   215
                        load_reg( R_ECX, Rn );
nkeynes@359
   216
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   217
                        load_reg( R_EAX, Rm );
nkeynes@359
   218
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   219
                        }
nkeynes@359
   220
                        break;
nkeynes@359
   221
                    case 0x5:
nkeynes@359
   222
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   223
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   224
                        }
nkeynes@359
   225
                        break;
nkeynes@359
   226
                    case 0x6:
nkeynes@359
   227
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   228
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   229
                        }
nkeynes@359
   230
                        break;
nkeynes@359
   231
                    case 0x7:
nkeynes@359
   232
                        { /* MUL.L Rm, Rn */
nkeynes@359
   233
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   234
                        }
nkeynes@359
   235
                        break;
nkeynes@359
   236
                    case 0x8:
nkeynes@359
   237
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   238
                            case 0x0:
nkeynes@359
   239
                                { /* CLRT */
nkeynes@359
   240
                                }
nkeynes@359
   241
                                break;
nkeynes@359
   242
                            case 0x1:
nkeynes@359
   243
                                { /* SETT */
nkeynes@359
   244
                                }
nkeynes@359
   245
                                break;
nkeynes@359
   246
                            case 0x2:
nkeynes@359
   247
                                { /* CLRMAC */
nkeynes@359
   248
                                }
nkeynes@359
   249
                                break;
nkeynes@359
   250
                            case 0x3:
nkeynes@359
   251
                                { /* LDTLB */
nkeynes@359
   252
                                }
nkeynes@359
   253
                                break;
nkeynes@359
   254
                            case 0x4:
nkeynes@359
   255
                                { /* CLRS */
nkeynes@359
   256
                                }
nkeynes@359
   257
                                break;
nkeynes@359
   258
                            case 0x5:
nkeynes@359
   259
                                { /* SETS */
nkeynes@359
   260
                                }
nkeynes@359
   261
                                break;
nkeynes@359
   262
                            default:
nkeynes@359
   263
                                UNDEF();
nkeynes@359
   264
                                break;
nkeynes@359
   265
                        }
nkeynes@359
   266
                        break;
nkeynes@359
   267
                    case 0x9:
nkeynes@359
   268
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   269
                            case 0x0:
nkeynes@359
   270
                                { /* NOP */
nkeynes@359
   271
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   272
                                }
nkeynes@359
   273
                                break;
nkeynes@359
   274
                            case 0x1:
nkeynes@359
   275
                                { /* DIV0U */
nkeynes@359
   276
                                }
nkeynes@359
   277
                                break;
nkeynes@359
   278
                            case 0x2:
nkeynes@359
   279
                                { /* MOVT Rn */
nkeynes@359
   280
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   281
                                load_spreg( R_EAX, R_T );
nkeynes@359
   282
                                store_reg( R_EAX, Rn );
nkeynes@359
   283
                                }
nkeynes@359
   284
                                break;
nkeynes@359
   285
                            default:
nkeynes@359
   286
                                UNDEF();
nkeynes@359
   287
                                break;
nkeynes@359
   288
                        }
nkeynes@359
   289
                        break;
nkeynes@359
   290
                    case 0xA:
nkeynes@359
   291
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   292
                            case 0x0:
nkeynes@359
   293
                                { /* STS MACH, Rn */
nkeynes@359
   294
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   295
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   296
                                store_reg( R_EAX, Rn );
nkeynes@359
   297
                                }
nkeynes@359
   298
                                break;
nkeynes@359
   299
                            case 0x1:
nkeynes@359
   300
                                { /* STS MACL, Rn */
nkeynes@359
   301
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   302
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   303
                                store_reg( R_EAX, Rn );
nkeynes@359
   304
                                }
nkeynes@359
   305
                                break;
nkeynes@359
   306
                            case 0x2:
nkeynes@359
   307
                                { /* STS PR, Rn */
nkeynes@359
   308
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   309
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   310
                                store_reg( R_EAX, Rn );
nkeynes@359
   311
                                }
nkeynes@359
   312
                                break;
nkeynes@359
   313
                            case 0x3:
nkeynes@359
   314
                                { /* STC SGR, Rn */
nkeynes@359
   315
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   316
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   317
                                store_reg( R_EAX, Rn );
nkeynes@359
   318
                                }
nkeynes@359
   319
                                break;
nkeynes@359
   320
                            case 0x5:
nkeynes@359
   321
                                { /* STS FPUL, Rn */
nkeynes@359
   322
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   323
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   324
                                store_reg( R_EAX, Rn );
nkeynes@359
   325
                                }
nkeynes@359
   326
                                break;
nkeynes@359
   327
                            case 0x6:
nkeynes@359
   328
                                { /* STS FPSCR, Rn */
nkeynes@359
   329
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   330
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   331
                                store_reg( R_EAX, Rn );
nkeynes@359
   332
                                }
nkeynes@359
   333
                                break;
nkeynes@359
   334
                            case 0xF:
nkeynes@359
   335
                                { /* STC DBR, Rn */
nkeynes@359
   336
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   337
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   338
                                store_reg( R_EAX, Rn );
nkeynes@359
   339
                                }
nkeynes@359
   340
                                break;
nkeynes@359
   341
                            default:
nkeynes@359
   342
                                UNDEF();
nkeynes@359
   343
                                break;
nkeynes@359
   344
                        }
nkeynes@359
   345
                        break;
nkeynes@359
   346
                    case 0xB:
nkeynes@359
   347
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   348
                            case 0x0:
nkeynes@359
   349
                                { /* RTS */
nkeynes@359
   350
                                }
nkeynes@359
   351
                                break;
nkeynes@359
   352
                            case 0x1:
nkeynes@359
   353
                                { /* SLEEP */
nkeynes@359
   354
                                }
nkeynes@359
   355
                                break;
nkeynes@359
   356
                            case 0x2:
nkeynes@359
   357
                                { /* RTE */
nkeynes@359
   358
                                }
nkeynes@359
   359
                                break;
nkeynes@359
   360
                            default:
nkeynes@359
   361
                                UNDEF();
nkeynes@359
   362
                                break;
nkeynes@359
   363
                        }
nkeynes@359
   364
                        break;
nkeynes@359
   365
                    case 0xC:
nkeynes@359
   366
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   367
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   368
                        load_reg( R_EAX, 0 );
nkeynes@359
   369
                        load_reg( R_ECX, Rm );
nkeynes@359
   370
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   371
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   372
                        store_reg( R_EAX, Rn );
nkeynes@359
   373
                        }
nkeynes@359
   374
                        break;
nkeynes@359
   375
                    case 0xD:
nkeynes@359
   376
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   377
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   378
                        }
nkeynes@359
   379
                        break;
nkeynes@359
   380
                    case 0xE:
nkeynes@359
   381
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   382
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   383
                        }
nkeynes@359
   384
                        break;
nkeynes@359
   385
                    case 0xF:
nkeynes@359
   386
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   387
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   388
                        }
nkeynes@359
   389
                        break;
nkeynes@359
   390
                    default:
nkeynes@359
   391
                        UNDEF();
nkeynes@359
   392
                        break;
nkeynes@359
   393
                }
nkeynes@359
   394
                break;
nkeynes@359
   395
            case 0x1:
nkeynes@359
   396
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   397
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@359
   398
                }
nkeynes@359
   399
                break;
nkeynes@359
   400
            case 0x2:
nkeynes@359
   401
                switch( ir&0xF ) {
nkeynes@359
   402
                    case 0x0:
nkeynes@359
   403
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   404
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   405
                        load_reg( R_EAX, Rm );
nkeynes@359
   406
                        load_reg( R_ECX, Rn );
nkeynes@359
   407
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   408
                        }
nkeynes@359
   409
                        break;
nkeynes@359
   410
                    case 0x1:
nkeynes@359
   411
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   412
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   413
                        }
nkeynes@359
   414
                        break;
nkeynes@359
   415
                    case 0x2:
nkeynes@359
   416
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   417
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   418
                        }
nkeynes@359
   419
                        break;
nkeynes@359
   420
                    case 0x4:
nkeynes@359
   421
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   422
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   423
                        load_reg( R_EAX, Rm );
nkeynes@359
   424
                        load_reg( R_ECX, Rn );
nkeynes@359
   425
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   426
                        store_reg( R_ECX, Rn );
nkeynes@359
   427
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   428
                        }
nkeynes@359
   429
                        break;
nkeynes@359
   430
                    case 0x5:
nkeynes@359
   431
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   432
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   433
                        }
nkeynes@359
   434
                        break;
nkeynes@359
   435
                    case 0x6:
nkeynes@359
   436
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   437
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   438
                        }
nkeynes@359
   439
                        break;
nkeynes@359
   440
                    case 0x7:
nkeynes@359
   441
                        { /* DIV0S Rm, Rn */
nkeynes@359
   442
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   443
                        }
nkeynes@359
   444
                        break;
nkeynes@359
   445
                    case 0x8:
nkeynes@359
   446
                        { /* TST Rm, Rn */
nkeynes@359
   447
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   448
                        }
nkeynes@359
   449
                        break;
nkeynes@359
   450
                    case 0x9:
nkeynes@359
   451
                        { /* AND Rm, Rn */
nkeynes@359
   452
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   453
                        load_reg( R_EAX, Rm );
nkeynes@359
   454
                        load_reg( R_ECX, Rn );
nkeynes@359
   455
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   456
                        store_reg( R_ECX, Rn );
nkeynes@359
   457
                        }
nkeynes@359
   458
                        break;
nkeynes@359
   459
                    case 0xA:
nkeynes@359
   460
                        { /* XOR Rm, Rn */
nkeynes@359
   461
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   462
                        load_reg( R_EAX, Rm );
nkeynes@359
   463
                        load_reg( R_ECX, Rn );
nkeynes@359
   464
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   465
                        store_reg( R_ECX, Rn );
nkeynes@359
   466
                        }
nkeynes@359
   467
                        break;
nkeynes@359
   468
                    case 0xB:
nkeynes@359
   469
                        { /* OR Rm, Rn */
nkeynes@359
   470
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   471
                        load_reg( R_EAX, Rm );
nkeynes@359
   472
                        load_reg( R_ECX, Rn );
nkeynes@359
   473
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   474
                        store_reg( R_ECX, Rn );
nkeynes@359
   475
                        }
nkeynes@359
   476
                        break;
nkeynes@359
   477
                    case 0xC:
nkeynes@359
   478
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   479
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   480
                        }
nkeynes@359
   481
                        break;
nkeynes@359
   482
                    case 0xD:
nkeynes@359
   483
                        { /* XTRCT Rm, Rn */
nkeynes@359
   484
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   485
                        }
nkeynes@359
   486
                        break;
nkeynes@359
   487
                    case 0xE:
nkeynes@359
   488
                        { /* MULU.W Rm, Rn */
nkeynes@359
   489
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   490
                        }
nkeynes@359
   491
                        break;
nkeynes@359
   492
                    case 0xF:
nkeynes@359
   493
                        { /* MULS.W Rm, Rn */
nkeynes@359
   494
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   495
                        }
nkeynes@359
   496
                        break;
nkeynes@359
   497
                    default:
nkeynes@359
   498
                        UNDEF();
nkeynes@359
   499
                        break;
nkeynes@359
   500
                }
nkeynes@359
   501
                break;
nkeynes@359
   502
            case 0x3:
nkeynes@359
   503
                switch( ir&0xF ) {
nkeynes@359
   504
                    case 0x0:
nkeynes@359
   505
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   506
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   507
                        load_reg( R_EAX, Rm );
nkeynes@359
   508
                        load_reg( R_ECX, Rn );
nkeynes@359
   509
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   510
                        SETE_t();
nkeynes@359
   511
                        }
nkeynes@359
   512
                        break;
nkeynes@359
   513
                    case 0x2:
nkeynes@359
   514
                        { /* CMP/HS Rm, Rn */
nkeynes@359
   515
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   516
                        load_reg( R_EAX, Rm );
nkeynes@359
   517
                        load_reg( R_ECX, Rn );
nkeynes@359
   518
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   519
                        SETAE_t();
nkeynes@359
   520
                        }
nkeynes@359
   521
                        break;
nkeynes@359
   522
                    case 0x3:
nkeynes@359
   523
                        { /* CMP/GE Rm, Rn */
nkeynes@359
   524
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   525
                        load_reg( R_EAX, Rm );
nkeynes@359
   526
                        load_reg( R_ECX, Rn );
nkeynes@359
   527
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   528
                        SETGE_t();
nkeynes@359
   529
                        }
nkeynes@359
   530
                        break;
nkeynes@359
   531
                    case 0x4:
nkeynes@359
   532
                        { /* DIV1 Rm, Rn */
nkeynes@359
   533
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   534
                        }
nkeynes@359
   535
                        break;
nkeynes@359
   536
                    case 0x5:
nkeynes@359
   537
                        { /* DMULU.L Rm, Rn */
nkeynes@359
   538
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   539
                        }
nkeynes@359
   540
                        break;
nkeynes@359
   541
                    case 0x6:
nkeynes@359
   542
                        { /* CMP/HI Rm, Rn */
nkeynes@359
   543
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   544
                        load_reg( R_EAX, Rm );
nkeynes@359
   545
                        load_reg( R_ECX, Rn );
nkeynes@359
   546
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   547
                        SETA_t();
nkeynes@359
   548
                        }
nkeynes@359
   549
                        break;
nkeynes@359
   550
                    case 0x7:
nkeynes@359
   551
                        { /* CMP/GT Rm, Rn */
nkeynes@359
   552
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   553
                        load_reg( R_EAX, Rm );
nkeynes@359
   554
                        load_reg( R_ECX, Rn );
nkeynes@359
   555
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   556
                        SETG_t();
nkeynes@359
   557
                        }
nkeynes@359
   558
                        break;
nkeynes@359
   559
                    case 0x8:
nkeynes@359
   560
                        { /* SUB Rm, Rn */
nkeynes@359
   561
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   562
                        load_reg( R_EAX, Rm );
nkeynes@359
   563
                        load_reg( R_ECX, Rn );
nkeynes@359
   564
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   565
                        store_reg( R_ECX, Rn );
nkeynes@359
   566
                        }
nkeynes@359
   567
                        break;
nkeynes@359
   568
                    case 0xA:
nkeynes@359
   569
                        { /* SUBC Rm, Rn */
nkeynes@359
   570
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   571
                        load_reg( R_EAX, Rm );
nkeynes@359
   572
                        load_reg( R_ECX, Rn );
nkeynes@359
   573
                        LDC_t();
nkeynes@359
   574
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   575
                        store_reg( R_ECX, Rn );
nkeynes@359
   576
                        }
nkeynes@359
   577
                        break;
nkeynes@359
   578
                    case 0xB:
nkeynes@359
   579
                        { /* SUBV Rm, Rn */
nkeynes@359
   580
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   581
                        load_reg( R_EAX, Rm );
nkeynes@359
   582
                        load_reg( R_ECX, Rn );
nkeynes@359
   583
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   584
                        store_reg( R_ECX, Rn );
nkeynes@359
   585
                        SETO_t();
nkeynes@359
   586
                        }
nkeynes@359
   587
                        break;
nkeynes@359
   588
                    case 0xC:
nkeynes@359
   589
                        { /* ADD Rm, Rn */
nkeynes@359
   590
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   591
                        load_reg( R_EAX, Rm );
nkeynes@359
   592
                        load_reg( R_ECX, Rn );
nkeynes@359
   593
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   594
                        store_reg( R_ECX, Rn );
nkeynes@359
   595
                        }
nkeynes@359
   596
                        break;
nkeynes@359
   597
                    case 0xD:
nkeynes@359
   598
                        { /* DMULS.L Rm, Rn */
nkeynes@359
   599
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   600
                        }
nkeynes@359
   601
                        break;
nkeynes@359
   602
                    case 0xE:
nkeynes@359
   603
                        { /* ADDC Rm, Rn */
nkeynes@359
   604
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   605
                        load_reg( R_EAX, Rm );
nkeynes@359
   606
                        load_reg( R_ECX, Rn );
nkeynes@359
   607
                        LDC_t();
nkeynes@359
   608
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   609
                        store_reg( R_ECX, Rn );
nkeynes@359
   610
                        SETC_t();
nkeynes@359
   611
                        }
nkeynes@359
   612
                        break;
nkeynes@359
   613
                    case 0xF:
nkeynes@359
   614
                        { /* ADDV Rm, Rn */
nkeynes@359
   615
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   616
                        load_reg( R_EAX, Rm );
nkeynes@359
   617
                        load_reg( R_ECX, Rn );
nkeynes@359
   618
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   619
                        store_reg( R_ECX, Rn );
nkeynes@359
   620
                        SETO_t();
nkeynes@359
   621
                        }
nkeynes@359
   622
                        break;
nkeynes@359
   623
                    default:
nkeynes@359
   624
                        UNDEF();
nkeynes@359
   625
                        break;
nkeynes@359
   626
                }
nkeynes@359
   627
                break;
nkeynes@359
   628
            case 0x4:
nkeynes@359
   629
                switch( ir&0xF ) {
nkeynes@359
   630
                    case 0x0:
nkeynes@359
   631
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   632
                            case 0x0:
nkeynes@359
   633
                                { /* SHLL Rn */
nkeynes@359
   634
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   635
                                load_reg( R_EAX, Rn );
nkeynes@359
   636
                                SHL1_r32( R_EAX );
nkeynes@359
   637
                                store_reg( R_EAX, Rn );
nkeynes@359
   638
                                }
nkeynes@359
   639
                                break;
nkeynes@359
   640
                            case 0x1:
nkeynes@359
   641
                                { /* DT Rn */
nkeynes@359
   642
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   643
                                load_reg( R_EAX, Rn );
nkeynes@359
   644
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
   645
                                store_reg( R_EAX, Rn );
nkeynes@359
   646
                                SETE_t();
nkeynes@359
   647
                                }
nkeynes@359
   648
                                break;
nkeynes@359
   649
                            case 0x2:
nkeynes@359
   650
                                { /* SHAL Rn */
nkeynes@359
   651
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   652
                                load_reg( R_EAX, Rn );
nkeynes@359
   653
                                SHL1_r32( R_EAX );
nkeynes@359
   654
                                store_reg( R_EAX, Rn );
nkeynes@359
   655
                                }
nkeynes@359
   656
                                break;
nkeynes@359
   657
                            default:
nkeynes@359
   658
                                UNDEF();
nkeynes@359
   659
                                break;
nkeynes@359
   660
                        }
nkeynes@359
   661
                        break;
nkeynes@359
   662
                    case 0x1:
nkeynes@359
   663
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   664
                            case 0x0:
nkeynes@359
   665
                                { /* SHLR Rn */
nkeynes@359
   666
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   667
                                load_reg( R_EAX, Rn );
nkeynes@359
   668
                                SHR1_r32( R_EAX );
nkeynes@359
   669
                                store_reg( R_EAX, Rn );
nkeynes@359
   670
                                }
nkeynes@359
   671
                                break;
nkeynes@359
   672
                            case 0x1:
nkeynes@359
   673
                                { /* CMP/PZ Rn */
nkeynes@359
   674
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   675
                                load_reg( R_EAX, Rn );
nkeynes@359
   676
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   677
                                SETGE_t();
nkeynes@359
   678
                                }
nkeynes@359
   679
                                break;
nkeynes@359
   680
                            case 0x2:
nkeynes@359
   681
                                { /* SHAR Rn */
nkeynes@359
   682
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   683
                                load_reg( R_EAX, Rn );
nkeynes@359
   684
                                SAR1_r32( R_EAX );
nkeynes@359
   685
                                store_reg( R_EAX, Rn );
nkeynes@359
   686
                                }
nkeynes@359
   687
                                break;
nkeynes@359
   688
                            default:
nkeynes@359
   689
                                UNDEF();
nkeynes@359
   690
                                break;
nkeynes@359
   691
                        }
nkeynes@359
   692
                        break;
nkeynes@359
   693
                    case 0x2:
nkeynes@359
   694
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   695
                            case 0x0:
nkeynes@359
   696
                                { /* STS.L MACH, @-Rn */
nkeynes@359
   697
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   698
                                load_reg( R_ECX, Rn );
nkeynes@359
   699
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   700
                                store_reg( R_ECX, Rn );
nkeynes@359
   701
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   702
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   703
                                }
nkeynes@359
   704
                                break;
nkeynes@359
   705
                            case 0x1:
nkeynes@359
   706
                                { /* STS.L MACL, @-Rn */
nkeynes@359
   707
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   708
                                load_reg( R_ECX, Rn );
nkeynes@359
   709
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   710
                                store_reg( R_ECX, Rn );
nkeynes@359
   711
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   712
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   713
                                }
nkeynes@359
   714
                                break;
nkeynes@359
   715
                            case 0x2:
nkeynes@359
   716
                                { /* STS.L PR, @-Rn */
nkeynes@359
   717
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   718
                                load_reg( R_ECX, Rn );
nkeynes@359
   719
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   720
                                store_reg( R_ECX, Rn );
nkeynes@359
   721
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   722
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   723
                                }
nkeynes@359
   724
                                break;
nkeynes@359
   725
                            case 0x3:
nkeynes@359
   726
                                { /* STC.L SGR, @-Rn */
nkeynes@359
   727
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   728
                                load_reg( R_ECX, Rn );
nkeynes@359
   729
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   730
                                store_reg( R_ECX, Rn );
nkeynes@359
   731
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   732
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   733
                                }
nkeynes@359
   734
                                break;
nkeynes@359
   735
                            case 0x5:
nkeynes@359
   736
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
   737
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   738
                                load_reg( R_ECX, Rn );
nkeynes@359
   739
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   740
                                store_reg( R_ECX, Rn );
nkeynes@359
   741
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   742
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   743
                                }
nkeynes@359
   744
                                break;
nkeynes@359
   745
                            case 0x6:
nkeynes@359
   746
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
   747
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   748
                                load_reg( R_ECX, Rn );
nkeynes@359
   749
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   750
                                store_reg( R_ECX, Rn );
nkeynes@359
   751
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   752
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   753
                                }
nkeynes@359
   754
                                break;
nkeynes@359
   755
                            case 0xF:
nkeynes@359
   756
                                { /* STC.L DBR, @-Rn */
nkeynes@359
   757
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   758
                                load_reg( R_ECX, Rn );
nkeynes@359
   759
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   760
                                store_reg( R_ECX, Rn );
nkeynes@359
   761
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   762
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   763
                                }
nkeynes@359
   764
                                break;
nkeynes@359
   765
                            default:
nkeynes@359
   766
                                UNDEF();
nkeynes@359
   767
                                break;
nkeynes@359
   768
                        }
nkeynes@359
   769
                        break;
nkeynes@359
   770
                    case 0x3:
nkeynes@359
   771
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   772
                            case 0x0:
nkeynes@359
   773
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   774
                                    case 0x0:
nkeynes@359
   775
                                        { /* STC.L SR, @-Rn */
nkeynes@359
   776
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   777
                                        /* TODO */
nkeynes@359
   778
                                        }
nkeynes@359
   779
                                        break;
nkeynes@359
   780
                                    case 0x1:
nkeynes@359
   781
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
   782
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   783
                                        load_reg( R_ECX, Rn );
nkeynes@359
   784
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   785
                                        store_reg( R_ECX, Rn );
nkeynes@359
   786
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   787
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   788
                                        }
nkeynes@359
   789
                                        break;
nkeynes@359
   790
                                    case 0x2:
nkeynes@359
   791
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
   792
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   793
                                        load_reg( R_ECX, Rn );
nkeynes@359
   794
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   795
                                        store_reg( R_ECX, Rn );
nkeynes@359
   796
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   797
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   798
                                        }
nkeynes@359
   799
                                        break;
nkeynes@359
   800
                                    case 0x3:
nkeynes@359
   801
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
   802
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   803
                                        load_reg( R_ECX, Rn );
nkeynes@359
   804
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   805
                                        store_reg( R_ECX, Rn );
nkeynes@359
   806
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   807
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   808
                                        }
nkeynes@359
   809
                                        break;
nkeynes@359
   810
                                    case 0x4:
nkeynes@359
   811
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
   812
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   813
                                        load_reg( R_ECX, Rn );
nkeynes@359
   814
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   815
                                        store_reg( R_ECX, Rn );
nkeynes@359
   816
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   817
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   818
                                        }
nkeynes@359
   819
                                        break;
nkeynes@359
   820
                                    default:
nkeynes@359
   821
                                        UNDEF();
nkeynes@359
   822
                                        break;
nkeynes@359
   823
                                }
nkeynes@359
   824
                                break;
nkeynes@359
   825
                            case 0x1:
nkeynes@359
   826
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
   827
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@359
   828
                                }
nkeynes@359
   829
                                break;
nkeynes@359
   830
                        }
nkeynes@359
   831
                        break;
nkeynes@359
   832
                    case 0x4:
nkeynes@359
   833
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   834
                            case 0x0:
nkeynes@359
   835
                                { /* ROTL Rn */
nkeynes@359
   836
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   837
                                load_reg( R_EAX, Rn );
nkeynes@359
   838
                                ROL1_r32( R_EAX );
nkeynes@359
   839
                                store_reg( R_EAX, Rn );
nkeynes@359
   840
                                SETC_t();
nkeynes@359
   841
                                }
nkeynes@359
   842
                                break;
nkeynes@359
   843
                            case 0x2:
nkeynes@359
   844
                                { /* ROTCL Rn */
nkeynes@359
   845
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   846
                                load_reg( R_EAX, Rn );
nkeynes@359
   847
                                LDC_t();
nkeynes@359
   848
                                RCL1_r32( R_EAX );
nkeynes@359
   849
                                store_reg( R_EAX, Rn );
nkeynes@359
   850
                                SETC_t();
nkeynes@359
   851
                                }
nkeynes@359
   852
                                break;
nkeynes@359
   853
                            default:
nkeynes@359
   854
                                UNDEF();
nkeynes@359
   855
                                break;
nkeynes@359
   856
                        }
nkeynes@359
   857
                        break;
nkeynes@359
   858
                    case 0x5:
nkeynes@359
   859
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   860
                            case 0x0:
nkeynes@359
   861
                                { /* ROTR Rn */
nkeynes@359
   862
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   863
                                load_reg( R_EAX, Rn );
nkeynes@359
   864
                                ROR1_r32( R_EAX );
nkeynes@359
   865
                                store_reg( R_EAX, Rn );
nkeynes@359
   866
                                SETC_t();
nkeynes@359
   867
                                }
nkeynes@359
   868
                                break;
nkeynes@359
   869
                            case 0x1:
nkeynes@359
   870
                                { /* CMP/PL Rn */
nkeynes@359
   871
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   872
                                load_reg( R_EAX, Rn );
nkeynes@359
   873
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   874
                                SETG_t();
nkeynes@359
   875
                                }
nkeynes@359
   876
                                break;
nkeynes@359
   877
                            case 0x2:
nkeynes@359
   878
                                { /* ROTCR Rn */
nkeynes@359
   879
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   880
                                load_reg( R_EAX, Rn );
nkeynes@359
   881
                                LDC_t();
nkeynes@359
   882
                                RCR1_r32( R_EAX );
nkeynes@359
   883
                                store_reg( R_EAX, Rn );
nkeynes@359
   884
                                SETC_t();
nkeynes@359
   885
                                }
nkeynes@359
   886
                                break;
nkeynes@359
   887
                            default:
nkeynes@359
   888
                                UNDEF();
nkeynes@359
   889
                                break;
nkeynes@359
   890
                        }
nkeynes@359
   891
                        break;
nkeynes@359
   892
                    case 0x6:
nkeynes@359
   893
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   894
                            case 0x0:
nkeynes@359
   895
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
   896
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   897
                                load_reg( R_EAX, Rm );
nkeynes@359
   898
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   899
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   900
                                store_reg( R_EAX, Rm );
nkeynes@359
   901
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   902
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   903
                                }
nkeynes@359
   904
                                break;
nkeynes@359
   905
                            case 0x1:
nkeynes@359
   906
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
   907
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   908
                                load_reg( R_EAX, Rm );
nkeynes@359
   909
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   910
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   911
                                store_reg( R_EAX, Rm );
nkeynes@359
   912
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   913
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
   914
                                }
nkeynes@359
   915
                                break;
nkeynes@359
   916
                            case 0x2:
nkeynes@359
   917
                                { /* LDS.L @Rm+, PR */
nkeynes@359
   918
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   919
                                load_reg( R_EAX, Rm );
nkeynes@359
   920
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   921
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   922
                                store_reg( R_EAX, Rm );
nkeynes@359
   923
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   924
                                store_spreg( R_EAX, R_PR );
nkeynes@359
   925
                                }
nkeynes@359
   926
                                break;
nkeynes@359
   927
                            case 0x3:
nkeynes@359
   928
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
   929
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   930
                                load_reg( R_EAX, Rm );
nkeynes@359
   931
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   932
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   933
                                store_reg( R_EAX, Rm );
nkeynes@359
   934
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   935
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
   936
                                }
nkeynes@359
   937
                                break;
nkeynes@359
   938
                            case 0x5:
nkeynes@359
   939
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
   940
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   941
                                load_reg( R_EAX, Rm );
nkeynes@359
   942
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   943
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   944
                                store_reg( R_EAX, Rm );
nkeynes@359
   945
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   946
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
   947
                                }
nkeynes@359
   948
                                break;
nkeynes@359
   949
                            case 0x6:
nkeynes@359
   950
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
   951
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   952
                                load_reg( R_EAX, Rm );
nkeynes@359
   953
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   954
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   955
                                store_reg( R_EAX, Rm );
nkeynes@359
   956
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   957
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
   958
                                }
nkeynes@359
   959
                                break;
nkeynes@359
   960
                            case 0xF:
nkeynes@359
   961
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
   962
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   963
                                load_reg( R_EAX, Rm );
nkeynes@359
   964
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   965
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   966
                                store_reg( R_EAX, Rm );
nkeynes@359
   967
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   968
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
   969
                                }
nkeynes@359
   970
                                break;
nkeynes@359
   971
                            default:
nkeynes@359
   972
                                UNDEF();
nkeynes@359
   973
                                break;
nkeynes@359
   974
                        }
nkeynes@359
   975
                        break;
nkeynes@359
   976
                    case 0x7:
nkeynes@359
   977
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   978
                            case 0x0:
nkeynes@359
   979
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   980
                                    case 0x0:
nkeynes@359
   981
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
   982
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   983
                                        }
nkeynes@359
   984
                                        break;
nkeynes@359
   985
                                    case 0x1:
nkeynes@359
   986
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
   987
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   988
                                        load_reg( R_EAX, Rm );
nkeynes@359
   989
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   990
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
   991
                                        store_reg( R_EAX, Rm );
nkeynes@359
   992
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
   993
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
   994
                                        }
nkeynes@359
   995
                                        break;
nkeynes@359
   996
                                    case 0x2:
nkeynes@359
   997
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
   998
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
   999
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1000
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1001
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1002
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1003
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1004
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1005
                                        }
nkeynes@359
  1006
                                        break;
nkeynes@359
  1007
                                    case 0x3:
nkeynes@359
  1008
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1009
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1010
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1011
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1012
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1013
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1014
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1015
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1016
                                        }
nkeynes@359
  1017
                                        break;
nkeynes@359
  1018
                                    case 0x4:
nkeynes@359
  1019
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1020
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1021
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1022
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1023
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1024
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1025
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1026
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1027
                                        }
nkeynes@359
  1028
                                        break;
nkeynes@359
  1029
                                    default:
nkeynes@359
  1030
                                        UNDEF();
nkeynes@359
  1031
                                        break;
nkeynes@359
  1032
                                }
nkeynes@359
  1033
                                break;
nkeynes@359
  1034
                            case 0x1:
nkeynes@359
  1035
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1036
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1037
                                }
nkeynes@359
  1038
                                break;
nkeynes@359
  1039
                        }
nkeynes@359
  1040
                        break;
nkeynes@359
  1041
                    case 0x8:
nkeynes@359
  1042
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1043
                            case 0x0:
nkeynes@359
  1044
                                { /* SHLL2 Rn */
nkeynes@359
  1045
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1046
                                load_reg( R_EAX, Rn );
nkeynes@359
  1047
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1048
                                store_reg( R_EAX, Rn );
nkeynes@359
  1049
                                }
nkeynes@359
  1050
                                break;
nkeynes@359
  1051
                            case 0x1:
nkeynes@359
  1052
                                { /* SHLL8 Rn */
nkeynes@359
  1053
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1054
                                load_reg( R_EAX, Rn );
nkeynes@359
  1055
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1056
                                store_reg( R_EAX, Rn );
nkeynes@359
  1057
                                }
nkeynes@359
  1058
                                break;
nkeynes@359
  1059
                            case 0x2:
nkeynes@359
  1060
                                { /* SHLL16 Rn */
nkeynes@359
  1061
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1062
                                load_reg( R_EAX, Rn );
nkeynes@359
  1063
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1064
                                store_reg( R_EAX, Rn );
nkeynes@359
  1065
                                }
nkeynes@359
  1066
                                break;
nkeynes@359
  1067
                            default:
nkeynes@359
  1068
                                UNDEF();
nkeynes@359
  1069
                                break;
nkeynes@359
  1070
                        }
nkeynes@359
  1071
                        break;
nkeynes@359
  1072
                    case 0x9:
nkeynes@359
  1073
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1074
                            case 0x0:
nkeynes@359
  1075
                                { /* SHLR2 Rn */
nkeynes@359
  1076
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1077
                                load_reg( R_EAX, Rn );
nkeynes@359
  1078
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1079
                                store_reg( R_EAX, Rn );
nkeynes@359
  1080
                                }
nkeynes@359
  1081
                                break;
nkeynes@359
  1082
                            case 0x1:
nkeynes@359
  1083
                                { /* SHLR8 Rn */
nkeynes@359
  1084
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1085
                                load_reg( R_EAX, Rn );
nkeynes@359
  1086
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1087
                                store_reg( R_EAX, Rn );
nkeynes@359
  1088
                                }
nkeynes@359
  1089
                                break;
nkeynes@359
  1090
                            case 0x2:
nkeynes@359
  1091
                                { /* SHLR16 Rn */
nkeynes@359
  1092
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1093
                                load_reg( R_EAX, Rn );
nkeynes@359
  1094
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1095
                                store_reg( R_EAX, Rn );
nkeynes@359
  1096
                                }
nkeynes@359
  1097
                                break;
nkeynes@359
  1098
                            default:
nkeynes@359
  1099
                                UNDEF();
nkeynes@359
  1100
                                break;
nkeynes@359
  1101
                        }
nkeynes@359
  1102
                        break;
nkeynes@359
  1103
                    case 0xA:
nkeynes@359
  1104
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1105
                            case 0x0:
nkeynes@359
  1106
                                { /* LDS Rm, MACH */
nkeynes@359
  1107
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1108
                                load_reg( R_EAX, Rm );
nkeynes@359
  1109
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1110
                                }
nkeynes@359
  1111
                                break;
nkeynes@359
  1112
                            case 0x1:
nkeynes@359
  1113
                                { /* LDS Rm, MACL */
nkeynes@359
  1114
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1115
                                load_reg( R_EAX, Rm );
nkeynes@359
  1116
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1117
                                }
nkeynes@359
  1118
                                break;
nkeynes@359
  1119
                            case 0x2:
nkeynes@359
  1120
                                { /* LDS Rm, PR */
nkeynes@359
  1121
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1122
                                load_reg( R_EAX, Rm );
nkeynes@359
  1123
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1124
                                }
nkeynes@359
  1125
                                break;
nkeynes@359
  1126
                            case 0x3:
nkeynes@359
  1127
                                { /* LDC Rm, SGR */
nkeynes@359
  1128
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1129
                                load_reg( R_EAX, Rm );
nkeynes@359
  1130
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1131
                                }
nkeynes@359
  1132
                                break;
nkeynes@359
  1133
                            case 0x5:
nkeynes@359
  1134
                                { /* LDS Rm, FPUL */
nkeynes@359
  1135
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1136
                                load_reg( R_EAX, Rm );
nkeynes@359
  1137
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1138
                                }
nkeynes@359
  1139
                                break;
nkeynes@359
  1140
                            case 0x6:
nkeynes@359
  1141
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1142
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1143
                                load_reg( R_EAX, Rm );
nkeynes@359
  1144
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1145
                                }
nkeynes@359
  1146
                                break;
nkeynes@359
  1147
                            case 0xF:
nkeynes@359
  1148
                                { /* LDC Rm, DBR */
nkeynes@359
  1149
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1150
                                load_reg( R_EAX, Rm );
nkeynes@359
  1151
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1152
                                }
nkeynes@359
  1153
                                break;
nkeynes@359
  1154
                            default:
nkeynes@359
  1155
                                UNDEF();
nkeynes@359
  1156
                                break;
nkeynes@359
  1157
                        }
nkeynes@359
  1158
                        break;
nkeynes@359
  1159
                    case 0xB:
nkeynes@359
  1160
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1161
                            case 0x0:
nkeynes@359
  1162
                                { /* JSR @Rn */
nkeynes@359
  1163
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1164
                                }
nkeynes@359
  1165
                                break;
nkeynes@359
  1166
                            case 0x1:
nkeynes@359
  1167
                                { /* TAS.B @Rn */
nkeynes@359
  1168
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1169
                                }
nkeynes@359
  1170
                                break;
nkeynes@359
  1171
                            case 0x2:
nkeynes@359
  1172
                                { /* JMP @Rn */
nkeynes@359
  1173
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1174
                                }
nkeynes@359
  1175
                                break;
nkeynes@359
  1176
                            default:
nkeynes@359
  1177
                                UNDEF();
nkeynes@359
  1178
                                break;
nkeynes@359
  1179
                        }
nkeynes@359
  1180
                        break;
nkeynes@359
  1181
                    case 0xC:
nkeynes@359
  1182
                        { /* SHAD Rm, Rn */
nkeynes@359
  1183
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1184
                        /* Annoyingly enough, not directly convertible */
nkeynes@359
  1185
                        }
nkeynes@359
  1186
                        break;
nkeynes@359
  1187
                    case 0xD:
nkeynes@359
  1188
                        { /* SHLD Rm, Rn */
nkeynes@359
  1189
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1190
                        }
nkeynes@359
  1191
                        break;
nkeynes@359
  1192
                    case 0xE:
nkeynes@359
  1193
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1194
                            case 0x0:
nkeynes@359
  1195
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1196
                                    case 0x0:
nkeynes@359
  1197
                                        { /* LDC Rm, SR */
nkeynes@359
  1198
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1199
                                        /* We need to be a little careful about SR */
nkeynes@359
  1200
                                        }
nkeynes@359
  1201
                                        break;
nkeynes@359
  1202
                                    case 0x1:
nkeynes@359
  1203
                                        { /* LDC Rm, GBR */
nkeynes@359
  1204
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1205
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1206
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1207
                                        }
nkeynes@359
  1208
                                        break;
nkeynes@359
  1209
                                    case 0x2:
nkeynes@359
  1210
                                        { /* LDC Rm, VBR */
nkeynes@359
  1211
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1212
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1213
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1214
                                        }
nkeynes@359
  1215
                                        break;
nkeynes@359
  1216
                                    case 0x3:
nkeynes@359
  1217
                                        { /* LDC Rm, SSR */
nkeynes@359
  1218
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1219
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1220
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1221
                                        }
nkeynes@359
  1222
                                        break;
nkeynes@359
  1223
                                    case 0x4:
nkeynes@359
  1224
                                        { /* LDC Rm, SPC */
nkeynes@359
  1225
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1226
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1227
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1228
                                        }
nkeynes@359
  1229
                                        break;
nkeynes@359
  1230
                                    default:
nkeynes@359
  1231
                                        UNDEF();
nkeynes@359
  1232
                                        break;
nkeynes@359
  1233
                                }
nkeynes@359
  1234
                                break;
nkeynes@359
  1235
                            case 0x1:
nkeynes@359
  1236
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1237
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1238
                                }
nkeynes@359
  1239
                                break;
nkeynes@359
  1240
                        }
nkeynes@359
  1241
                        break;
nkeynes@359
  1242
                    case 0xF:
nkeynes@359
  1243
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1244
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1245
                        }
nkeynes@359
  1246
                        break;
nkeynes@359
  1247
                }
nkeynes@359
  1248
                break;
nkeynes@359
  1249
            case 0x5:
nkeynes@359
  1250
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1251
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@359
  1252
                }
nkeynes@359
  1253
                break;
nkeynes@359
  1254
            case 0x6:
nkeynes@359
  1255
                switch( ir&0xF ) {
nkeynes@359
  1256
                    case 0x0:
nkeynes@359
  1257
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1258
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1259
                        load_reg( R_ECX, Rm );
nkeynes@359
  1260
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1261
                        store_reg( R_ECX, Rn );
nkeynes@359
  1262
                        }
nkeynes@359
  1263
                        break;
nkeynes@359
  1264
                    case 0x1:
nkeynes@359
  1265
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1266
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1267
                        }
nkeynes@359
  1268
                        break;
nkeynes@359
  1269
                    case 0x2:
nkeynes@359
  1270
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1271
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1272
                        }
nkeynes@359
  1273
                        break;
nkeynes@359
  1274
                    case 0x3:
nkeynes@359
  1275
                        { /* MOV Rm, Rn */
nkeynes@359
  1276
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1277
                        load_reg( R_EAX, Rm );
nkeynes@359
  1278
                        store_reg( R_EAX, Rn );
nkeynes@359
  1279
                        }
nkeynes@359
  1280
                        break;
nkeynes@359
  1281
                    case 0x4:
nkeynes@359
  1282
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1283
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1284
                        load_reg( R_ECX, Rm );
nkeynes@359
  1285
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1286
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1287
                        store_reg( R_EAX, Rm );
nkeynes@359
  1288
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1289
                        store_reg( R_EAX, Rn );
nkeynes@359
  1290
                        }
nkeynes@359
  1291
                        break;
nkeynes@359
  1292
                    case 0x5:
nkeynes@359
  1293
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1294
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1295
                        }
nkeynes@359
  1296
                        break;
nkeynes@359
  1297
                    case 0x6:
nkeynes@359
  1298
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1299
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1300
                        }
nkeynes@359
  1301
                        break;
nkeynes@359
  1302
                    case 0x7:
nkeynes@359
  1303
                        { /* NOT Rm, Rn */
nkeynes@359
  1304
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1305
                        load_reg( R_EAX, Rm );
nkeynes@359
  1306
                        NOT_r32( R_EAX );
nkeynes@359
  1307
                        store_reg( R_EAX, Rn );
nkeynes@359
  1308
                        }
nkeynes@359
  1309
                        break;
nkeynes@359
  1310
                    case 0x8:
nkeynes@359
  1311
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1312
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1313
                        load_reg( R_EAX, Rm );
nkeynes@359
  1314
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1315
                        store_reg( R_EAX, Rn );
nkeynes@359
  1316
                        }
nkeynes@359
  1317
                        break;
nkeynes@359
  1318
                    case 0x9:
nkeynes@359
  1319
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1320
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1321
                        load_reg( R_EAX, Rm );
nkeynes@359
  1322
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1323
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1324
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1325
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1326
                        store_reg( R_ECX, Rn );
nkeynes@359
  1327
                        }
nkeynes@359
  1328
                        break;
nkeynes@359
  1329
                    case 0xA:
nkeynes@359
  1330
                        { /* NEGC Rm, Rn */
nkeynes@359
  1331
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1332
                        load_reg( R_EAX, Rm );
nkeynes@359
  1333
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1334
                        LDC_t();
nkeynes@359
  1335
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1336
                        store_reg( R_ECX, Rn );
nkeynes@359
  1337
                        SETC_t();
nkeynes@359
  1338
                        }
nkeynes@359
  1339
                        break;
nkeynes@359
  1340
                    case 0xB:
nkeynes@359
  1341
                        { /* NEG Rm, Rn */
nkeynes@359
  1342
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1343
                        load_reg( R_EAX, Rm );
nkeynes@359
  1344
                        NEG_r32( R_EAX );
nkeynes@359
  1345
                        store_reg( R_EAX, Rn );
nkeynes@359
  1346
                        }
nkeynes@359
  1347
                        break;
nkeynes@359
  1348
                    case 0xC:
nkeynes@359
  1349
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1350
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1351
                        }
nkeynes@359
  1352
                        break;
nkeynes@359
  1353
                    case 0xD:
nkeynes@359
  1354
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1355
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1356
                        }
nkeynes@359
  1357
                        break;
nkeynes@359
  1358
                    case 0xE:
nkeynes@359
  1359
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1360
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1361
                        load_reg( R_EAX, Rm );
nkeynes@359
  1362
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1363
                        store_reg( R_EAX, Rn );
nkeynes@359
  1364
                        }
nkeynes@359
  1365
                        break;
nkeynes@359
  1366
                    case 0xF:
nkeynes@359
  1367
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1368
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1369
                        }
nkeynes@359
  1370
                        break;
nkeynes@359
  1371
                }
nkeynes@359
  1372
                break;
nkeynes@359
  1373
            case 0x7:
nkeynes@359
  1374
                { /* ADD #imm, Rn */
nkeynes@359
  1375
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1376
                load_reg( R_EAX, Rn );
nkeynes@359
  1377
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  1378
                store_reg( R_EAX, Rn );
nkeynes@359
  1379
                }
nkeynes@359
  1380
                break;
nkeynes@359
  1381
            case 0x8:
nkeynes@359
  1382
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1383
                    case 0x0:
nkeynes@359
  1384
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  1385
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1386
                        load_reg( R_EAX, 0 );
nkeynes@359
  1387
                        load_reg( R_ECX, Rn );
nkeynes@359
  1388
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1389
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1390
                        }
nkeynes@359
  1391
                        break;
nkeynes@359
  1392
                    case 0x1:
nkeynes@359
  1393
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  1394
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@359
  1395
                        }
nkeynes@359
  1396
                        break;
nkeynes@359
  1397
                    case 0x4:
nkeynes@359
  1398
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  1399
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1400
                        load_reg( R_ECX, Rm );
nkeynes@359
  1401
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1402
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1403
                        store_reg( R_EAX, 0 );
nkeynes@359
  1404
                        }
nkeynes@359
  1405
                        break;
nkeynes@359
  1406
                    case 0x5:
nkeynes@359
  1407
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  1408
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@359
  1409
                        }
nkeynes@359
  1410
                        break;
nkeynes@359
  1411
                    case 0x8:
nkeynes@359
  1412
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  1413
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1414
                        load_reg( R_EAX, 0 );
nkeynes@359
  1415
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  1416
                        SETE_t();
nkeynes@359
  1417
                        }
nkeynes@359
  1418
                        break;
nkeynes@359
  1419
                    case 0x9:
nkeynes@359
  1420
                        { /* BT disp */
nkeynes@359
  1421
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1422
                        /* If true, result PC += 4 + disp. else result PC = pc+2 */
nkeynes@359
  1423
                          return pc + 2;
nkeynes@359
  1424
                        }
nkeynes@359
  1425
                        break;
nkeynes@359
  1426
                    case 0xB:
nkeynes@359
  1427
                        { /* BF disp */
nkeynes@359
  1428
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1429
                        }
nkeynes@359
  1430
                        break;
nkeynes@359
  1431
                    case 0xD:
nkeynes@359
  1432
                        { /* BT/S disp */
nkeynes@359
  1433
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1434
                        return pc + 4;
nkeynes@359
  1435
                        }
nkeynes@359
  1436
                        break;
nkeynes@359
  1437
                    case 0xF:
nkeynes@359
  1438
                        { /* BF/S disp */
nkeynes@359
  1439
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1440
                        }
nkeynes@359
  1441
                        break;
nkeynes@359
  1442
                    default:
nkeynes@359
  1443
                        UNDEF();
nkeynes@359
  1444
                        break;
nkeynes@359
  1445
                }
nkeynes@359
  1446
                break;
nkeynes@359
  1447
            case 0x9:
nkeynes@359
  1448
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  1449
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@359
  1450
                }
nkeynes@359
  1451
                break;
nkeynes@359
  1452
            case 0xA:
nkeynes@359
  1453
                { /* BRA disp */
nkeynes@359
  1454
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@359
  1455
                }
nkeynes@359
  1456
                break;
nkeynes@359
  1457
            case 0xB:
nkeynes@359
  1458
                { /* BSR disp */
nkeynes@359
  1459
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@359
  1460
                }
nkeynes@359
  1461
                break;
nkeynes@359
  1462
            case 0xC:
nkeynes@359
  1463
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1464
                    case 0x0:
nkeynes@359
  1465
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  1466
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1467
                        load_reg( R_EAX, 0 );
nkeynes@359
  1468
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1469
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1470
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1471
                        }
nkeynes@359
  1472
                        break;
nkeynes@359
  1473
                    case 0x1:
nkeynes@359
  1474
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  1475
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@359
  1476
                        }
nkeynes@359
  1477
                        break;
nkeynes@359
  1478
                    case 0x2:
nkeynes@359
  1479
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  1480
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@359
  1481
                        }
nkeynes@359
  1482
                        break;
nkeynes@359
  1483
                    case 0x3:
nkeynes@359
  1484
                        { /* TRAPA #imm */
nkeynes@359
  1485
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1486
                        }
nkeynes@359
  1487
                        break;
nkeynes@359
  1488
                    case 0x4:
nkeynes@359
  1489
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  1490
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1491
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1492
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1493
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1494
                        store_reg( R_EAX, 0 );
nkeynes@359
  1495
                        }
nkeynes@359
  1496
                        break;
nkeynes@359
  1497
                    case 0x5:
nkeynes@359
  1498
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  1499
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@359
  1500
                        }
nkeynes@359
  1501
                        break;
nkeynes@359
  1502
                    case 0x6:
nkeynes@359
  1503
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  1504
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@359
  1505
                        }
nkeynes@359
  1506
                        break;
nkeynes@359
  1507
                    case 0x7:
nkeynes@359
  1508
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  1509
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@359
  1510
                        }
nkeynes@359
  1511
                        break;
nkeynes@359
  1512
                    case 0x8:
nkeynes@359
  1513
                        { /* TST #imm, R0 */
nkeynes@359
  1514
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1515
                        }
nkeynes@359
  1516
                        break;
nkeynes@359
  1517
                    case 0x9:
nkeynes@359
  1518
                        { /* AND #imm, R0 */
nkeynes@359
  1519
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1520
                        // Note: x86 AND imm8 sign-extends, SH4 version zero-extends. So 
nkeynes@359
  1521
                        // need to use the imm32 version
nkeynes@359
  1522
                        load_reg( R_EAX, 0 );
nkeynes@359
  1523
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  1524
                        store_reg( R_EAX, 0 );
nkeynes@359
  1525
                        }
nkeynes@359
  1526
                        break;
nkeynes@359
  1527
                    case 0xA:
nkeynes@359
  1528
                        { /* XOR #imm, R0 */
nkeynes@359
  1529
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1530
                        load_reg( R_EAX, 0 );
nkeynes@359
  1531
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1532
                        store_reg( R_EAX, 0 );
nkeynes@359
  1533
                        }
nkeynes@359
  1534
                        break;
nkeynes@359
  1535
                    case 0xB:
nkeynes@359
  1536
                        { /* OR #imm, R0 */
nkeynes@359
  1537
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1538
                        load_reg( R_EAX, 0 );
nkeynes@359
  1539
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  1540
                        store_reg( R_EAX, 0 );
nkeynes@359
  1541
                        }
nkeynes@359
  1542
                        break;
nkeynes@359
  1543
                    case 0xC:
nkeynes@359
  1544
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  1545
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1546
                        }
nkeynes@359
  1547
                        break;
nkeynes@359
  1548
                    case 0xD:
nkeynes@359
  1549
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  1550
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1551
                        load_reg( R_EAX, 0 );
nkeynes@359
  1552
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1553
                        ADD_r32_r32( R_EAX, R_EBX );
nkeynes@359
  1554
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1555
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  1556
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1557
                        }
nkeynes@359
  1558
                        break;
nkeynes@359
  1559
                    case 0xE:
nkeynes@359
  1560
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  1561
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1562
                        load_reg( R_EAX, 0 );
nkeynes@359
  1563
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1564
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1565
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1566
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1567
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1568
                        }
nkeynes@359
  1569
                        break;
nkeynes@359
  1570
                    case 0xF:
nkeynes@359
  1571
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  1572
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1573
                        }
nkeynes@359
  1574
                        break;
nkeynes@359
  1575
                }
nkeynes@359
  1576
                break;
nkeynes@359
  1577
            case 0xD:
nkeynes@359
  1578
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  1579
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@359
  1580
                }
nkeynes@359
  1581
                break;
nkeynes@359
  1582
            case 0xE:
nkeynes@359
  1583
                { /* MOV #imm, Rn */
nkeynes@359
  1584
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1585
                load_imm32( R_EAX, imm );
nkeynes@359
  1586
                store_reg( R_EAX, Rn );
nkeynes@359
  1587
                }
nkeynes@359
  1588
                break;
nkeynes@359
  1589
            case 0xF:
nkeynes@359
  1590
                switch( ir&0xF ) {
nkeynes@359
  1591
                    case 0x0:
nkeynes@359
  1592
                        { /* FADD FRm, FRn */
nkeynes@359
  1593
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1594
                        }
nkeynes@359
  1595
                        break;
nkeynes@359
  1596
                    case 0x1:
nkeynes@359
  1597
                        { /* FSUB FRm, FRn */
nkeynes@359
  1598
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1599
                        }
nkeynes@359
  1600
                        break;
nkeynes@359
  1601
                    case 0x2:
nkeynes@359
  1602
                        { /* FMUL FRm, FRn */
nkeynes@359
  1603
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1604
                        }
nkeynes@359
  1605
                        break;
nkeynes@359
  1606
                    case 0x3:
nkeynes@359
  1607
                        { /* FDIV FRm, FRn */
nkeynes@359
  1608
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1609
                        }
nkeynes@359
  1610
                        break;
nkeynes@359
  1611
                    case 0x4:
nkeynes@359
  1612
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  1613
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1614
                        }
nkeynes@359
  1615
                        break;
nkeynes@359
  1616
                    case 0x5:
nkeynes@359
  1617
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  1618
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1619
                        }
nkeynes@359
  1620
                        break;
nkeynes@359
  1621
                    case 0x6:
nkeynes@359
  1622
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  1623
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1624
                        }
nkeynes@359
  1625
                        break;
nkeynes@359
  1626
                    case 0x7:
nkeynes@359
  1627
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@359
  1628
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1629
                        }
nkeynes@359
  1630
                        break;
nkeynes@359
  1631
                    case 0x8:
nkeynes@359
  1632
                        { /* FMOV @Rm, FRn */
nkeynes@359
  1633
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1634
                        }
nkeynes@359
  1635
                        break;
nkeynes@359
  1636
                    case 0x9:
nkeynes@359
  1637
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  1638
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1639
                        }
nkeynes@359
  1640
                        break;
nkeynes@359
  1641
                    case 0xA:
nkeynes@359
  1642
                        { /* FMOV FRm, @Rn */
nkeynes@359
  1643
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1644
                        }
nkeynes@359
  1645
                        break;
nkeynes@359
  1646
                    case 0xB:
nkeynes@359
  1647
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  1648
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1649
                        }
nkeynes@359
  1650
                        break;
nkeynes@359
  1651
                    case 0xC:
nkeynes@359
  1652
                        { /* FMOV FRm, FRn */
nkeynes@359
  1653
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1654
                        }
nkeynes@359
  1655
                        break;
nkeynes@359
  1656
                    case 0xD:
nkeynes@359
  1657
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1658
                            case 0x0:
nkeynes@359
  1659
                                { /* FSTS FPUL, FRn */
nkeynes@359
  1660
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1661
                                }
nkeynes@359
  1662
                                break;
nkeynes@359
  1663
                            case 0x1:
nkeynes@359
  1664
                                { /* FLDS FRm, FPUL */
nkeynes@359
  1665
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1666
                                }
nkeynes@359
  1667
                                break;
nkeynes@359
  1668
                            case 0x2:
nkeynes@359
  1669
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  1670
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1671
                                }
nkeynes@359
  1672
                                break;
nkeynes@359
  1673
                            case 0x3:
nkeynes@359
  1674
                                { /* FTRC FRm, FPUL */
nkeynes@359
  1675
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1676
                                }
nkeynes@359
  1677
                                break;
nkeynes@359
  1678
                            case 0x4:
nkeynes@359
  1679
                                { /* FNEG FRn */
nkeynes@359
  1680
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1681
                                }
nkeynes@359
  1682
                                break;
nkeynes@359
  1683
                            case 0x5:
nkeynes@359
  1684
                                { /* FABS FRn */
nkeynes@359
  1685
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1686
                                }
nkeynes@359
  1687
                                break;
nkeynes@359
  1688
                            case 0x6:
nkeynes@359
  1689
                                { /* FSQRT FRn */
nkeynes@359
  1690
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1691
                                }
nkeynes@359
  1692
                                break;
nkeynes@359
  1693
                            case 0x7:
nkeynes@359
  1694
                                { /* FSRRA FRn */
nkeynes@359
  1695
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1696
                                }
nkeynes@359
  1697
                                break;
nkeynes@359
  1698
                            case 0x8:
nkeynes@359
  1699
                                { /* FLDI0 FRn */
nkeynes@359
  1700
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1701
                                }
nkeynes@359
  1702
                                break;
nkeynes@359
  1703
                            case 0x9:
nkeynes@359
  1704
                                { /* FLDI1 FRn */
nkeynes@359
  1705
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1706
                                }
nkeynes@359
  1707
                                break;
nkeynes@359
  1708
                            case 0xA:
nkeynes@359
  1709
                                { /* FCNVSD FPUL, FRn */
nkeynes@359
  1710
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1711
                                }
nkeynes@359
  1712
                                break;
nkeynes@359
  1713
                            case 0xB:
nkeynes@359
  1714
                                { /* FCNVDS FRm, FPUL */
nkeynes@359
  1715
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1716
                                }
nkeynes@359
  1717
                                break;
nkeynes@359
  1718
                            case 0xE:
nkeynes@359
  1719
                                { /* FIPR FVm, FVn */
nkeynes@359
  1720
                                uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
nkeynes@359
  1721
                                }
nkeynes@359
  1722
                                break;
nkeynes@359
  1723
                            case 0xF:
nkeynes@359
  1724
                                switch( (ir&0x100) >> 8 ) {
nkeynes@359
  1725
                                    case 0x0:
nkeynes@359
  1726
                                        { /* FSCA FPUL, FRn */
nkeynes@359
  1727
                                        uint32_t FRn = ((ir>>9)&0x7)<<1; 
nkeynes@359
  1728
                                        }
nkeynes@359
  1729
                                        break;
nkeynes@359
  1730
                                    case 0x1:
nkeynes@359
  1731
                                        switch( (ir&0x200) >> 9 ) {
nkeynes@359
  1732
                                            case 0x0:
nkeynes@359
  1733
                                                { /* FTRV XMTRX, FVn */
nkeynes@359
  1734
                                                uint32_t FVn = ((ir>>10)&0x3); 
nkeynes@359
  1735
                                                }
nkeynes@359
  1736
                                                break;
nkeynes@359
  1737
                                            case 0x1:
nkeynes@359
  1738
                                                switch( (ir&0xC00) >> 10 ) {
nkeynes@359
  1739
                                                    case 0x0:
nkeynes@359
  1740
                                                        { /* FSCHG */
nkeynes@359
  1741
                                                        }
nkeynes@359
  1742
                                                        break;
nkeynes@359
  1743
                                                    case 0x2:
nkeynes@359
  1744
                                                        { /* FRCHG */
nkeynes@359
  1745
                                                        }
nkeynes@359
  1746
                                                        break;
nkeynes@359
  1747
                                                    case 0x3:
nkeynes@359
  1748
                                                        { /* UNDEF */
nkeynes@359
  1749
                                                        }
nkeynes@359
  1750
                                                        break;
nkeynes@359
  1751
                                                    default:
nkeynes@359
  1752
                                                        UNDEF();
nkeynes@359
  1753
                                                        break;
nkeynes@359
  1754
                                                }
nkeynes@359
  1755
                                                break;
nkeynes@359
  1756
                                        }
nkeynes@359
  1757
                                        break;
nkeynes@359
  1758
                                }
nkeynes@359
  1759
                                break;
nkeynes@359
  1760
                            default:
nkeynes@359
  1761
                                UNDEF();
nkeynes@359
  1762
                                break;
nkeynes@359
  1763
                        }
nkeynes@359
  1764
                        break;
nkeynes@359
  1765
                    case 0xE:
nkeynes@359
  1766
                        { /* FMAC FR0, FRm, FRn */
nkeynes@359
  1767
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1768
                        }
nkeynes@359
  1769
                        break;
nkeynes@359
  1770
                    default:
nkeynes@359
  1771
                        UNDEF();
nkeynes@359
  1772
                        break;
nkeynes@359
  1773
                }
nkeynes@359
  1774
                break;
nkeynes@359
  1775
        }
nkeynes@359
  1776
nkeynes@359
  1777
nkeynes@359
  1778
    return 0;
nkeynes@359
  1779
}
.