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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 941:c67574ed4355
prev939:6f2302afeb89
next946:d41ee7994db7
author nkeynes
date Sat Jan 03 08:55:15 2009 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Implement CORE_EXIT_EXCEPTION for use when direct frame messing about doesn't work
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "sh4/mmu.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            JMP_exc(EXC_SLOT_ILLEGAL); \
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        } else { \
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            JMP_exc(EXC_ILLEGAL ); \
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        } \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
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 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
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 */
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#ifdef HAVE_FRAME_ADDRESS
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#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
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        call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
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#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
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        call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
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#else 
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#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)
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#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
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#endif
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#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)
nkeynes@939
   311
#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
nkeynes@939
   312
#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
nkeynes@939
   313
#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
nkeynes@368
   314
nkeynes@937
   315
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   316
nkeynes@539
   317
/****** Import appropriate calling conventions ******/
nkeynes@675
   318
#if SIZEOF_VOID_P == 8
nkeynes@539
   319
#include "sh4/ia64abi.h"
nkeynes@675
   320
#else /* 32-bit system */
nkeynes@539
   321
#include "sh4/ia32abi.h"
nkeynes@539
   322
#endif
nkeynes@539
   323
nkeynes@901
   324
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   325
{
nkeynes@927
   326
    enter_block();
nkeynes@901
   327
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   328
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   329
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   330
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   331
    sh4_x86.block_start_pc = pc;
nkeynes@939
   332
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   334
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   335
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   336
}
nkeynes@901
   337
nkeynes@901
   338
nkeynes@593
   339
uint32_t sh4_translate_end_block_size()
nkeynes@593
   340
{
nkeynes@596
   341
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   342
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   343
    } else {
nkeynes@901
   344
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   345
    }
nkeynes@593
   346
}
nkeynes@593
   347
nkeynes@593
   348
nkeynes@590
   349
/**
nkeynes@590
   350
 * Embed a breakpoint into the generated code
nkeynes@590
   351
 */
nkeynes@586
   352
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   353
{
nkeynes@591
   354
    load_imm32( R_EAX, pc );
nkeynes@591
   355
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   356
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   357
}
nkeynes@590
   358
nkeynes@601
   359
nkeynes@601
   360
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   361
nkeynes@590
   362
/**
nkeynes@590
   363
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   364
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   365
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   366
 *
nkeynes@601
   367
 * Performs:
nkeynes@601
   368
 *   Set PC = endpc
nkeynes@601
   369
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   370
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   371
 *   Call sh4_execute_instruction
nkeynes@601
   372
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   373
 */
nkeynes@601
   374
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   375
{
nkeynes@590
   376
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   377
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   378
    
nkeynes@601
   379
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   380
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   381
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   382
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   383
nkeynes@590
   384
    call_func0( sh4_execute_instruction );    
nkeynes@601
   385
    load_spreg( R_EAX, R_PC );
nkeynes@590
   386
    if( sh4_x86.tlb_on ) {
nkeynes@590
   387
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   388
    } else {
nkeynes@590
   389
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   390
    }
nkeynes@926
   391
    exit_block();
nkeynes@590
   392
} 
nkeynes@539
   393
nkeynes@359
   394
/**
nkeynes@359
   395
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   396
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   397
 * 
nkeynes@586
   398
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   399
 *
nkeynes@359
   400
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   401
 * (eg a branch or 
nkeynes@359
   402
 */
nkeynes@590
   403
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   404
{
nkeynes@388
   405
    uint32_t ir;
nkeynes@586
   406
    /* Read instruction from icache */
nkeynes@586
   407
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   408
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   409
    
nkeynes@586
   410
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   411
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   412
    }
nkeynes@359
   413
%%
nkeynes@359
   414
/* ALU operations */
nkeynes@359
   415
ADD Rm, Rn {:
nkeynes@671
   416
    COUNT_INST(I_ADD);
nkeynes@359
   417
    load_reg( R_EAX, Rm );
nkeynes@359
   418
    load_reg( R_ECX, Rn );
nkeynes@359
   419
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   420
    store_reg( R_ECX, Rn );
nkeynes@417
   421
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   422
:}
nkeynes@359
   423
ADD #imm, Rn {:  
nkeynes@671
   424
    COUNT_INST(I_ADDI);
nkeynes@939
   425
    ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   427
:}
nkeynes@359
   428
ADDC Rm, Rn {:
nkeynes@671
   429
    COUNT_INST(I_ADDC);
nkeynes@417
   430
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   431
        LDC_t();
nkeynes@417
   432
    }
nkeynes@359
   433
    load_reg( R_EAX, Rm );
nkeynes@359
   434
    load_reg( R_ECX, Rn );
nkeynes@359
   435
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   436
    store_reg( R_ECX, Rn );
nkeynes@359
   437
    SETC_t();
nkeynes@417
   438
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   439
:}
nkeynes@359
   440
ADDV Rm, Rn {:
nkeynes@671
   441
    COUNT_INST(I_ADDV);
nkeynes@359
   442
    load_reg( R_EAX, Rm );
nkeynes@359
   443
    load_reg( R_ECX, Rn );
nkeynes@359
   444
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   445
    store_reg( R_ECX, Rn );
nkeynes@359
   446
    SETO_t();
nkeynes@417
   447
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   448
:}
nkeynes@359
   449
AND Rm, Rn {:
nkeynes@671
   450
    COUNT_INST(I_AND);
nkeynes@359
   451
    load_reg( R_EAX, Rm );
nkeynes@359
   452
    load_reg( R_ECX, Rn );
nkeynes@359
   453
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   454
    store_reg( R_ECX, Rn );
nkeynes@417
   455
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   456
:}
nkeynes@359
   457
AND #imm, R0 {:  
nkeynes@671
   458
    COUNT_INST(I_ANDI);
nkeynes@359
   459
    load_reg( R_EAX, 0 );
nkeynes@359
   460
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   461
    store_reg( R_EAX, 0 );
nkeynes@417
   462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   463
:}
nkeynes@359
   464
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   465
    COUNT_INST(I_ANDB);
nkeynes@359
   466
    load_reg( R_EAX, 0 );
nkeynes@939
   467
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
   468
    MOV_r32_esp8(R_EAX, 0);
nkeynes@930
   469
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@930
   470
    MOV_esp8_r32(0, R_EAX);
nkeynes@905
   471
    AND_imm32_r32(imm, R_EDX );
nkeynes@930
   472
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   473
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   474
:}
nkeynes@359
   475
CMP/EQ Rm, Rn {:  
nkeynes@671
   476
    COUNT_INST(I_CMPEQ);
nkeynes@359
   477
    load_reg( R_EAX, Rm );
nkeynes@359
   478
    load_reg( R_ECX, Rn );
nkeynes@359
   479
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   480
    SETE_t();
nkeynes@417
   481
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   482
:}
nkeynes@359
   483
CMP/EQ #imm, R0 {:  
nkeynes@671
   484
    COUNT_INST(I_CMPEQI);
nkeynes@359
   485
    load_reg( R_EAX, 0 );
nkeynes@359
   486
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   487
    SETE_t();
nkeynes@417
   488
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   489
:}
nkeynes@359
   490
CMP/GE Rm, Rn {:  
nkeynes@671
   491
    COUNT_INST(I_CMPGE);
nkeynes@359
   492
    load_reg( R_EAX, Rm );
nkeynes@359
   493
    load_reg( R_ECX, Rn );
nkeynes@359
   494
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   495
    SETGE_t();
nkeynes@417
   496
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   497
:}
nkeynes@359
   498
CMP/GT Rm, Rn {: 
nkeynes@671
   499
    COUNT_INST(I_CMPGT);
nkeynes@359
   500
    load_reg( R_EAX, Rm );
nkeynes@359
   501
    load_reg( R_ECX, Rn );
nkeynes@359
   502
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   503
    SETG_t();
nkeynes@417
   504
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   505
:}
nkeynes@359
   506
CMP/HI Rm, Rn {:  
nkeynes@671
   507
    COUNT_INST(I_CMPHI);
nkeynes@359
   508
    load_reg( R_EAX, Rm );
nkeynes@359
   509
    load_reg( R_ECX, Rn );
nkeynes@359
   510
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   511
    SETA_t();
nkeynes@417
   512
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   513
:}
nkeynes@359
   514
CMP/HS Rm, Rn {: 
nkeynes@671
   515
    COUNT_INST(I_CMPHS);
nkeynes@359
   516
    load_reg( R_EAX, Rm );
nkeynes@359
   517
    load_reg( R_ECX, Rn );
nkeynes@359
   518
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   519
    SETAE_t();
nkeynes@417
   520
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   521
 :}
nkeynes@359
   522
CMP/PL Rn {: 
nkeynes@671
   523
    COUNT_INST(I_CMPPL);
nkeynes@359
   524
    load_reg( R_EAX, Rn );
nkeynes@359
   525
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   526
    SETG_t();
nkeynes@417
   527
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   528
:}
nkeynes@359
   529
CMP/PZ Rn {:  
nkeynes@671
   530
    COUNT_INST(I_CMPPZ);
nkeynes@359
   531
    load_reg( R_EAX, Rn );
nkeynes@359
   532
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   533
    SETGE_t();
nkeynes@417
   534
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   535
:}
nkeynes@361
   536
CMP/STR Rm, Rn {:  
nkeynes@671
   537
    COUNT_INST(I_CMPSTR);
nkeynes@368
   538
    load_reg( R_EAX, Rm );
nkeynes@368
   539
    load_reg( R_ECX, Rn );
nkeynes@368
   540
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   541
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   542
    JE_rel8(target1);
nkeynes@669
   543
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   544
    JE_rel8(target2);
nkeynes@669
   545
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   546
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   547
    JE_rel8(target3);
nkeynes@669
   548
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   549
    JMP_TARGET(target1);
nkeynes@380
   550
    JMP_TARGET(target2);
nkeynes@380
   551
    JMP_TARGET(target3);
nkeynes@368
   552
    SETE_t();
nkeynes@417
   553
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   554
:}
nkeynes@361
   555
DIV0S Rm, Rn {:
nkeynes@671
   556
    COUNT_INST(I_DIV0S);
nkeynes@361
   557
    load_reg( R_EAX, Rm );
nkeynes@386
   558
    load_reg( R_ECX, Rn );
nkeynes@361
   559
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   560
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   561
    store_spreg( R_EAX, R_M );
nkeynes@361
   562
    store_spreg( R_ECX, R_Q );
nkeynes@361
   563
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   564
    SETNE_t();
nkeynes@417
   565
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   566
:}
nkeynes@361
   567
DIV0U {:  
nkeynes@671
   568
    COUNT_INST(I_DIV0U);
nkeynes@361
   569
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   570
    store_spreg( R_EAX, R_Q );
nkeynes@361
   571
    store_spreg( R_EAX, R_M );
nkeynes@361
   572
    store_spreg( R_EAX, R_T );
nkeynes@417
   573
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   574
:}
nkeynes@386
   575
DIV1 Rm, Rn {:
nkeynes@671
   576
    COUNT_INST(I_DIV1);
nkeynes@386
   577
    load_spreg( R_ECX, R_M );
nkeynes@386
   578
    load_reg( R_EAX, Rn );
nkeynes@417
   579
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   580
	LDC_t();
nkeynes@417
   581
    }
nkeynes@386
   582
    RCL1_r32( R_EAX );
nkeynes@386
   583
    SETC_r8( R_DL ); // Q'
nkeynes@386
   584
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   585
    JE_rel8(mqequal);
nkeynes@386
   586
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   587
    JMP_rel8(end);
nkeynes@380
   588
    JMP_TARGET(mqequal);
nkeynes@386
   589
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   590
    JMP_TARGET(end);
nkeynes@386
   591
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   592
    SETC_r8(R_AL); // tmp1
nkeynes@386
   593
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   594
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   595
    store_spreg( R_ECX, R_Q );
nkeynes@386
   596
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   597
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   598
    store_spreg( R_EAX, R_T );
nkeynes@417
   599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   600
:}
nkeynes@361
   601
DMULS.L Rm, Rn {:  
nkeynes@671
   602
    COUNT_INST(I_DMULS);
nkeynes@361
   603
    load_reg( R_EAX, Rm );
nkeynes@361
   604
    load_reg( R_ECX, Rn );
nkeynes@361
   605
    IMUL_r32(R_ECX);
nkeynes@361
   606
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   607
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   609
:}
nkeynes@361
   610
DMULU.L Rm, Rn {:  
nkeynes@671
   611
    COUNT_INST(I_DMULU);
nkeynes@361
   612
    load_reg( R_EAX, Rm );
nkeynes@361
   613
    load_reg( R_ECX, Rn );
nkeynes@361
   614
    MUL_r32(R_ECX);
nkeynes@361
   615
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   616
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   617
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   618
:}
nkeynes@359
   619
DT Rn {:  
nkeynes@671
   620
    COUNT_INST(I_DT);
nkeynes@359
   621
    load_reg( R_EAX, Rn );
nkeynes@382
   622
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   623
    store_reg( R_EAX, Rn );
nkeynes@359
   624
    SETE_t();
nkeynes@417
   625
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   626
:}
nkeynes@359
   627
EXTS.B Rm, Rn {:  
nkeynes@671
   628
    COUNT_INST(I_EXTSB);
nkeynes@359
   629
    load_reg( R_EAX, Rm );
nkeynes@359
   630
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   631
    store_reg( R_EAX, Rn );
nkeynes@359
   632
:}
nkeynes@361
   633
EXTS.W Rm, Rn {:  
nkeynes@671
   634
    COUNT_INST(I_EXTSW);
nkeynes@361
   635
    load_reg( R_EAX, Rm );
nkeynes@361
   636
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   637
    store_reg( R_EAX, Rn );
nkeynes@361
   638
:}
nkeynes@361
   639
EXTU.B Rm, Rn {:  
nkeynes@671
   640
    COUNT_INST(I_EXTUB);
nkeynes@361
   641
    load_reg( R_EAX, Rm );
nkeynes@361
   642
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   643
    store_reg( R_EAX, Rn );
nkeynes@361
   644
:}
nkeynes@361
   645
EXTU.W Rm, Rn {:  
nkeynes@671
   646
    COUNT_INST(I_EXTUW);
nkeynes@361
   647
    load_reg( R_EAX, Rm );
nkeynes@361
   648
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   649
    store_reg( R_EAX, Rn );
nkeynes@361
   650
:}
nkeynes@586
   651
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   652
    COUNT_INST(I_MACL);
nkeynes@586
   653
    if( Rm == Rn ) {
nkeynes@586
   654
	load_reg( R_EAX, Rm );
nkeynes@586
   655
	check_ralign32( R_EAX );
nkeynes@939
   656
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   657
	MOV_r32_esp8(R_EAX, 0);
nkeynes@939
   658
	load_reg( R_EAX, Rm );
nkeynes@939
   659
	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
   660
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
   661
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   662
    } else {
nkeynes@586
   663
	load_reg( R_EAX, Rm );
nkeynes@586
   664
	check_ralign32( R_EAX );
nkeynes@939
   665
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   666
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   667
	load_reg( R_EAX, Rn );
nkeynes@926
   668
	check_ralign32( R_EAX );
nkeynes@939
   669
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   670
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   671
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   672
    }
nkeynes@939
   673
    
nkeynes@939
   674
    IMUL_esp8( 0 );
nkeynes@386
   675
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   676
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   677
nkeynes@386
   678
    load_spreg( R_ECX, R_S );
nkeynes@386
   679
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   680
    JE_rel8( nosat );
nkeynes@386
   681
    call_func0( signsat48 );
nkeynes@386
   682
    JMP_TARGET( nosat );
nkeynes@417
   683
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   684
:}
nkeynes@386
   685
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   686
    COUNT_INST(I_MACW);
nkeynes@586
   687
    if( Rm == Rn ) {
nkeynes@586
   688
	load_reg( R_EAX, Rm );
nkeynes@586
   689
	check_ralign16( R_EAX );
nkeynes@939
   690
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   691
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@939
   692
	load_reg( R_EAX, Rm );
nkeynes@939
   693
	LEA_r32disp8_r32( R_EAX, 2, R_EAX );
nkeynes@939
   694
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   695
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   696
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   697
	// adding a page-boundary check to skip the second translation
nkeynes@586
   698
    } else {
nkeynes@586
   699
	load_reg( R_EAX, Rm );
nkeynes@586
   700
	check_ralign16( R_EAX );
nkeynes@939
   701
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   702
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   703
	load_reg( R_EAX, Rn );
nkeynes@926
   704
	check_ralign16( R_EAX );
nkeynes@939
   705
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   706
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   707
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   708
    }
nkeynes@939
   709
    IMUL_esp8( 0 );
nkeynes@386
   710
    load_spreg( R_ECX, R_S );
nkeynes@386
   711
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   712
    JE_rel8( nosat );
nkeynes@386
   713
nkeynes@386
   714
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   715
    JNO_rel8( end );            // 2
nkeynes@386
   716
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   717
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   718
    JS_rel8( positive );        // 2
nkeynes@386
   719
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   720
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   721
    JMP_rel8(end2);           // 2
nkeynes@386
   722
nkeynes@386
   723
    JMP_TARGET(positive);
nkeynes@386
   724
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   725
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   726
    JMP_rel8(end3);            // 2
nkeynes@386
   727
nkeynes@386
   728
    JMP_TARGET(nosat);
nkeynes@386
   729
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   730
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   731
    JMP_TARGET(end);
nkeynes@386
   732
    JMP_TARGET(end2);
nkeynes@386
   733
    JMP_TARGET(end3);
nkeynes@417
   734
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   735
:}
nkeynes@359
   736
MOVT Rn {:  
nkeynes@671
   737
    COUNT_INST(I_MOVT);
nkeynes@359
   738
    load_spreg( R_EAX, R_T );
nkeynes@359
   739
    store_reg( R_EAX, Rn );
nkeynes@359
   740
:}
nkeynes@361
   741
MUL.L Rm, Rn {:  
nkeynes@671
   742
    COUNT_INST(I_MULL);
nkeynes@361
   743
    load_reg( R_EAX, Rm );
nkeynes@361
   744
    load_reg( R_ECX, Rn );
nkeynes@361
   745
    MUL_r32( R_ECX );
nkeynes@361
   746
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   747
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   748
:}
nkeynes@374
   749
MULS.W Rm, Rn {:
nkeynes@671
   750
    COUNT_INST(I_MULSW);
nkeynes@374
   751
    load_reg16s( R_EAX, Rm );
nkeynes@374
   752
    load_reg16s( R_ECX, Rn );
nkeynes@374
   753
    MUL_r32( R_ECX );
nkeynes@374
   754
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   755
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   756
:}
nkeynes@374
   757
MULU.W Rm, Rn {:  
nkeynes@671
   758
    COUNT_INST(I_MULUW);
nkeynes@374
   759
    load_reg16u( R_EAX, Rm );
nkeynes@374
   760
    load_reg16u( R_ECX, Rn );
nkeynes@374
   761
    MUL_r32( R_ECX );
nkeynes@374
   762
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   764
:}
nkeynes@359
   765
NEG Rm, Rn {:
nkeynes@671
   766
    COUNT_INST(I_NEG);
nkeynes@359
   767
    load_reg( R_EAX, Rm );
nkeynes@359
   768
    NEG_r32( R_EAX );
nkeynes@359
   769
    store_reg( R_EAX, Rn );
nkeynes@417
   770
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   771
:}
nkeynes@359
   772
NEGC Rm, Rn {:  
nkeynes@671
   773
    COUNT_INST(I_NEGC);
nkeynes@359
   774
    load_reg( R_EAX, Rm );
nkeynes@359
   775
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   776
    LDC_t();
nkeynes@359
   777
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   778
    store_reg( R_ECX, Rn );
nkeynes@359
   779
    SETC_t();
nkeynes@417
   780
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   781
:}
nkeynes@359
   782
NOT Rm, Rn {:  
nkeynes@671
   783
    COUNT_INST(I_NOT);
nkeynes@359
   784
    load_reg( R_EAX, Rm );
nkeynes@359
   785
    NOT_r32( R_EAX );
nkeynes@359
   786
    store_reg( R_EAX, Rn );
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   788
:}
nkeynes@359
   789
OR Rm, Rn {:  
nkeynes@671
   790
    COUNT_INST(I_OR);
nkeynes@359
   791
    load_reg( R_EAX, Rm );
nkeynes@359
   792
    load_reg( R_ECX, Rn );
nkeynes@359
   793
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   794
    store_reg( R_ECX, Rn );
nkeynes@417
   795
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   796
:}
nkeynes@359
   797
OR #imm, R0 {:
nkeynes@671
   798
    COUNT_INST(I_ORI);
nkeynes@359
   799
    load_reg( R_EAX, 0 );
nkeynes@359
   800
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   801
    store_reg( R_EAX, 0 );
nkeynes@417
   802
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   803
:}
nkeynes@374
   804
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   805
    COUNT_INST(I_ORB);
nkeynes@374
   806
    load_reg( R_EAX, 0 );
nkeynes@939
   807
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
   808
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
   809
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@930
   810
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
   811
    OR_imm32_r32(imm, R_EDX );
nkeynes@930
   812
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   813
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   814
:}
nkeynes@359
   815
ROTCL Rn {:
nkeynes@671
   816
    COUNT_INST(I_ROTCL);
nkeynes@359
   817
    load_reg( R_EAX, Rn );
nkeynes@417
   818
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   819
	LDC_t();
nkeynes@417
   820
    }
nkeynes@359
   821
    RCL1_r32( R_EAX );
nkeynes@359
   822
    store_reg( R_EAX, Rn );
nkeynes@359
   823
    SETC_t();
nkeynes@417
   824
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   825
:}
nkeynes@359
   826
ROTCR Rn {:  
nkeynes@671
   827
    COUNT_INST(I_ROTCR);
nkeynes@359
   828
    load_reg( R_EAX, Rn );
nkeynes@417
   829
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   830
	LDC_t();
nkeynes@417
   831
    }
nkeynes@359
   832
    RCR1_r32( R_EAX );
nkeynes@359
   833
    store_reg( R_EAX, Rn );
nkeynes@359
   834
    SETC_t();
nkeynes@417
   835
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   836
:}
nkeynes@359
   837
ROTL Rn {:  
nkeynes@671
   838
    COUNT_INST(I_ROTL);
nkeynes@359
   839
    load_reg( R_EAX, Rn );
nkeynes@359
   840
    ROL1_r32( R_EAX );
nkeynes@359
   841
    store_reg( R_EAX, Rn );
nkeynes@359
   842
    SETC_t();
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   844
:}
nkeynes@359
   845
ROTR Rn {:  
nkeynes@671
   846
    COUNT_INST(I_ROTR);
nkeynes@359
   847
    load_reg( R_EAX, Rn );
nkeynes@359
   848
    ROR1_r32( R_EAX );
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@359
   850
    SETC_t();
nkeynes@417
   851
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   852
:}
nkeynes@359
   853
SHAD Rm, Rn {:
nkeynes@671
   854
    COUNT_INST(I_SHAD);
nkeynes@359
   855
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   856
    load_reg( R_EAX, Rn );
nkeynes@361
   857
    load_reg( R_ECX, Rm );
nkeynes@361
   858
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   859
    JGE_rel8(doshl);
nkeynes@361
   860
                    
nkeynes@361
   861
    NEG_r32( R_ECX );      // 2
nkeynes@361
   862
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   863
    JE_rel8(emptysar);     // 2
nkeynes@361
   864
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   865
    JMP_rel8(end);          // 2
nkeynes@386
   866
nkeynes@386
   867
    JMP_TARGET(emptysar);
nkeynes@386
   868
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   869
    JMP_rel8(end2);
nkeynes@382
   870
nkeynes@380
   871
    JMP_TARGET(doshl);
nkeynes@361
   872
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   873
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   874
    JMP_TARGET(end);
nkeynes@386
   875
    JMP_TARGET(end2);
nkeynes@361
   876
    store_reg( R_EAX, Rn );
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   878
:}
nkeynes@359
   879
SHLD Rm, Rn {:  
nkeynes@671
   880
    COUNT_INST(I_SHLD);
nkeynes@368
   881
    load_reg( R_EAX, Rn );
nkeynes@368
   882
    load_reg( R_ECX, Rm );
nkeynes@382
   883
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   884
    JGE_rel8(doshl);
nkeynes@368
   885
nkeynes@382
   886
    NEG_r32( R_ECX );      // 2
nkeynes@382
   887
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   888
    JE_rel8(emptyshr );
nkeynes@382
   889
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   890
    JMP_rel8(end);          // 2
nkeynes@386
   891
nkeynes@386
   892
    JMP_TARGET(emptyshr);
nkeynes@386
   893
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   894
    JMP_rel8(end2);
nkeynes@382
   895
nkeynes@382
   896
    JMP_TARGET(doshl);
nkeynes@382
   897
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   898
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   899
    JMP_TARGET(end);
nkeynes@386
   900
    JMP_TARGET(end2);
nkeynes@368
   901
    store_reg( R_EAX, Rn );
nkeynes@417
   902
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   903
:}
nkeynes@359
   904
SHAL Rn {: 
nkeynes@671
   905
    COUNT_INST(I_SHAL);
nkeynes@359
   906
    load_reg( R_EAX, Rn );
nkeynes@359
   907
    SHL1_r32( R_EAX );
nkeynes@397
   908
    SETC_t();
nkeynes@359
   909
    store_reg( R_EAX, Rn );
nkeynes@417
   910
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   911
:}
nkeynes@359
   912
SHAR Rn {:  
nkeynes@671
   913
    COUNT_INST(I_SHAR);
nkeynes@359
   914
    load_reg( R_EAX, Rn );
nkeynes@359
   915
    SAR1_r32( R_EAX );
nkeynes@397
   916
    SETC_t();
nkeynes@359
   917
    store_reg( R_EAX, Rn );
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   919
:}
nkeynes@359
   920
SHLL Rn {:  
nkeynes@671
   921
    COUNT_INST(I_SHLL);
nkeynes@359
   922
    load_reg( R_EAX, Rn );
nkeynes@359
   923
    SHL1_r32( R_EAX );
nkeynes@397
   924
    SETC_t();
nkeynes@359
   925
    store_reg( R_EAX, Rn );
nkeynes@417
   926
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   927
:}
nkeynes@359
   928
SHLL2 Rn {:
nkeynes@671
   929
    COUNT_INST(I_SHLL);
nkeynes@359
   930
    load_reg( R_EAX, Rn );
nkeynes@359
   931
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   932
    store_reg( R_EAX, Rn );
nkeynes@417
   933
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   934
:}
nkeynes@359
   935
SHLL8 Rn {:  
nkeynes@671
   936
    COUNT_INST(I_SHLL);
nkeynes@359
   937
    load_reg( R_EAX, Rn );
nkeynes@359
   938
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   939
    store_reg( R_EAX, Rn );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
:}
nkeynes@359
   942
SHLL16 Rn {:  
nkeynes@671
   943
    COUNT_INST(I_SHLL);
nkeynes@359
   944
    load_reg( R_EAX, Rn );
nkeynes@359
   945
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   946
    store_reg( R_EAX, Rn );
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   948
:}
nkeynes@359
   949
SHLR Rn {:  
nkeynes@671
   950
    COUNT_INST(I_SHLR);
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@359
   952
    SHR1_r32( R_EAX );
nkeynes@397
   953
    SETC_t();
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@417
   955
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   956
:}
nkeynes@359
   957
SHLR2 Rn {:  
nkeynes@671
   958
    COUNT_INST(I_SHLR);
nkeynes@359
   959
    load_reg( R_EAX, Rn );
nkeynes@359
   960
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   961
    store_reg( R_EAX, Rn );
nkeynes@417
   962
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   963
:}
nkeynes@359
   964
SHLR8 Rn {:  
nkeynes@671
   965
    COUNT_INST(I_SHLR);
nkeynes@359
   966
    load_reg( R_EAX, Rn );
nkeynes@359
   967
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   968
    store_reg( R_EAX, Rn );
nkeynes@417
   969
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   970
:}
nkeynes@359
   971
SHLR16 Rn {:  
nkeynes@671
   972
    COUNT_INST(I_SHLR);
nkeynes@359
   973
    load_reg( R_EAX, Rn );
nkeynes@359
   974
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   975
    store_reg( R_EAX, Rn );
nkeynes@417
   976
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   977
:}
nkeynes@359
   978
SUB Rm, Rn {:  
nkeynes@671
   979
    COUNT_INST(I_SUB);
nkeynes@359
   980
    load_reg( R_EAX, Rm );
nkeynes@359
   981
    load_reg( R_ECX, Rn );
nkeynes@359
   982
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   983
    store_reg( R_ECX, Rn );
nkeynes@417
   984
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   985
:}
nkeynes@359
   986
SUBC Rm, Rn {:  
nkeynes@671
   987
    COUNT_INST(I_SUBC);
nkeynes@359
   988
    load_reg( R_EAX, Rm );
nkeynes@359
   989
    load_reg( R_ECX, Rn );
nkeynes@417
   990
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   991
	LDC_t();
nkeynes@417
   992
    }
nkeynes@359
   993
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
    store_reg( R_ECX, Rn );
nkeynes@394
   995
    SETC_t();
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   997
:}
nkeynes@359
   998
SUBV Rm, Rn {:  
nkeynes@671
   999
    COUNT_INST(I_SUBV);
nkeynes@359
  1000
    load_reg( R_EAX, Rm );
nkeynes@359
  1001
    load_reg( R_ECX, Rn );
nkeynes@359
  1002
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1003
    store_reg( R_ECX, Rn );
nkeynes@359
  1004
    SETO_t();
nkeynes@417
  1005
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1006
:}
nkeynes@359
  1007
SWAP.B Rm, Rn {:  
nkeynes@671
  1008
    COUNT_INST(I_SWAPB);
nkeynes@359
  1009
    load_reg( R_EAX, Rm );
nkeynes@601
  1010
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1011
    store_reg( R_EAX, Rn );
nkeynes@359
  1012
:}
nkeynes@359
  1013
SWAP.W Rm, Rn {:  
nkeynes@671
  1014
    COUNT_INST(I_SWAPB);
nkeynes@359
  1015
    load_reg( R_EAX, Rm );
nkeynes@359
  1016
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1017
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1018
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1019
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
    store_reg( R_ECX, Rn );
nkeynes@417
  1021
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1022
:}
nkeynes@361
  1023
TAS.B @Rn {:  
nkeynes@671
  1024
    COUNT_INST(I_TASB);
nkeynes@586
  1025
    load_reg( R_EAX, Rn );
nkeynes@930
  1026
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
  1027
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1028
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1029
    SETE_t();
nkeynes@905
  1030
    OR_imm8_r8( 0x80, R_DL );
nkeynes@930
  1031
    MOV_esp8_r32( 0, R_EAX );
nkeynes@930
  1032
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1033
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1034
:}
nkeynes@361
  1035
TST Rm, Rn {:  
nkeynes@671
  1036
    COUNT_INST(I_TST);
nkeynes@361
  1037
    load_reg( R_EAX, Rm );
nkeynes@361
  1038
    load_reg( R_ECX, Rn );
nkeynes@361
  1039
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1040
    SETE_t();
nkeynes@417
  1041
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1042
:}
nkeynes@368
  1043
TST #imm, R0 {:  
nkeynes@671
  1044
    COUNT_INST(I_TSTI);
nkeynes@368
  1045
    load_reg( R_EAX, 0 );
nkeynes@368
  1046
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1047
    SETE_t();
nkeynes@417
  1048
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1049
:}
nkeynes@368
  1050
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1051
    COUNT_INST(I_TSTB);
nkeynes@368
  1052
    load_reg( R_EAX, 0);
nkeynes@939
  1053
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@930
  1054
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1055
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1056
    SETE_t();
nkeynes@417
  1057
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1058
:}
nkeynes@359
  1059
XOR Rm, Rn {:  
nkeynes@671
  1060
    COUNT_INST(I_XOR);
nkeynes@359
  1061
    load_reg( R_EAX, Rm );
nkeynes@359
  1062
    load_reg( R_ECX, Rn );
nkeynes@359
  1063
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1064
    store_reg( R_ECX, Rn );
nkeynes@417
  1065
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1066
:}
nkeynes@359
  1067
XOR #imm, R0 {:  
nkeynes@671
  1068
    COUNT_INST(I_XORI);
nkeynes@359
  1069
    load_reg( R_EAX, 0 );
nkeynes@359
  1070
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1071
    store_reg( R_EAX, 0 );
nkeynes@417
  1072
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1073
:}
nkeynes@359
  1074
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1075
    COUNT_INST(I_XORB);
nkeynes@359
  1076
    load_reg( R_EAX, 0 );
nkeynes@939
  1077
    ADD_sh4r_r32( R_GBR, R_EAX ); 
nkeynes@930
  1078
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@930
  1079
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@930
  1080
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1081
    XOR_imm32_r32( imm, R_EDX );
nkeynes@930
  1082
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1083
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1084
:}
nkeynes@361
  1085
XTRCT Rm, Rn {:
nkeynes@671
  1086
    COUNT_INST(I_XTRCT);
nkeynes@361
  1087
    load_reg( R_EAX, Rm );
nkeynes@394
  1088
    load_reg( R_ECX, Rn );
nkeynes@394
  1089
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1090
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1091
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1092
    store_reg( R_ECX, Rn );
nkeynes@417
  1093
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1094
:}
nkeynes@359
  1095
nkeynes@359
  1096
/* Data move instructions */
nkeynes@359
  1097
MOV Rm, Rn {:  
nkeynes@671
  1098
    COUNT_INST(I_MOV);
nkeynes@359
  1099
    load_reg( R_EAX, Rm );
nkeynes@359
  1100
    store_reg( R_EAX, Rn );
nkeynes@359
  1101
:}
nkeynes@359
  1102
MOV #imm, Rn {:  
nkeynes@671
  1103
    COUNT_INST(I_MOVI);
nkeynes@359
  1104
    load_imm32( R_EAX, imm );
nkeynes@359
  1105
    store_reg( R_EAX, Rn );
nkeynes@359
  1106
:}
nkeynes@359
  1107
MOV.B Rm, @Rn {:  
nkeynes@671
  1108
    COUNT_INST(I_MOVB);
nkeynes@586
  1109
    load_reg( R_EAX, Rn );
nkeynes@930
  1110
    load_reg( R_EDX, Rm );
nkeynes@930
  1111
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1112
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1113
:}
nkeynes@359
  1114
MOV.B Rm, @-Rn {:  
nkeynes@671
  1115
    COUNT_INST(I_MOVB);
nkeynes@586
  1116
    load_reg( R_EAX, Rn );
nkeynes@939
  1117
    LEA_r32disp8_r32( R_EAX, -1, R_EAX );
nkeynes@930
  1118
    load_reg( R_EDX, Rm );
nkeynes@939
  1119
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@586
  1120
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1121
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1122
:}
nkeynes@359
  1123
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1124
    COUNT_INST(I_MOVB);
nkeynes@359
  1125
    load_reg( R_EAX, 0 );
nkeynes@939
  1126
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@930
  1127
    load_reg( R_EDX, Rm );
nkeynes@930
  1128
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1129
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1130
:}
nkeynes@359
  1131
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1132
    COUNT_INST(I_MOVB);
nkeynes@586
  1133
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1134
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1135
    load_reg( R_EDX, 0 );
nkeynes@930
  1136
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1138
:}
nkeynes@359
  1139
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1140
    COUNT_INST(I_MOVB);
nkeynes@586
  1141
    load_reg( R_EAX, Rn );
nkeynes@586
  1142
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1143
    load_reg( R_EDX, 0 );
nkeynes@930
  1144
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B @Rm, Rn {:  
nkeynes@671
  1148
    COUNT_INST(I_MOVB);
nkeynes@586
  1149
    load_reg( R_EAX, Rm );
nkeynes@930
  1150
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1151
    store_reg( R_EAX, Rn );
nkeynes@417
  1152
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
:}
nkeynes@359
  1154
MOV.B @Rm+, Rn {:  
nkeynes@671
  1155
    COUNT_INST(I_MOVB);
nkeynes@586
  1156
    load_reg( R_EAX, Rm );
nkeynes@930
  1157
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@939
  1158
    if( Rm != Rn ) {
nkeynes@939
  1159
    	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1160
    }
nkeynes@359
  1161
    store_reg( R_EAX, Rn );
nkeynes@417
  1162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1163
:}
nkeynes@359
  1164
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1165
    COUNT_INST(I_MOVB);
nkeynes@359
  1166
    load_reg( R_EAX, 0 );
nkeynes@939
  1167
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@930
  1168
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1169
    store_reg( R_EAX, Rn );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1171
:}
nkeynes@359
  1172
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1173
    COUNT_INST(I_MOVB);
nkeynes@586
  1174
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1175
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1176
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1177
    store_reg( R_EAX, 0 );
nkeynes@417
  1178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1179
:}
nkeynes@359
  1180
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1181
    COUNT_INST(I_MOVB);
nkeynes@586
  1182
    load_reg( R_EAX, Rm );
nkeynes@586
  1183
    ADD_imm32_r32( disp, R_EAX );
nkeynes@930
  1184
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1185
    store_reg( R_EAX, 0 );
nkeynes@417
  1186
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1187
:}
nkeynes@374
  1188
MOV.L Rm, @Rn {:
nkeynes@671
  1189
    COUNT_INST(I_MOVL);
nkeynes@586
  1190
    load_reg( R_EAX, Rn );
nkeynes@586
  1191
    check_walign32(R_EAX);
nkeynes@930
  1192
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@930
  1193
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@930
  1194
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@930
  1195
    JNE_rel8( notsq );
nkeynes@930
  1196
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@930
  1197
    load_reg( R_EDX, Rm );
nkeynes@930
  1198
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@930
  1199
    JMP_rel8(end);
nkeynes@930
  1200
    JMP_TARGET(notsq);
nkeynes@930
  1201
    load_reg( R_EDX, Rm );
nkeynes@930
  1202
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@930
  1203
    JMP_TARGET(end);
nkeynes@417
  1204
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1205
:}
nkeynes@361
  1206
MOV.L Rm, @-Rn {:  
nkeynes@671
  1207
    COUNT_INST(I_MOVL);
nkeynes@586
  1208
    load_reg( R_EAX, Rn );
nkeynes@586
  1209
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1210
    check_walign32( R_EAX );
nkeynes@930
  1211
    load_reg( R_EDX, Rm );
nkeynes@939
  1212
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  1213
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1214
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1215
:}
nkeynes@361
  1216
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1217
    COUNT_INST(I_MOVL);
nkeynes@361
  1218
    load_reg( R_EAX, 0 );
nkeynes@939
  1219
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1220
    check_walign32( R_EAX );
nkeynes@930
  1221
    load_reg( R_EDX, Rm );
nkeynes@930
  1222
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1223
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1224
:}
nkeynes@361
  1225
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1226
    COUNT_INST(I_MOVL);
nkeynes@586
  1227
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1228
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1229
    check_walign32( R_EAX );
nkeynes@930
  1230
    load_reg( R_EDX, 0 );
nkeynes@930
  1231
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1233
:}
nkeynes@361
  1234
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1235
    COUNT_INST(I_MOVL);
nkeynes@586
  1236
    load_reg( R_EAX, Rn );
nkeynes@586
  1237
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1238
    check_walign32( R_EAX );
nkeynes@930
  1239
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@930
  1240
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@930
  1241
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@930
  1242
    JNE_rel8( notsq );
nkeynes@930
  1243
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@930
  1244
    load_reg( R_EDX, Rm );
nkeynes@930
  1245
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@930
  1246
    JMP_rel8(end);
nkeynes@930
  1247
    JMP_TARGET(notsq);
nkeynes@930
  1248
    load_reg( R_EDX, Rm );
nkeynes@930
  1249
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@930
  1250
    JMP_TARGET(end);
nkeynes@417
  1251
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1252
:}
nkeynes@361
  1253
MOV.L @Rm, Rn {:  
nkeynes@671
  1254
    COUNT_INST(I_MOVL);
nkeynes@586
  1255
    load_reg( R_EAX, Rm );
nkeynes@586
  1256
    check_ralign32( R_EAX );
nkeynes@930
  1257
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1258
    store_reg( R_EAX, Rn );
nkeynes@417
  1259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1260
:}
nkeynes@361
  1261
MOV.L @Rm+, Rn {:  
nkeynes@671
  1262
    COUNT_INST(I_MOVL);
nkeynes@361
  1263
    load_reg( R_EAX, Rm );
nkeynes@382
  1264
    check_ralign32( R_EAX );
nkeynes@930
  1265
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1266
    if( Rm != Rn ) {
nkeynes@939
  1267
    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1268
    }
nkeynes@361
  1269
    store_reg( R_EAX, Rn );
nkeynes@417
  1270
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1271
:}
nkeynes@361
  1272
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1273
    COUNT_INST(I_MOVL);
nkeynes@361
  1274
    load_reg( R_EAX, 0 );
nkeynes@939
  1275
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1276
    check_ralign32( R_EAX );
nkeynes@930
  1277
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1278
    store_reg( R_EAX, Rn );
nkeynes@417
  1279
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1280
:}
nkeynes@361
  1281
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1282
    COUNT_INST(I_MOVL);
nkeynes@586
  1283
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1284
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1285
    check_ralign32( R_EAX );
nkeynes@930
  1286
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1287
    store_reg( R_EAX, 0 );
nkeynes@417
  1288
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1289
:}
nkeynes@361
  1290
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1291
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1292
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1293
	SLOTILLEGAL();
nkeynes@374
  1294
    } else {
nkeynes@388
  1295
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1296
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1297
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1298
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1299
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1300
nkeynes@586
  1301
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1302
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1303
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1304
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1305
	    // behaviour though.
nkeynes@586
  1306
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1307
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1308
	} else {
nkeynes@586
  1309
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1310
	    // different virtual address than the translation was done with,
nkeynes@586
  1311
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1312
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1313
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@930
  1314
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1315
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1316
	}
nkeynes@382
  1317
	store_reg( R_EAX, Rn );
nkeynes@374
  1318
    }
nkeynes@361
  1319
:}
nkeynes@361
  1320
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1321
    COUNT_INST(I_MOVL);
nkeynes@586
  1322
    load_reg( R_EAX, Rm );
nkeynes@586
  1323
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1324
    check_ralign32( R_EAX );
nkeynes@930
  1325
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1326
    store_reg( R_EAX, Rn );
nkeynes@417
  1327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1328
:}
nkeynes@361
  1329
MOV.W Rm, @Rn {:  
nkeynes@671
  1330
    COUNT_INST(I_MOVW);
nkeynes@586
  1331
    load_reg( R_EAX, Rn );
nkeynes@586
  1332
    check_walign16( R_EAX );
nkeynes@930
  1333
    load_reg( R_EDX, Rm );
nkeynes@930
  1334
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1336
:}
nkeynes@361
  1337
MOV.W Rm, @-Rn {:  
nkeynes@671
  1338
    COUNT_INST(I_MOVW);
nkeynes@586
  1339
    load_reg( R_EAX, Rn );
nkeynes@586
  1340
    check_walign16( R_EAX );
nkeynes@939
  1341
    LEA_r32disp8_r32( R_EAX, -2, R_EAX );
nkeynes@930
  1342
    load_reg( R_EDX, Rm );
nkeynes@939
  1343
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@586
  1344
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1345
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1346
:}
nkeynes@361
  1347
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1348
    COUNT_INST(I_MOVW);
nkeynes@361
  1349
    load_reg( R_EAX, 0 );
nkeynes@939
  1350
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1351
    check_walign16( R_EAX );
nkeynes@930
  1352
    load_reg( R_EDX, Rm );
nkeynes@930
  1353
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1355
:}
nkeynes@361
  1356
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1357
    COUNT_INST(I_MOVW);
nkeynes@586
  1358
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1359
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1360
    check_walign16( R_EAX );
nkeynes@930
  1361
    load_reg( R_EDX, 0 );
nkeynes@930
  1362
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1364
:}
nkeynes@361
  1365
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1366
    COUNT_INST(I_MOVW);
nkeynes@586
  1367
    load_reg( R_EAX, Rn );
nkeynes@586
  1368
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1369
    check_walign16( R_EAX );
nkeynes@930
  1370
    load_reg( R_EDX, 0 );
nkeynes@930
  1371
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1373
:}
nkeynes@361
  1374
MOV.W @Rm, Rn {:  
nkeynes@671
  1375
    COUNT_INST(I_MOVW);
nkeynes@586
  1376
    load_reg( R_EAX, Rm );
nkeynes@586
  1377
    check_ralign16( R_EAX );
nkeynes@930
  1378
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1379
    store_reg( R_EAX, Rn );
nkeynes@417
  1380
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1381
:}
nkeynes@361
  1382
MOV.W @Rm+, Rn {:  
nkeynes@671
  1383
    COUNT_INST(I_MOVW);
nkeynes@361
  1384
    load_reg( R_EAX, Rm );
nkeynes@374
  1385
    check_ralign16( R_EAX );
nkeynes@930
  1386
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@939
  1387
    if( Rm != Rn ) {
nkeynes@939
  1388
        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1389
    }
nkeynes@361
  1390
    store_reg( R_EAX, Rn );
nkeynes@417
  1391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1392
:}
nkeynes@361
  1393
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1394
    COUNT_INST(I_MOVW);
nkeynes@361
  1395
    load_reg( R_EAX, 0 );
nkeynes@939
  1396
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1397
    check_ralign16( R_EAX );
nkeynes@930
  1398
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1399
    store_reg( R_EAX, Rn );
nkeynes@417
  1400
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1401
:}
nkeynes@361
  1402
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1403
    COUNT_INST(I_MOVW);
nkeynes@586
  1404
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1405
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1406
    check_ralign16( R_EAX );
nkeynes@930
  1407
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1408
    store_reg( R_EAX, 0 );
nkeynes@417
  1409
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1410
:}
nkeynes@361
  1411
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1412
    COUNT_INST(I_MOVW);
nkeynes@374
  1413
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1414
	SLOTILLEGAL();
nkeynes@374
  1415
    } else {
nkeynes@586
  1416
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1417
	uint32_t target = pc + disp + 4;
nkeynes@586
  1418
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1419
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1420
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1421
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1422
	} else {
nkeynes@586
  1423
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1424
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1425
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1426
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1427
	}
nkeynes@374
  1428
	store_reg( R_EAX, Rn );
nkeynes@374
  1429
    }
nkeynes@361
  1430
:}
nkeynes@361
  1431
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1432
    COUNT_INST(I_MOVW);
nkeynes@586
  1433
    load_reg( R_EAX, Rm );
nkeynes@586
  1434
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1435
    check_ralign16( R_EAX );
nkeynes@930
  1436
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1437
    store_reg( R_EAX, 0 );
nkeynes@417
  1438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1439
:}
nkeynes@361
  1440
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1441
    COUNT_INST(I_MOVA);
nkeynes@374
  1442
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1443
	SLOTILLEGAL();
nkeynes@374
  1444
    } else {
nkeynes@586
  1445
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1446
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1447
	store_reg( R_ECX, 0 );
nkeynes@586
  1448
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1449
    }
nkeynes@361
  1450
:}
nkeynes@361
  1451
MOVCA.L R0, @Rn {:  
nkeynes@671
  1452
    COUNT_INST(I_MOVCA);
nkeynes@586
  1453
    load_reg( R_EAX, Rn );
nkeynes@586
  1454
    check_walign32( R_EAX );
nkeynes@930
  1455
    load_reg( R_EDX, 0 );
nkeynes@930
  1456
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1458
:}
nkeynes@359
  1459
nkeynes@359
  1460
/* Control transfer instructions */
nkeynes@374
  1461
BF disp {:
nkeynes@671
  1462
    COUNT_INST(I_BF);
nkeynes@374
  1463
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1464
	SLOTILLEGAL();
nkeynes@374
  1465
    } else {
nkeynes@586
  1466
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1467
	JT_rel8( nottaken );
nkeynes@586
  1468
	exit_block_rel(target, pc+2 );
nkeynes@380
  1469
	JMP_TARGET(nottaken);
nkeynes@408
  1470
	return 2;
nkeynes@374
  1471
    }
nkeynes@374
  1472
:}
nkeynes@374
  1473
BF/S disp {:
nkeynes@671
  1474
    COUNT_INST(I_BFS);
nkeynes@374
  1475
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1476
	SLOTILLEGAL();
nkeynes@374
  1477
    } else {
nkeynes@590
  1478
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1479
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1480
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1481
	    JT_rel8(nottaken);
nkeynes@601
  1482
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1483
	    JMP_TARGET(nottaken);
nkeynes@601
  1484
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1485
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1486
	    exit_block_emu(pc+2);
nkeynes@601
  1487
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1488
	    return 2;
nkeynes@601
  1489
	} else {
nkeynes@601
  1490
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1491
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1492
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1493
	    }
nkeynes@601
  1494
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1495
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1496
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1497
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1498
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1499
	    
nkeynes@601
  1500
	    // not taken
nkeynes@601
  1501
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1502
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1503
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1504
	    return 4;
nkeynes@417
  1505
	}
nkeynes@374
  1506
    }
nkeynes@374
  1507
:}
nkeynes@374
  1508
BRA disp {:  
nkeynes@671
  1509
    COUNT_INST(I_BRA);
nkeynes@374
  1510
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1511
	SLOTILLEGAL();
nkeynes@374
  1512
    } else {
nkeynes@590
  1513
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1514
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1515
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1516
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1517
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1518
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1519
	    exit_block_emu(pc+2);
nkeynes@601
  1520
	    return 2;
nkeynes@601
  1521
	} else {
nkeynes@601
  1522
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1523
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1524
	    return 4;
nkeynes@601
  1525
	}
nkeynes@374
  1526
    }
nkeynes@374
  1527
:}
nkeynes@374
  1528
BRAF Rn {:  
nkeynes@671
  1529
    COUNT_INST(I_BRAF);
nkeynes@374
  1530
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1531
	SLOTILLEGAL();
nkeynes@374
  1532
    } else {
nkeynes@590
  1533
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1534
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1535
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1536
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1537
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1538
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1539
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1540
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1541
	    exit_block_emu(pc+2);
nkeynes@601
  1542
	    return 2;
nkeynes@601
  1543
	} else {
nkeynes@601
  1544
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1545
	    exit_block_newpcset(pc+2);
nkeynes@601
  1546
	    return 4;
nkeynes@601
  1547
	}
nkeynes@374
  1548
    }
nkeynes@374
  1549
:}
nkeynes@374
  1550
BSR disp {:  
nkeynes@671
  1551
    COUNT_INST(I_BSR);
nkeynes@374
  1552
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1553
	SLOTILLEGAL();
nkeynes@374
  1554
    } else {
nkeynes@590
  1555
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1556
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1557
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1558
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1559
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1560
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1561
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1562
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1563
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1564
	    exit_block_emu(pc+2);
nkeynes@601
  1565
	    return 2;
nkeynes@601
  1566
	} else {
nkeynes@601
  1567
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1568
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1569
	    return 4;
nkeynes@601
  1570
	}
nkeynes@374
  1571
    }
nkeynes@374
  1572
:}
nkeynes@374
  1573
BSRF Rn {:  
nkeynes@671
  1574
    COUNT_INST(I_BSRF);
nkeynes@374
  1575
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1576
	SLOTILLEGAL();
nkeynes@374
  1577
    } else {
nkeynes@590
  1578
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1579
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1580
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1581
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1582
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1583
nkeynes@601
  1584
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1585
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1586
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1587
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1588
	    exit_block_emu(pc+2);
nkeynes@601
  1589
	    return 2;
nkeynes@601
  1590
	} else {
nkeynes@601
  1591
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1592
	    exit_block_newpcset(pc+2);
nkeynes@601
  1593
	    return 4;
nkeynes@601
  1594
	}
nkeynes@374
  1595
    }
nkeynes@374
  1596
:}
nkeynes@374
  1597
BT disp {:
nkeynes@671
  1598
    COUNT_INST(I_BT);
nkeynes@374
  1599
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1600
	SLOTILLEGAL();
nkeynes@374
  1601
    } else {
nkeynes@586
  1602
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1603
	JF_rel8( nottaken );
nkeynes@586
  1604
	exit_block_rel(target, pc+2 );
nkeynes@380
  1605
	JMP_TARGET(nottaken);
nkeynes@408
  1606
	return 2;
nkeynes@374
  1607
    }
nkeynes@374
  1608
:}
nkeynes@374
  1609
BT/S disp {:
nkeynes@671
  1610
    COUNT_INST(I_BTS);
nkeynes@374
  1611
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1612
	SLOTILLEGAL();
nkeynes@374
  1613
    } else {
nkeynes@590
  1614
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1615
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1616
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1617
	    JF_rel8(nottaken);
nkeynes@601
  1618
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1619
	    JMP_TARGET(nottaken);
nkeynes@601
  1620
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1621
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1622
	    exit_block_emu(pc+2);
nkeynes@601
  1623
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1624
	    return 2;
nkeynes@601
  1625
	} else {
nkeynes@601
  1626
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1627
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1628
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1629
	    }
nkeynes@601
  1630
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1631
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1632
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1633
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1634
	    // not taken
nkeynes@601
  1635
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1636
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1637
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1638
	    return 4;
nkeynes@417
  1639
	}
nkeynes@374
  1640
    }
nkeynes@374
  1641
:}
nkeynes@374
  1642
JMP @Rn {:  
nkeynes@671
  1643
    COUNT_INST(I_JMP);
nkeynes@374
  1644
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1645
	SLOTILLEGAL();
nkeynes@374
  1646
    } else {
nkeynes@408
  1647
	load_reg( R_ECX, Rn );
nkeynes@590
  1648
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1649
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1650
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1651
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1652
	    exit_block_emu(pc+2);
nkeynes@601
  1653
	    return 2;
nkeynes@601
  1654
	} else {
nkeynes@601
  1655
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1656
	    exit_block_newpcset(pc+2);
nkeynes@601
  1657
	    return 4;
nkeynes@601
  1658
	}
nkeynes@374
  1659
    }
nkeynes@374
  1660
:}
nkeynes@374
  1661
JSR @Rn {:  
nkeynes@671
  1662
    COUNT_INST(I_JSR);
nkeynes@374
  1663
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1664
	SLOTILLEGAL();
nkeynes@374
  1665
    } else {
nkeynes@590
  1666
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1667
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1668
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1669
	load_reg( R_ECX, Rn );
nkeynes@590
  1670
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1671
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1672
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1673
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1674
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1675
	    exit_block_emu(pc+2);
nkeynes@601
  1676
	    return 2;
nkeynes@601
  1677
	} else {
nkeynes@601
  1678
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1679
	    exit_block_newpcset(pc+2);
nkeynes@601
  1680
	    return 4;
nkeynes@601
  1681
	}
nkeynes@374
  1682
    }
nkeynes@374
  1683
:}
nkeynes@374
  1684
RTE {:  
nkeynes@671
  1685
    COUNT_INST(I_RTE);
nkeynes@374
  1686
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1687
	SLOTILLEGAL();
nkeynes@374
  1688
    } else {
nkeynes@408
  1689
	check_priv();
nkeynes@408
  1690
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1691
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1692
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1693
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1694
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1695
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1696
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1697
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1698
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1699
	    exit_block_emu(pc+2);
nkeynes@601
  1700
	    return 2;
nkeynes@601
  1701
	} else {
nkeynes@601
  1702
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1703
	    exit_block_newpcset(pc+2);
nkeynes@601
  1704
	    return 4;
nkeynes@601
  1705
	}
nkeynes@374
  1706
    }
nkeynes@374
  1707
:}
nkeynes@374
  1708
RTS {:  
nkeynes@671
  1709
    COUNT_INST(I_RTS);
nkeynes@374
  1710
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1711
	SLOTILLEGAL();
nkeynes@374
  1712
    } else {
nkeynes@408
  1713
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1714
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1715
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1716
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1717
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1718
	    exit_block_emu(pc+2);
nkeynes@601
  1719
	    return 2;
nkeynes@601
  1720
	} else {
nkeynes@601
  1721
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1722
	    exit_block_newpcset(pc+2);
nkeynes@601
  1723
	    return 4;
nkeynes@601
  1724
	}
nkeynes@374
  1725
    }
nkeynes@374
  1726
:}
nkeynes@374
  1727
TRAPA #imm {:  
nkeynes@671
  1728
    COUNT_INST(I_TRAPA);
nkeynes@374
  1729
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1730
	SLOTILLEGAL();
nkeynes@374
  1731
    } else {
nkeynes@590
  1732
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1733
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1734
	load_imm32( R_EAX, imm );
nkeynes@527
  1735
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1736
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1737
	exit_block_pcset(pc);
nkeynes@409
  1738
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1739
	return 2;
nkeynes@374
  1740
    }
nkeynes@374
  1741
:}
nkeynes@374
  1742
UNDEF {:  
nkeynes@671
  1743
    COUNT_INST(I_UNDEF);
nkeynes@374
  1744
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1745
	SLOTILLEGAL();
nkeynes@374
  1746
    } else {
nkeynes@586
  1747
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1748
	return 2;
nkeynes@374
  1749
    }
nkeynes@368
  1750
:}
nkeynes@374
  1751
nkeynes@374
  1752
CLRMAC {:  
nkeynes@671
  1753
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1754
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1755
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1756
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1758
:}
nkeynes@374
  1759
CLRS {:
nkeynes@671
  1760
    COUNT_INST(I_CLRS);
nkeynes@374
  1761
    CLC();
nkeynes@374
  1762
    SETC_sh4r(R_S);
nkeynes@872
  1763
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1764
:}
nkeynes@374
  1765
CLRT {:  
nkeynes@671
  1766
    COUNT_INST(I_CLRT);
nkeynes@374
  1767
    CLC();
nkeynes@374
  1768
    SETC_t();
nkeynes@417
  1769
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1770
:}
nkeynes@374
  1771
SETS {:  
nkeynes@671
  1772
    COUNT_INST(I_SETS);
nkeynes@374
  1773
    STC();
nkeynes@374
  1774
    SETC_sh4r(R_S);
nkeynes@872
  1775
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1776
:}
nkeynes@374
  1777
SETT {:  
nkeynes@671
  1778
    COUNT_INST(I_SETT);
nkeynes@374
  1779
    STC();
nkeynes@374
  1780
    SETC_t();
nkeynes@417
  1781
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1782
:}
nkeynes@359
  1783
nkeynes@375
  1784
/* Floating point moves */
nkeynes@375
  1785
FMOV FRm, FRn {:  
nkeynes@671
  1786
    COUNT_INST(I_FMOV1);
nkeynes@377
  1787
    check_fpuen();
nkeynes@901
  1788
    if( sh4_x86.double_size ) {
nkeynes@901
  1789
        load_dr0( R_EAX, FRm );
nkeynes@901
  1790
        load_dr1( R_ECX, FRm );
nkeynes@901
  1791
        store_dr0( R_EAX, FRn );
nkeynes@901
  1792
        store_dr1( R_ECX, FRn );
nkeynes@901
  1793
    } else {
nkeynes@901
  1794
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1795
        store_fr( R_EAX, FRn );
nkeynes@901
  1796
    }
nkeynes@375
  1797
:}
nkeynes@416
  1798
FMOV FRm, @Rn {: 
nkeynes@671
  1799
    COUNT_INST(I_FMOV2);
nkeynes@586
  1800
    check_fpuen();
nkeynes@586
  1801
    load_reg( R_EAX, Rn );
nkeynes@901
  1802
    if( sh4_x86.double_size ) {
nkeynes@901
  1803
        check_walign64( R_EAX );
nkeynes@930
  1804
        load_dr0( R_EDX, FRm );
nkeynes@939
  1805
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1806
        load_reg( R_EAX, Rn );
nkeynes@939
  1807
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1808
        load_dr1( R_EDX, FRm );
nkeynes@939
  1809
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1810
    } else {
nkeynes@901
  1811
        check_walign32( R_EAX );
nkeynes@930
  1812
        load_fr( R_EDX, FRm );
nkeynes@930
  1813
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1814
    }
nkeynes@417
  1815
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1816
:}
nkeynes@375
  1817
FMOV @Rm, FRn {:  
nkeynes@671
  1818
    COUNT_INST(I_FMOV5);
nkeynes@586
  1819
    check_fpuen();
nkeynes@586
  1820
    load_reg( R_EAX, Rm );
nkeynes@901
  1821
    if( sh4_x86.double_size ) {
nkeynes@901
  1822
        check_ralign64( R_EAX );
nkeynes@939
  1823
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1824
        store_dr0( R_EAX, FRn );
nkeynes@939
  1825
        load_reg( R_EAX, Rm );
nkeynes@939
  1826
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1827
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1828
        store_dr1( R_EAX, FRn );
nkeynes@901
  1829
    } else {
nkeynes@901
  1830
        check_ralign32( R_EAX );
nkeynes@930
  1831
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1832
        store_fr( R_EAX, FRn );
nkeynes@901
  1833
    }
nkeynes@417
  1834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1835
:}
nkeynes@377
  1836
FMOV FRm, @-Rn {:  
nkeynes@671
  1837
    COUNT_INST(I_FMOV3);
nkeynes@586
  1838
    check_fpuen();
nkeynes@586
  1839
    load_reg( R_EAX, Rn );
nkeynes@901
  1840
    if( sh4_x86.double_size ) {
nkeynes@901
  1841
        check_walign64( R_EAX );
nkeynes@939
  1842
        LEA_r32disp8_r32( R_EAX, -8, R_EAX );
nkeynes@930
  1843
        load_dr0( R_EDX, FRm );
nkeynes@939
  1844
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1845
        load_reg( R_EAX, Rn );
nkeynes@939
  1846
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@939
  1847
        load_dr1( R_EDX, FRm );
nkeynes@939
  1848
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1849
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1850
    } else {
nkeynes@901
  1851
        check_walign32( R_EAX );
nkeynes@939
  1852
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@930
  1853
        load_fr( R_EDX, FRm );
nkeynes@939
  1854
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1855
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1856
    }
nkeynes@417
  1857
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1858
:}
nkeynes@416
  1859
FMOV @Rm+, FRn {:
nkeynes@671
  1860
    COUNT_INST(I_FMOV6);
nkeynes@586
  1861
    check_fpuen();
nkeynes@586
  1862
    load_reg( R_EAX, Rm );
nkeynes@901
  1863
    if( sh4_x86.double_size ) {
nkeynes@901
  1864
        check_ralign64( R_EAX );
nkeynes@939
  1865
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1866
        store_dr0( R_EAX, FRn );
nkeynes@939
  1867
        load_reg( R_EAX, Rm );
nkeynes@939
  1868
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1869
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1870
        store_dr1( R_EAX, FRn );
nkeynes@901
  1871
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1872
    } else {
nkeynes@901
  1873
        check_ralign32( R_EAX );
nkeynes@930
  1874
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1875
        store_fr( R_EAX, FRn );
nkeynes@939
  1876
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1877
    }
nkeynes@417
  1878
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1879
:}
nkeynes@377
  1880
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1881
    COUNT_INST(I_FMOV4);
nkeynes@586
  1882
    check_fpuen();
nkeynes@586
  1883
    load_reg( R_EAX, Rn );
nkeynes@586
  1884
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1885
    if( sh4_x86.double_size ) {
nkeynes@901
  1886
        check_walign64( R_EAX );
nkeynes@930
  1887
        load_dr0( R_EDX, FRm );
nkeynes@939
  1888
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@939
  1889
        load_reg( R_EAX, Rn );
nkeynes@939
  1890
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@939
  1891
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1892
        load_dr1( R_EDX, FRm );
nkeynes@939
  1893
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1894
    } else {
nkeynes@901
  1895
        check_walign32( R_EAX );
nkeynes@930
  1896
        load_fr( R_EDX, FRm );
nkeynes@930
  1897
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1898
    }
nkeynes@417
  1899
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1900
:}
nkeynes@377
  1901
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1902
    COUNT_INST(I_FMOV7);
nkeynes@586
  1903
    check_fpuen();
nkeynes@586
  1904
    load_reg( R_EAX, Rm );
nkeynes@586
  1905
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1906
    if( sh4_x86.double_size ) {
nkeynes@901
  1907
        check_ralign64( R_EAX );
nkeynes@939
  1908
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@939
  1909
        store_dr0( R_EAX, FRn );
nkeynes@939
  1910
        load_reg( R_EAX, Rm );
nkeynes@939
  1911
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@939
  1912
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@939
  1913
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1914
        store_dr1( R_EAX, FRn );
nkeynes@901
  1915
    } else {
nkeynes@901
  1916
        check_ralign32( R_EAX );
nkeynes@930
  1917
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1918
        store_fr( R_EAX, FRn );
nkeynes@901
  1919
    }
nkeynes@417
  1920
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1921
:}
nkeynes@377
  1922
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1923
    COUNT_INST(I_FLDI0);
nkeynes@377
  1924
    check_fpuen();
nkeynes@901
  1925
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1926
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1927
        store_fr( R_EAX, FRn );
nkeynes@901
  1928
    }
nkeynes@417
  1929
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1930
:}
nkeynes@377
  1931
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1932
    COUNT_INST(I_FLDI1);
nkeynes@377
  1933
    check_fpuen();
nkeynes@901
  1934
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1935
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1936
        store_fr( R_EAX, FRn );
nkeynes@901
  1937
    }
nkeynes@377
  1938
:}
nkeynes@377
  1939
nkeynes@377
  1940
FLOAT FPUL, FRn {:  
nkeynes@671
  1941
    COUNT_INST(I_FLOAT);
nkeynes@377
  1942
    check_fpuen();
nkeynes@377
  1943
    FILD_sh4r(R_FPUL);
nkeynes@901
  1944
    if( sh4_x86.double_prec ) {
nkeynes@901
  1945
        pop_dr( FRn );
nkeynes@901
  1946
    } else {
nkeynes@901
  1947
        pop_fr( FRn );
nkeynes@901
  1948
    }
nkeynes@377
  1949
:}
nkeynes@377
  1950
FTRC FRm, FPUL {:  
nkeynes@671
  1951
    COUNT_INST(I_FTRC);
nkeynes@377
  1952
    check_fpuen();
nkeynes@901
  1953
    if( sh4_x86.double_prec ) {
nkeynes@901
  1954
        push_dr( FRm );
nkeynes@901
  1955
    } else {
nkeynes@901
  1956
        push_fr( FRm );
nkeynes@901
  1957
    }
nkeynes@789
  1958
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1959
    FILD_r32ind( R_ECX );
nkeynes@388
  1960
    FCOMIP_st(1);
nkeynes@669
  1961
    JNA_rel8( sat );
nkeynes@789
  1962
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  1963
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1964
    FCOMIP_st(1);                   // 2
nkeynes@669
  1965
    JAE_rel8( sat2 );            // 2
nkeynes@789
  1966
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  1967
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  1968
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  1969
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1970
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1971
    FLDCW_r32ind( R_EAX );
nkeynes@669
  1972
    JMP_rel8(end);             // 2
nkeynes@388
  1973
nkeynes@388
  1974
    JMP_TARGET(sat);
nkeynes@388
  1975
    JMP_TARGET(sat2);
nkeynes@388
  1976
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1977
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1978
    FPOP_st();
nkeynes@388
  1979
    JMP_TARGET(end);
nkeynes@417
  1980
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1981
:}
nkeynes@377
  1982
FLDS FRm, FPUL {:  
nkeynes@671
  1983
    COUNT_INST(I_FLDS);
nkeynes@377
  1984
    check_fpuen();
nkeynes@669
  1985
    load_fr( R_EAX, FRm );
nkeynes@377
  1986
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1987
:}
nkeynes@377
  1988
FSTS FPUL, FRn {:  
nkeynes@671
  1989
    COUNT_INST(I_FSTS);
nkeynes@377
  1990
    check_fpuen();
nkeynes@377
  1991
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  1992
    store_fr( R_EAX, FRn );
nkeynes@377
  1993
:}
nkeynes@377
  1994
FCNVDS FRm, FPUL {:  
nkeynes@671
  1995
    COUNT_INST(I_FCNVDS);
nkeynes@377
  1996
    check_fpuen();
nkeynes@901
  1997
    if( sh4_x86.double_prec ) {
nkeynes@901
  1998
        push_dr( FRm );
nkeynes@901
  1999
        pop_fpul();
nkeynes@901
  2000
    }
nkeynes@377
  2001
:}
nkeynes@377
  2002
FCNVSD FPUL, FRn {:  
nkeynes@671
  2003
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2004
    check_fpuen();
nkeynes@901
  2005
    if( sh4_x86.double_prec ) {
nkeynes@901
  2006
        push_fpul();
nkeynes@901
  2007
        pop_dr( FRn );
nkeynes@901
  2008
    }
nkeynes@377
  2009
:}
nkeynes@375
  2010
nkeynes@359
  2011
/* Floating point instructions */
nkeynes@374
  2012
FABS FRn {:  
nkeynes@671
  2013
    COUNT_INST(I_FABS);
nkeynes@377
  2014
    check_fpuen();
nkeynes@901
  2015
    if( sh4_x86.double_prec ) {
nkeynes@901
  2016
        push_dr(FRn);
nkeynes@901
  2017
        FABS_st0();
nkeynes@901
  2018
        pop_dr(FRn);
nkeynes@901
  2019
    } else {
nkeynes@901
  2020
        push_fr(FRn);
nkeynes@901
  2021
        FABS_st0();
nkeynes@901
  2022
        pop_fr(FRn);
nkeynes@901
  2023
    }
nkeynes@374
  2024
:}
nkeynes@377
  2025
FADD FRm, FRn {:  
nkeynes@671
  2026
    COUNT_INST(I_FADD);
nkeynes@377
  2027
    check_fpuen();
nkeynes@901
  2028
    if( sh4_x86.double_prec ) {
nkeynes@901
  2029
        push_dr(FRm);
nkeynes@901
  2030
        push_dr(FRn);
nkeynes@901
  2031
        FADDP_st(1);
nkeynes@901
  2032
        pop_dr(FRn);
nkeynes@901
  2033
    } else {
nkeynes@901
  2034
        push_fr(FRm);
nkeynes@901
  2035
        push_fr(FRn);
nkeynes@901
  2036
        FADDP_st(1);
nkeynes@901
  2037
        pop_fr(FRn);
nkeynes@901
  2038
    }
nkeynes@375
  2039
:}
nkeynes@377
  2040
FDIV FRm, FRn {:  
nkeynes@671
  2041
    COUNT_INST(I_FDIV);
nkeynes@377
  2042
    check_fpuen();
nkeynes@901
  2043
    if( sh4_x86.double_prec ) {
nkeynes@901
  2044
        push_dr(FRn);
nkeynes@901
  2045
        push_dr(FRm);
nkeynes@901
  2046
        FDIVP_st(1);
nkeynes@901
  2047
        pop_dr(FRn);
nkeynes@901
  2048
    } else {
nkeynes@901
  2049
        push_fr(FRn);
nkeynes@901
  2050
        push_fr(FRm);
nkeynes@901
  2051
        FDIVP_st(1);
nkeynes@901
  2052
        pop_fr(FRn);
nkeynes@901
  2053
    }
nkeynes@375
  2054
:}
nkeynes@375
  2055
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2056
    COUNT_INST(I_FMAC);
nkeynes@377
  2057
    check_fpuen();
nkeynes@901
  2058
    if( sh4_x86.double_prec ) {
nkeynes@901
  2059
        push_dr( 0 );
nkeynes@901
  2060
        push_dr( FRm );
nkeynes@901
  2061
        FMULP_st(1);
nkeynes@901
  2062
        push_dr( FRn );
nkeynes@901
  2063
        FADDP_st(1);
nkeynes@901
  2064
        pop_dr( FRn );
nkeynes@901
  2065
    } else {
nkeynes@901
  2066
        push_fr( 0 );
nkeynes@901
  2067
        push_fr( FRm );
nkeynes@901
  2068
        FMULP_st(1);
nkeynes@901
  2069
        push_fr( FRn );
nkeynes@901
  2070
        FADDP_st(1);
nkeynes@901
  2071
        pop_fr( FRn );
nkeynes@901
  2072
    }
nkeynes@375
  2073
:}
nkeynes@375
  2074
nkeynes@377
  2075
FMUL FRm, FRn {:  
nkeynes@671
  2076
    COUNT_INST(I_FMUL);
nkeynes@377
  2077
    check_fpuen();
nkeynes@901
  2078
    if( sh4_x86.double_prec ) {
nkeynes@901
  2079
        push_dr(FRm);
nkeynes@901
  2080
        push_dr(FRn);
nkeynes@901
  2081
        FMULP_st(1);
nkeynes@901
  2082
        pop_dr(FRn);
nkeynes@901
  2083
    } else {
nkeynes@901
  2084
        push_fr(FRm);
nkeynes@901
  2085
        push_fr(FRn);
nkeynes@901
  2086
        FMULP_st(1);
nkeynes@901
  2087
        pop_fr(FRn);
nkeynes@901
  2088
    }
nkeynes@377
  2089
:}
nkeynes@377
  2090
FNEG FRn {:  
nkeynes@671
  2091
    COUNT_INST(I_FNEG);
nkeynes@377
  2092
    check_fpuen();
nkeynes@901
  2093
    if( sh4_x86.double_prec ) {
nkeynes@901
  2094
        push_dr(FRn);
nkeynes@901
  2095
        FCHS_st0();
nkeynes@901
  2096
        pop_dr(FRn);
nkeynes@901
  2097
    } else {
nkeynes@901
  2098
        push_fr(FRn);
nkeynes@901
  2099
        FCHS_st0();
nkeynes@901
  2100
        pop_fr(FRn);
nkeynes@901
  2101
    }
nkeynes@377
  2102
:}
nkeynes@377
  2103
FSRRA FRn {:  
nkeynes@671
  2104
    COUNT_INST(I_FSRRA);
nkeynes@377
  2105
    check_fpuen();
nkeynes@901
  2106
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2107
        FLD1_st0();
nkeynes@901
  2108
        push_fr(FRn);
nkeynes@901
  2109
        FSQRT_st0();
nkeynes@901
  2110
        FDIVP_st(1);
nkeynes@901
  2111
        pop_fr(FRn);
nkeynes@901
  2112
    }
nkeynes@377
  2113
:}
nkeynes@377
  2114
FSQRT FRn {:  
nkeynes@671
  2115
    COUNT_INST(I_FSQRT);
nkeynes@377
  2116
    check_fpuen();
nkeynes@901
  2117
    if( sh4_x86.double_prec ) {
nkeynes@901
  2118
        push_dr(FRn);
nkeynes@901
  2119
        FSQRT_st0();
nkeynes@901
  2120
        pop_dr(FRn);
nkeynes@901
  2121
    } else {
nkeynes@901
  2122
        push_fr(FRn);
nkeynes@901
  2123
        FSQRT_st0();
nkeynes@901
  2124
        pop_fr(FRn);
nkeynes@901
  2125
    }
nkeynes@377
  2126
:}
nkeynes@377
  2127
FSUB FRm, FRn {:  
nkeynes@671
  2128
    COUNT_INST(I_FSUB);
nkeynes@377
  2129
    check_fpuen();
nkeynes@901
  2130
    if( sh4_x86.double_prec ) {
nkeynes@901
  2131
        push_dr(FRn);
nkeynes@901
  2132
        push_dr(FRm);
nkeynes@901
  2133
        FSUBP_st(1);
nkeynes@901
  2134
        pop_dr(FRn);
nkeynes@901
  2135
    } else {
nkeynes@901
  2136
        push_fr(FRn);
nkeynes@901
  2137
        push_fr(FRm);
nkeynes@901
  2138
        FSUBP_st(1);
nkeynes@901
  2139
        pop_fr(FRn);
nkeynes@901
  2140
    }
nkeynes@377
  2141
:}
nkeynes@377
  2142
nkeynes@377
  2143
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2144
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2145
    check_fpuen();
nkeynes@901
  2146
    if( sh4_x86.double_prec ) {
nkeynes@901
  2147
        push_dr(FRm);
nkeynes@901
  2148
        push_dr(FRn);
nkeynes@901
  2149
    } else {
nkeynes@901
  2150
        push_fr(FRm);
nkeynes@901
  2151
        push_fr(FRn);
nkeynes@901
  2152
    }
nkeynes@377
  2153
    FCOMIP_st(1);
nkeynes@377
  2154
    SETE_t();
nkeynes@377
  2155
    FPOP_st();
nkeynes@901
  2156
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2157
:}
nkeynes@377
  2158
FCMP/GT FRm, FRn {:  
nkeynes@671
  2159
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2160
    check_fpuen();
nkeynes@901
  2161
    if( sh4_x86.double_prec ) {
nkeynes@901
  2162
        push_dr(FRm);
nkeynes@901
  2163
        push_dr(FRn);
nkeynes@901
  2164
    } else {
nkeynes@901
  2165
        push_fr(FRm);
nkeynes@901
  2166
        push_fr(FRn);
nkeynes@901
  2167
    }
nkeynes@377
  2168
    FCOMIP_st(1);
nkeynes@377
  2169
    SETA_t();
nkeynes@377
  2170
    FPOP_st();
nkeynes@901
  2171
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2172
:}
nkeynes@377
  2173
nkeynes@377
  2174
FSCA FPUL, FRn {:  
nkeynes@671
  2175
    COUNT_INST(I_FSCA);
nkeynes@377
  2176
    check_fpuen();
nkeynes@901
  2177
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2178
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2179
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2180
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2181
    }
nkeynes@417
  2182
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2183
:}
nkeynes@377
  2184
FIPR FVm, FVn {:  
nkeynes@671
  2185
    COUNT_INST(I_FIPR);
nkeynes@377
  2186
    check_fpuen();
nkeynes@901
  2187
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2188
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2189
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2190
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2191
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2192
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2193
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2194
        } else {
nkeynes@904
  2195
            push_fr( FVm<<2 );
nkeynes@903
  2196
            push_fr( FVn<<2 );
nkeynes@903
  2197
            FMULP_st(1);
nkeynes@903
  2198
            push_fr( (FVm<<2)+1);
nkeynes@903
  2199
            push_fr( (FVn<<2)+1);
nkeynes@903
  2200
            FMULP_st(1);
nkeynes@903
  2201
            FADDP_st(1);
nkeynes@903
  2202
            push_fr( (FVm<<2)+2);
nkeynes@903
  2203
            push_fr( (FVn<<2)+2);
nkeynes@903
  2204
            FMULP_st(1);
nkeynes@903
  2205
            FADDP_st(1);
nkeynes@903
  2206
            push_fr( (FVm<<2)+3);
nkeynes@903
  2207
            push_fr( (FVn<<2)+3);
nkeynes@903
  2208
            FMULP_st(1);
nkeynes@903
  2209
            FADDP_st(1);
nkeynes@903
  2210
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2211
        }
nkeynes@901
  2212
    }
nkeynes@377
  2213
:}
nkeynes@377
  2214
FTRV XMTRX, FVn {:  
nkeynes@671
  2215
    COUNT_INST(I_FTRV);
nkeynes@377
  2216
    check_fpuen();
nkeynes@901
  2217
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2218
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2219
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2220
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2221
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2222
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2223
nkeynes@903
  2224
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2225
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2226
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2227
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2228
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2229
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2230
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2231
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2232
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2233
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2234
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2235
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2236
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2237
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2238
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2239
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2240
        } else {
nkeynes@903
  2241
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2242
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2243
        }
nkeynes@901
  2244
    }
nkeynes@417
  2245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2246
:}
nkeynes@377
  2247
nkeynes@377
  2248
FRCHG {:  
nkeynes@671
  2249
    COUNT_INST(I_FRCHG);
nkeynes@377
  2250
    check_fpuen();
nkeynes@936
  2251
    XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );
nkeynes@669
  2252
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2254
:}
nkeynes@377
  2255
FSCHG {:  
nkeynes@671
  2256
    COUNT_INST(I_FSCHG);
nkeynes@377
  2257
    check_fpuen();
nkeynes@936
  2258
    XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);
nkeynes@936
  2259
    XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2261
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2262
:}
nkeynes@359
  2263
nkeynes@359
  2264
/* Processor control instructions */
nkeynes@368
  2265
LDC Rm, SR {:
nkeynes@671
  2266
    COUNT_INST(I_LDCSR);
nkeynes@386
  2267
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2268
	SLOTILLEGAL();
nkeynes@386
  2269
    } else {
nkeynes@386
  2270
	check_priv();
nkeynes@386
  2271
	load_reg( R_EAX, Rm );
nkeynes@386
  2272
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2273
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2274
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2275
	return 2;
nkeynes@386
  2276
    }
nkeynes@368
  2277
:}
nkeynes@359
  2278
LDC Rm, GBR {: 
nkeynes@671
  2279
    COUNT_INST(I_LDC);
nkeynes@359
  2280
    load_reg( R_EAX, Rm );
nkeynes@359
  2281
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2282
:}
nkeynes@359
  2283
LDC Rm, VBR {:  
nkeynes@671
  2284
    COUNT_INST(I_LDC);
nkeynes@386
  2285
    check_priv();
nkeynes@359
  2286
    load_reg( R_EAX, Rm );
nkeynes@359
  2287
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2288
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2289
:}
nkeynes@359
  2290
LDC Rm, SSR {:  
nkeynes@671
  2291
    COUNT_INST(I_LDC);
nkeynes@386
  2292
    check_priv();
nkeynes@359
  2293
    load_reg( R_EAX, Rm );
nkeynes@359
  2294
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2296
:}
nkeynes@359
  2297
LDC Rm, SGR {:  
nkeynes@671
  2298
    COUNT_INST(I_LDC);
nkeynes@386
  2299
    check_priv();
nkeynes@359
  2300
    load_reg( R_EAX, Rm );
nkeynes@359
  2301
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2302
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2303
:}
nkeynes@359
  2304
LDC Rm, SPC {:  
nkeynes@671
  2305
    COUNT_INST(I_LDC);
nkeynes@386
  2306
    check_priv();
nkeynes@359
  2307
    load_reg( R_EAX, Rm );
nkeynes@359
  2308
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2309
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2310
:}
nkeynes@359
  2311
LDC Rm, DBR {:  
nkeynes@671
  2312
    COUNT_INST(I_LDC);
nkeynes@386
  2313
    check_priv();
nkeynes@359
  2314
    load_reg( R_EAX, Rm );
nkeynes@359
  2315
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2316
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2317
:}
nkeynes@374
  2318
LDC Rm, Rn_BANK {:  
nkeynes@671
  2319
    COUNT_INST(I_LDC);
nkeynes@386
  2320
    check_priv();
nkeynes@374
  2321
    load_reg( R_EAX, Rm );
nkeynes@374
  2322
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2323
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2324
:}
nkeynes@359
  2325
LDC.L @Rm+, GBR {:  
nkeynes@671
  2326
    COUNT_INST(I_LDCM);
nkeynes@359
  2327
    load_reg( R_EAX, Rm );
nkeynes@395
  2328
    check_ralign32( R_EAX );
nkeynes@939
  2329
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2330
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2331
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2332
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2333
:}
nkeynes@368
  2334
LDC.L @Rm+, SR {:
nkeynes@671
  2335
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2336
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2337
	SLOTILLEGAL();
nkeynes@386
  2338
    } else {
nkeynes@586
  2339
	check_priv();
nkeynes@386
  2340
	load_reg( R_EAX, Rm );
nkeynes@395
  2341
	check_ralign32( R_EAX );
nkeynes@939
  2342
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2343
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
  2344
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2345
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2346
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@937
  2347
	return 2;
nkeynes@386
  2348
    }
nkeynes@359
  2349
:}
nkeynes@359
  2350
LDC.L @Rm+, VBR {:  
nkeynes@671
  2351
    COUNT_INST(I_LDCM);
nkeynes@586
  2352
    check_priv();
nkeynes@359
  2353
    load_reg( R_EAX, Rm );
nkeynes@395
  2354
    check_ralign32( R_EAX );
nkeynes@939
  2355
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2356
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2357
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2359
:}
nkeynes@359
  2360
LDC.L @Rm+, SSR {:
nkeynes@671
  2361
    COUNT_INST(I_LDCM);
nkeynes@586
  2362
    check_priv();
nkeynes@359
  2363
    load_reg( R_EAX, Rm );
nkeynes@416
  2364
    check_ralign32( R_EAX );
nkeynes@939
  2365
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2366
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2367
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2369
:}
nkeynes@359
  2370
LDC.L @Rm+, SGR {:  
nkeynes@671
  2371
    COUNT_INST(I_LDCM);
nkeynes@586
  2372
    check_priv();
nkeynes@359
  2373
    load_reg( R_EAX, Rm );
nkeynes@395
  2374
    check_ralign32( R_EAX );
nkeynes@939
  2375
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2376
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2377
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2379
:}
nkeynes@359
  2380
LDC.L @Rm+, SPC {:  
nkeynes@671
  2381
    COUNT_INST(I_LDCM);
nkeynes@586
  2382
    check_priv();
nkeynes@359
  2383
    load_reg( R_EAX, Rm );
nkeynes@395
  2384
    check_ralign32( R_EAX );
nkeynes@939
  2385
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2386
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2387
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2388
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2389
:}
nkeynes@359
  2390
LDC.L @Rm+, DBR {:  
nkeynes@671
  2391
    COUNT_INST(I_LDCM);
nkeynes@586
  2392
    check_priv();
nkeynes@359
  2393
    load_reg( R_EAX, Rm );
nkeynes@395
  2394
    check_ralign32( R_EAX );
nkeynes@939
  2395
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2396
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2397
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2399
:}
nkeynes@359
  2400
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2401
    COUNT_INST(I_LDCM);
nkeynes@586
  2402
    check_priv();
nkeynes@374
  2403
    load_reg( R_EAX, Rm );
nkeynes@395
  2404
    check_ralign32( R_EAX );
nkeynes@939
  2405
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2406
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@374
  2407
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2408
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2409
:}
nkeynes@626
  2410
LDS Rm, FPSCR {:
nkeynes@673
  2411
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2412
    check_fpuen();
nkeynes@359
  2413
    load_reg( R_EAX, Rm );
nkeynes@669
  2414
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2416
    return 2;
nkeynes@359
  2417
:}
nkeynes@359
  2418
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2419
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2420
    check_fpuen();
nkeynes@359
  2421
    load_reg( R_EAX, Rm );
nkeynes@395
  2422
    check_ralign32( R_EAX );
nkeynes@939
  2423
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2424
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@669
  2425
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2427
    return 2;
nkeynes@359
  2428
:}
nkeynes@359
  2429
LDS Rm, FPUL {:  
nkeynes@671
  2430
    COUNT_INST(I_LDS);
nkeynes@626
  2431
    check_fpuen();
nkeynes@359
  2432
    load_reg( R_EAX, Rm );
nkeynes@359
  2433
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2434
:}
nkeynes@359
  2435
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2436
    COUNT_INST(I_LDSM);
nkeynes@626
  2437
    check_fpuen();
nkeynes@359
  2438
    load_reg( R_EAX, Rm );
nkeynes@395
  2439
    check_ralign32( R_EAX );
nkeynes@939
  2440
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2441
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2442
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2443
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2444
:}
nkeynes@359
  2445
LDS Rm, MACH {: 
nkeynes@671
  2446
    COUNT_INST(I_LDS);
nkeynes@359
  2447
    load_reg( R_EAX, Rm );
nkeynes@359
  2448
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2449
:}
nkeynes@359
  2450
LDS.L @Rm+, MACH {:  
nkeynes@671
  2451
    COUNT_INST(I_LDSM);
nkeynes@359
  2452
    load_reg( R_EAX, Rm );
nkeynes@395
  2453
    check_ralign32( R_EAX );
nkeynes@939
  2454
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2455
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2456
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2458
:}
nkeynes@359
  2459
LDS Rm, MACL {:  
nkeynes@671
  2460
    COUNT_INST(I_LDS);
nkeynes@359
  2461
    load_reg( R_EAX, Rm );
nkeynes@359
  2462
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2463
:}
nkeynes@359
  2464
LDS.L @Rm+, MACL {:  
nkeynes@671
  2465
    COUNT_INST(I_LDSM);
nkeynes@359
  2466
    load_reg( R_EAX, Rm );
nkeynes@395
  2467
    check_ralign32( R_EAX );
nkeynes@939
  2468
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2469
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2470
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2471
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2472
:}
nkeynes@359
  2473
LDS Rm, PR {:  
nkeynes@671
  2474
    COUNT_INST(I_LDS);
nkeynes@359
  2475
    load_reg( R_EAX, Rm );
nkeynes@359
  2476
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2477
:}
nkeynes@359
  2478
LDS.L @Rm+, PR {:  
nkeynes@671
  2479
    COUNT_INST(I_LDSM);
nkeynes@359
  2480
    load_reg( R_EAX, Rm );
nkeynes@395
  2481
    check_ralign32( R_EAX );
nkeynes@939
  2482
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2483
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2484
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2486
:}
nkeynes@550
  2487
LDTLB {:  
nkeynes@671
  2488
    COUNT_INST(I_LDTLB);
nkeynes@553
  2489
    call_func0( MMU_ldtlb );
nkeynes@875
  2490
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2491
:}
nkeynes@671
  2492
OCBI @Rn {:
nkeynes@671
  2493
    COUNT_INST(I_OCBI);
nkeynes@671
  2494
:}
nkeynes@671
  2495
OCBP @Rn {:
nkeynes@671
  2496
    COUNT_INST(I_OCBP);
nkeynes@671
  2497
:}
nkeynes@671
  2498
OCBWB @Rn {:
nkeynes@671
  2499
    COUNT_INST(I_OCBWB);
nkeynes@671
  2500
:}
nkeynes@374
  2501
PREF @Rn {:
nkeynes@671
  2502
    COUNT_INST(I_PREF);
nkeynes@374
  2503
    load_reg( R_EAX, Rn );
nkeynes@532
  2504
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2505
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2506
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2507
    JNE_rel8(end);
nkeynes@911
  2508
    if( sh4_x86.tlb_on ) {
nkeynes@911
  2509
    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
nkeynes@911
  2510
        TEST_r32_r32( R_EAX, R_EAX );
nkeynes@911
  2511
        JE_exc(-1);
nkeynes@911
  2512
    } else {
nkeynes@911
  2513
    	call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@911
  2514
   	}
nkeynes@380
  2515
    JMP_TARGET(end);
nkeynes@417
  2516
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2517
:}
nkeynes@388
  2518
SLEEP {: 
nkeynes@671
  2519
    COUNT_INST(I_SLEEP);
nkeynes@388
  2520
    check_priv();
nkeynes@388
  2521
    call_func0( sh4_sleep );
nkeynes@417
  2522
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2523
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2524
    return 2;
nkeynes@388
  2525
:}
nkeynes@386
  2526
STC SR, Rn {:
nkeynes@671
  2527
    COUNT_INST(I_STCSR);
nkeynes@386
  2528
    check_priv();
nkeynes@386
  2529
    call_func0(sh4_read_sr);
nkeynes@386
  2530
    store_reg( R_EAX, Rn );
nkeynes@417
  2531
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2532
:}
nkeynes@359
  2533
STC GBR, Rn {:  
nkeynes@671
  2534
    COUNT_INST(I_STC);
nkeynes@359
  2535
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2536
    store_reg( R_EAX, Rn );
nkeynes@359
  2537
:}
nkeynes@359
  2538
STC VBR, Rn {:  
nkeynes@671
  2539
    COUNT_INST(I_STC);
nkeynes@386
  2540
    check_priv();
nkeynes@359
  2541
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2542
    store_reg( R_EAX, Rn );
nkeynes@417
  2543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2544
:}
nkeynes@359
  2545
STC SSR, Rn {:  
nkeynes@671
  2546
    COUNT_INST(I_STC);
nkeynes@386
  2547
    check_priv();
nkeynes@359
  2548
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2549
    store_reg( R_EAX, Rn );
nkeynes@417
  2550
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2551
:}
nkeynes@359
  2552
STC SPC, Rn {:  
nkeynes@671
  2553
    COUNT_INST(I_STC);
nkeynes@386
  2554
    check_priv();
nkeynes@359
  2555
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2556
    store_reg( R_EAX, Rn );
nkeynes@417
  2557
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2558
:}
nkeynes@359
  2559
STC SGR, Rn {:  
nkeynes@671
  2560
    COUNT_INST(I_STC);
nkeynes@386
  2561
    check_priv();
nkeynes@359
  2562
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2563
    store_reg( R_EAX, Rn );
nkeynes@417
  2564
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2565
:}
nkeynes@359
  2566
STC DBR, Rn {:  
nkeynes@671
  2567
    COUNT_INST(I_STC);
nkeynes@386
  2568
    check_priv();
nkeynes@359
  2569
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2570
    store_reg( R_EAX, Rn );
nkeynes@417
  2571
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2572
:}
nkeynes@374
  2573
STC Rm_BANK, Rn {:
nkeynes@671
  2574
    COUNT_INST(I_STC);
nkeynes@386
  2575
    check_priv();
nkeynes@374
  2576
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2577
    store_reg( R_EAX, Rn );
nkeynes@417
  2578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2579
:}
nkeynes@374
  2580
STC.L SR, @-Rn {:
nkeynes@671
  2581
    COUNT_INST(I_STCSRM);
nkeynes@586
  2582
    check_priv();
nkeynes@939
  2583
    call_func0( sh4_read_sr );
nkeynes@939
  2584
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@586
  2585
    load_reg( R_EAX, Rn );
nkeynes@586
  2586
    check_walign32( R_EAX );
nkeynes@939
  2587
    LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@939
  2588
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2589
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2591
:}
nkeynes@359
  2592
STC.L VBR, @-Rn {:  
nkeynes@671
  2593
    COUNT_INST(I_STCM);
nkeynes@586
  2594
    check_priv();
nkeynes@586
  2595
    load_reg( R_EAX, Rn );
nkeynes@586
  2596
    check_walign32( R_EAX );
nkeynes@586
  2597
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2598
    load_spreg( R_EDX, R_VBR );
nkeynes@939
  2599
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2600
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2602
:}
nkeynes@359
  2603
STC.L SSR, @-Rn {:  
nkeynes@671
  2604
    COUNT_INST(I_STCM);
nkeynes@586
  2605
    check_priv();
nkeynes@586
  2606
    load_reg( R_EAX, Rn );
nkeynes@586
  2607
    check_walign32( R_EAX );
nkeynes@586
  2608
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2609
    load_spreg( R_EDX, R_SSR );
nkeynes@939
  2610
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2611
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2613
:}
nkeynes@416
  2614
STC.L SPC, @-Rn {:
nkeynes@671
  2615
    COUNT_INST(I_STCM);
nkeynes@586
  2616
    check_priv();
nkeynes@586
  2617
    load_reg( R_EAX, Rn );
nkeynes@586
  2618
    check_walign32( R_EAX );
nkeynes@586
  2619
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2620
    load_spreg( R_EDX, R_SPC );
nkeynes@939
  2621
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2622
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2623
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2624
:}
nkeynes@359
  2625
STC.L SGR, @-Rn {:  
nkeynes@671
  2626
    COUNT_INST(I_STCM);
nkeynes@586
  2627
    check_priv();
nkeynes@586
  2628
    load_reg( R_EAX, Rn );
nkeynes@586
  2629
    check_walign32( R_EAX );
nkeynes@586
  2630
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2631
    load_spreg( R_EDX, R_SGR );
nkeynes@939
  2632
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2633
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2634
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2635
:}
nkeynes@359
  2636
STC.L DBR, @-Rn {:  
nkeynes@671
  2637
    COUNT_INST(I_STCM);
nkeynes@586
  2638
    check_priv();
nkeynes@586
  2639
    load_reg( R_EAX, Rn );
nkeynes@586
  2640
    check_walign32( R_EAX );
nkeynes@586
  2641
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2642
    load_spreg( R_EDX, R_DBR );
nkeynes@939
  2643
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2644
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2645
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2646
:}
nkeynes@374
  2647
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2648
    COUNT_INST(I_STCM);
nkeynes@586
  2649
    check_priv();
nkeynes@586
  2650
    load_reg( R_EAX, Rn );
nkeynes@586
  2651
    check_walign32( R_EAX );
nkeynes@586
  2652
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2653
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@939
  2654
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2655
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2656
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2657
:}
nkeynes@359
  2658
STC.L GBR, @-Rn {:  
nkeynes@671
  2659
    COUNT_INST(I_STCM);
nkeynes@586
  2660
    load_reg( R_EAX, Rn );
nkeynes@586
  2661
    check_walign32( R_EAX );
nkeynes@586
  2662
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2663
    load_spreg( R_EDX, R_GBR );
nkeynes@939
  2664
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2665
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2667
:}
nkeynes@359
  2668
STS FPSCR, Rn {:  
nkeynes@673
  2669
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2670
    check_fpuen();
nkeynes@359
  2671
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2672
    store_reg( R_EAX, Rn );
nkeynes@359
  2673
:}
nkeynes@359
  2674
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2675
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2676
    check_fpuen();
nkeynes@586
  2677
    load_reg( R_EAX, Rn );
nkeynes@586
  2678
    check_walign32( R_EAX );
nkeynes@586
  2679
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2680
    load_spreg( R_EDX, R_FPSCR );
nkeynes@939
  2681
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2682
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2683
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2684
:}
nkeynes@359
  2685
STS FPUL, Rn {:  
nkeynes@671
  2686
    COUNT_INST(I_STS);
nkeynes@626
  2687
    check_fpuen();
nkeynes@359
  2688
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2689
    store_reg( R_EAX, Rn );
nkeynes@359
  2690
:}
nkeynes@359
  2691
STS.L FPUL, @-Rn {:  
nkeynes@671
  2692
    COUNT_INST(I_STSM);
nkeynes@626
  2693
    check_fpuen();
nkeynes@586
  2694
    load_reg( R_EAX, Rn );
nkeynes@586
  2695
    check_walign32( R_EAX );
nkeynes@586
  2696
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2697
    load_spreg( R_EDX, R_FPUL );
nkeynes@939
  2698
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2699
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2700
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2701
:}
nkeynes@359
  2702
STS MACH, Rn {:  
nkeynes@671
  2703
    COUNT_INST(I_STS);
nkeynes@359
  2704
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2705
    store_reg( R_EAX, Rn );
nkeynes@359
  2706
:}
nkeynes@359
  2707
STS.L MACH, @-Rn {:  
nkeynes@671
  2708
    COUNT_INST(I_STSM);
nkeynes@586
  2709
    load_reg( R_EAX, Rn );
nkeynes@586
  2710
    check_walign32( R_EAX );
nkeynes@586
  2711
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2712
    load_spreg( R_EDX, R_MACH );
nkeynes@939
  2713
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2714
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2715
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2716
:}
nkeynes@359
  2717
STS MACL, Rn {:  
nkeynes@671
  2718
    COUNT_INST(I_STS);
nkeynes@359
  2719
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2720
    store_reg( R_EAX, Rn );
nkeynes@359
  2721
:}
nkeynes@359
  2722
STS.L MACL, @-Rn {:  
nkeynes@671
  2723
    COUNT_INST(I_STSM);
nkeynes@586
  2724
    load_reg( R_EAX, Rn );
nkeynes@586
  2725
    check_walign32( R_EAX );
nkeynes@586
  2726
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2727
    load_spreg( R_EDX, R_MACL );
nkeynes@939
  2728
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2729
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2730
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2731
:}
nkeynes@359
  2732
STS PR, Rn {:  
nkeynes@671
  2733
    COUNT_INST(I_STS);
nkeynes@359
  2734
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2735
    store_reg( R_EAX, Rn );
nkeynes@359
  2736
:}
nkeynes@359
  2737
STS.L PR, @-Rn {:  
nkeynes@671
  2738
    COUNT_INST(I_STSM);
nkeynes@586
  2739
    load_reg( R_EAX, Rn );
nkeynes@586
  2740
    check_walign32( R_EAX );
nkeynes@586
  2741
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@930
  2742
    load_spreg( R_EDX, R_PR );