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lxdream.org :: lxdream/src/sh4/timer.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/timer.c
changeset 260:c82e26ec0cac
prev115:699aa8916803
next264:e3b8a3ab32b8
author nkeynes
date Wed Jan 03 09:00:17 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Adjust timers when they're read rather than waiting until the next time
slice. Also temporarily cut the CPU time by 4.
Initialize the FRQCR register to 0x0E0A for convenience
file annotate diff log raw
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/**
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 * $Id: timer.c,v 1.5 2007-01-03 09:00:17 nkeynes Exp $
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 * 
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 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
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 * keep things simple (they intertwine a bit).
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include "dream.h"
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#include "mem.h"
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#include "clock.h"
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#include "sh4core.h"
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#include "sh4mmio.h"
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#include "intc.h"
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/********************************* CPG *************************************/
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/* This is the base clock from which all other clocks are derived */
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uint32_t sh4_input_freq = SH4_BASE_RATE;
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uint32_t sh4_cpu_freq = SH4_BASE_RATE;
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uint32_t sh4_bus_freq = SH4_BASE_RATE;
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uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
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uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
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uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
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uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
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int32_t mmio_region_CPG_read( uint32_t reg )
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{
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    return MMIO_READ( CPG, reg );
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}
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/* CPU + bus dividers (note officially only the first 6 values are valid) */
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int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
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/* Peripheral clock dividers (only first 5 are officially valid) */
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int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
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void mmio_region_CPG_write( uint32_t reg, uint32_t val )
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{
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    uint32_t div;
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    switch( reg ) {
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    case FRQCR: /* Frequency control */
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	div = ifc_divider[(val >> 6) & 0x07];
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	sh4_cpu_freq = sh4_input_freq / div;
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	sh4_cpu_period = 4000 * div / sh4_input_freq;
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	div = ifc_divider[(val >> 3) & 0x07];
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	sh4_bus_freq = sh4_input_freq / div;
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	sh4_bus_period = 1000 * div / sh4_input_freq;
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	div = pfc_divider[val & 0x07];
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	sh4_peripheral_freq = sh4_input_freq / div;
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	sh4_peripheral_period = 1000 * div / sh4_input_freq;
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	/* Update everything that depends on the peripheral frequency */
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	SCIF_update_line_speed();
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	break;
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    case WTCSR: /* Watchdog timer */
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	break;
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    }
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    MMIO_WRITE( CPG, reg, val );
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}
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/**
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 * We don't really know what the default reset value is as it's determined
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 * by the mode select pins. This is the standard value that the BIOS sets,
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 * however, so it works for now.
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 */
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void CPG_reset( )
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{
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    mmio_region_CPG_write( FRQCR, 0x0E0A );
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}
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/********************************** RTC *************************************/
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uint32_t rtc_output_period;
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int32_t mmio_region_RTC_read( uint32_t reg )
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{
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    return MMIO_READ( RTC, reg );
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}
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void mmio_region_RTC_write( uint32_t reg, uint32_t val )
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{
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    MMIO_WRITE( RTC, reg, val );
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}
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/********************************** TMU *************************************/
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uint32_t TMU_count( int timer, uint32_t nanosecs );
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#define TCR_ICPF 0x0200
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#define TCR_UNF  0x0100
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#define TCR_UNIE 0x0020
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#define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
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struct TMU_timer {
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    uint32_t timer_period;
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    uint32_t timer_remainder; /* left-over cycles from last count */
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    uint32_t timer_run; /* cycles already run from this slice */
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};
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struct TMU_timer TMU_timers[3];
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int32_t mmio_region_TMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case TCNT0:
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	TMU_count( 0, sh4r.slice_cycle );
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	TMU_timers[0].timer_run = sh4r.slice_cycle;
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	break;
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    case TCNT1:
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	TMU_count( 1, sh4r.slice_cycle );
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	TMU_timers[1].timer_run = sh4r.slice_cycle;
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	break;
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    case TCNT2:
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	TMU_count( 2, sh4r.slice_cycle );
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	TMU_timers[2].timer_run = sh4r.slice_cycle;
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	break;
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    }
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    return MMIO_READ( TMU, reg );
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}
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void TMU_set_timer_control( int timer,  int tcr )
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{
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    uint32_t period = 1;
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    uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
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    if( (oldtcr & TCR_UNF) == 0 ) {
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	tcr = tcr & (~TCR_UNF);
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    } else {
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	if( (oldtcr & TCR_UNIE == 0) && 
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	    (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
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	    intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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	} else if( (oldtcr & TCR_UNIE) != 0 && 
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		   (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
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	    intc_clear_interrupt( INT_TMU_TUNI0 + timer );
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	}
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    }
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    switch( tcr & 0x07 ) {
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    case 0:
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	period = sh4_peripheral_period << 2 ;
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	break;
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    case 1: 
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	period = sh4_peripheral_period << 4;
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	break;
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    case 2:
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	period = sh4_peripheral_period << 6;
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	break;
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    case 3: 
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	period = sh4_peripheral_period << 8;
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	break;
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    case 4:
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	period = sh4_peripheral_period << 10;
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	break;
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    case 5:
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	/* Illegal value. */
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	ERROR( "TMU %d period set to illegal value (5)", timer );
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	period = sh4_peripheral_period << 12; /* for something to do */
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	break;
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    case 6:
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	period = rtc_output_period;
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	break;
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    case 7:
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	/* External clock... Hrm? */
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	period = sh4_peripheral_period; /* I dunno... */
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	break;
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    }
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    TMU_timers[timer].timer_period = period;
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    MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
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}
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void TMU_start( int timer )
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{
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    TMU_timers[timer].timer_run = sh4r.slice_cycle;
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    TMU_timers[timer].timer_remainder = 0;
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}
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void TMU_stop( int timer )
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{
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}
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/**
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 * Count the specified timer for a given number of nanoseconds.
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 */
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uint32_t TMU_count( int timer, uint32_t nanosecs ) 
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{
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    nanosecs = nanosecs + TMU_timers[timer].timer_remainder -
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	TMU_timers[timer].timer_run;
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    TMU_timers[timer].timer_remainder = 
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	nanosecs % TMU_timers[timer].timer_period;
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    uint32_t count = nanosecs / TMU_timers[timer].timer_period;
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    uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
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    uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
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    if( count > value ) {
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	uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
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	tcr |= TCR_UNF;
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	count -= value;
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        value = reset - (count % reset);
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	MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
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	if( tcr & TCR_UNIE ) 
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	    intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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    } else {
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	value -= count;
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    }
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    MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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    return value;
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}
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void mmio_region_TMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t oldval;
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    int i;
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    switch( reg ) {
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    case TSTR:
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	oldval = MMIO_READ( TMU, TSTR );
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	for( i=0; i<3; i++ ) {
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	    uint32_t tmp = 1<<i;
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	    if( (oldval & tmp) == 1 && (val&tmp) == 0  )
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		TMU_stop(i);
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	    else if( (oldval&tmp) == 0 && (val&tmp) == 1 )
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		TMU_start(i);
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	}
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	break;
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    case TCR0:
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	TMU_set_timer_control( 0, val );
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	return;
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    case TCR1:
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	TMU_set_timer_control( 1, val );
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	return;
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    case TCR2:
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	TMU_set_timer_control( 2, val );
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	return;
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    }
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    MMIO_WRITE( TMU, reg, val );
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}
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void TMU_run_slice( uint32_t nanosecs )
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{
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    int tcr = MMIO_READ( TMU, TSTR );
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    if( tcr & 0x01 ) {
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	TMU_count( 0, nanosecs );
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	TMU_timers[0].timer_run = 0;
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    }
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    if( tcr & 0x02 ) {
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	TMU_count( 1, nanosecs );
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	TMU_timers[1].timer_run = 0;
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    }
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    if( tcr & 0x04 ) {
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	TMU_count( 2, nanosecs );
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	TMU_timers[2].timer_run = 0;
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    }
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}
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void TMU_update_clocks()
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{
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    TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
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    TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
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    TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
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}
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void TMU_reset( )
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{
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    TMU_timers[0].timer_remainder = 0;
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    TMU_timers[0].timer_run = 0;
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    TMU_timers[1].timer_remainder = 0;
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    TMU_timers[1].timer_run = 0;
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    TMU_timers[2].timer_remainder = 0;
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    TMU_timers[2].timer_run = 0;
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    TMU_update_clocks();
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}
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void TMU_save_state( FILE *f ) {
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    fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
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}
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int TMU_load_state( FILE *f ) 
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{
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    fread( &TMU_timers, sizeof(TMU_timers), 1, f );
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    return 0;
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}
.