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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1298:d0eb2307b847
prev1292:799fdd4f704a
next1301:b76840ccf94b
author nkeynes
date Wed Feb 04 08:38:23 2015 +1000 (5 years ago)
permissions -rw-r--r--
last change Fix assorted compile warnings reported by Clang
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4dasm.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "xlat/xlatdasm.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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#define SH4_MODE_UNKNOWN -1
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    uint8_t *code;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    uint32_t sh4_mode;     /* Mirror of sh4r.xlat_sh4_mode */
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    int tstate;
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    /* mode settings */
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    gboolean tlb_on; /* True if tlb translation is active */
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    struct mem_region_fn **priv_address_space;
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    struct mem_region_fn **user_address_space;
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    /* Instrumentation */
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    xlat_block_begin_callback_t begin_callback;
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    xlat_block_end_callback_t end_callback;
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    gboolean fastmem;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint8_t sh4_entry_stub[128];
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typedef FASTCALL void (*entry_point_t)(void *);
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entry_point_t sh4_translate_enter;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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static void sh4_x86_translate_unlink_block( void *use_list );
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static struct xlat_target_fns x86_target_fns = {
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	sh4_x86_translate_unlink_block
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};	
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_set_address_space( struct mem_region_fn **priv, struct mem_region_fn **user )
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{
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    sh4_x86.priv_address_space = priv;
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    sh4_x86.user_address_space = user;
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}
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void sh4_translate_write_entry_stub(void)
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{
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	mem_unprotect(sh4_entry_stub, sizeof(sh4_entry_stub));
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	xlat_output = sh4_entry_stub;
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	PUSH_r32(REG_EBP);
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	MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
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	PUSH_r32(REG_EBX);
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	PUSH_r32(REG_SAVE1);
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	PUSH_r32(REG_SAVE2);
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#if SIZEOF_VOID_P == 8
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    PUSH_r32(REG_SAVE3);
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    PUSH_r32(REG_SAVE4);
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    CALL_r32( REG_ARG1 );
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    POP_r32(REG_SAVE4);
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    POP_r32(REG_SAVE3);
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#else
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    SUBL_imms_r32( 8, REG_ESP ); 
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	CALL_r32( REG_ARG1 );
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	ADDL_imms_r32( 8, REG_ESP );
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#endif
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	POP_r32(REG_SAVE2);	
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	POP_r32(REG_SAVE1);
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	POP_r32(REG_EBX);
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	POP_r32(REG_EBP);
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	RET();
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	sh4_translate_enter = (entry_point_t)sh4_entry_stub;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.begin_callback = NULL;
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    sh4_x86.end_callback = NULL;
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    sh4_x86.fastmem = TRUE;
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    sh4_x86.sse3_enabled = is_sse3_supported();
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    xlat_set_target_fns(&x86_target_fns);
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    sh4_translate_set_address_space( sh4_address_space, sh4_user_address_space );
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    sh4_translate_write_entry_stub();
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}
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void sh4_translate_set_callbacks( xlat_block_begin_callback_t begin, xlat_block_end_callback_t end )
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{
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    sh4_x86.begin_callback = begin;
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    sh4_x86.end_callback = end;
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}
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void sh4_translate_set_fastmem( gboolean flag )
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{
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    sh4_x86.fastmem = flag;
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JBE_label(label) JCC_cc_rel8(X86_COND_BE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JP_label(label)  JCC_cc_rel8(X86_COND_P,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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#define LOAD_t() if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; }     
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) LOAD_t() \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) LOAD_t() \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991
   303
#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991
   304
#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   305
#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   306
#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   307
#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   308
#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   309
#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   310
#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991
   311
#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377
   312
nkeynes@991
   313
#ifdef ENABLE_SH4STATS
nkeynes@995
   314
#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991
   315
#else
nkeynes@991
   316
#define COUNT_INST(id)
nkeynes@991
   317
#endif
nkeynes@377
   318
nkeynes@374
   319
nkeynes@368
   320
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   321
nkeynes@416
   322
#define check_priv( ) \
nkeynes@1112
   323
    if( (sh4_x86.sh4_mode & SR_MD) == 0 ) { \
nkeynes@937
   324
        if( sh4_x86.in_delay_slot ) { \
nkeynes@1191
   325
            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2), 4 ); \
nkeynes@937
   326
        } else { \
nkeynes@1191
   327
            exit_block_exc(EXC_ILLEGAL, pc, 2); \
nkeynes@937
   328
        } \
nkeynes@956
   329
        sh4_x86.branch_taken = TRUE; \
nkeynes@937
   330
        sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@937
   331
        return 2; \
nkeynes@937
   332
    }
nkeynes@416
   333
nkeynes@416
   334
#define check_fpuen( ) \
nkeynes@416
   335
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   336
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995
   337
	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991
   338
	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416
   339
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   340
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   341
	} else {\
nkeynes@586
   342
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   343
	}\
nkeynes@875
   344
	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416
   345
    }
nkeynes@416
   346
nkeynes@586
   347
#define check_ralign16( x86reg ) \
nkeynes@991
   348
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   349
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   350
nkeynes@586
   351
#define check_walign16( x86reg ) \
nkeynes@991
   352
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   353
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   354
nkeynes@586
   355
#define check_ralign32( x86reg ) \
nkeynes@991
   356
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   357
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   358
nkeynes@586
   359
#define check_walign32( x86reg ) \
nkeynes@991
   360
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   361
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   362
nkeynes@732
   363
#define check_ralign64( x86reg ) \
nkeynes@991
   364
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   365
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732
   366
nkeynes@732
   367
#define check_walign64( x86reg ) \
nkeynes@991
   368
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   369
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732
   370
nkeynes@1125
   371
#define address_space() ((sh4_x86.sh4_mode&SR_MD) ? (uintptr_t)sh4_x86.priv_address_space : (uintptr_t)sh4_x86.user_address_space)
nkeynes@1004
   372
nkeynes@824
   373
#define UNDEF(ir)
nkeynes@939
   374
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@939
   375
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@586
   376
 */
nkeynes@941
   377
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   378
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   379
{
nkeynes@1292
   380
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1112
   381
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@1292
   382
        CALL1_r32disp_r32(REG_CALLPTR, offset, addr_reg);
nkeynes@995
   383
    } else {
nkeynes@995
   384
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   385
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   386
        }
nkeynes@995
   387
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   388
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   389
        CALL2_r32disp_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   390
    }
nkeynes@995
   391
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   392
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   393
    }
nkeynes@995
   394
}
nkeynes@995
   395
nkeynes@995
   396
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   397
{
nkeynes@1292
   398
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1112
   399
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@1292
   400
        CALL2_r32disp_r32_r32(REG_CALLPTR, offset, addr_reg, value_reg);
nkeynes@995
   401
    } else {
nkeynes@995
   402
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   403
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   404
	}        
nkeynes@995
   405
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   406
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   407
        }
nkeynes@995
   408
#if MAX_REG_ARG > 2        
nkeynes@995
   409
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   410
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   411
        CALL3_r32disp_r32_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   412
#else
nkeynes@995
   413
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   414
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@1292
   415
        CALL3_r32disp_r32_r32_r32(REG_CALLPTR, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   416
#endif
nkeynes@995
   417
    }
nkeynes@995
   418
}
nkeynes@995
   419
#else
nkeynes@995
   420
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   421
{
nkeynes@1292
   422
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1292
   423
    CALL1_r32disp_r32(REG_CALLPTR, offset, addr_reg);
nkeynes@995
   424
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   425
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   426
    }
nkeynes@995
   427
}     
nkeynes@995
   428
nkeynes@996
   429
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   430
{
nkeynes@1292
   431
    decode_address(address_space(), addr_reg, REG_CALLPTR);
nkeynes@1292
   432
    CALL2_r32disp_r32_r32(REG_CALLPTR, offset, addr_reg, value_reg);
nkeynes@995
   433
}
nkeynes@941
   434
#endif
nkeynes@939
   435
                
nkeynes@995
   436
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   437
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   438
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   439
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   440
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   441
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   442
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   443
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   444
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@368
   445
nkeynes@1191
   446
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@539
   447
nkeynes@1182
   448
/** Offset of xlat_sh4_mode field relative to the code pointer */ 
nkeynes@1186
   449
#define XLAT_SH4_MODE_CODE_OFFSET  (int32_t)(offsetof(struct xlat_cache_block, xlat_sh4_mode) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   450
#define XLAT_CHAIN_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, chain) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   451
#define XLAT_ACTIVE_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, active) - offsetof(struct xlat_cache_block,code) )
nkeynes@1182
   452
nkeynes@901
   453
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   454
{
nkeynes@1112
   455
	sh4_x86.code = xlat_output;
nkeynes@901
   456
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   457
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   458
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   459
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   460
    sh4_x86.block_start_pc = pc;
nkeynes@939
   461
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   463
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   464
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@1112
   465
    sh4_x86.sh4_mode = sh4r.xlat_sh4_mode;
nkeynes@1125
   466
    if( sh4_x86.begin_callback ) {
nkeynes@1125
   467
        CALL_ptr( sh4_x86.begin_callback );
nkeynes@1125
   468
    }
nkeynes@1218
   469
    if( sh4_profile_blocks ) {
nkeynes@1186
   470
    	MOVP_immptr_rptr( sh4_x86.code + XLAT_ACTIVE_CODE_OFFSET, REG_EAX );
nkeynes@1182
   471
    	ADDL_imms_r32disp( 1, REG_EAX, 0 );
nkeynes@1182
   472
    }  
nkeynes@901
   473
}
nkeynes@901
   474
nkeynes@901
   475
nkeynes@593
   476
uint32_t sh4_translate_end_block_size()
nkeynes@593
   477
{
nkeynes@1196
   478
	uint32_t epilogue_size = EPILOGUE_SIZE;
nkeynes@1196
   479
	if( sh4_x86.end_callback ) {
nkeynes@1196
   480
	    epilogue_size += (CALL1_PTR_MIN_SIZE - 1);
nkeynes@1196
   481
	}
nkeynes@596
   482
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1196
   483
        epilogue_size += (sh4_x86.backpatch_posn*(12+CALL1_PTR_MIN_SIZE));
nkeynes@596
   484
    } else {
nkeynes@1196
   485
        epilogue_size += (3*(12+CALL1_PTR_MIN_SIZE)) + (sh4_x86.backpatch_posn-3)*(15+CALL1_PTR_MIN_SIZE);
nkeynes@596
   486
    }
nkeynes@1196
   487
    return epilogue_size;
nkeynes@593
   488
}
nkeynes@593
   489
nkeynes@593
   490
nkeynes@590
   491
/**
nkeynes@590
   492
 * Embed a breakpoint into the generated code
nkeynes@590
   493
 */
nkeynes@586
   494
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   495
{
nkeynes@995
   496
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   497
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   499
}
nkeynes@590
   500
nkeynes@601
   501
nkeynes@601
   502
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   503
nkeynes@1112
   504
/**
nkeynes@1112
   505
 * Test if the loaded target code pointer in %eax is valid, and if so jump
nkeynes@1112
   506
 * directly into it, bypassing the normal exit.
nkeynes@1112
   507
 */
nkeynes@1112
   508
static void jump_next_block()
nkeynes@1112
   509
{
nkeynes@1149
   510
	uint8_t *ptr = xlat_output;
nkeynes@1112
   511
	TESTP_rptr_rptr(REG_EAX, REG_EAX);
nkeynes@1112
   512
	JE_label(nocode);
nkeynes@1112
   513
	if( sh4_x86.sh4_mode == SH4_MODE_UNKNOWN ) {
nkeynes@1112
   514
	    /* sr/fpscr was changed, possibly updated xlat_sh4_mode, so reload it */
nkeynes@1112
   515
	    MOVL_rbpdisp_r32( REG_OFFSET(xlat_sh4_mode), REG_ECX );
nkeynes@1112
   516
	    CMPL_r32_r32disp( REG_ECX, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   517
	} else {
nkeynes@1112
   518
	    CMPL_imms_r32disp( sh4_x86.sh4_mode, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   519
	}
nkeynes@1112
   520
	JNE_label(wrongmode);
nkeynes@1125
   521
	if( sh4_x86.end_callback ) {
nkeynes@1125
   522
	    /* Note this does leave the stack out of alignment, but doesn't matter
nkeynes@1125
   523
	     * for what we're currently using it for.
nkeynes@1125
   524
	     */
nkeynes@1125
   525
	    PUSH_r32(REG_EAX);
nkeynes@1125
   526
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   527
	    JMP_rptr(REG_ECX);
nkeynes@1125
   528
	} else {
nkeynes@1125
   529
	    JMP_rptr(REG_EAX);
nkeynes@1125
   530
	}
nkeynes@1149
   531
	JMP_TARGET(wrongmode);
nkeynes@1176
   532
	MOVP_rptrdisp_rptr( REG_EAX, XLAT_CHAIN_CODE_OFFSET, REG_EAX );
nkeynes@1149
   533
	int rel = ptr - xlat_output;
nkeynes@1149
   534
    JMP_prerel(rel);
nkeynes@1149
   535
	JMP_TARGET(nocode); 
nkeynes@1112
   536
}
nkeynes@1112
   537
nkeynes@1186
   538
/**
nkeynes@1186
   539
 * 
nkeynes@1186
   540
 */
nkeynes@1263
   541
void FASTCALL sh4_translate_link_block( uint32_t pc )
nkeynes@1186
   542
{
nkeynes@1186
   543
    uint8_t *target = (uint8_t *)xlat_get_code_by_vma(pc);
nkeynes@1186
   544
    while( target != NULL && sh4r.xlat_sh4_mode != XLAT_BLOCK_MODE(target) ) {
nkeynes@1186
   545
        target = XLAT_BLOCK_CHAIN(target);
nkeynes@1186
   546
	}
nkeynes@1186
   547
    if( target == NULL ) {
nkeynes@1186
   548
        target = sh4_translate_basic_block( pc );
nkeynes@1186
   549
    }
nkeynes@1186
   550
    uint8_t *backpatch = ((uint8_t *)__builtin_return_address(0)) - (CALL1_PTR_MIN_SIZE);
nkeynes@1186
   551
    *backpatch = 0xE9;
nkeynes@1292
   552
    *(uint32_t *)(backpatch+1) = (uint32_t)(target-backpatch)-5;
nkeynes@1186
   553
    *(void **)(backpatch+5) = XLAT_BLOCK_FOR_CODE(target)->use_list;
nkeynes@1186
   554
    XLAT_BLOCK_FOR_CODE(target)->use_list = backpatch; 
nkeynes@1186
   555
nkeynes@1198
   556
    uint8_t * volatile *retptr = ((uint8_t * volatile *)__builtin_frame_address(0))+1;
nkeynes@1186
   557
    assert( *retptr == ((uint8_t *)__builtin_return_address(0)) );
nkeynes@1186
   558
	*retptr = backpatch;
nkeynes@1186
   559
}
nkeynes@1186
   560
nkeynes@1186
   561
static void emit_translate_and_backpatch()
nkeynes@1186
   562
{
nkeynes@1186
   563
    /* NB: this is either 7 bytes (i386) or 12 bytes (x86-64) */
nkeynes@1263
   564
    CALL1_ptr_r32(sh4_translate_link_block, REG_ARG1);
nkeynes@1186
   565
nkeynes@1186
   566
    /* When patched, the jmp instruction will be 5 bytes (either platform) -
nkeynes@1186
   567
     * we need to reserve sizeof(void*) bytes for the use-list
nkeynes@1186
   568
	 * pointer
nkeynes@1186
   569
	 */ 
nkeynes@1186
   570
    if( sizeof(void*) == 8 ) {
nkeynes@1186
   571
        NOP();
nkeynes@1186
   572
    } else {
nkeynes@1186
   573
        NOP2();
nkeynes@1186
   574
    }
nkeynes@1186
   575
}
nkeynes@1186
   576
nkeynes@1186
   577
/**
nkeynes@1186
   578
 * If we're jumping to a fixed address (or at least fixed relative to the
nkeynes@1186
   579
 * current PC, then we can do a direct branch. REG_ARG1 should contain
nkeynes@1186
   580
 * the PC at this point.
nkeynes@1186
   581
 */
nkeynes@1186
   582
static void jump_next_block_fixed_pc( sh4addr_t pc )
nkeynes@1186
   583
{
nkeynes@1186
   584
	if( IS_IN_ICACHE(pc) ) {
nkeynes@1194
   585
	    if( sh4_x86.sh4_mode != SH4_MODE_UNKNOWN && sh4_x86.end_callback == NULL ) {
nkeynes@1186
   586
	        /* Fixed address, in cache, and fixed SH4 mode - generate a call to the
nkeynes@1186
   587
	         * fetch-and-backpatch routine, which will replace the call with a branch */
nkeynes@1186
   588
           emit_translate_and_backpatch();	         
nkeynes@1186
   589
           return;
nkeynes@1186
   590
		} else {
nkeynes@1186
   591
            MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@1186
   592
            ANDP_imms_rptr( -4, REG_EAX );
nkeynes@1186
   593
        }
nkeynes@1186
   594
	} else if( sh4_x86.tlb_on ) {
nkeynes@1186
   595
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@1186
   596
    } else {
nkeynes@1186
   597
        CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@1186
   598
    }
nkeynes@1186
   599
    jump_next_block();
nkeynes@1186
   600
nkeynes@1186
   601
nkeynes@1186
   602
}
nkeynes@1186
   603
nkeynes@1214
   604
static void sh4_x86_translate_unlink_block( void *use_list )
nkeynes@1186
   605
{
nkeynes@1186
   606
	uint8_t *tmp = xlat_output; /* In case something is active, which should never happen */
nkeynes@1186
   607
	void *next = use_list;
nkeynes@1186
   608
	while( next != NULL ) {
nkeynes@1186
   609
    	xlat_output = (uint8_t *)next;
nkeynes@1186
   610
 	    next = *(void **)(xlat_output+5);
nkeynes@1186
   611
 		emit_translate_and_backpatch();
nkeynes@1186
   612
 	}
nkeynes@1186
   613
 	xlat_output = tmp;
nkeynes@1186
   614
}
nkeynes@1186
   615
nkeynes@1186
   616
nkeynes@1186
   617
nkeynes@1125
   618
static void exit_block()
nkeynes@1125
   619
{
nkeynes@1125
   620
	if( sh4_x86.end_callback ) {
nkeynes@1125
   621
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   622
	    JMP_rptr(REG_ECX);
nkeynes@1125
   623
	} else {
nkeynes@1125
   624
	    RET();
nkeynes@1125
   625
	}
nkeynes@1125
   626
}
nkeynes@1125
   627
nkeynes@590
   628
/**
nkeynes@995
   629
 * Exit the block with sh4r.pc already written
nkeynes@995
   630
 */
nkeynes@995
   631
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   632
{
nkeynes@995
   633
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   634
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   635
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   636
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   637
    JBE_label(exitloop);
nkeynes@995
   638
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   639
    if( sh4_x86.tlb_on ) {
nkeynes@995
   640
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   641
    } else {
nkeynes@995
   642
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   643
    }
nkeynes@1112
   644
    
nkeynes@1112
   645
    jump_next_block();
nkeynes@1112
   646
    JMP_TARGET(exitloop);
nkeynes@995
   647
    exit_block();
nkeynes@995
   648
}
nkeynes@995
   649
nkeynes@995
   650
/**
nkeynes@995
   651
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   652
 */
nkeynes@995
   653
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   654
{
nkeynes@995
   655
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   656
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   657
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   658
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   659
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   660
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   661
    JBE_label(exitloop);
nkeynes@995
   662
    if( sh4_x86.tlb_on ) {
nkeynes@995
   663
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   664
    } else {
nkeynes@995
   665
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   666
    }
nkeynes@1112
   667
	
nkeynes@1112
   668
	jump_next_block();
nkeynes@1112
   669
    JMP_TARGET(exitloop);
nkeynes@995
   670
    exit_block();
nkeynes@995
   671
}
nkeynes@995
   672
nkeynes@995
   673
nkeynes@995
   674
/**
nkeynes@995
   675
 * Exit the block to an absolute PC
nkeynes@995
   676
 */
nkeynes@995
   677
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   678
{
nkeynes@1112
   679
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   680
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   681
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   682
nkeynes@1112
   683
    MOVL_imm32_r32( pc, REG_ARG1 );
nkeynes@1112
   684
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   685
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   686
    JBE_label(exitloop);
nkeynes@1186
   687
    jump_next_block_fixed_pc(pc);    
nkeynes@1112
   688
    JMP_TARGET(exitloop);
nkeynes@995
   689
    exit_block();
nkeynes@995
   690
}
nkeynes@995
   691
nkeynes@995
   692
/**
nkeynes@995
   693
 * Exit the block to a relative PC
nkeynes@995
   694
 */
nkeynes@995
   695
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   696
{
nkeynes@1112
   697
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   698
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   699
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   700
nkeynes@1112
   701
	if( pc == sh4_x86.block_start_pc && sh4_x86.sh4_mode == sh4r.xlat_sh4_mode ) {
nkeynes@1112
   702
	    /* Special case for tight loops - the PC doesn't change, and
nkeynes@1112
   703
	     * we already know the target address. Just check events pending before
nkeynes@1112
   704
	     * looping.
nkeynes@1112
   705
	     */
nkeynes@1112
   706
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1292
   707
        uint32_t backdisp = ((uintptr_t)(sh4_x86.code - xlat_output));
nkeynes@1112
   708
        JCC_cc_prerel(X86_COND_A, backdisp);
nkeynes@1112
   709
	} else {
nkeynes@1112
   710
        MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ARG1 );
nkeynes@1112
   711
        ADDL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@1112
   712
        MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   713
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   714
        JBE_label(exitloop2);
nkeynes@1186
   715
        
nkeynes@1186
   716
        jump_next_block_fixed_pc(pc);
nkeynes@1112
   717
        JMP_TARGET(exitloop2);
nkeynes@995
   718
    }
nkeynes@995
   719
    exit_block();
nkeynes@995
   720
}
nkeynes@995
   721
nkeynes@995
   722
/**
nkeynes@995
   723
 * Exit unconditionally with a general exception
nkeynes@995
   724
 */
nkeynes@1191
   725
void exit_block_exc( int code, sh4addr_t pc, int inst_adjust )
nkeynes@995
   726
{
nkeynes@995
   727
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   728
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@1191
   729
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc + inst_adjust)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   730
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   731
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   732
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   733
    exit_block();
nkeynes@995
   734
}    
nkeynes@995
   735
nkeynes@995
   736
/**
nkeynes@590
   737
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   738
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   739
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   740
 *
nkeynes@601
   741
 * Performs:
nkeynes@601
   742
 *   Set PC = endpc
nkeynes@601
   743
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   744
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   745
 *   Call sh4_execute_instruction
nkeynes@601
   746
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   747
 */
nkeynes@601
   748
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   749
{
nkeynes@995
   750
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   751
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   752
    
nkeynes@995
   753
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   754
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   755
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   756
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   757
nkeynes@1112
   758
    CALL_ptr( sh4_execute_instruction );
nkeynes@926
   759
    exit_block();
nkeynes@590
   760
} 
nkeynes@539
   761
nkeynes@359
   762
/**
nkeynes@995
   763
 * Write the block trailer (exception handling block)
nkeynes@995
   764
 */
nkeynes@995
   765
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   766
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   767
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   768
        exit_block_rel( pc, pc );
nkeynes@995
   769
    }
nkeynes@995
   770
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   771
        unsigned int i;
nkeynes@995
   772
        // Exception raised - cleanup and exit
nkeynes@995
   773
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   774
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   775
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   776
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   777
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@1191
   778
        INC_r32( REG_EDX );  /* Add 1 for the aborting instruction itself */ 
nkeynes@995
   779
        MULL_r32( REG_EDX );
nkeynes@995
   780
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   781
        exit_block();
nkeynes@995
   782
nkeynes@995
   783
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   784
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   785
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   786
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   787
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   788
                } else {
nkeynes@995
   789
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   790
                }
nkeynes@995
   791
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   792
                int rel = end_ptr - xlat_output;
nkeynes@995
   793
                JMP_prerel(rel);
nkeynes@995
   794
            } else {
nkeynes@995
   795
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   796
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   797
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   798
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   799
                int rel = end_ptr - xlat_output;
nkeynes@995
   800
                JMP_prerel(rel);
nkeynes@995
   801
            }
nkeynes@995
   802
        }
nkeynes@995
   803
    }
nkeynes@995
   804
}
nkeynes@539
   805
nkeynes@359
   806
/**
nkeynes@359
   807
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   808
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   809
 * 
nkeynes@586
   810
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   811
 *
nkeynes@359
   812
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   813
 * (eg a branch or 
nkeynes@359
   814
 */
nkeynes@590
   815
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   816
{
nkeynes@388
   817
    uint32_t ir;
nkeynes@586
   818
    /* Read instruction from icache */
nkeynes@586
   819
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   820
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   821
    
nkeynes@586
   822
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   823
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   824
    }
nkeynes@1003
   825
    
nkeynes@1003
   826
    /* check for breakpoints at this pc */
nkeynes@1003
   827
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   828
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   829
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   830
            break;
nkeynes@1003
   831
        }
nkeynes@571
   832
    }
nkeynes@359
   833
%%
nkeynes@359
   834
/* ALU operations */
nkeynes@359
   835
ADD Rm, Rn {:
nkeynes@671
   836
    COUNT_INST(I_ADD);
nkeynes@991
   837
    load_reg( REG_EAX, Rm );
nkeynes@991
   838
    load_reg( REG_ECX, Rn );
nkeynes@991
   839
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   840
    store_reg( REG_ECX, Rn );
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   842
:}
nkeynes@359
   843
ADD #imm, Rn {:  
nkeynes@671
   844
    COUNT_INST(I_ADDI);
nkeynes@991
   845
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   846
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   847
:}
nkeynes@359
   848
ADDC Rm, Rn {:
nkeynes@671
   849
    COUNT_INST(I_ADDC);
nkeynes@417
   850
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   851
        LDC_t();
nkeynes@417
   852
    }
nkeynes@991
   853
    load_reg( REG_EAX, Rm );
nkeynes@991
   854
    load_reg( REG_ECX, Rn );
nkeynes@991
   855
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   856
    store_reg( REG_ECX, Rn );
nkeynes@359
   857
    SETC_t();
nkeynes@417
   858
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   859
:}
nkeynes@359
   860
ADDV Rm, Rn {:
nkeynes@671
   861
    COUNT_INST(I_ADDV);
nkeynes@991
   862
    load_reg( REG_EAX, Rm );
nkeynes@991
   863
    load_reg( REG_ECX, Rn );
nkeynes@991
   864
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   865
    store_reg( REG_ECX, Rn );
nkeynes@359
   866
    SETO_t();
nkeynes@417
   867
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   868
:}
nkeynes@359
   869
AND Rm, Rn {:
nkeynes@671
   870
    COUNT_INST(I_AND);
nkeynes@991
   871
    load_reg( REG_EAX, Rm );
nkeynes@991
   872
    load_reg( REG_ECX, Rn );
nkeynes@991
   873
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   874
    store_reg( REG_ECX, Rn );
nkeynes@417
   875
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   876
:}
nkeynes@359
   877
AND #imm, R0 {:  
nkeynes@671
   878
    COUNT_INST(I_ANDI);
nkeynes@991
   879
    load_reg( REG_EAX, 0 );
nkeynes@991
   880
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   881
    store_reg( REG_EAX, 0 );
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   883
:}
nkeynes@359
   884
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   885
    COUNT_INST(I_ANDB);
nkeynes@991
   886
    load_reg( REG_EAX, 0 );
nkeynes@991
   887
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@1292
   888
    MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
   889
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@1292
   890
    MOVL_r32_r32(REG_SAVE1, REG_EAX);
nkeynes@991
   891
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   892
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   893
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   894
:}
nkeynes@359
   895
CMP/EQ Rm, Rn {:  
nkeynes@671
   896
    COUNT_INST(I_CMPEQ);
nkeynes@991
   897
    load_reg( REG_EAX, Rm );
nkeynes@991
   898
    load_reg( REG_ECX, Rn );
nkeynes@991
   899
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   900
    SETE_t();
nkeynes@417
   901
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   902
:}
nkeynes@359
   903
CMP/EQ #imm, R0 {:  
nkeynes@671
   904
    COUNT_INST(I_CMPEQI);
nkeynes@991
   905
    load_reg( REG_EAX, 0 );
nkeynes@991
   906
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   907
    SETE_t();
nkeynes@417
   908
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   909
:}
nkeynes@359
   910
CMP/GE Rm, Rn {:  
nkeynes@671
   911
    COUNT_INST(I_CMPGE);
nkeynes@991
   912
    load_reg( REG_EAX, Rm );
nkeynes@991
   913
    load_reg( REG_ECX, Rn );
nkeynes@991
   914
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   915
    SETGE_t();
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   917
:}
nkeynes@359
   918
CMP/GT Rm, Rn {: 
nkeynes@671
   919
    COUNT_INST(I_CMPGT);
nkeynes@991
   920
    load_reg( REG_EAX, Rm );
nkeynes@991
   921
    load_reg( REG_ECX, Rn );
nkeynes@991
   922
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   923
    SETG_t();
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   925
:}
nkeynes@359
   926
CMP/HI Rm, Rn {:  
nkeynes@671
   927
    COUNT_INST(I_CMPHI);
nkeynes@991
   928
    load_reg( REG_EAX, Rm );
nkeynes@991
   929
    load_reg( REG_ECX, Rn );
nkeynes@991
   930
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   931
    SETA_t();
nkeynes@417
   932
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   933
:}
nkeynes@359
   934
CMP/HS Rm, Rn {: 
nkeynes@671
   935
    COUNT_INST(I_CMPHS);
nkeynes@991
   936
    load_reg( REG_EAX, Rm );
nkeynes@991
   937
    load_reg( REG_ECX, Rn );
nkeynes@991
   938
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   939
    SETAE_t();
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   941
 :}
nkeynes@359
   942
CMP/PL Rn {: 
nkeynes@671
   943
    COUNT_INST(I_CMPPL);
nkeynes@991
   944
    load_reg( REG_EAX, Rn );
nkeynes@991
   945
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   946
    SETG_t();
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   948
:}
nkeynes@359
   949
CMP/PZ Rn {:  
nkeynes@671
   950
    COUNT_INST(I_CMPPZ);
nkeynes@991
   951
    load_reg( REG_EAX, Rn );
nkeynes@991
   952
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   953
    SETGE_t();
nkeynes@417
   954
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   955
:}
nkeynes@361
   956
CMP/STR Rm, Rn {:  
nkeynes@671
   957
    COUNT_INST(I_CMPSTR);
nkeynes@991
   958
    load_reg( REG_EAX, Rm );
nkeynes@991
   959
    load_reg( REG_ECX, Rn );
nkeynes@991
   960
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   961
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   962
    JE_label(target1);
nkeynes@991
   963
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   964
    JE_label(target2);
nkeynes@991
   965
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   966
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   967
    JE_label(target3);
nkeynes@991
   968
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   969
    JMP_TARGET(target1);
nkeynes@380
   970
    JMP_TARGET(target2);
nkeynes@380
   971
    JMP_TARGET(target3);
nkeynes@368
   972
    SETE_t();
nkeynes@417
   973
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   974
:}
nkeynes@361
   975
DIV0S Rm, Rn {:
nkeynes@671
   976
    COUNT_INST(I_DIV0S);
nkeynes@991
   977
    load_reg( REG_EAX, Rm );
nkeynes@991
   978
    load_reg( REG_ECX, Rn );
nkeynes@991
   979
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   980
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
   981
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   982
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   983
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   984
    SETNE_t();
nkeynes@417
   985
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   986
:}
nkeynes@361
   987
DIV0U {:  
nkeynes@671
   988
    COUNT_INST(I_DIV0U);
nkeynes@991
   989
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
   990
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
   991
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   992
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   993
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   994
:}
nkeynes@386
   995
DIV1 Rm, Rn {:
nkeynes@671
   996
    COUNT_INST(I_DIV1);
nkeynes@995
   997
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
   998
    load_reg( REG_EAX, Rn );
nkeynes@417
   999
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1000
	LDC_t();
nkeynes@417
  1001
    }
nkeynes@991
  1002
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1003
    SETC_r8( REG_DL ); // Q'
nkeynes@991
  1004
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
  1005
    JE_label(mqequal);
nkeynes@991
  1006
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1007
    JMP_label(end);
nkeynes@380
  1008
    JMP_TARGET(mqequal);
nkeynes@991
  1009
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
  1010
    JMP_TARGET(end);
nkeynes@991
  1011
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
  1012
    SETC_r8(REG_AL); // tmp1
nkeynes@991
  1013
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
  1014
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
  1015
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1016
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
  1017
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
  1018
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1019
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1020
:}
nkeynes@361
  1021
DMULS.L Rm, Rn {:  
nkeynes@671
  1022
    COUNT_INST(I_DMULS);
nkeynes@991
  1023
    load_reg( REG_EAX, Rm );
nkeynes@991
  1024
    load_reg( REG_ECX, Rn );
nkeynes@991
  1025
    IMULL_r32(REG_ECX);
nkeynes@995
  1026
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1027
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1028
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1029
:}
nkeynes@361
  1030
DMULU.L Rm, Rn {:  
nkeynes@671
  1031
    COUNT_INST(I_DMULU);
nkeynes@991
  1032
    load_reg( REG_EAX, Rm );
nkeynes@991
  1033
    load_reg( REG_ECX, Rn );
nkeynes@991
  1034
    MULL_r32(REG_ECX);
nkeynes@995
  1035
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1036
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
  1037
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1038
:}
nkeynes@359
  1039
DT Rn {:  
nkeynes@671
  1040
    COUNT_INST(I_DT);
nkeynes@991
  1041
    load_reg( REG_EAX, Rn );
nkeynes@991
  1042
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
  1043
    store_reg( REG_EAX, Rn );
nkeynes@359
  1044
    SETE_t();
nkeynes@417
  1045
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1046
:}
nkeynes@359
  1047
EXTS.B Rm, Rn {:  
nkeynes@671
  1048
    COUNT_INST(I_EXTSB);
nkeynes@991
  1049
    load_reg( REG_EAX, Rm );
nkeynes@991
  1050
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1051
    store_reg( REG_EAX, Rn );
nkeynes@359
  1052
:}
nkeynes@361
  1053
EXTS.W Rm, Rn {:  
nkeynes@671
  1054
    COUNT_INST(I_EXTSW);
nkeynes@991
  1055
    load_reg( REG_EAX, Rm );
nkeynes@991
  1056
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1057
    store_reg( REG_EAX, Rn );
nkeynes@361
  1058
:}
nkeynes@361
  1059
EXTU.B Rm, Rn {:  
nkeynes@671
  1060
    COUNT_INST(I_EXTUB);
nkeynes@991
  1061
    load_reg( REG_EAX, Rm );
nkeynes@991
  1062
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1063
    store_reg( REG_EAX, Rn );
nkeynes@361
  1064
:}
nkeynes@361
  1065
EXTU.W Rm, Rn {:  
nkeynes@671
  1066
    COUNT_INST(I_EXTUW);
nkeynes@991
  1067
    load_reg( REG_EAX, Rm );
nkeynes@991
  1068
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1069
    store_reg( REG_EAX, Rn );
nkeynes@361
  1070
:}
nkeynes@586
  1071
MAC.L @Rm+, @Rn+ {:
nkeynes@671
  1072
    COUNT_INST(I_MACL);
nkeynes@586
  1073
    if( Rm == Rn ) {
nkeynes@991
  1074
	load_reg( REG_EAX, Rm );
nkeynes@991
  1075
	check_ralign32( REG_EAX );
nkeynes@991
  1076
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@1292
  1077
	MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
  1078
	load_reg( REG_EAX, Rm );
nkeynes@991
  1079
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1080
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1081
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
  1082
    } else {
nkeynes@991
  1083
	load_reg( REG_EAX, Rm );
nkeynes@991
  1084
	check_ralign32( REG_EAX );
nkeynes@991
  1085
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@1292
  1086
	MOVL_r32_r32(REG_EAX, REG_SAVE1);
nkeynes@991
  1087
	load_reg( REG_EAX, Rn );
nkeynes@991
  1088
	check_ralign32( REG_EAX );
nkeynes@991
  1089
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1090
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
  1091
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1092
    }
nkeynes@939
  1093
    
nkeynes@1292
  1094
    IMULL_r32( REG_SAVE1 );
nkeynes@991
  1095
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
  1096
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
  1097
nkeynes@995
  1098
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1099
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
  1100
    JE_label( nosat );
nkeynes@995
  1101
    CALL_ptr( signsat48 );
nkeynes@386
  1102
    JMP_TARGET( nosat );
nkeynes@417
  1103
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1104
:}
nkeynes@386
  1105
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
  1106
    COUNT_INST(I_MACW);
nkeynes@586
  1107
    if( Rm == Rn ) {
nkeynes@991
  1108
	load_reg( REG_EAX, Rm );
nkeynes@991
  1109
	check_ralign16( REG_EAX );
nkeynes@991
  1110
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@1292
  1111
        MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1112
	load_reg( REG_EAX, Rm );
nkeynes@991
  1113
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
  1114
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1115
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1116
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  1117
	// adding a page-boundary check to skip the second translation
nkeynes@586
  1118
    } else {
nkeynes@1193
  1119
	load_reg( REG_EAX, Rn );
nkeynes@991
  1120
	check_ralign16( REG_EAX );
nkeynes@991
  1121
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@1292
  1122
        MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@1193
  1123
	load_reg( REG_EAX, Rm );
nkeynes@991
  1124
	check_ralign16( REG_EAX );
nkeynes@991
  1125
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1126
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
  1127
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1128
    }
nkeynes@1292
  1129
    IMULL_r32( REG_SAVE1 );
nkeynes@995
  1130
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1131
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
  1132
    JE_label( nosat );
nkeynes@386
  1133
nkeynes@991
  1134
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1135
    JNO_label( end );            // 2
nkeynes@995
  1136
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
  1137
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
  1138
    JS_label( positive );        // 2
nkeynes@995
  1139
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
  1140
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1141
    JMP_label(end2);           // 2
nkeynes@386
  1142
nkeynes@386
  1143
    JMP_TARGET(positive);
nkeynes@995
  1144
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
  1145
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1146
    JMP_label(end3);            // 2
nkeynes@386
  1147
nkeynes@386
  1148
    JMP_TARGET(nosat);
nkeynes@991
  1149
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1150
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
  1151
    JMP_TARGET(end);
nkeynes@386
  1152
    JMP_TARGET(end2);
nkeynes@386
  1153
    JMP_TARGET(end3);
nkeynes@417
  1154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1155
:}
nkeynes@359
  1156
MOVT Rn {:  
nkeynes@671
  1157
    COUNT_INST(I_MOVT);
nkeynes@995
  1158
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
  1159
    store_reg( REG_EAX, Rn );
nkeynes@359
  1160
:}
nkeynes@361
  1161
MUL.L Rm, Rn {:  
nkeynes@671
  1162
    COUNT_INST(I_MULL);
nkeynes@991
  1163
    load_reg( REG_EAX, Rm );
nkeynes@991
  1164
    load_reg( REG_ECX, Rn );
nkeynes@991
  1165
    MULL_r32( REG_ECX );
nkeynes@995
  1166
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1167
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1168
:}
nkeynes@374
  1169
MULS.W Rm, Rn {:
nkeynes@671
  1170
    COUNT_INST(I_MULSW);
nkeynes@995
  1171
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1172
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1173
    MULL_r32( REG_ECX );
nkeynes@995
  1174
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1175
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1176
:}
nkeynes@374
  1177
MULU.W Rm, Rn {:  
nkeynes@671
  1178
    COUNT_INST(I_MULUW);
nkeynes@995
  1179
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1180
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1181
    MULL_r32( REG_ECX );
nkeynes@995
  1182
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1183
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1184
:}
nkeynes@359
  1185
NEG Rm, Rn {:
nkeynes@671
  1186
    COUNT_INST(I_NEG);
nkeynes@991
  1187
    load_reg( REG_EAX, Rm );
nkeynes@991
  1188
    NEGL_r32( REG_EAX );
nkeynes@991
  1189
    store_reg( REG_EAX, Rn );
nkeynes@417
  1190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
:}
nkeynes@359
  1192
NEGC Rm, Rn {:  
nkeynes@671
  1193
    COUNT_INST(I_NEGC);
nkeynes@991
  1194
    load_reg( REG_EAX, Rm );
nkeynes@991
  1195
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
  1196
    LDC_t();
nkeynes@991
  1197
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1198
    store_reg( REG_ECX, Rn );
nkeynes@359
  1199
    SETC_t();
nkeynes@417
  1200
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1201
:}
nkeynes@359
  1202
NOT Rm, Rn {:  
nkeynes@671
  1203
    COUNT_INST(I_NOT);
nkeynes@991
  1204
    load_reg( REG_EAX, Rm );
nkeynes@991
  1205
    NOTL_r32( REG_EAX );
nkeynes@991
  1206
    store_reg( REG_EAX, Rn );
nkeynes@417
  1207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1208
:}
nkeynes@359
  1209
OR Rm, Rn {:  
nkeynes@671
  1210
    COUNT_INST(I_OR);
nkeynes@991
  1211
    load_reg( REG_EAX, Rm );
nkeynes@991
  1212
    load_reg( REG_ECX, Rn );
nkeynes@991
  1213
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1214
    store_reg( REG_ECX, Rn );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1216
:}
nkeynes@359
  1217
OR #imm, R0 {:
nkeynes@671
  1218
    COUNT_INST(I_ORI);
nkeynes@991
  1219
    load_reg( REG_EAX, 0 );
nkeynes@991
  1220
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1221
    store_reg( REG_EAX, 0 );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@374
  1224
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1225
    COUNT_INST(I_ORB);
nkeynes@991
  1226
    load_reg( REG_EAX, 0 );
nkeynes@991
  1227
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@1292
  1228
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1229
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@1292
  1230
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1231
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1232
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1233
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1234
:}
nkeynes@359
  1235
ROTCL Rn {:
nkeynes@671
  1236
    COUNT_INST(I_ROTCL);
nkeynes@991
  1237
    load_reg( REG_EAX, Rn );
nkeynes@417
  1238
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1239
	LDC_t();
nkeynes@417
  1240
    }
nkeynes@991
  1241
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1242
    store_reg( REG_EAX, Rn );
nkeynes@359
  1243
    SETC_t();
nkeynes@417
  1244
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1245
:}
nkeynes@359
  1246
ROTCR Rn {:  
nkeynes@671
  1247
    COUNT_INST(I_ROTCR);
nkeynes@991
  1248
    load_reg( REG_EAX, Rn );
nkeynes@417
  1249
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1250
	LDC_t();
nkeynes@417
  1251
    }
nkeynes@991
  1252
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1253
    store_reg( REG_EAX, Rn );
nkeynes@359
  1254
    SETC_t();
nkeynes@417
  1255
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1256
:}
nkeynes@359
  1257
ROTL Rn {:  
nkeynes@671
  1258
    COUNT_INST(I_ROTL);
nkeynes@991
  1259
    load_reg( REG_EAX, Rn );
nkeynes@991
  1260
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1261
    store_reg( REG_EAX, Rn );
nkeynes@359
  1262
    SETC_t();
nkeynes@417
  1263
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1264
:}
nkeynes@359
  1265
ROTR Rn {:  
nkeynes@671
  1266
    COUNT_INST(I_ROTR);
nkeynes@991
  1267
    load_reg( REG_EAX, Rn );
nkeynes@991
  1268
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1269
    store_reg( REG_EAX, Rn );
nkeynes@359
  1270
    SETC_t();
nkeynes@417
  1271
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1272
:}
nkeynes@359
  1273
SHAD Rm, Rn {:
nkeynes@671
  1274
    COUNT_INST(I_SHAD);
nkeynes@359
  1275
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1276
    load_reg( REG_EAX, Rn );
nkeynes@991
  1277
    load_reg( REG_ECX, Rm );
nkeynes@991
  1278
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1279
    JGE_label(doshl);
nkeynes@361
  1280
                    
nkeynes@991
  1281
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1282
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1283
    JE_label(emptysar);     // 2
nkeynes@991
  1284
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1285
    JMP_label(end);          // 2
nkeynes@386
  1286
nkeynes@386
  1287
    JMP_TARGET(emptysar);
nkeynes@991
  1288
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1289
    JMP_label(end2);
nkeynes@382
  1290
nkeynes@380
  1291
    JMP_TARGET(doshl);
nkeynes@991
  1292
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1293
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1294
    JMP_TARGET(end);
nkeynes@386
  1295
    JMP_TARGET(end2);
nkeynes@991
  1296
    store_reg( REG_EAX, Rn );
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1298
:}
nkeynes@359
  1299
SHLD Rm, Rn {:  
nkeynes@671
  1300
    COUNT_INST(I_SHLD);
nkeynes@991
  1301
    load_reg( REG_EAX, Rn );
nkeynes@991
  1302
    load_reg( REG_ECX, Rm );
nkeynes@991
  1303
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1304
    JGE_label(doshl);
nkeynes@368
  1305
nkeynes@991
  1306
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1307
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1308
    JE_label(emptyshr );
nkeynes@991
  1309
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1310
    JMP_label(end);          // 2
nkeynes@386
  1311
nkeynes@386
  1312
    JMP_TARGET(emptyshr);
nkeynes@991
  1313
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1314
    JMP_label(end2);
nkeynes@382
  1315
nkeynes@382
  1316
    JMP_TARGET(doshl);
nkeynes@991
  1317
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1318
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1319
    JMP_TARGET(end);
nkeynes@386
  1320
    JMP_TARGET(end2);
nkeynes@991
  1321
    store_reg( REG_EAX, Rn );
nkeynes@417
  1322
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1323
:}
nkeynes@359
  1324
SHAL Rn {: 
nkeynes@671
  1325
    COUNT_INST(I_SHAL);
nkeynes@991
  1326
    load_reg( REG_EAX, Rn );
nkeynes@991
  1327
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1328
    SETC_t();
nkeynes@991
  1329
    store_reg( REG_EAX, Rn );
nkeynes@417
  1330
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1331
:}
nkeynes@359
  1332
SHAR Rn {:  
nkeynes@671
  1333
    COUNT_INST(I_SHAR);
nkeynes@991
  1334
    load_reg( REG_EAX, Rn );
nkeynes@991
  1335
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1336
    SETC_t();
nkeynes@991
  1337
    store_reg( REG_EAX, Rn );
nkeynes@417
  1338
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1339
:}
nkeynes@359
  1340
SHLL Rn {:  
nkeynes@671
  1341
    COUNT_INST(I_SHLL);
nkeynes@991
  1342
    load_reg( REG_EAX, Rn );
nkeynes@991
  1343
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1344
    SETC_t();
nkeynes@991
  1345
    store_reg( REG_EAX, Rn );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1347
:}
nkeynes@359
  1348
SHLL2 Rn {:
nkeynes@671
  1349
    COUNT_INST(I_SHLL);
nkeynes@991
  1350
    load_reg( REG_EAX, Rn );
nkeynes@991
  1351
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1352
    store_reg( REG_EAX, Rn );
nkeynes@417
  1353
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1354
:}
nkeynes@359
  1355
SHLL8 Rn {:  
nkeynes@671
  1356
    COUNT_INST(I_SHLL);
nkeynes@991
  1357
    load_reg( REG_EAX, Rn );
nkeynes@991
  1358
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1359
    store_reg( REG_EAX, Rn );
nkeynes@417
  1360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1361
:}
nkeynes@359
  1362
SHLL16 Rn {:  
nkeynes@671
  1363
    COUNT_INST(I_SHLL);
nkeynes@991
  1364
    load_reg( REG_EAX, Rn );
nkeynes@991
  1365
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1366
    store_reg( REG_EAX, Rn );
nkeynes@417
  1367
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1368
:}
nkeynes@359
  1369
SHLR Rn {:  
nkeynes@671
  1370
    COUNT_INST(I_SHLR);
nkeynes@991
  1371
    load_reg( REG_EAX, Rn );
nkeynes@991
  1372
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1373
    SETC_t();
nkeynes@991
  1374
    store_reg( REG_EAX, Rn );
nkeynes@417
  1375
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1376
:}
nkeynes@359
  1377
SHLR2 Rn {:  
nkeynes@671
  1378
    COUNT_INST(I_SHLR);
nkeynes@991
  1379
    load_reg( REG_EAX, Rn );
nkeynes@991
  1380
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1381
    store_reg( REG_EAX, Rn );
nkeynes@417
  1382
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1383
:}
nkeynes@359
  1384
SHLR8 Rn {:  
nkeynes@671
  1385
    COUNT_INST(I_SHLR);
nkeynes@991
  1386
    load_reg( REG_EAX, Rn );
nkeynes@991
  1387
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1388
    store_reg( REG_EAX, Rn );
nkeynes@417
  1389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1390
:}
nkeynes@359
  1391
SHLR16 Rn {:  
nkeynes@671
  1392
    COUNT_INST(I_SHLR);
nkeynes@991
  1393
    load_reg( REG_EAX, Rn );
nkeynes@991
  1394
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1395
    store_reg( REG_EAX, Rn );
nkeynes@417
  1396
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1397
:}
nkeynes@359
  1398
SUB Rm, Rn {:  
nkeynes@671
  1399
    COUNT_INST(I_SUB);
nkeynes@991
  1400
    load_reg( REG_EAX, Rm );
nkeynes@991
  1401
    load_reg( REG_ECX, Rn );
nkeynes@991
  1402
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1403
    store_reg( REG_ECX, Rn );
nkeynes@417
  1404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1405
:}
nkeynes@359
  1406
SUBC Rm, Rn {:  
nkeynes@671
  1407
    COUNT_INST(I_SUBC);
nkeynes@991
  1408
    load_reg( REG_EAX, Rm );
nkeynes@991
  1409
    load_reg( REG_ECX, Rn );
nkeynes@417
  1410
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1411
	LDC_t();
nkeynes@417
  1412
    }
nkeynes@991
  1413
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1414
    store_reg( REG_ECX, Rn );
nkeynes@394
  1415
    SETC_t();
nkeynes@417
  1416
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1417
:}
nkeynes@359
  1418
SUBV Rm, Rn {:  
nkeynes@671
  1419
    COUNT_INST(I_SUBV);
nkeynes@991
  1420
    load_reg( REG_EAX, Rm );
nkeynes@991
  1421
    load_reg( REG_ECX, Rn );
nkeynes@991
  1422
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1423
    store_reg( REG_ECX, Rn );
nkeynes@359
  1424
    SETO_t();
nkeynes@417
  1425
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1426
:}
nkeynes@359
  1427
SWAP.B Rm, Rn {:  
nkeynes@671
  1428
    COUNT_INST(I_SWAPB);
nkeynes@991
  1429
    load_reg( REG_EAX, Rm );
nkeynes@991
  1430
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1431
    store_reg( REG_EAX, Rn );
nkeynes@359
  1432
:}
nkeynes@359
  1433
SWAP.W Rm, Rn {:  
nkeynes@671
  1434
    COUNT_INST(I_SWAPB);
nkeynes@991
  1435
    load_reg( REG_EAX, Rm );
nkeynes@991
  1436
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1437
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1438
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1439
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1440
    store_reg( REG_ECX, Rn );
nkeynes@417
  1441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1442
:}
nkeynes@361
  1443
TAS.B @Rn {:  
nkeynes@671
  1444
    COUNT_INST(I_TASB);
nkeynes@991
  1445
    load_reg( REG_EAX, Rn );
nkeynes@1292
  1446
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1447
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1448
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1449
    SETE_t();
nkeynes@991
  1450
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@1292
  1451
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1452
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1454
:}
nkeynes@361
  1455
TST Rm, Rn {:  
nkeynes@671
  1456
    COUNT_INST(I_TST);
nkeynes@991
  1457
    load_reg( REG_EAX, Rm );
nkeynes@991
  1458
    load_reg( REG_ECX, Rn );
nkeynes@991
  1459
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1460
    SETE_t();
nkeynes@417
  1461
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1462
:}
nkeynes@368
  1463
TST #imm, R0 {:  
nkeynes@671
  1464
    COUNT_INST(I_TSTI);
nkeynes@991
  1465
    load_reg( REG_EAX, 0 );
nkeynes@991
  1466
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1467
    SETE_t();
nkeynes@417
  1468
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1469
:}
nkeynes@368
  1470
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1471
    COUNT_INST(I_TSTB);
nkeynes@991
  1472
    load_reg( REG_EAX, 0);
nkeynes@991
  1473
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1474
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1475
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1476
    SETE_t();
nkeynes@417
  1477
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1478
:}
nkeynes@359
  1479
XOR Rm, Rn {:  
nkeynes@671
  1480
    COUNT_INST(I_XOR);
nkeynes@991
  1481
    load_reg( REG_EAX, Rm );
nkeynes@991
  1482
    load_reg( REG_ECX, Rn );
nkeynes@991
  1483
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1484
    store_reg( REG_ECX, Rn );
nkeynes@417
  1485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1486
:}
nkeynes@359
  1487
XOR #imm, R0 {:  
nkeynes@671
  1488
    COUNT_INST(I_XORI);
nkeynes@991
  1489
    load_reg( REG_EAX, 0 );
nkeynes@991
  1490
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1491
    store_reg( REG_EAX, 0 );
nkeynes@417
  1492
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1493
:}
nkeynes@359
  1494
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1495
    COUNT_INST(I_XORB);
nkeynes@991
  1496
    load_reg( REG_EAX, 0 );
nkeynes@991
  1497
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@1292
  1498
    MOVL_r32_r32( REG_EAX, REG_SAVE1 );
nkeynes@991
  1499
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@1292
  1500
    MOVL_r32_r32( REG_SAVE1, REG_EAX );
nkeynes@991
  1501
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1502
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1503
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1504
:}
nkeynes@361
  1505
XTRCT Rm, Rn {:
nkeynes@671
  1506
    COUNT_INST(I_XTRCT);
nkeynes@991
  1507
    load_reg( REG_EAX, Rm );
nkeynes@991
  1508
    load_reg( REG_ECX, Rn );
nkeynes@991
  1509
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1510
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1511
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1512
    store_reg( REG_ECX, Rn );
nkeynes@417
  1513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1514
:}
nkeynes@359
  1515
nkeynes@359
  1516
/* Data move instructions */
nkeynes@359
  1517
MOV Rm, Rn {:  
nkeynes@671
  1518
    COUNT_INST(I_MOV);
nkeynes@991
  1519
    load_reg( REG_EAX, Rm );
nkeynes@991
  1520
    store_reg( REG_EAX, Rn );
nkeynes@359
  1521
:}
nkeynes@359
  1522
MOV #imm, Rn {:  
nkeynes@671
  1523
    COUNT_INST(I_MOVI);
nkeynes@995
  1524
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1525
    store_reg( REG_EAX, Rn );
nkeynes@359
  1526
:}
nkeynes@359
  1527
MOV.B Rm, @Rn {:  
nkeynes@671
  1528
    COUNT_INST(I_MOVB);
nkeynes@991
  1529
    load_reg( REG_EAX, Rn );
nkeynes@991
  1530
    load_reg( REG_EDX, Rm );
nkeynes@991
  1531
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1532
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1533
:}
nkeynes@359
  1534
MOV.B Rm, @-Rn {:  
nkeynes@671
  1535
    COUNT_INST(I_MOVB);
nkeynes@991
  1536
    load_reg( REG_EAX, Rn );
nkeynes@991
  1537
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1538
    load_reg( REG_EDX, Rm );
nkeynes@991
  1539
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1540
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1541
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1542
:}
nkeynes@359
  1543
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1544
    COUNT_INST(I_MOVB);
nkeynes@991
  1545
    load_reg( REG_EAX, 0 );
nkeynes@991
  1546
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1547
    load_reg( REG_EDX, Rm );
nkeynes@991
  1548
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1549
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1550
:}
nkeynes@359
  1551
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1552
    COUNT_INST(I_MOVB);
nkeynes@995
  1553
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1554
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1555
    load_reg( REG_EDX, 0 );
nkeynes@991
  1556
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1557
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1558
:}
nkeynes@359
  1559
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1560
    COUNT_INST(I_MOVB);
nkeynes@991
  1561
    load_reg( REG_EAX, Rn );
nkeynes@991
  1562
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1563
    load_reg( REG_EDX, 0 );
nkeynes@991
  1564
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1565
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1566
:}
nkeynes@359
  1567
MOV.B @Rm, Rn {:  
nkeynes@671
  1568
    COUNT_INST(I_MOVB);
nkeynes@991
  1569
    load_reg( REG_EAX, Rm );
nkeynes@991
  1570
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1571
    store_reg( REG_EAX, Rn );
nkeynes@417
  1572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1573
:}
nkeynes@359
  1574
MOV.B @Rm+, Rn {:  
nkeynes@671
  1575
    COUNT_INST(I_MOVB);
nkeynes@991
  1576
    load_reg( REG_EAX, Rm );
nkeynes@991
  1577
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@939
  1578
    if( Rm != Rn ) {
nkeynes@991
  1579
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1580
    }
nkeynes@991
  1581
    store_reg( REG_EAX, Rn );
nkeynes@417
  1582
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1583
:}
nkeynes@359
  1584
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1585
    COUNT_INST(I_MOVB);
nkeynes@991
  1586
    load_reg( REG_EAX, 0 );
nkeynes@991
  1587
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1588
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1589
    store_reg( REG_EAX, Rn );
nkeynes@417
  1590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1591
:}
nkeynes@359
  1592
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1593
    COUNT_INST(I_MOVB);
nkeynes@995
  1594
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1595
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1596
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1597
    store_reg( REG_EAX, 0 );
nkeynes@417
  1598
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1599
:}
nkeynes@359
  1600
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1601
    COUNT_INST(I_MOVB);
nkeynes@991
  1602
    load_reg( REG_EAX, Rm );
nkeynes@991
  1603
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1604
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1605
    store_reg( REG_EAX, 0 );
nkeynes@417
  1606
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1607
:}
nkeynes@374
  1608
MOV.L Rm, @Rn {:
nkeynes@671
  1609
    COUNT_INST(I_MOVL);
nkeynes@991
  1610
    load_reg( REG_EAX, Rn );
nkeynes@991
  1611
    check_walign32(REG_EAX);
nkeynes@991
  1612
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1613
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1614
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1615
    JNE_label( notsq );
nkeynes@991
  1616
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1617
    load_reg( REG_EDX, Rm );
nkeynes@991
  1618
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1619
    JMP_label(end);
nkeynes@930
  1620
    JMP_TARGET(notsq);
nkeynes@991
  1621
    load_reg( REG_EDX, Rm );
nkeynes@991
  1622
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1623
    JMP_TARGET(end);
nkeynes@417
  1624
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1625
:}
nkeynes@361
  1626
MOV.L Rm, @-Rn {:  
nkeynes@671
  1627
    COUNT_INST(I_MOVL);
nkeynes@991
  1628
    load_reg( REG_EAX, Rn );
nkeynes@991
  1629
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1630
    check_walign32( REG_EAX );
nkeynes@991
  1631
    load_reg( REG_EDX, Rm );
nkeynes@991
  1632
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1633
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1634
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1635
:}
nkeynes@361
  1636
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1637
    COUNT_INST(I_MOVL);
nkeynes@991
  1638
    load_reg( REG_EAX, 0 );
nkeynes@991
  1639
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1640
    check_walign32( REG_EAX );
nkeynes@991
  1641
    load_reg( REG_EDX, Rm );
nkeynes@991
  1642
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1643
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1644
:}
nkeynes@361
  1645
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1646
    COUNT_INST(I_MOVL);
nkeynes@995
  1647
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1648
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1649
    check_walign32( REG_EAX );
nkeynes@991
  1650
    load_reg( REG_EDX, 0 );
nkeynes@991
  1651
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1653
:}
nkeynes@361
  1654
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1655
    COUNT_INST(I_MOVL);
nkeynes@991
  1656
    load_reg( REG_EAX, Rn );
nkeynes@991
  1657
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1658
    check_walign32( REG_EAX );
nkeynes@991
  1659
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1660
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1661
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1662
    JNE_label( notsq );
nkeynes@991
  1663
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1664
    load_reg( REG_EDX, Rm );
nkeynes@991
  1665
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1666
    JMP_label(end);
nkeynes@930
  1667
    JMP_TARGET(notsq);
nkeynes@991
  1668
    load_reg( REG_EDX, Rm );
nkeynes@991
  1669
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1670
    JMP_TARGET(end);
nkeynes@417
  1671
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1672
:}
nkeynes@361
  1673
MOV.L @Rm, Rn {:  
nkeynes@671
  1674
    COUNT_INST(I_MOVL);
nkeynes@991
  1675
    load_reg( REG_EAX, Rm );
nkeynes@991
  1676
    check_ralign32( REG_EAX );
nkeynes@991
  1677
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1678
    store_reg( REG_EAX, Rn );
nkeynes@417
  1679
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1680
:}
nkeynes@361
  1681
MOV.L @Rm+, Rn {:  
nkeynes@671
  1682
    COUNT_INST(I_MOVL);
nkeynes@991
  1683
    load_reg( REG_EAX, Rm );
nkeynes@991
  1684
    check_ralign32( REG_EAX );
nkeynes@991
  1685
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@939
  1686
    if( Rm != Rn ) {
nkeynes@991
  1687
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1688
    }
nkeynes@991
  1689
    store_reg( REG_EAX, Rn );
nkeynes@417
  1690
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1691
:}
nkeynes@361
  1692
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1693
    COUNT_INST(I_MOVL);
nkeynes@991
  1694
    load_reg( REG_EAX, 0 );
nkeynes@991
  1695
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1696
    check_ralign32( REG_EAX );
nkeynes@991
  1697
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1698
    store_reg( REG_EAX, Rn );
nkeynes@417
  1699
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1700
:}
nkeynes@361
  1701
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1702
    COUNT_INST(I_MOVL);
nkeynes@995
  1703
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1704
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1705
    check_ralign32( REG_EAX );
nkeynes@991
  1706
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1707
    store_reg( REG_EAX, 0 );
nkeynes@417
  1708
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1709
:}
nkeynes@361
  1710
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1711
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1712
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1713
	SLOTILLEGAL();
nkeynes@374
  1714
    } else {
nkeynes@388
  1715
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@1125
  1716
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1717
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1718
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1719
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1720
nkeynes@586
  1721
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1722
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1723
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1724
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1725
	    // behaviour though.
nkeynes@586
  1726
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1727
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1728
	} else {
nkeynes@586
  1729
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1730
	    // different virtual address than the translation was done with,
nkeynes@586
  1731
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1732
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1733
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1734
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1735
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1736
	}
nkeynes@991
  1737
	store_reg( REG_EAX, Rn );
nkeynes@374
  1738
    }
nkeynes@361
  1739
:}
nkeynes@361
  1740
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1741
    COUNT_INST(I_MOVL);
nkeynes@991
  1742
    load_reg( REG_EAX, Rm );
nkeynes@991
  1743
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1744
    check_ralign32( REG_EAX );
nkeynes@991
  1745
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1746
    store_reg( REG_EAX, Rn );
nkeynes@417
  1747
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1748
:}
nkeynes@361
  1749
MOV.W Rm, @Rn {:  
nkeynes@671
  1750
    COUNT_INST(I_MOVW);
nkeynes@991
  1751
    load_reg( REG_EAX, Rn );
nkeynes@991
  1752
    check_walign16( REG_EAX );
nkeynes@991
  1753
    load_reg( REG_EDX, Rm );
nkeynes@991
  1754
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1755
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1756
:}
nkeynes@361
  1757
MOV.W Rm, @-Rn {:  
nkeynes@671
  1758
    COUNT_INST(I_MOVW);
nkeynes@991
  1759
    load_reg( REG_EAX, Rn );
nkeynes@991
  1760
    check_walign16( REG_EAX );
nkeynes@991
  1761
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1762
    load_reg( REG_EDX, Rm );
nkeynes@991
  1763
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1764
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1765
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1766
:}
nkeynes@361
  1767
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1768
    COUNT_INST(I_MOVW);
nkeynes@991
  1769
    load_reg( REG_EAX, 0 );
nkeynes@991
  1770
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1771
    check_walign16( REG_EAX );
nkeynes@991
  1772
    load_reg( REG_EDX, Rm );
nkeynes@991
  1773
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1774
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1775
:}
nkeynes@361
  1776
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1777
    COUNT_INST(I_MOVW);
nkeynes@995
  1778
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1779
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1780
    check_walign16( REG_EAX );
nkeynes@991
  1781
    load_reg( REG_EDX, 0 );
nkeynes@991
  1782
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1783
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1784
:}
nkeynes@361
  1785
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1786
    COUNT_INST(I_MOVW);
nkeynes@991
  1787
    load_reg( REG_EAX, Rn );
nkeynes@991
  1788
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1789
    check_walign16( REG_EAX );
nkeynes@991
  1790
    load_reg( REG_EDX, 0 );
nkeynes@991
  1791
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1792
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1793
:}
nkeynes@361
  1794
MOV.W @Rm, Rn {:  
nkeynes@671
  1795
    COUNT_INST(I_MOVW);
nkeynes@991
  1796
    load_reg( REG_EAX, Rm );
nkeynes@991
  1797
    check_ralign16( REG_EAX );
nkeynes@991
  1798
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1799
    store_reg( REG_EAX, Rn );
nkeynes@417
  1800
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1801
:}
nkeynes@361
  1802
MOV.W @Rm+, Rn {:  
nkeynes@671
  1803
    COUNT_INST(I_MOVW);
nkeynes@991
  1804
    load_reg( REG_EAX, Rm );
nkeynes@991
  1805
    check_ralign16( REG_EAX );
nkeynes@991
  1806
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@939
  1807
    if( Rm != Rn ) {
nkeynes@991
  1808
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1809
    }
nkeynes@991
  1810
    store_reg( REG_EAX, Rn );
nkeynes@417
  1811
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1812
:}
nkeynes@361
  1813
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1814
    COUNT_INST(I_MOVW);
nkeynes@991
  1815
    load_reg( REG_EAX, 0 );
nkeynes@991
  1816
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1817
    check_ralign16( REG_EAX );
nkeynes@991
  1818
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1819
    store_reg( REG_EAX, Rn );
nkeynes@417
  1820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1821
:}
nkeynes@361
  1822
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1823
    COUNT_INST(I_MOVW);
nkeynes@995
  1824
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1825
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1826
    check_ralign16( REG_EAX );
nkeynes@991
  1827
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1828
    store_reg( REG_EAX, 0 );
nkeynes@417
  1829
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1830
:}
nkeynes@361
  1831
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1832
    COUNT_INST(I_MOVW);
nkeynes@374
  1833
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1834
	SLOTILLEGAL();
nkeynes@374
  1835
    } else {
nkeynes@586
  1836
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1837
	uint32_t target = pc + disp + 4;
nkeynes@1125
  1838
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1839
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1840
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1841
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1842
	} else {
nkeynes@995
  1843
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1844
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1845
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1846
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1847
	}
nkeynes@991
  1848
	store_reg( REG_EAX, Rn );
nkeynes@374
  1849
    }
nkeynes@361
  1850
:}
nkeynes@361
  1851
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1852
    COUNT_INST(I_MOVW);
nkeynes@991
  1853
    load_reg( REG_EAX, Rm );
nkeynes@991
  1854
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1855
    check_ralign16( REG_EAX );
nkeynes@991
  1856
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1857
    store_reg( REG_EAX, 0 );
nkeynes@417
  1858
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1859
:}
nkeynes@361
  1860
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1861
    COUNT_INST(I_MOVA);
nkeynes@374
  1862
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1863
	SLOTILLEGAL();
nkeynes@374
  1864
    } else {
nkeynes@995
  1865
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1866
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1867
	store_reg( REG_ECX, 0 );
nkeynes@586
  1868
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1869
    }
nkeynes@361
  1870
:}
nkeynes@361
  1871
MOVCA.L R0, @Rn {:  
nkeynes@671
  1872
    COUNT_INST(I_MOVCA);
nkeynes@991
  1873
    load_reg( REG_EAX, Rn );
nkeynes@991
  1874
    check_walign32( REG_EAX );
nkeynes@991
  1875
    load_reg( REG_EDX, 0 );
nkeynes@991
  1876
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1878
:}
nkeynes@359
  1879
nkeynes@359
  1880
/* Control transfer instructions */
nkeynes@374
  1881
BF disp {:
nkeynes@671
  1882
    COUNT_INST(I_BF);
nkeynes@374
  1883
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1884
	SLOTILLEGAL();
nkeynes@374
  1885
    } else {
nkeynes@586
  1886
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1887
	JT_label( nottaken );
nkeynes@586
  1888
	exit_block_rel(target, pc+2 );
nkeynes@380
  1889
	JMP_TARGET(nottaken);
nkeynes@408
  1890
	return 2;
nkeynes@374
  1891
    }
nkeynes@374
  1892
:}
nkeynes@374
  1893
BF/S disp {:
nkeynes@671
  1894
    COUNT_INST(I_BFS);
nkeynes@374
  1895
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1896
	SLOTILLEGAL();
nkeynes@374
  1897
    } else {
nkeynes@590
  1898
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1899
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1900
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1901
	    JT_label(nottaken);
nkeynes@991
  1902
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1903
	    JMP_TARGET(nottaken);
nkeynes@991
  1904
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1905
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1906
	    exit_block_emu(pc+2);
nkeynes@601
  1907
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1908
	    return 2;
nkeynes@601
  1909
	} else {
nkeynes@1197
  1910
	    LOAD_t();
nkeynes@601
  1911
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1912
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1913
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1914
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1915
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1916
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1917
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1918
	    
nkeynes@601
  1919
	    // not taken
nkeynes@601
  1920
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1921
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1922
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1923
	    return 4;
nkeynes@417
  1924
	}
nkeynes@374
  1925
    }
nkeynes@374
  1926
:}
nkeynes@374
  1927
BRA disp {:  
nkeynes@671
  1928
    COUNT_INST(I_BRA);
nkeynes@374
  1929
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1930
	SLOTILLEGAL();
nkeynes@374
  1931
    } else {
nkeynes@590
  1932
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1933
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1934
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1935
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1936
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1937
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1938
	    exit_block_emu(pc+2);
nkeynes@601
  1939
	    return 2;
nkeynes@601
  1940
	} else {
nkeynes@601
  1941
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1942
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1943
	    return 4;
nkeynes@601
  1944
	}
nkeynes@374
  1945
    }
nkeynes@374
  1946
:}
nkeynes@374
  1947
BRAF Rn {:  
nkeynes@671
  1948
    COUNT_INST(I_BRAF);
nkeynes@374
  1949
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1950
	SLOTILLEGAL();
nkeynes@374
  1951
    } else {
nkeynes@995
  1952
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1953
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1954
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1955
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1956
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1957
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1958
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1959
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1960
	    exit_block_emu(pc+2);
nkeynes@601
  1961
	    return 2;
nkeynes@601
  1962
	} else {
nkeynes@601
  1963
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1964
	    exit_block_newpcset(pc+4);
nkeynes@601
  1965
	    return 4;
nkeynes@601
  1966
	}
nkeynes@374
  1967
    }
nkeynes@374
  1968
:}
nkeynes@374
  1969
BSR disp {:  
nkeynes@671
  1970
    COUNT_INST(I_BSR);
nkeynes@374
  1971
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1972
	SLOTILLEGAL();
nkeynes@374
  1973
    } else {
nkeynes@995
  1974
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1975
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1976
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  1977
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1978
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1979
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1980
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1981
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  1982
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1983
	    exit_block_emu(pc+2);
nkeynes@601
  1984
	    return 2;
nkeynes@601
  1985
	} else {
nkeynes@601
  1986
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1987
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1988
	    return 4;
nkeynes@601
  1989
	}
nkeynes@374
  1990
    }
nkeynes@374
  1991
:}
nkeynes@374
  1992
BSRF Rn {:  
nkeynes@671
  1993
    COUNT_INST(I_BSRF);
nkeynes@374
  1994
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1995
	SLOTILLEGAL();
nkeynes@374
  1996
    } else {
nkeynes@995
  1997
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1998
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1999
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2000
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  2001
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  2002
nkeynes@601
  2003
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2004
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2005
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2006
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2007
	    exit_block_emu(pc+2);
nkeynes@601
  2008
	    return 2;
nkeynes@601
  2009
	} else {
nkeynes@601
  2010
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2011
	    exit_block_newpcset(pc+4);
nkeynes@601
  2012
	    return 4;
nkeynes@601
  2013
	}
nkeynes@374
  2014
    }
nkeynes@374
  2015
:}
nkeynes@374
  2016
BT disp {:
nkeynes@671
  2017
    COUNT_INST(I_BT);
nkeynes@374
  2018
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2019
	SLOTILLEGAL();
nkeynes@374
  2020
    } else {
nkeynes@586
  2021
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  2022
	JF_label( nottaken );
nkeynes@586
  2023
	exit_block_rel(target, pc+2 );
nkeynes@380
  2024
	JMP_TARGET(nottaken);
nkeynes@408
  2025
	return 2;
nkeynes@374
  2026
    }
nkeynes@374
  2027
:}
nkeynes@374
  2028
BT/S disp {:
nkeynes@671
  2029
    COUNT_INST(I_BTS);
nkeynes@374
  2030
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2031
	SLOTILLEGAL();
nkeynes@374
  2032
    } else {
nkeynes@590
  2033
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2034
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  2035
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  2036
	    JF_label(nottaken);
nkeynes@991
  2037
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  2038
	    JMP_TARGET(nottaken);
nkeynes@991
  2039
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  2040
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2041
	    exit_block_emu(pc+2);
nkeynes@601
  2042
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2043
	    return 2;
nkeynes@601
  2044
	} else {
nkeynes@1197
  2045
		LOAD_t();
nkeynes@991
  2046
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  2047
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  2048
nkeynes@879
  2049
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  2050
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  2051
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  2052
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2053
	    // not taken
nkeynes@601
  2054
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  2055
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  2056
	    sh4_translate_instruction(pc+2);
nkeynes@601
  2057
	    return 4;
nkeynes@417
  2058
	}
nkeynes@374
  2059
    }
nkeynes@374
  2060
:}
nkeynes@374
  2061
JMP @Rn {:  
nkeynes@671
  2062
    COUNT_INST(I_JMP);
nkeynes@374
  2063
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2064
	SLOTILLEGAL();
nkeynes@374
  2065
    } else {
nkeynes@991
  2066
	load_reg( REG_ECX, Rn );
nkeynes@995
  2067
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2068
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2069
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2070
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2071
	    exit_block_emu(pc+2);
nkeynes@601
  2072
	    return 2;
nkeynes@601
  2073
	} else {
nkeynes@601
  2074
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2075
	    exit_block_newpcset(pc+4);
nkeynes@601
  2076
	    return 4;
nkeynes@601
  2077
	}
nkeynes@374
  2078
    }
nkeynes@374
  2079
:}
nkeynes@374
  2080
JSR @Rn {:  
nkeynes@671
  2081
    COUNT_INST(I_JSR);
nkeynes@374
  2082
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2083
	SLOTILLEGAL();
nkeynes@374
  2084
    } else {
nkeynes@995
  2085
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2086
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2087
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2088
	load_reg( REG_ECX, Rn );
nkeynes@995
  2089
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  2090
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2091
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2092
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2093
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2094
	    exit_block_emu(pc+2);
nkeynes@601
  2095
	    return 2;
nkeynes@601
  2096
	} else {
nkeynes@601
  2097
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2098
	    exit_block_newpcset(pc+4);
nkeynes@601
  2099
	    return 4;
nkeynes@601
  2100
	}
nkeynes@374
  2101
    }
nkeynes@374
  2102
:}
nkeynes@374
  2103
RTE {:  
nkeynes@671
  2104
    COUNT_INST(I_RTE);
nkeynes@374
  2105
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2106
	SLOTILLEGAL();
nkeynes@374
  2107
    } else {
nkeynes@408
  2108
	check_priv();
nkeynes@995
  2109
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  2110
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  2111
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  2112
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  2113
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  2114
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2115
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2116
	sh4_x86.branch_taken = TRUE;
nkeynes@1112
  2117
    sh4_x86.sh4_mode = SH4_MODE_UNKNOWN;
nkeynes@601
  2118
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2119
	    exit_block_emu(pc+2);
nkeynes@601
  2120
	    return 2;
nkeynes@601
  2121
	} else {
nkeynes@601
  2122
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2123
	    exit_block_newpcset(pc+4);
nkeynes@601
  2124
	    return 4;
nkeynes@601
  2125
	}
nkeynes@374
  2126
    }
nkeynes@374
  2127
:}
nkeynes@374
  2128
RTS {:  
nkeynes@671
  2129
    COUNT_INST(I_RTS);
nkeynes@374
  2130
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2131
	SLOTILLEGAL();
nkeynes@374
  2132
    } else {
nkeynes@995
  2133
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  2134
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2135
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2136
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2137
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2138
	    exit_block_emu(pc+2);
nkeynes@601
  2139
	    return 2;
nkeynes@601
  2140
	} else {
nkeynes@601
  2141
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2142
	    exit_block_newpcset(pc+4);
nkeynes@601
  2143
	    return 4;
nkeynes@601
  2144
	}
nkeynes@374
  2145
    }
nkeynes@374
  2146
:}
nkeynes@374
  2147
TRAPA #imm {:  
nkeynes@671
  2148
    COUNT_INST(I_TRAPA);
nkeynes@374
  2149
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2150
	SLOTILLEGAL();
nkeynes@374
  2151
    } else {
nkeynes@995
  2152
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  2153
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  2154
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  2155
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  2156
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  2157
	exit_block_pcset(pc+2);
nkeynes@409
  2158
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2159
	return 2;
nkeynes@374
  2160
    }
nkeynes@374
  2161
:}
nkeynes@374
  2162
UNDEF {:  
nkeynes@671
  2163
    COUNT_INST(I_UNDEF);
nkeynes@374
  2164
    if( sh4_x86.in_delay_slot ) {
nkeynes@1191
  2165
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4);    
nkeynes@374
  2166
    } else {
nkeynes@1191
  2167
	exit_block_exc(EXC_ILLEGAL, pc, 2);    
nkeynes@408
  2168
	return 2;
nkeynes@374
  2169
    }
nkeynes@368
  2170
:}
nkeynes@374
  2171
nkeynes@374
  2172
CLRMAC {:  
nkeynes@671
  2173
    COUNT_INST(I_CLRMAC);
nkeynes@991
  2174
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  2175
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  2176
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2178
:}
nkeynes@374
  2179
CLRS {:
nkeynes@671
  2180
    COUNT_INST(I_CLRS);
nkeynes@374
  2181
    CLC();
nkeynes@991
  2182
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2183
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2184
:}
nkeynes@374
  2185
CLRT {:  
nkeynes@671
  2186
    COUNT_INST(I_CLRT);
nkeynes@374
  2187
    CLC();
nkeynes@374
  2188
    SETC_t();
nkeynes@417
  2189
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2190
:}
nkeynes@374
  2191
SETS {:  
nkeynes@671
  2192
    COUNT_INST(I_SETS);
nkeynes@374
  2193
    STC();
nkeynes@991
  2194
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2196
:}
nkeynes@374
  2197
SETT {:  
nkeynes@671
  2198
    COUNT_INST(I_SETT);
nkeynes@374
  2199
    STC();
nkeynes@374
  2200
    SETC_t();
nkeynes@417
  2201
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  2202
:}
nkeynes@359
  2203
nkeynes@375
  2204
/* Floating point moves */
nkeynes@375
  2205
FMOV FRm, FRn {:  
nkeynes@671
  2206
    COUNT_INST(I_FMOV1);
nkeynes@377
  2207
    check_fpuen();
nkeynes@901
  2208
    if( sh4_x86.double_size ) {
nkeynes@991
  2209
        load_dr0( REG_EAX, FRm );
nkeynes@991
  2210
        load_dr1( REG_ECX, FRm );
nkeynes@991
  2211
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2212
        store_dr1( REG_ECX, FRn );
nkeynes@901
  2213
    } else {
nkeynes@991
  2214
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  2215
        store_fr( REG_EAX, FRn );
nkeynes@901
  2216
    }
nkeynes@375
  2217
:}
nkeynes@416
  2218
FMOV FRm, @Rn {: 
nkeynes@671
  2219
    COUNT_INST(I_FMOV2);
nkeynes@586
  2220
    check_fpuen();
nkeynes@991
  2221
    load_reg( REG_EAX, Rn );
nkeynes@901
  2222
    if( sh4_x86.double_size ) {
nkeynes@991
  2223
        check_walign64( REG_EAX );
nkeynes@991
  2224
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2225
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2226
        load_reg( REG_EAX, Rn );
nkeynes@991
  2227
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2228
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2229
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2230
    } else {
nkeynes@991
  2231
        check_walign32( REG_EAX );
nkeynes@991
  2232
        load_fr( REG_EDX, FRm );
nkeynes@991
  2233
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2234
    }
nkeynes@417
  2235
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2236
:}
nkeynes@375
  2237
FMOV @Rm, FRn {:  
nkeynes@671
  2238
    COUNT_INST(I_FMOV5);
nkeynes@586
  2239
    check_fpuen();
nkeynes@991
  2240
    load_reg( REG_EAX, Rm );
nkeynes@901
  2241
    if( sh4_x86.double_size ) {
nkeynes@991
  2242
        check_ralign64( REG_EAX );
nkeynes@991
  2243
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2244
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2245
        load_reg( REG_EAX, Rm );
nkeynes@991
  2246
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2247
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2248
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2249
    } else {
nkeynes@991
  2250
        check_ralign32( REG_EAX );
nkeynes@991
  2251
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2252
        store_fr( REG_EAX, FRn );
nkeynes@901
  2253
    }
nkeynes@417
  2254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2255
:}
nkeynes@377
  2256
FMOV FRm, @-Rn {:  
nkeynes@671
  2257
    COUNT_INST(I_FMOV3);
nkeynes@586
  2258
    check_fpuen();
nkeynes@991
  2259
    load_reg( REG_EAX, Rn );
nkeynes@901
  2260
    if( sh4_x86.double_size ) {
nkeynes@991
  2261
        check_walign64( REG_EAX );
nkeynes@991
  2262
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2263
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2264
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2265
        load_reg( REG_EAX, Rn );
nkeynes@991
  2266
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2267
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2268
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2269
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2270
    } else {
nkeynes@991
  2271
        check_walign32( REG_EAX );
nkeynes@991
  2272
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2273
        load_fr( REG_EDX, FRm );
nkeynes@991
  2274
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2275
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2276
    }
nkeynes@417
  2277
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2278
:}
nkeynes@416
  2279
FMOV @Rm+, FRn {:
nkeynes@671
  2280
    COUNT_INST(I_FMOV6);
nkeynes@586
  2281
    check_fpuen();
nkeynes@991
  2282
    load_reg( REG_EAX, Rm );
nkeynes@901
  2283
    if( sh4_x86.double_size ) {
nkeynes@991
  2284
        check_ralign64( REG_EAX );
nkeynes@991
  2285
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2286
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2287
        load_reg( REG_EAX, Rm );
nkeynes@991
  2288
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2289
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2290
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2291
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2292
    } else {
nkeynes@991
  2293
        check_ralign32( REG_EAX );
nkeynes@991
  2294
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2295
        store_fr( REG_EAX, FRn );
nkeynes@991
  2296
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2297
    }
nkeynes@417
  2298
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2299
:}
nkeynes@377
  2300
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2301
    COUNT_INST(I_FMOV4);
nkeynes@586
  2302
    check_fpuen();
nkeynes@991
  2303
    load_reg( REG_EAX, Rn );
nkeynes@991
  2304
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2305
    if( sh4_x86.double_size ) {
nkeynes@991
  2306
        check_walign64( REG_EAX );
nkeynes@991
  2307
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2308
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2309
        load_reg( REG_EAX, Rn );
nkeynes@991
  2310
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2311
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2312
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2313
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2314
    } else {
nkeynes@991
  2315
        check_walign32( REG_EAX );
nkeynes@991
  2316
        load_fr( REG_EDX, FRm );
nkeynes@991
  2317
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2318
    }
nkeynes@417
  2319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2320
:}
nkeynes@377
  2321
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2322
    COUNT_INST(I_FMOV7);
nkeynes@586
  2323
    check_fpuen();
nkeynes@991
  2324
    load_reg( REG_EAX, Rm );
nkeynes@991
  2325
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2326
    if( sh4_x86.double_size ) {
nkeynes@991
  2327
        check_ralign64( REG_EAX );
nkeynes@991
  2328
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2329
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2330
        load_reg( REG_EAX, Rm );
nkeynes@991
  2331
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2332
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2333
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2334
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2335
    } else {
nkeynes@991
  2336
        check_ralign32( REG_EAX );
nkeynes@991
  2337
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2338
        store_fr( REG_EAX, FRn );
nkeynes@901
  2339
    }
nkeynes@417
  2340
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2341
:}
nkeynes@377
  2342
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2343
    COUNT_INST(I_FLDI0);
nkeynes@377
  2344
    check_fpuen();
nkeynes@901
  2345
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2346
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2347
        store_fr( REG_EAX, FRn );
nkeynes@901
  2348
    }
nkeynes@417
  2349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2350
:}
nkeynes@377
  2351
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2352
    COUNT_INST(I_FLDI1);
nkeynes@377
  2353
    check_fpuen();
nkeynes@901
  2354
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2355
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2356
        store_fr( REG_EAX, FRn );
nkeynes@901
  2357
    }
nkeynes@377
  2358
:}
nkeynes@377
  2359
nkeynes@377
  2360
FLOAT FPUL, FRn {:  
nkeynes@671
  2361
    COUNT_INST(I_FLOAT);
nkeynes@377
  2362
    check_fpuen();
nkeynes@991
  2363
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2364
    if( sh4_x86.double_prec ) {
nkeynes@901
  2365
        pop_dr( FRn );
nkeynes@901
  2366
    } else {
nkeynes@901
  2367
        pop_fr( FRn );
nkeynes@901
  2368
    }
nkeynes@377
  2369
:}
nkeynes@377
  2370
FTRC FRm, FPUL {:  
nkeynes@671
  2371
    COUNT_INST(I_FTRC);
nkeynes@377
  2372
    check_fpuen();
nkeynes@901
  2373
    if( sh4_x86.double_prec ) {
nkeynes@901
  2374
        push_dr( FRm );
nkeynes@901
  2375
    } else {
nkeynes@901
  2376
        push_fr( FRm );
nkeynes@901
  2377
    }
nkeynes@1197
  2378
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@1197
  2379
    FILD_r32disp( REG_ECX, 0 );
nkeynes@1197
  2380
    FCOMIP_st(1);              
nkeynes@1197
  2381
    JAE_label( sat );     
nkeynes@1197
  2382
    JP_label( sat2 );       
nkeynes@995
  2383
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2384
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2385
    FCOMIP_st(1);
nkeynes@1197
  2386
    JNA_label( sat3 );
nkeynes@995
  2387
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2388
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2389
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2390
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2391
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2392
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2393
    JMP_label(end);             
nkeynes@388
  2394
nkeynes@388
  2395
    JMP_TARGET(sat);
nkeynes@388
  2396
    JMP_TARGET(sat2);
nkeynes@1197
  2397
    JMP_TARGET(sat3);
nkeynes@991
  2398
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2399
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2400
    FPOP_st();
nkeynes@388
  2401
    JMP_TARGET(end);
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2403
:}
nkeynes@377
  2404
FLDS FRm, FPUL {:  
nkeynes@671
  2405
    COUNT_INST(I_FLDS);
nkeynes@377
  2406
    check_fpuen();
nkeynes@991
  2407
    load_fr( REG_EAX, FRm );
nkeynes@995
  2408
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2409
:}
nkeynes@377
  2410
FSTS FPUL, FRn {:  
nkeynes@671
  2411
    COUNT_INST(I_FSTS);
nkeynes@377
  2412
    check_fpuen();
nkeynes@995
  2413
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2414
    store_fr( REG_EAX, FRn );
nkeynes@377
  2415
:}
nkeynes@377
  2416
FCNVDS FRm, FPUL {:  
nkeynes@671
  2417
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2418
    check_fpuen();
nkeynes@901
  2419
    if( sh4_x86.double_prec ) {
nkeynes@901
  2420
        push_dr( FRm );
nkeynes@901
  2421
        pop_fpul();
nkeynes@901
  2422
    }
nkeynes@377
  2423
:}
nkeynes@377
  2424
FCNVSD FPUL, FRn {:  
nkeynes@671
  2425
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2426
    check_fpuen();
nkeynes@901
  2427
    if( sh4_x86.double_prec ) {
nkeynes@901
  2428
        push_fpul();
nkeynes@901
  2429
        pop_dr( FRn );
nkeynes@901
  2430
    }
nkeynes@377
  2431
:}
nkeynes@375
  2432
nkeynes@359
  2433
/* Floating point instructions */
nkeynes@374
  2434
FABS FRn {:  
nkeynes@671
  2435
    COUNT_INST(I_FABS);
nkeynes@377
  2436
    check_fpuen();
nkeynes@901
  2437
    if( sh4_x86.double_prec ) {
nkeynes@901
  2438
        push_dr(FRn);
nkeynes@901
  2439
        FABS_st0();
nkeynes@901
  2440
        pop_dr(FRn);
nkeynes@901
  2441
    } else {
nkeynes@901
  2442
        push_fr(FRn);
nkeynes@901
  2443
        FABS_st0();
nkeynes@901
  2444
        pop_fr(FRn);
nkeynes@901
  2445
    }
nkeynes@374
  2446
:}
nkeynes@377
  2447
FADD FRm, FRn {:  
nkeynes@671
  2448
    COUNT_INST(I_FADD);
nkeynes@377
  2449
    check_fpuen();
nkeynes@901
  2450
    if( sh4_x86.double_prec ) {
nkeynes@901
  2451
        push_dr(FRm);
nkeynes@901
  2452
        push_dr(FRn);
nkeynes@901
  2453
        FADDP_st(1);
nkeynes@901
  2454
        pop_dr(FRn);
nkeynes@901
  2455
    } else {
nkeynes@901
  2456
        push_fr(FRm);
nkeynes@901
  2457
        push_fr(FRn);
nkeynes@901
  2458
        FADDP_st(1);
nkeynes@901
  2459
        pop_fr(FRn);
nkeynes@901
  2460
    }
nkeynes@375
  2461
:}
nkeynes@377
  2462
FDIV FRm, FRn {:  
nkeynes@671
  2463
    COUNT_INST(I_FDIV);
nkeynes@377
  2464
    check_fpuen();
nkeynes@901
  2465
    if( sh4_x86.double_prec ) {
nkeynes@901
  2466
        push_dr(FRn);
nkeynes@901
  2467
        push_dr(FRm);
nkeynes@901
  2468
        FDIVP_st(1);
nkeynes@901
  2469
        pop_dr(FRn);
nkeynes@901
  2470
    } else {
nkeynes@901
  2471
        push_fr(FRn);
nkeynes@901
  2472
        push_fr(FRm);
nkeynes@901
  2473
        FDIVP_st(1);
nkeynes@901
  2474
        pop_fr(FRn);
nkeynes@901
  2475
    }
nkeynes@375
  2476
:}
nkeynes@375
  2477
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2478
    COUNT_INST(I_FMAC);
nkeynes@377
  2479
    check_fpuen();
nkeynes@901
  2480
    if( sh4_x86.double_prec ) {
nkeynes@901
  2481
        push_dr( 0 );
nkeynes@901
  2482
        push_dr( FRm );
nkeynes@901
  2483
        FMULP_st(1);
nkeynes@901
  2484
        push_dr( FRn );
nkeynes@901
  2485
        FADDP_st(1);
nkeynes@901
  2486
        pop_dr( FRn );
nkeynes@901
  2487
    } else {
nkeynes@901
  2488
        push_fr( 0 );
nkeynes@901
  2489
        push_fr( FRm );
nkeynes@901
  2490
        FMULP_st(1);
nkeynes@901
  2491
        push_fr( FRn );
nkeynes@901
  2492
        FADDP_st(1);
nkeynes@901
  2493
        pop_fr( FRn );
nkeynes@901
  2494
    }
nkeynes@375
  2495
:}
nkeynes@375
  2496
nkeynes@377
  2497
FMUL FRm, FRn {:  
nkeynes@671
  2498
    COUNT_INST(I_FMUL);
nkeynes@377
  2499
    check_fpuen();
nkeynes@901
  2500
    if( sh4_x86.double_prec ) {
nkeynes@901
  2501
        push_dr(FRm);
nkeynes@901
  2502
        push_dr(FRn);
nkeynes@901
  2503
        FMULP_st(1);
nkeynes@901
  2504
        pop_dr(FRn);
nkeynes@901
  2505
    } else {
nkeynes@901
  2506
        push_fr(FRm);
nkeynes@901
  2507
        push_fr(FRn);
nkeynes@901
  2508
        FMULP_st(1);
nkeynes@901
  2509
        pop_fr(FRn);
nkeynes@901
  2510
    }
nkeynes@377
  2511
:}
nkeynes@377
  2512
FNEG FRn {:  
nkeynes@671
  2513
    COUNT_INST(I_FNEG);
nkeynes@377
  2514
    check_fpuen();
nkeynes@901
  2515
    if( sh4_x86.double_prec ) {
nkeynes@901
  2516
        push_dr(FRn);
nkeynes@901
  2517
        FCHS_st0();
nkeynes@901
  2518
        pop_dr(FRn);
nkeynes@901
  2519
    } else {
nkeynes@901
  2520
        push_fr(FRn);
nkeynes@901
  2521
        FCHS_st0();
nkeynes@901
  2522
        pop_fr(FRn);
nkeynes@901
  2523
    }
nkeynes@377
  2524
:}
nkeynes@377
  2525
FSRRA FRn {:  
nkeynes@671
  2526
    COUNT_INST(I_FSRRA);
nkeynes@377
  2527
    check_fpuen();
nkeynes@901
  2528
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2529
        FLD1_st0();
nkeynes@901
  2530
        push_fr(FRn);
nkeynes@901
  2531
        FSQRT_st0();
nkeynes@901
  2532
        FDIVP_st(1);
nkeynes@901
  2533
        pop_fr(FRn);
nkeynes@901
  2534
    }
nkeynes@377
  2535
:}
nkeynes@377
  2536
FSQRT FRn {:  
nkeynes@671
  2537
    COUNT_INST(I_FSQRT);
nkeynes@377
  2538
    check_fpuen();
nkeynes@901
  2539
    if( sh4_x86.double_prec ) {
nkeynes@901
  2540
        push_dr(FRn);
nkeynes@901
  2541
        FSQRT_st0();
nkeynes@901
  2542
        pop_dr(FRn);
nkeynes@901
  2543
    } else {
nkeynes@901
  2544
        push_fr(FRn);
nkeynes@901
  2545
        FSQRT_st0();
nkeynes@901
  2546
        pop_fr(FRn);
nkeynes@901
  2547
    }
nkeynes@377
  2548
:}
nkeynes@377
  2549
FSUB FRm, FRn {:  
nkeynes@671
  2550
    COUNT_INST(I_FSUB);
nkeynes@377
  2551
    check_fpuen();
nkeynes@901
  2552
    if( sh4_x86.double_prec ) {
nkeynes@901
  2553
        push_dr(FRn);
nkeynes@901
  2554
        push_dr(FRm);
nkeynes@901
  2555
        FSUBP_st(1);
nkeynes@901
  2556
        pop_dr(FRn);
nkeynes@901
  2557
    } else {
nkeynes@901
  2558
        push_fr(FRn);
nkeynes@901
  2559
        push_fr(FRm);
nkeynes@901
  2560
        FSUBP_st(1);
nkeynes@901
  2561
        pop_fr(FRn);
nkeynes@901
  2562
    }
nkeynes@377
  2563
:}
nkeynes@377
  2564
nkeynes@377
  2565
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2566
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2567
    check_fpuen();
nkeynes@901
  2568
    if( sh4_x86.double_prec ) {
nkeynes@901
  2569
        push_dr(FRm);
nkeynes@901
  2570
        push_dr(FRn);
nkeynes@901
  2571
    } else {
nkeynes@901
  2572
        push_fr(FRm);
nkeynes@901
  2573
        push_fr(FRn);
nkeynes@901
  2574
    }
nkeynes@1197
  2575
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@1197
  2576
    XORL_r32_r32(REG_EDX, REG_EDX);
nkeynes@377
  2577
    FCOMIP_st(1);
nkeynes@1197
  2578
    SETCCB_cc_r8(X86_COND_NP, REG_DL);
nkeynes@1197
  2579
    CMOVCCL_cc_r32_r32(X86_COND_E, REG_EDX, REG_EAX);
nkeynes@1197
  2580
    MOVL_r32_rbpdisp(REG_EAX, R_T);
nkeynes@377
  2581
    FPOP_st();
nkeynes@1197
  2582
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2583
:}
nkeynes@377
  2584
FCMP/GT FRm, FRn {:  
nkeynes@671
  2585
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2586
    check_fpuen();
nkeynes@901
  2587
    if( sh4_x86.double_prec ) {
nkeynes@901
  2588
        push_dr(FRm);
nkeynes@901
  2589
        push_dr(FRn);
nkeynes@901
  2590
    } else {
nkeynes@901
  2591
        push_fr(FRm);
nkeynes@901
  2592
        push_fr(FRn);
nkeynes@901
  2593
    }
nkeynes@377
  2594
    FCOMIP_st(1);
nkeynes@377
  2595
    SETA_t();
nkeynes@377
  2596
    FPOP_st();
nkeynes@901
  2597
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2598
:}
nkeynes@377
  2599
nkeynes@377
  2600
FSCA FPUL, FRn {:  
nkeynes@671
  2601
    COUNT_INST(I_FSCA);
nkeynes@377
  2602
    check_fpuen();
nkeynes@901
  2603
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2604
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2605
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2606
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2607
    }
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2609
:}
nkeynes@377
  2610
FIPR FVm, FVn {:  
nkeynes@671
  2611
    COUNT_INST(I_FIPR);
nkeynes@377
  2612
    check_fpuen();
nkeynes@901
  2613
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2614
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2615
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2616
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2617
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2618
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2619
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2620
        } else {
nkeynes@904
  2621
            push_fr( FVm<<2 );
nkeynes@903
  2622
            push_fr( FVn<<2 );
nkeynes@903
  2623
            FMULP_st(1);
nkeynes@903
  2624
            push_fr( (FVm<<2)+1);
nkeynes@903
  2625
            push_fr( (FVn<<2)+1);
nkeynes@903
  2626
            FMULP_st(1);
nkeynes@903
  2627
            FADDP_st(1);
nkeynes@903
  2628
            push_fr( (FVm<<2)+2);
nkeynes@903
  2629
            push_fr( (FVn<<2)+2);
nkeynes@903
  2630
            FMULP_st(1);
nkeynes@903
  2631
            FADDP_st(1);
nkeynes@903
  2632
            push_fr( (FVm<<2)+3);
nkeynes@903
  2633
            push_fr( (FVn<<2)+3);
nkeynes@903
  2634
            FMULP_st(1);
nkeynes@903
  2635
            FADDP_st(1);
nkeynes@903
  2636
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2637
        }
nkeynes@901
  2638
    }
nkeynes@377
  2639
:}
nkeynes@377
  2640
FTRV XMTRX, FVn {:  
nkeynes@671
  2641
    COUNT_INST(I_FTRV);
nkeynes@377
  2642
    check_fpuen();
nkeynes@901
  2643
    if( sh4_x86.double_prec == 0 ) {
nkeynes@1194
  2644
        if( sh4_x86.sse3_enabled && sh4_x86.begin_callback == NULL ) {
nkeynes@1194
  2645
        	/* FIXME: For now, disable this inlining when we're running in shadow mode -
nkeynes@1194
  2646
        	 * it gives slightly different results from the emu core. Need to
nkeynes@1194
  2647
        	 * fix the precision so both give the right results.
nkeynes@1194
  2648
        	 */
nkeynes@991
  2649
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2650
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2651
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2652
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2653
nkeynes@991
  2654
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2655
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2656
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2657
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2658
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2659
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2660
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2661
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2662
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2663
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2664
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2665
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2666
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2667
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2668
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2669
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2670
        } else {
nkeynes@991
  2671
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][