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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (13 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "mem.h"
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>PAGE_BITS)
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#define OCRAM_END   (0x20000000>>PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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	return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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	return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch(reg) {
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    case PTEH:
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	val &= 0xFFFFFCFF;
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	if( (val & 0xFF) != mmu_asid ) {
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	    mmu_asid = val&0xFF;
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	    sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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	}
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	break;
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    case PTEL:
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	val &= 0x1FFFFDFF;
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	break;
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    case PTEA:
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	val &= 0x0000000F;
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	break;
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    case MMUCR:
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	if( val & MMUCR_TI ) {
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	    mmu_invalidate_tlb();
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	}
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	mmu_urc = (val >> 10) & 0x3F;
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	mmu_urb = (val >> 18) & 0x3F;
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	mmu_lrui = (val >> 26) & 0x3F;
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	val &= 0x00000301;
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	tmp = MMIO_READ( MMU, MMUCR );
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	if( ((val ^ tmp) & MMUCR_AT) ) {
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	    // AT flag has changed state - flush the xlt cache as all bets
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	    // are off now. We also need to force an immediate exit from the
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	    // current block
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	    xlat_flush_cache();
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	}
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	break;
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    case CCR:
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	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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	break;
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    default:
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	break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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	return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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	return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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	return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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        case MEM_OC_INDEX0: /* OIX=0 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
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            break;
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        case MEM_OC_INDEX1: /* OIX=1 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
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            break;
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        default: /* disabled */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = NULL;
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            break;
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    }
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}
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/* TLB maintanence */
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static void mmu_invalidate_tlb()
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{
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    int i;
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    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
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	mmu_itlb[i].flags &= (~TLB_VALID);
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    }
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    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
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	mmu_utlb[i].flags &= (~TLB_VALID);
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    }
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}
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#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
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int32_t mmu_itlb_addr_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
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}
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int32_t mmu_itlb_data_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->ppn | ent->flags;
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}
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void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->vpn = val & 0xFFFFFC00;
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    ent->asid = val & 0x000000FF;
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    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
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}
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void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->ppn = val & 0x1FFFFC00;
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    ent->flags = val & 0x00001DA;
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    ent->mask = get_mask_for_flags(val);
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}
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#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
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#define UTLB_ASSOC(addr) (addr&0x80)
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#define UTLB_DATA2(addr) (addr&0x00800000)
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int32_t mmu_utlb_addr_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
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	((ent->flags & TLB_DIRTY)<<7);
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}
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int32_t mmu_utlb_data_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    if( UTLB_DATA2(addr) ) {
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	return ent->pcmcia;
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    } else {
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	return ent->ppn | ent->flags;
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    }
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}
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/**
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 * Find a UTLB entry for the associative TLB write - same as the normal
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 * lookup but ignores the valid bit.
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 */
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static inline mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
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{
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    int result = -1;
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    unsigned int i;
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    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
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	if( ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
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	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@570
   335
	    if( result != -1 ) {
nkeynes@570
   336
		return -2;
nkeynes@570
   337
	    }
nkeynes@570
   338
	    result = i;
nkeynes@570
   339
	}
nkeynes@570
   340
    }
nkeynes@570
   341
    return result;
nkeynes@570
   342
}
nkeynes@570
   343
nkeynes@570
   344
/**
nkeynes@570
   345
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@570
   346
 * lookup but ignores the valid bit.
nkeynes@570
   347
 */
nkeynes@570
   348
static inline mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@570
   349
{
nkeynes@570
   350
    int result = -1;
nkeynes@570
   351
    unsigned int i;
nkeynes@570
   352
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@570
   353
	if( ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
nkeynes@570
   354
	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@570
   355
	    if( result != -1 ) {
nkeynes@570
   356
		return -2;
nkeynes@570
   357
	    }
nkeynes@570
   358
	    result = i;
nkeynes@570
   359
	}
nkeynes@570
   360
    }
nkeynes@570
   361
    return result;
nkeynes@570
   362
}
nkeynes@570
   363
nkeynes@570
   364
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   365
{
nkeynes@570
   366
    if( UTLB_ASSOC(addr) ) {
nkeynes@570
   367
	uint32_t asid = MMIO_READ( MMU, PTEH ) & 0xFF;
nkeynes@570
   368
	int utlb = mmu_utlb_lookup_assoc( val, asid );
nkeynes@570
   369
	if( utlb >= 0 ) {
nkeynes@570
   370
	    struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@570
   371
	    ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@570
   372
	    ent->flags |= (val & TLB_VALID);
nkeynes@570
   373
	    ent->flags |= ((val & 0x200)>>7);
nkeynes@570
   374
	}
nkeynes@570
   375
nkeynes@570
   376
	int itlb = mmu_itlb_lookup_assoc( val, asid );
nkeynes@570
   377
	if( itlb >= 0 ) {
nkeynes@570
   378
	    struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@570
   379
	    ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@570
   380
	}
nkeynes@570
   381
nkeynes@570
   382
	if( itlb == -2 || utlb == -2 ) {
nkeynes@570
   383
	    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@570
   384
	    return;
nkeynes@570
   385
	}
nkeynes@570
   386
    } else {
nkeynes@570
   387
	struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@570
   388
	ent->vpn = (val & 0xFFFFFC00);
nkeynes@570
   389
	ent->asid = (val & 0xFF);
nkeynes@570
   390
	ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@570
   391
	ent->flags |= (val & TLB_VALID);
nkeynes@570
   392
	ent->flags |= ((val & 0x200)>>7);
nkeynes@570
   393
    }
nkeynes@570
   394
}
nkeynes@570
   395
nkeynes@570
   396
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   397
{
nkeynes@570
   398
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@570
   399
    if( UTLB_DATA2(addr) ) {
nkeynes@570
   400
	ent->pcmcia = val & 0x0000000F;
nkeynes@570
   401
    } else {
nkeynes@570
   402
	ent->ppn = (val & 0x1FFFFC00);
nkeynes@570
   403
	ent->flags = (val & 0x000001FF);
nkeynes@570
   404
	ent->mask = get_mask_for_flags(val);
nkeynes@570
   405
    }
nkeynes@570
   406
}
nkeynes@570
   407
nkeynes@570
   408
/* Cache access - not implemented */
nkeynes@570
   409
nkeynes@570
   410
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@570
   411
{
nkeynes@570
   412
    return 0; // not implemented
nkeynes@570
   413
}
nkeynes@570
   414
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@570
   415
{
nkeynes@570
   416
    return 0; // not implemented
nkeynes@570
   417
}
nkeynes@570
   418
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@570
   419
{
nkeynes@570
   420
    return 0; // not implemented
nkeynes@570
   421
}
nkeynes@570
   422
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@570
   423
{
nkeynes@570
   424
    return 0; // not implemented
nkeynes@570
   425
}
nkeynes@570
   426
nkeynes@570
   427
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   428
{
nkeynes@570
   429
}
nkeynes@570
   430
nkeynes@570
   431
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   432
{
nkeynes@570
   433
}
nkeynes@570
   434
nkeynes@570
   435
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   436
{
nkeynes@570
   437
}
nkeynes@570
   438
nkeynes@570
   439
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@570
   440
{
nkeynes@570
   441
}
nkeynes@570
   442
nkeynes@570
   443
/******************************************************************************/
nkeynes@570
   444
/*                        MMU TLB address translation                         */
nkeynes@570
   445
/******************************************************************************/
nkeynes@570
   446
nkeynes@570
   447
/**
nkeynes@559
   448
 * The translations are excessively complicated, but unfortunately it's a 
nkeynes@570
   449
 * complicated system. TODO: make this not be painfully slow.
nkeynes@559
   450
 */
nkeynes@559
   451
nkeynes@559
   452
/**
nkeynes@569
   453
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@559
   454
 * Possible utcomes are:
nkeynes@559
   455
 *   0..63 Single match - good, return entry found
nkeynes@559
   456
 *   -1 No match - raise a tlb data miss exception
nkeynes@559
   457
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@559
   458
 * @param vpn virtual address to resolve
nkeynes@559
   459
 * @return the resultant UTLB entry, or an error.
nkeynes@559
   460
 */
nkeynes@569
   461
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@559
   462
{
nkeynes@559
   463
    int result = -1;
nkeynes@559
   464
    unsigned int i;
nkeynes@559
   465
nkeynes@559
   466
    mmu_urc++;
nkeynes@559
   467
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@559
   468
	mmu_urc = 0;
nkeynes@559
   469
    }
nkeynes@559
   470
nkeynes@569
   471
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@569
   472
	if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@569
   473
	    ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) && 
nkeynes@569
   474
	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@569
   475
	    if( result != -1 ) {
nkeynes@569
   476
		return -2;
nkeynes@550
   477
	    }
nkeynes@569
   478
	    result = i;
nkeynes@550
   479
	}
nkeynes@550
   480
    }
nkeynes@559
   481
    return result;
nkeynes@559
   482
}
nkeynes@559
   483
nkeynes@559
   484
/**
nkeynes@569
   485
 * Perform the actual utlb lookup matching on vpn only
nkeynes@569
   486
 * Possible utcomes are:
nkeynes@569
   487
 *   0..63 Single match - good, return entry found
nkeynes@569
   488
 *   -1 No match - raise a tlb data miss exception
nkeynes@569
   489
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@569
   490
 * @param vpn virtual address to resolve
nkeynes@569
   491
 * @return the resultant UTLB entry, or an error.
nkeynes@569
   492
 */
nkeynes@569
   493
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@569
   494
{
nkeynes@569
   495
    int result = -1;
nkeynes@569
   496
    unsigned int i;
nkeynes@569
   497
nkeynes@569
   498
    mmu_urc++;
nkeynes@569
   499
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@569
   500
	mmu_urc = 0;
nkeynes@569
   501
    }
nkeynes@569
   502
nkeynes@569
   503
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@569
   504
	if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@569
   505
	    ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@569
   506
	    if( result != -1 ) {
nkeynes@569
   507
		return -2;
nkeynes@569
   508
	    }
nkeynes@569
   509
	    result = i;
nkeynes@569
   510
	}
nkeynes@569
   511
    }
nkeynes@569
   512
nkeynes@569
   513
    return result;
nkeynes@569
   514
}
nkeynes@569
   515
nkeynes@569
   516
/**
nkeynes@569
   517
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@569
   518
 * @return the number (0-3) of the replaced entry.
nkeynes@559
   519
 */
nkeynes@559
   520
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@559
   521
{
nkeynes@559
   522
    int replace;
nkeynes@559
   523
    /* Determine entry to replace based on lrui */
nkeynes@559
   524
    if( mmu_lrui & 0x38 == 0x38 ) {
nkeynes@559
   525
	replace = 0;
nkeynes@559
   526
	mmu_lrui = mmu_lrui & 0x07;
nkeynes@559
   527
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@559
   528
	replace = 1;
nkeynes@559
   529
	mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@559
   530
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@559
   531
	replace = 2;
nkeynes@559
   532
	mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@559
   533
    } else { // Note - gets invalid entries too
nkeynes@559
   534
	replace = 3;
nkeynes@559
   535
	mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@559
   536
    } 
nkeynes@559
   537
nkeynes@559
   538
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@559
   539
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@559
   540
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@559
   541
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@559
   542
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@559
   543
    return replace;
nkeynes@559
   544
}
nkeynes@559
   545
nkeynes@559
   546
/**
nkeynes@569
   547
 * Perform the actual itlb lookup w/ asid protection
nkeynes@569
   548
 * Possible utcomes are:
nkeynes@569
   549
 *   0..63 Single match - good, return entry found
nkeynes@569
   550
 *   -1 No match - raise a tlb data miss exception
nkeynes@569
   551
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@569
   552
 * @param vpn virtual address to resolve
nkeynes@569
   553
 * @return the resultant ITLB entry, or an error.
nkeynes@569
   554
 */
nkeynes@569
   555
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@569
   556
{
nkeynes@569
   557
    int result = -1;
nkeynes@569
   558
    unsigned int i;
nkeynes@569
   559
nkeynes@569
   560
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@569
   561
	if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@569
   562
	    ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) && 
nkeynes@569
   563
	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@569
   564
	    if( result != -1 ) {
nkeynes@569
   565
		return -2;
nkeynes@569
   566
	    }
nkeynes@569
   567
	    result = i;
nkeynes@569
   568
	}
nkeynes@569
   569
    }
nkeynes@569
   570
nkeynes@569
   571
    if( result == -1 ) {
nkeynes@569
   572
	int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@569
   573
	if( utlbEntry == -1 ) {
nkeynes@569
   574
	    return -1;
nkeynes@569
   575
	} else {
nkeynes@569
   576
	    return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@569
   577
	}
nkeynes@569
   578
    }
nkeynes@569
   579
nkeynes@569
   580
    switch( result ) {
nkeynes@569
   581
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@569
   582
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@569
   583
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@569
   584
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@569
   585
    }
nkeynes@569
   586
	
nkeynes@569
   587
    return result;
nkeynes@569
   588
}
nkeynes@569
   589
nkeynes@569
   590
/**
nkeynes@569
   591
 * Perform the actual itlb lookup on vpn only
nkeynes@569
   592
 * Possible utcomes are:
nkeynes@569
   593
 *   0..63 Single match - good, return entry found
nkeynes@569
   594
 *   -1 No match - raise a tlb data miss exception
nkeynes@569
   595
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@569
   596
 * @param vpn virtual address to resolve
nkeynes@569
   597
 * @return the resultant ITLB entry, or an error.
nkeynes@569
   598
 */
nkeynes@569
   599
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@569
   600
{
nkeynes@569
   601
    int result = -1;
nkeynes@569
   602
    unsigned int i;
nkeynes@569
   603
nkeynes@569
   604
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@569
   605
	if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@569
   606
	    ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@569
   607
	    if( result != -1 ) {
nkeynes@569
   608
		return -2;
nkeynes@569
   609
	    }
nkeynes@569
   610
	    result = i;
nkeynes@569
   611
	}
nkeynes@569
   612
    }
nkeynes@569
   613
nkeynes@569
   614
    if( result == -1 ) {
nkeynes@569
   615
	int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@569
   616
	if( utlbEntry == -1 ) {
nkeynes@569
   617
	    return -1;
nkeynes@569
   618
	} else {
nkeynes@569
   619
	    return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@569
   620
	}
nkeynes@569
   621
    }
nkeynes@569
   622
nkeynes@569
   623
    switch( result ) {
nkeynes@569
   624
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@569
   625
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@569
   626
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@569
   627
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@569
   628
    }
nkeynes@569
   629
	
nkeynes@569
   630
    return result;
nkeynes@569
   631
}
nkeynes@569
   632
nkeynes@570
   633
sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@559
   634
{
nkeynes@559
   635
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@559
   636
    if( addr & 0x80000000 ) {
nkeynes@559
   637
	if( IS_SH4_PRIVMODE() ) {
nkeynes@570
   638
	    if( addr >= 0xE0000000 ) {
nkeynes@570
   639
		return addr; /* P4 - passthrough */
nkeynes@570
   640
	    } else if( addr < 0xC0000000 ) {
nkeynes@570
   641
		/* P1, P2 regions are pass-through (no translation) */
nkeynes@570
   642
		return VMA_TO_EXT_ADDR(addr);
nkeynes@559
   643
	    }
nkeynes@559
   644
	} else {
nkeynes@559
   645
	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@559
   646
		((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@559
   647
		/* Conditional user-mode access to the store-queue (no translation) */
nkeynes@570
   648
		return addr;
nkeynes@559
   649
	    }
nkeynes@570
   650
	    MMU_READ_ADDR_ERROR();
nkeynes@570
   651
	    return MMU_VMA_ERROR;
nkeynes@559
   652
	}
nkeynes@559
   653
    }
nkeynes@559
   654
    
nkeynes@559
   655
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@570
   656
	return VMA_TO_EXT_ADDR(addr);
nkeynes@570
   657
    }
nkeynes@570
   658
nkeynes@570
   659
    /* If we get this far, translation is required */
nkeynes@570
   660
    int entryNo;
nkeynes@570
   661
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@570
   662
	entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@570
   663
    } else {
nkeynes@570
   664
	entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@570
   665
    }
nkeynes@570
   666
nkeynes@570
   667
    switch(entryNo) {
nkeynes@570
   668
    case -1:
nkeynes@570
   669
	MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@570
   670
	return MMU_VMA_ERROR;
nkeynes@570
   671
    case -2:
nkeynes@570
   672
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@570
   673
	return MMU_VMA_ERROR;
nkeynes@570
   674
    default:
nkeynes@570
   675
	if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@570
   676
	    !IS_SH4_PRIVMODE() ) {
nkeynes@570
   677
	    /* protection violation */
nkeynes@570
   678
	    MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@570
   679
	    return MMU_VMA_ERROR;
nkeynes@570
   680
	}
nkeynes@570
   681
nkeynes@570
   682
	/* finally generate the target address */
nkeynes@570
   683
	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@570
   684
	    (addr & (~mmu_utlb[entryNo].mask));
nkeynes@570
   685
    }
nkeynes@570
   686
}
nkeynes@570
   687
nkeynes@570
   688
sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@570
   689
{
nkeynes@570
   690
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@570
   691
    if( addr & 0x80000000 ) {
nkeynes@570
   692
	if( IS_SH4_PRIVMODE() ) {
nkeynes@570
   693
	    if( addr >= 0xE0000000 ) {
nkeynes@570
   694
		return addr; /* P4 - passthrough */
nkeynes@570
   695
	    } else if( addr < 0xC0000000 ) {
nkeynes@570
   696
		/* P1, P2 regions are pass-through (no translation) */
nkeynes@570
   697
		return VMA_TO_EXT_ADDR(addr);
nkeynes@570
   698
	    }
nkeynes@570
   699
	} else {
nkeynes@570
   700
	    if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@570
   701
		((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@570
   702
		/* Conditional user-mode access to the store-queue (no translation) */
nkeynes@570
   703
		return addr;
nkeynes@570
   704
	    }
nkeynes@570
   705
	    MMU_WRITE_ADDR_ERROR();
nkeynes@570
   706
	    return MMU_VMA_ERROR;
nkeynes@570
   707
	}
nkeynes@570
   708
    }
nkeynes@570
   709
    
nkeynes@570
   710
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@570
   711
	return VMA_TO_EXT_ADDR(addr);
nkeynes@559
   712
    }
nkeynes@559
   713
nkeynes@559
   714
    /* If we get this far, translation is required */
nkeynes@569
   715
    int entryNo;
nkeynes@569
   716
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@569
   717
	entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@569
   718
    } else {
nkeynes@569
   719
	entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@569
   720
    }
nkeynes@559
   721
nkeynes@559
   722
    switch(entryNo) {
nkeynes@559
   723
    case -1:
nkeynes@559
   724
	MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@570
   725
	return MMU_VMA_ERROR;
nkeynes@559
   726
    case -2:
nkeynes@559
   727
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@570
   728
	return MMU_VMA_ERROR;
nkeynes@559
   729
    default:
nkeynes@559
   730
	if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@559
   731
	    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@559
   732
	    /* protection violation */
nkeynes@559
   733
	    MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@570
   734
	    return MMU_VMA_ERROR;
nkeynes@559
   735
	}
nkeynes@559
   736
nkeynes@559
   737
	if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@559
   738
	    MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@570
   739
	    return MMU_VMA_ERROR;
nkeynes@559
   740
	}
nkeynes@559
   741
nkeynes@559
   742
	/* finally generate the target address */
nkeynes@559
   743
	return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@559
   744
	    (addr & (~mmu_utlb[entryNo].mask));
nkeynes@559
   745
    }
nkeynes@550
   746
}
nkeynes@569
   747
nkeynes@569
   748
/**
nkeynes@569
   749
 * Update the icache for an untranslated address
nkeynes@569
   750
 */
nkeynes@569
   751
void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@569
   752
{
nkeynes@569
   753
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@569
   754
	/* Main ram */
nkeynes@569
   755
	sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@569
   756
	sh4_icache.page_ppa = 0x0C000000;
nkeynes@569
   757
	sh4_icache.mask = 0xFF000000;
nkeynes@569
   758
	sh4_icache.page = sh4_main_ram;
nkeynes@570
   759
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@569
   760
	/* BIOS ROM */
nkeynes@569
   761
	sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@569
   762
	sh4_icache.page_ppa = 0;
nkeynes@569
   763
	sh4_icache.mask = 0xFFE00000;
nkeynes@569
   764
	sh4_icache.page = mem_get_region(0);
nkeynes@569
   765
    } else {
nkeynes@569
   766
	/* not supported */
nkeynes@569
   767
	sh4_icache.page_vma = -1;
nkeynes@569
   768
    }
nkeynes@569
   769
}
nkeynes@569
   770
nkeynes@569
   771
/**
nkeynes@569
   772
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@569
   773
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@569
   774
 * will be invalidated instead.
nkeynes@569
   775
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@569
   776
 * (hence this method should only be used immediately prior to execution of
nkeynes@569
   777
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@569
   778
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@569
   779
 * the icache.
nkeynes@569
   780
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@569
   781
 * if an exception was raised.
nkeynes@569
   782
 */
nkeynes@569
   783
gboolean mmu_update_icache( sh4vma_t addr )
nkeynes@569
   784
{
nkeynes@569
   785
    int entryNo;
nkeynes@569
   786
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@569
   787
	if( addr & 0x80000000 ) {
nkeynes@569
   788
	    if( addr < 0xC0000000 ) {
nkeynes@569
   789
		/* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@569
   790
		mmu_update_icache_phys(addr);
nkeynes@569
   791
		return TRUE;
nkeynes@569
   792
	    } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@569
   793
		MMU_READ_ADDR_ERROR();
nkeynes@569
   794
		return FALSE;
nkeynes@569
   795
	    }
nkeynes@569
   796
	}
nkeynes@569
   797
    
nkeynes@569
   798
	uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@569
   799
	if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@569
   800
	    mmu_update_icache_phys(addr);
nkeynes@569
   801
	    return TRUE;
nkeynes@569
   802
	}
nkeynes@569
   803
nkeynes@569
   804
	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@569
   805
    } else {
nkeynes@569
   806
	if( addr & 0x80000000 ) {
nkeynes@569
   807
	    MMU_READ_ADDR_ERROR();
nkeynes@569
   808
	    return FALSE;
nkeynes@569
   809
	}
nkeynes@569
   810
nkeynes@569
   811
	uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@569
   812
	if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@569
   813
	    mmu_update_icache_phys(addr);
nkeynes@569
   814
	    return TRUE;
nkeynes@569
   815
	}
nkeynes@569
   816
	
nkeynes@569
   817
	if( mmucr & MMUCR_SV ) {
nkeynes@569
   818
	    entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@569
   819
	} else {
nkeynes@569
   820
	    entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@569
   821
	}
nkeynes@569
   822
	if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@569
   823
	    MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@569
   824
	    return FALSE;
nkeynes@569
   825
	}
nkeynes@569
   826
    }
nkeynes@569
   827
nkeynes@569
   828
    switch(entryNo) {
nkeynes@569
   829
    case -1:
nkeynes@569
   830
	MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@569
   831
	return FALSE;
nkeynes@569
   832
    case -2:
nkeynes@569
   833
	MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@569
   834
	return FALSE;
nkeynes@569
   835
    default:
nkeynes@569
   836
	sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@569
   837
	sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@569
   838
	if( sh4_icache.page == NULL ) {
nkeynes@569
   839
	    sh4_icache.page_vma = -1;
nkeynes@569
   840
	} else {
nkeynes@569
   841
	    sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@569
   842
	    sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@569
   843
	}
nkeynes@569
   844
	return TRUE;
nkeynes@569
   845
    }
nkeynes@569
   846
}
.