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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE_PHYS( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD_PHYS( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG_PHYS( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE_PHYS( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD_PHYS( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG_PHYS( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define MEM_READ_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_byte, R_EAX); MEM_RESULT(value_reg)
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#define MEM_READ_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_word, R_EAX); MEM_RESULT(value_reg)
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#define MEM_READ_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_long, R_EAX); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_byte, R_EAX, value_reg)
nkeynes@570
   323
#define MEM_WRITE_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_word, R_EAX, value_reg)
nkeynes@570
   324
#define MEM_WRITE_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_long, R_EAX, value_reg)
nkeynes@570
   325
nkeynes@570
   326
#define MEM_READ_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_BYTE_VMA(addr_reg,value_reg);}else{MEM_READ_BYTE_PHYS(addr_reg, value_reg);}
nkeynes@570
   327
#define MEM_READ_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_WORD_VMA(addr_reg,value_reg);}else{MEM_READ_WORD_PHYS(addr_reg, value_reg);}
nkeynes@570
   328
#define MEM_READ_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_LONG_VMA(addr_reg,value_reg);}else{MEM_READ_LONG_PHYS(addr_reg, value_reg);}
nkeynes@570
   329
#define MEM_WRITE_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_BYTE_VMA(addr_reg,value_reg);}else{MEM_WRITE_BYTE_PHYS(addr_reg, value_reg);}
nkeynes@570
   330
#define MEM_WRITE_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_WORD_VMA(addr_reg,value_reg);}else{MEM_WRITE_WORD_PHYS(addr_reg, value_reg);}
nkeynes@570
   331
#define MEM_WRITE_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_LONG_VMA(addr_reg,value_reg);}else{MEM_WRITE_LONG_PHYS(addr_reg, value_reg);}
nkeynes@570
   332
nkeynes@570
   333
#define MEM_READ_SIZE_PHYS (CALL_FUNC1_SIZE)
nkeynes@570
   334
#define MEM_WRITE_SIZE_PHYS (CALL_FUNC2_SIZE)
nkeynes@570
   335
#define MEM_READ_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC1_SIZE + 12)
nkeynes@570
   336
#define MEM_WRITE_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC2_SIZE + 12)
nkeynes@570
   337
nkeynes@570
   338
#define MEM_READ_SIZE (sh4_x86.tlb_on?MEM_READ_SIZE_VMA:MEM_READ_SIZE_PHYS)
nkeynes@570
   339
#define MEM_WRITE_SIZE (sh4_x86.tlb_on?MEM_WRITE_SIZE_VMA:MEM_WRITE_SIZE_PHYS)
nkeynes@559
   340
nkeynes@559
   341
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   342
nkeynes@539
   343
/****** Import appropriate calling conventions ******/
nkeynes@539
   344
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   345
#include "sh4/ia64abi.h"
nkeynes@539
   346
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   347
#ifdef APPLE_BUILD
nkeynes@539
   348
#include "sh4/ia32mac.h"
nkeynes@539
   349
#else
nkeynes@539
   350
#include "sh4/ia32abi.h"
nkeynes@539
   351
#endif
nkeynes@539
   352
#endif
nkeynes@539
   353
nkeynes@539
   354
nkeynes@359
   355
/**
nkeynes@359
   356
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   357
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   358
 * 
nkeynes@359
   359
 *
nkeynes@359
   360
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   361
 * (eg a branch or 
nkeynes@359
   362
 */
nkeynes@526
   363
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   364
{
nkeynes@388
   365
    uint32_t ir;
nkeynes@388
   366
    /* Read instruction */
nkeynes@569
   367
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   368
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   369
    } else {
nkeynes@569
   370
	ir = sh4_read_word(pc);
nkeynes@388
   371
    }
nkeynes@359
   372
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   373
            case 0x0:
nkeynes@359
   374
                switch( ir&0xF ) {
nkeynes@359
   375
                    case 0x2:
nkeynes@359
   376
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   377
                            case 0x0:
nkeynes@359
   378
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   379
                                    case 0x0:
nkeynes@359
   380
                                        { /* STC SR, Rn */
nkeynes@359
   381
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   382
                                        check_priv();
nkeynes@374
   383
                                        call_func0(sh4_read_sr);
nkeynes@368
   384
                                        store_reg( R_EAX, Rn );
nkeynes@417
   385
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   386
                                        }
nkeynes@359
   387
                                        break;
nkeynes@359
   388
                                    case 0x1:
nkeynes@359
   389
                                        { /* STC GBR, Rn */
nkeynes@359
   390
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   391
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   392
                                        store_reg( R_EAX, Rn );
nkeynes@359
   393
                                        }
nkeynes@359
   394
                                        break;
nkeynes@359
   395
                                    case 0x2:
nkeynes@359
   396
                                        { /* STC VBR, Rn */
nkeynes@359
   397
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   398
                                        check_priv();
nkeynes@359
   399
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   400
                                        store_reg( R_EAX, Rn );
nkeynes@417
   401
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   402
                                        }
nkeynes@359
   403
                                        break;
nkeynes@359
   404
                                    case 0x3:
nkeynes@359
   405
                                        { /* STC SSR, Rn */
nkeynes@359
   406
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   407
                                        check_priv();
nkeynes@359
   408
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   409
                                        store_reg( R_EAX, Rn );
nkeynes@417
   410
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   411
                                        }
nkeynes@359
   412
                                        break;
nkeynes@359
   413
                                    case 0x4:
nkeynes@359
   414
                                        { /* STC SPC, Rn */
nkeynes@359
   415
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   416
                                        check_priv();
nkeynes@359
   417
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   418
                                        store_reg( R_EAX, Rn );
nkeynes@417
   419
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   420
                                        }
nkeynes@359
   421
                                        break;
nkeynes@359
   422
                                    default:
nkeynes@359
   423
                                        UNDEF();
nkeynes@359
   424
                                        break;
nkeynes@359
   425
                                }
nkeynes@359
   426
                                break;
nkeynes@359
   427
                            case 0x1:
nkeynes@359
   428
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   429
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   430
                                check_priv();
nkeynes@374
   431
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   432
                                store_reg( R_EAX, Rn );
nkeynes@417
   433
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   434
                                }
nkeynes@359
   435
                                break;
nkeynes@359
   436
                        }
nkeynes@359
   437
                        break;
nkeynes@359
   438
                    case 0x3:
nkeynes@359
   439
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   440
                            case 0x0:
nkeynes@359
   441
                                { /* BSRF Rn */
nkeynes@359
   442
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   443
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   444
                            	SLOTILLEGAL();
nkeynes@374
   445
                                } else {
nkeynes@408
   446
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   447
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   448
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   449
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   450
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   451
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   452
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   453
                            	exit_block_pcset(pc+2);
nkeynes@409
   454
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   455
                            	return 4;
nkeynes@374
   456
                                }
nkeynes@359
   457
                                }
nkeynes@359
   458
                                break;
nkeynes@359
   459
                            case 0x2:
nkeynes@359
   460
                                { /* BRAF Rn */
nkeynes@359
   461
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   462
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   463
                            	SLOTILLEGAL();
nkeynes@374
   464
                                } else {
nkeynes@408
   465
                            	load_reg( R_EAX, Rn );
nkeynes@408
   466
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   467
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   468
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   469
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   470
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   471
                            	exit_block_pcset(pc+2);
nkeynes@409
   472
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   473
                            	return 4;
nkeynes@374
   474
                                }
nkeynes@359
   475
                                }
nkeynes@359
   476
                                break;
nkeynes@359
   477
                            case 0x8:
nkeynes@359
   478
                                { /* PREF @Rn */
nkeynes@359
   479
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   480
                                load_reg( R_EAX, Rn );
nkeynes@532
   481
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   482
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   483
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
   484
                                JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
   485
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
   486
                                JMP_TARGET(end);
nkeynes@417
   487
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   488
                                }
nkeynes@359
   489
                                break;
nkeynes@359
   490
                            case 0x9:
nkeynes@359
   491
                                { /* OCBI @Rn */
nkeynes@359
   492
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   493
                                }
nkeynes@359
   494
                                break;
nkeynes@359
   495
                            case 0xA:
nkeynes@359
   496
                                { /* OCBP @Rn */
nkeynes@359
   497
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   498
                                }
nkeynes@359
   499
                                break;
nkeynes@359
   500
                            case 0xB:
nkeynes@359
   501
                                { /* OCBWB @Rn */
nkeynes@359
   502
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   503
                                }
nkeynes@359
   504
                                break;
nkeynes@359
   505
                            case 0xC:
nkeynes@359
   506
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   507
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   508
                                load_reg( R_EAX, 0 );
nkeynes@361
   509
                                load_reg( R_ECX, Rn );
nkeynes@374
   510
                                check_walign32( R_ECX );
nkeynes@361
   511
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   512
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   513
                                }
nkeynes@359
   514
                                break;
nkeynes@359
   515
                            default:
nkeynes@359
   516
                                UNDEF();
nkeynes@359
   517
                                break;
nkeynes@359
   518
                        }
nkeynes@359
   519
                        break;
nkeynes@359
   520
                    case 0x4:
nkeynes@359
   521
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   522
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   523
                        load_reg( R_EAX, 0 );
nkeynes@359
   524
                        load_reg( R_ECX, Rn );
nkeynes@359
   525
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   526
                        load_reg( R_EAX, Rm );
nkeynes@359
   527
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   528
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   529
                        }
nkeynes@359
   530
                        break;
nkeynes@359
   531
                    case 0x5:
nkeynes@359
   532
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   533
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   534
                        load_reg( R_EAX, 0 );
nkeynes@361
   535
                        load_reg( R_ECX, Rn );
nkeynes@361
   536
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   537
                        check_walign16( R_ECX );
nkeynes@361
   538
                        load_reg( R_EAX, Rm );
nkeynes@361
   539
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   540
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   541
                        }
nkeynes@359
   542
                        break;
nkeynes@359
   543
                    case 0x6:
nkeynes@359
   544
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   545
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   546
                        load_reg( R_EAX, 0 );
nkeynes@361
   547
                        load_reg( R_ECX, Rn );
nkeynes@361
   548
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   549
                        check_walign32( R_ECX );
nkeynes@361
   550
                        load_reg( R_EAX, Rm );
nkeynes@361
   551
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   552
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   553
                        }
nkeynes@359
   554
                        break;
nkeynes@359
   555
                    case 0x7:
nkeynes@359
   556
                        { /* MUL.L Rm, Rn */
nkeynes@359
   557
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   558
                        load_reg( R_EAX, Rm );
nkeynes@361
   559
                        load_reg( R_ECX, Rn );
nkeynes@361
   560
                        MUL_r32( R_ECX );
nkeynes@361
   561
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   562
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   563
                        }
nkeynes@359
   564
                        break;
nkeynes@359
   565
                    case 0x8:
nkeynes@359
   566
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   567
                            case 0x0:
nkeynes@359
   568
                                { /* CLRT */
nkeynes@374
   569
                                CLC();
nkeynes@374
   570
                                SETC_t();
nkeynes@417
   571
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   572
                                }
nkeynes@359
   573
                                break;
nkeynes@359
   574
                            case 0x1:
nkeynes@359
   575
                                { /* SETT */
nkeynes@374
   576
                                STC();
nkeynes@374
   577
                                SETC_t();
nkeynes@417
   578
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   579
                                }
nkeynes@359
   580
                                break;
nkeynes@359
   581
                            case 0x2:
nkeynes@359
   582
                                { /* CLRMAC */
nkeynes@374
   583
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   584
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   585
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   586
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   587
                                }
nkeynes@359
   588
                                break;
nkeynes@359
   589
                            case 0x3:
nkeynes@359
   590
                                { /* LDTLB */
nkeynes@553
   591
                                call_func0( MMU_ldtlb );
nkeynes@359
   592
                                }
nkeynes@359
   593
                                break;
nkeynes@359
   594
                            case 0x4:
nkeynes@359
   595
                                { /* CLRS */
nkeynes@374
   596
                                CLC();
nkeynes@374
   597
                                SETC_sh4r(R_S);
nkeynes@417
   598
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   599
                                }
nkeynes@359
   600
                                break;
nkeynes@359
   601
                            case 0x5:
nkeynes@359
   602
                                { /* SETS */
nkeynes@374
   603
                                STC();
nkeynes@374
   604
                                SETC_sh4r(R_S);
nkeynes@417
   605
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   606
                                }
nkeynes@359
   607
                                break;
nkeynes@359
   608
                            default:
nkeynes@359
   609
                                UNDEF();
nkeynes@359
   610
                                break;
nkeynes@359
   611
                        }
nkeynes@359
   612
                        break;
nkeynes@359
   613
                    case 0x9:
nkeynes@359
   614
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   615
                            case 0x0:
nkeynes@359
   616
                                { /* NOP */
nkeynes@359
   617
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   618
                                }
nkeynes@359
   619
                                break;
nkeynes@359
   620
                            case 0x1:
nkeynes@359
   621
                                { /* DIV0U */
nkeynes@361
   622
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   623
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   624
                                store_spreg( R_EAX, R_M );
nkeynes@361
   625
                                store_spreg( R_EAX, R_T );
nkeynes@417
   626
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   627
                                }
nkeynes@359
   628
                                break;
nkeynes@359
   629
                            case 0x2:
nkeynes@359
   630
                                { /* MOVT Rn */
nkeynes@359
   631
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   632
                                load_spreg( R_EAX, R_T );
nkeynes@359
   633
                                store_reg( R_EAX, Rn );
nkeynes@359
   634
                                }
nkeynes@359
   635
                                break;
nkeynes@359
   636
                            default:
nkeynes@359
   637
                                UNDEF();
nkeynes@359
   638
                                break;
nkeynes@359
   639
                        }
nkeynes@359
   640
                        break;
nkeynes@359
   641
                    case 0xA:
nkeynes@359
   642
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   643
                            case 0x0:
nkeynes@359
   644
                                { /* STS MACH, Rn */
nkeynes@359
   645
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   646
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   647
                                store_reg( R_EAX, Rn );
nkeynes@359
   648
                                }
nkeynes@359
   649
                                break;
nkeynes@359
   650
                            case 0x1:
nkeynes@359
   651
                                { /* STS MACL, Rn */
nkeynes@359
   652
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   653
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   654
                                store_reg( R_EAX, Rn );
nkeynes@359
   655
                                }
nkeynes@359
   656
                                break;
nkeynes@359
   657
                            case 0x2:
nkeynes@359
   658
                                { /* STS PR, Rn */
nkeynes@359
   659
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   660
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   661
                                store_reg( R_EAX, Rn );
nkeynes@359
   662
                                }
nkeynes@359
   663
                                break;
nkeynes@359
   664
                            case 0x3:
nkeynes@359
   665
                                { /* STC SGR, Rn */
nkeynes@359
   666
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   667
                                check_priv();
nkeynes@359
   668
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   669
                                store_reg( R_EAX, Rn );
nkeynes@417
   670
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   671
                                }
nkeynes@359
   672
                                break;
nkeynes@359
   673
                            case 0x5:
nkeynes@359
   674
                                { /* STS FPUL, Rn */
nkeynes@359
   675
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   676
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   677
                                store_reg( R_EAX, Rn );
nkeynes@359
   678
                                }
nkeynes@359
   679
                                break;
nkeynes@359
   680
                            case 0x6:
nkeynes@359
   681
                                { /* STS FPSCR, Rn */
nkeynes@359
   682
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   683
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   684
                                store_reg( R_EAX, Rn );
nkeynes@359
   685
                                }
nkeynes@359
   686
                                break;
nkeynes@359
   687
                            case 0xF:
nkeynes@359
   688
                                { /* STC DBR, Rn */
nkeynes@359
   689
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   690
                                check_priv();
nkeynes@359
   691
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   692
                                store_reg( R_EAX, Rn );
nkeynes@417
   693
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   694
                                }
nkeynes@359
   695
                                break;
nkeynes@359
   696
                            default:
nkeynes@359
   697
                                UNDEF();
nkeynes@359
   698
                                break;
nkeynes@359
   699
                        }
nkeynes@359
   700
                        break;
nkeynes@359
   701
                    case 0xB:
nkeynes@359
   702
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   703
                            case 0x0:
nkeynes@359
   704
                                { /* RTS */
nkeynes@374
   705
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   706
                            	SLOTILLEGAL();
nkeynes@374
   707
                                } else {
nkeynes@408
   708
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
   709
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   710
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
   711
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   712
                            	exit_block_pcset(pc+2);
nkeynes@409
   713
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   714
                            	return 4;
nkeynes@374
   715
                                }
nkeynes@359
   716
                                }
nkeynes@359
   717
                                break;
nkeynes@359
   718
                            case 0x1:
nkeynes@359
   719
                                { /* SLEEP */
nkeynes@388
   720
                                check_priv();
nkeynes@388
   721
                                call_func0( sh4_sleep );
nkeynes@417
   722
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
   723
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
   724
                                return 2;
nkeynes@359
   725
                                }
nkeynes@359
   726
                                break;
nkeynes@359
   727
                            case 0x2:
nkeynes@359
   728
                                { /* RTE */
nkeynes@374
   729
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   730
                            	SLOTILLEGAL();
nkeynes@374
   731
                                } else {
nkeynes@408
   732
                            	check_priv();
nkeynes@408
   733
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
   734
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   735
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   736
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   737
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   738
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   739
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   740
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   741
                            	sh4_translate_instruction(pc+2);
nkeynes@408
   742
                            	exit_block_pcset(pc+2);
nkeynes@409
   743
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   744
                            	return 4;
nkeynes@374
   745
                                }
nkeynes@359
   746
                                }
nkeynes@359
   747
                                break;
nkeynes@359
   748
                            default:
nkeynes@359
   749
                                UNDEF();
nkeynes@359
   750
                                break;
nkeynes@359
   751
                        }
nkeynes@359
   752
                        break;
nkeynes@359
   753
                    case 0xC:
nkeynes@359
   754
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   755
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   756
                        load_reg( R_EAX, 0 );
nkeynes@359
   757
                        load_reg( R_ECX, Rm );
nkeynes@359
   758
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   759
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   760
                        store_reg( R_EAX, Rn );
nkeynes@417
   761
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   762
                        }
nkeynes@359
   763
                        break;
nkeynes@359
   764
                    case 0xD:
nkeynes@359
   765
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   766
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   767
                        load_reg( R_EAX, 0 );
nkeynes@361
   768
                        load_reg( R_ECX, Rm );
nkeynes@361
   769
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   770
                        check_ralign16( R_ECX );
nkeynes@361
   771
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   772
                        store_reg( R_EAX, Rn );
nkeynes@417
   773
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   774
                        }
nkeynes@359
   775
                        break;
nkeynes@359
   776
                    case 0xE:
nkeynes@359
   777
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   778
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   779
                        load_reg( R_EAX, 0 );
nkeynes@361
   780
                        load_reg( R_ECX, Rm );
nkeynes@361
   781
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   782
                        check_ralign32( R_ECX );
nkeynes@361
   783
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   784
                        store_reg( R_EAX, Rn );
nkeynes@417
   785
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   786
                        }
nkeynes@359
   787
                        break;
nkeynes@359
   788
                    case 0xF:
nkeynes@359
   789
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   790
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   791
                        load_reg( R_ECX, Rm );
nkeynes@386
   792
                        check_ralign32( R_ECX );
nkeynes@386
   793
                        load_reg( R_ECX, Rn );
nkeynes@386
   794
                        check_ralign32( R_ECX );
nkeynes@386
   795
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   796
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   797
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
   798
                        load_reg( R_ECX, Rm );
nkeynes@386
   799
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   800
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   801
                        POP_realigned_r32( R_ECX );
nkeynes@386
   802
                        IMUL_r32( R_ECX );
nkeynes@386
   803
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   804
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   805
                    
nkeynes@386
   806
                        load_spreg( R_ECX, R_S );
nkeynes@386
   807
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   808
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   809
                        call_func0( signsat48 );
nkeynes@386
   810
                        JMP_TARGET( nosat );
nkeynes@417
   811
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   812
                        }
nkeynes@359
   813
                        break;
nkeynes@359
   814
                    default:
nkeynes@359
   815
                        UNDEF();
nkeynes@359
   816
                        break;
nkeynes@359
   817
                }
nkeynes@359
   818
                break;
nkeynes@359
   819
            case 0x1:
nkeynes@359
   820
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   821
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   822
                load_reg( R_ECX, Rn );
nkeynes@361
   823
                load_reg( R_EAX, Rm );
nkeynes@361
   824
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   825
                check_walign32( R_ECX );
nkeynes@361
   826
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   827
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   828
                }
nkeynes@359
   829
                break;
nkeynes@359
   830
            case 0x2:
nkeynes@359
   831
                switch( ir&0xF ) {
nkeynes@359
   832
                    case 0x0:
nkeynes@359
   833
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   834
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   835
                        load_reg( R_EAX, Rm );
nkeynes@359
   836
                        load_reg( R_ECX, Rn );
nkeynes@359
   837
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   838
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   839
                        }
nkeynes@359
   840
                        break;
nkeynes@359
   841
                    case 0x1:
nkeynes@359
   842
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   843
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   844
                        load_reg( R_ECX, Rn );
nkeynes@374
   845
                        check_walign16( R_ECX );
nkeynes@386
   846
                        load_reg( R_EAX, Rm );
nkeynes@386
   847
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   848
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   849
                        }
nkeynes@359
   850
                        break;
nkeynes@359
   851
                    case 0x2:
nkeynes@359
   852
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   853
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   854
                        load_reg( R_EAX, Rm );
nkeynes@361
   855
                        load_reg( R_ECX, Rn );
nkeynes@374
   856
                        check_walign32(R_ECX);
nkeynes@361
   857
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   858
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   859
                        }
nkeynes@359
   860
                        break;
nkeynes@359
   861
                    case 0x4:
nkeynes@359
   862
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   863
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   864
                        load_reg( R_EAX, Rm );
nkeynes@359
   865
                        load_reg( R_ECX, Rn );
nkeynes@386
   866
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   867
                        store_reg( R_ECX, Rn );
nkeynes@359
   868
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   869
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   870
                        }
nkeynes@359
   871
                        break;
nkeynes@359
   872
                    case 0x5:
nkeynes@359
   873
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   874
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   875
                        load_reg( R_ECX, Rn );
nkeynes@374
   876
                        check_walign16( R_ECX );
nkeynes@361
   877
                        load_reg( R_EAX, Rm );
nkeynes@361
   878
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
   879
                        store_reg( R_ECX, Rn );
nkeynes@361
   880
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   881
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   882
                        }
nkeynes@359
   883
                        break;
nkeynes@359
   884
                    case 0x6:
nkeynes@359
   885
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   886
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   887
                        load_reg( R_EAX, Rm );
nkeynes@361
   888
                        load_reg( R_ECX, Rn );
nkeynes@374
   889
                        check_walign32( R_ECX );
nkeynes@361
   890
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   891
                        store_reg( R_ECX, Rn );
nkeynes@361
   892
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   893
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   894
                        }
nkeynes@359
   895
                        break;
nkeynes@359
   896
                    case 0x7:
nkeynes@359
   897
                        { /* DIV0S Rm, Rn */
nkeynes@359
   898
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   899
                        load_reg( R_EAX, Rm );
nkeynes@386
   900
                        load_reg( R_ECX, Rn );
nkeynes@361
   901
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   902
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   903
                        store_spreg( R_EAX, R_M );
nkeynes@361
   904
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   905
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   906
                        SETNE_t();
nkeynes@417
   907
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
   908
                        }
nkeynes@359
   909
                        break;
nkeynes@359
   910
                    case 0x8:
nkeynes@359
   911
                        { /* TST Rm, Rn */
nkeynes@359
   912
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   913
                        load_reg( R_EAX, Rm );
nkeynes@361
   914
                        load_reg( R_ECX, Rn );
nkeynes@361
   915
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   916
                        SETE_t();
nkeynes@417
   917
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   918
                        }
nkeynes@359
   919
                        break;
nkeynes@359
   920
                    case 0x9:
nkeynes@359
   921
                        { /* AND Rm, Rn */
nkeynes@359
   922
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   923
                        load_reg( R_EAX, Rm );
nkeynes@359
   924
                        load_reg( R_ECX, Rn );
nkeynes@359
   925
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   926
                        store_reg( R_ECX, Rn );
nkeynes@417
   927
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   928
                        }
nkeynes@359
   929
                        break;
nkeynes@359
   930
                    case 0xA:
nkeynes@359
   931
                        { /* XOR Rm, Rn */
nkeynes@359
   932
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   933
                        load_reg( R_EAX, Rm );
nkeynes@359
   934
                        load_reg( R_ECX, Rn );
nkeynes@359
   935
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   936
                        store_reg( R_ECX, Rn );
nkeynes@417
   937
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   938
                        }
nkeynes@359
   939
                        break;
nkeynes@359
   940
                    case 0xB:
nkeynes@359
   941
                        { /* OR Rm, Rn */
nkeynes@359
   942
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   943
                        load_reg( R_EAX, Rm );
nkeynes@359
   944
                        load_reg( R_ECX, Rn );
nkeynes@359
   945
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   946
                        store_reg( R_ECX, Rn );
nkeynes@417
   947
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   948
                        }
nkeynes@359
   949
                        break;
nkeynes@359
   950
                    case 0xC:
nkeynes@359
   951
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   952
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   953
                        load_reg( R_EAX, Rm );
nkeynes@368
   954
                        load_reg( R_ECX, Rn );
nkeynes@368
   955
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   956
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   957
                        JE_rel8(13, target1);
nkeynes@368
   958
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   959
                        JE_rel8(9, target2);
nkeynes@368
   960
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   961
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   962
                        JE_rel8(2, target3);
nkeynes@368
   963
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   964
                        JMP_TARGET(target1);
nkeynes@380
   965
                        JMP_TARGET(target2);
nkeynes@380
   966
                        JMP_TARGET(target3);
nkeynes@368
   967
                        SETE_t();
nkeynes@417
   968
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
   969
                        }
nkeynes@359
   970
                        break;
nkeynes@359
   971
                    case 0xD:
nkeynes@359
   972
                        { /* XTRCT Rm, Rn */
nkeynes@359
   973
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   974
                        load_reg( R_EAX, Rm );
nkeynes@394
   975
                        load_reg( R_ECX, Rn );
nkeynes@394
   976
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   977
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   978
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   979
                        store_reg( R_ECX, Rn );
nkeynes@417
   980
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   981
                        }
nkeynes@359
   982
                        break;
nkeynes@359
   983
                    case 0xE:
nkeynes@359
   984
                        { /* MULU.W Rm, Rn */
nkeynes@359
   985
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   986
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   987
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   988
                        MUL_r32( R_ECX );
nkeynes@374
   989
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   990
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   991
                        }
nkeynes@359
   992
                        break;
nkeynes@359
   993
                    case 0xF:
nkeynes@359
   994
                        { /* MULS.W Rm, Rn */
nkeynes@359
   995
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   996
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   997
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   998
                        MUL_r32( R_ECX );
nkeynes@374
   999
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1000
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1001
                        }
nkeynes@359
  1002
                        break;
nkeynes@359
  1003
                    default:
nkeynes@359
  1004
                        UNDEF();
nkeynes@359
  1005
                        break;
nkeynes@359
  1006
                }
nkeynes@359
  1007
                break;
nkeynes@359
  1008
            case 0x3:
nkeynes@359
  1009
                switch( ir&0xF ) {
nkeynes@359
  1010
                    case 0x0:
nkeynes@359
  1011
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1012
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1013
                        load_reg( R_EAX, Rm );
nkeynes@359
  1014
                        load_reg( R_ECX, Rn );
nkeynes@359
  1015
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1016
                        SETE_t();
nkeynes@417
  1017
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1018
                        }
nkeynes@359
  1019
                        break;
nkeynes@359
  1020
                    case 0x2:
nkeynes@359
  1021
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1022
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1023
                        load_reg( R_EAX, Rm );
nkeynes@359
  1024
                        load_reg( R_ECX, Rn );
nkeynes@359
  1025
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1026
                        SETAE_t();
nkeynes@417
  1027
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1028
                        }
nkeynes@359
  1029
                        break;
nkeynes@359
  1030
                    case 0x3:
nkeynes@359
  1031
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1032
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1033
                        load_reg( R_EAX, Rm );
nkeynes@359
  1034
                        load_reg( R_ECX, Rn );
nkeynes@359
  1035
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1036
                        SETGE_t();
nkeynes@417
  1037
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1038
                        }
nkeynes@359
  1039
                        break;
nkeynes@359
  1040
                    case 0x4:
nkeynes@359
  1041
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1042
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1043
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1044
                        load_reg( R_EAX, Rn );
nkeynes@417
  1045
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1046
                    	LDC_t();
nkeynes@417
  1047
                        }
nkeynes@386
  1048
                        RCL1_r32( R_EAX );
nkeynes@386
  1049
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1050
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1051
                        JE_rel8(5, mqequal);
nkeynes@386
  1052
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1053
                        JMP_rel8(3, end);
nkeynes@380
  1054
                        JMP_TARGET(mqequal);
nkeynes@386
  1055
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1056
                        JMP_TARGET(end);
nkeynes@386
  1057
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1058
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1059
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1060
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1061
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1062
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1063
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1064
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1065
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1066
                        }
nkeynes@359
  1067
                        break;
nkeynes@359
  1068
                    case 0x5:
nkeynes@359
  1069
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1070
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1071
                        load_reg( R_EAX, Rm );
nkeynes@361
  1072
                        load_reg( R_ECX, Rn );
nkeynes@361
  1073
                        MUL_r32(R_ECX);
nkeynes@361
  1074
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1075
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1076
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1077
                        }
nkeynes@359
  1078
                        break;
nkeynes@359
  1079
                    case 0x6:
nkeynes@359
  1080
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1081
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1082
                        load_reg( R_EAX, Rm );
nkeynes@359
  1083
                        load_reg( R_ECX, Rn );
nkeynes@359
  1084
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1085
                        SETA_t();
nkeynes@417
  1086
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1087
                        }
nkeynes@359
  1088
                        break;
nkeynes@359
  1089
                    case 0x7:
nkeynes@359
  1090
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1091
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1092
                        load_reg( R_EAX, Rm );
nkeynes@359
  1093
                        load_reg( R_ECX, Rn );
nkeynes@359
  1094
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1095
                        SETG_t();
nkeynes@417
  1096
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1097
                        }
nkeynes@359
  1098
                        break;
nkeynes@359
  1099
                    case 0x8:
nkeynes@359
  1100
                        { /* SUB Rm, Rn */
nkeynes@359
  1101
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1102
                        load_reg( R_EAX, Rm );
nkeynes@359
  1103
                        load_reg( R_ECX, Rn );
nkeynes@359
  1104
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1105
                        store_reg( R_ECX, Rn );
nkeynes@417
  1106
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
                        }
nkeynes@359
  1108
                        break;
nkeynes@359
  1109
                    case 0xA:
nkeynes@359
  1110
                        { /* SUBC Rm, Rn */
nkeynes@359
  1111
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1112
                        load_reg( R_EAX, Rm );
nkeynes@359
  1113
                        load_reg( R_ECX, Rn );
nkeynes@417
  1114
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1115
                    	LDC_t();
nkeynes@417
  1116
                        }
nkeynes@359
  1117
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1118
                        store_reg( R_ECX, Rn );
nkeynes@394
  1119
                        SETC_t();
nkeynes@417
  1120
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1121
                        }
nkeynes@359
  1122
                        break;
nkeynes@359
  1123
                    case 0xB:
nkeynes@359
  1124
                        { /* SUBV Rm, Rn */
nkeynes@359
  1125
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1126
                        load_reg( R_EAX, Rm );
nkeynes@359
  1127
                        load_reg( R_ECX, Rn );
nkeynes@359
  1128
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1129
                        store_reg( R_ECX, Rn );
nkeynes@359
  1130
                        SETO_t();
nkeynes@417
  1131
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1132
                        }
nkeynes@359
  1133
                        break;
nkeynes@359
  1134
                    case 0xC:
nkeynes@359
  1135
                        { /* ADD Rm, Rn */
nkeynes@359
  1136
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1137
                        load_reg( R_EAX, Rm );
nkeynes@359
  1138
                        load_reg( R_ECX, Rn );
nkeynes@359
  1139
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1140
                        store_reg( R_ECX, Rn );
nkeynes@417
  1141
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1142
                        }
nkeynes@359
  1143
                        break;
nkeynes@359
  1144
                    case 0xD:
nkeynes@359
  1145
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1146
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1147
                        load_reg( R_EAX, Rm );
nkeynes@361
  1148
                        load_reg( R_ECX, Rn );
nkeynes@361
  1149
                        IMUL_r32(R_ECX);
nkeynes@361
  1150
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1151
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1152
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
                        }
nkeynes@359
  1154
                        break;
nkeynes@359
  1155
                    case 0xE:
nkeynes@359
  1156
                        { /* ADDC Rm, Rn */
nkeynes@359
  1157
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1158
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1159
                    	LDC_t();
nkeynes@417
  1160
                        }
nkeynes@359
  1161
                        load_reg( R_EAX, Rm );
nkeynes@359
  1162
                        load_reg( R_ECX, Rn );
nkeynes@359
  1163
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1164
                        store_reg( R_ECX, Rn );
nkeynes@359
  1165
                        SETC_t();
nkeynes@417
  1166
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1167
                        }
nkeynes@359
  1168
                        break;
nkeynes@359
  1169
                    case 0xF:
nkeynes@359
  1170
                        { /* ADDV Rm, Rn */
nkeynes@359
  1171
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1172
                        load_reg( R_EAX, Rm );
nkeynes@359
  1173
                        load_reg( R_ECX, Rn );
nkeynes@359
  1174
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1175
                        store_reg( R_ECX, Rn );
nkeynes@359
  1176
                        SETO_t();
nkeynes@417
  1177
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1178
                        }
nkeynes@359
  1179
                        break;
nkeynes@359
  1180
                    default:
nkeynes@359
  1181
                        UNDEF();
nkeynes@359
  1182
                        break;
nkeynes@359
  1183
                }
nkeynes@359
  1184
                break;
nkeynes@359
  1185
            case 0x4:
nkeynes@359
  1186
                switch( ir&0xF ) {
nkeynes@359
  1187
                    case 0x0:
nkeynes@359
  1188
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1189
                            case 0x0:
nkeynes@359
  1190
                                { /* SHLL Rn */
nkeynes@359
  1191
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1192
                                load_reg( R_EAX, Rn );
nkeynes@359
  1193
                                SHL1_r32( R_EAX );
nkeynes@397
  1194
                                SETC_t();
nkeynes@359
  1195
                                store_reg( R_EAX, Rn );
nkeynes@417
  1196
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1197
                                }
nkeynes@359
  1198
                                break;
nkeynes@359
  1199
                            case 0x1:
nkeynes@359
  1200
                                { /* DT Rn */
nkeynes@359
  1201
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1202
                                load_reg( R_EAX, Rn );
nkeynes@386
  1203
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1204
                                store_reg( R_EAX, Rn );
nkeynes@359
  1205
                                SETE_t();
nkeynes@417
  1206
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1207
                                }
nkeynes@359
  1208
                                break;
nkeynes@359
  1209
                            case 0x2:
nkeynes@359
  1210
                                { /* SHAL Rn */
nkeynes@359
  1211
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1212
                                load_reg( R_EAX, Rn );
nkeynes@359
  1213
                                SHL1_r32( R_EAX );
nkeynes@397
  1214
                                SETC_t();
nkeynes@359
  1215
                                store_reg( R_EAX, Rn );
nkeynes@417
  1216
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1217
                                }
nkeynes@359
  1218
                                break;
nkeynes@359
  1219
                            default:
nkeynes@359
  1220
                                UNDEF();
nkeynes@359
  1221
                                break;
nkeynes@359
  1222
                        }
nkeynes@359
  1223
                        break;
nkeynes@359
  1224
                    case 0x1:
nkeynes@359
  1225
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1226
                            case 0x0:
nkeynes@359
  1227
                                { /* SHLR Rn */
nkeynes@359
  1228
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1229
                                load_reg( R_EAX, Rn );
nkeynes@359
  1230
                                SHR1_r32( R_EAX );
nkeynes@397
  1231
                                SETC_t();
nkeynes@359
  1232
                                store_reg( R_EAX, Rn );
nkeynes@417
  1233
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1234
                                }
nkeynes@359
  1235
                                break;
nkeynes@359
  1236
                            case 0x1:
nkeynes@359
  1237
                                { /* CMP/PZ Rn */
nkeynes@359
  1238
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1239
                                load_reg( R_EAX, Rn );
nkeynes@359
  1240
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1241
                                SETGE_t();
nkeynes@417
  1242
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1243
                                }
nkeynes@359
  1244
                                break;
nkeynes@359
  1245
                            case 0x2:
nkeynes@359
  1246
                                { /* SHAR Rn */
nkeynes@359
  1247
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1248
                                load_reg( R_EAX, Rn );
nkeynes@359
  1249
                                SAR1_r32( R_EAX );
nkeynes@397
  1250
                                SETC_t();
nkeynes@359
  1251
                                store_reg( R_EAX, Rn );
nkeynes@417
  1252
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1253
                                }
nkeynes@359
  1254
                                break;
nkeynes@359
  1255
                            default:
nkeynes@359
  1256
                                UNDEF();
nkeynes@359
  1257
                                break;
nkeynes@359
  1258
                        }
nkeynes@359
  1259
                        break;
nkeynes@359
  1260
                    case 0x2:
nkeynes@359
  1261
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1262
                            case 0x0:
nkeynes@359
  1263
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1264
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1265
                                load_reg( R_ECX, Rn );
nkeynes@395
  1266
                                check_walign32( R_ECX );
nkeynes@386
  1267
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1268
                                store_reg( R_ECX, Rn );
nkeynes@359
  1269
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1270
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1271
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1272
                                }
nkeynes@359
  1273
                                break;
nkeynes@359
  1274
                            case 0x1:
nkeynes@359
  1275
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1276
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1277
                                load_reg( R_ECX, Rn );
nkeynes@395
  1278
                                check_walign32( R_ECX );
nkeynes@386
  1279
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1280
                                store_reg( R_ECX, Rn );
nkeynes@359
  1281
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1282
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1283
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1284
                                }
nkeynes@359
  1285
                                break;
nkeynes@359
  1286
                            case 0x2:
nkeynes@359
  1287
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1288
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1289
                                load_reg( R_ECX, Rn );
nkeynes@395
  1290
                                check_walign32( R_ECX );
nkeynes@386
  1291
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1292
                                store_reg( R_ECX, Rn );
nkeynes@359
  1293
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1294
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1295
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1296
                                }
nkeynes@359
  1297
                                break;
nkeynes@359
  1298
                            case 0x3:
nkeynes@359
  1299
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1300
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1301
                                check_priv();
nkeynes@359
  1302
                                load_reg( R_ECX, Rn );
nkeynes@395
  1303
                                check_walign32( R_ECX );
nkeynes@386
  1304
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1305
                                store_reg( R_ECX, Rn );
nkeynes@359
  1306
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1307
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1308
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1309
                                }
nkeynes@359
  1310
                                break;
nkeynes@359
  1311
                            case 0x5:
nkeynes@359
  1312
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1313
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1314
                                load_reg( R_ECX, Rn );
nkeynes@395
  1315
                                check_walign32( R_ECX );
nkeynes@386
  1316
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1317
                                store_reg( R_ECX, Rn );
nkeynes@359
  1318
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1319
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1320
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1321
                                }
nkeynes@359
  1322
                                break;
nkeynes@359
  1323
                            case 0x6:
nkeynes@359
  1324
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1325
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1326
                                load_reg( R_ECX, Rn );
nkeynes@395
  1327
                                check_walign32( R_ECX );
nkeynes@386
  1328
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1329
                                store_reg( R_ECX, Rn );
nkeynes@359
  1330
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1331
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1332
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1333
                                }
nkeynes@359
  1334
                                break;
nkeynes@359
  1335
                            case 0xF:
nkeynes@359
  1336
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1337
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1338
                                check_priv();
nkeynes@359
  1339
                                load_reg( R_ECX, Rn );
nkeynes@395
  1340
                                check_walign32( R_ECX );
nkeynes@386
  1341
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1342
                                store_reg( R_ECX, Rn );
nkeynes@359
  1343
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1344
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1345
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1346
                                }
nkeynes@359
  1347
                                break;
nkeynes@359
  1348
                            default:
nkeynes@359
  1349
                                UNDEF();
nkeynes@359
  1350
                                break;
nkeynes@359
  1351
                        }
nkeynes@359
  1352
                        break;
nkeynes@359
  1353
                    case 0x3:
nkeynes@359
  1354
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1355
                            case 0x0:
nkeynes@359
  1356
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1357
                                    case 0x0:
nkeynes@359
  1358
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1359
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1360
                                        check_priv();
nkeynes@395
  1361
                                        call_func0( sh4_read_sr );
nkeynes@374
  1362
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1363
                                        check_walign32( R_ECX );
nkeynes@386
  1364
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1365
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1366
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1367
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1368
                                        }
nkeynes@359
  1369
                                        break;
nkeynes@359
  1370
                                    case 0x1:
nkeynes@359
  1371
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1372
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1373
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1374
                                        check_walign32( R_ECX );
nkeynes@386
  1375
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1376
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1377
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1378
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1379
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1380
                                        }
nkeynes@359
  1381
                                        break;
nkeynes@359
  1382
                                    case 0x2:
nkeynes@359
  1383
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1384
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1385
                                        check_priv();
nkeynes@359
  1386
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1387
                                        check_walign32( R_ECX );
nkeynes@386
  1388
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1389
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1390
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1391
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1392
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1393
                                        }
nkeynes@359
  1394
                                        break;
nkeynes@359
  1395
                                    case 0x3:
nkeynes@359
  1396
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1397
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1398
                                        check_priv();
nkeynes@359
  1399
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1400
                                        check_walign32( R_ECX );
nkeynes@386
  1401
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1402
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1403
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1404
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1405
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1406
                                        }
nkeynes@359
  1407
                                        break;
nkeynes@359
  1408
                                    case 0x4:
nkeynes@359
  1409
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1410
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@559
  1411
                                        check_priv();
nkeynes@359
  1412
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1413
                                        check_walign32( R_ECX );
nkeynes@386
  1414
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1415
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1416
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1417
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1418
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1419
                                        }
nkeynes@359
  1420
                                        break;
nkeynes@359
  1421
                                    default:
nkeynes@359
  1422
                                        UNDEF();
nkeynes@359
  1423
                                        break;
nkeynes@359
  1424
                                }
nkeynes@359
  1425
                                break;
nkeynes@359
  1426
                            case 0x1:
nkeynes@359
  1427
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1428
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1429
                                check_priv();
nkeynes@374
  1430
                                load_reg( R_ECX, Rn );
nkeynes@395
  1431
                                check_walign32( R_ECX );
nkeynes@386
  1432
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1433
                                store_reg( R_ECX, Rn );
nkeynes@374
  1434
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1435
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1436
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1437
                                }
nkeynes@359
  1438
                                break;
nkeynes@359
  1439
                        }
nkeynes@359
  1440
                        break;
nkeynes@359
  1441
                    case 0x4:
nkeynes@359
  1442
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1443
                            case 0x0:
nkeynes@359
  1444
                                { /* ROTL Rn */
nkeynes@359
  1445
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1446
                                load_reg( R_EAX, Rn );
nkeynes@359
  1447
                                ROL1_r32( R_EAX );
nkeynes@359
  1448
                                store_reg( R_EAX, Rn );
nkeynes@359
  1449
                                SETC_t();
nkeynes@417
  1450
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1451
                                }
nkeynes@359
  1452
                                break;
nkeynes@359
  1453
                            case 0x2:
nkeynes@359
  1454
                                { /* ROTCL Rn */
nkeynes@359
  1455
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1456
                                load_reg( R_EAX, Rn );
nkeynes@417
  1457
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1458
                            	LDC_t();
nkeynes@417
  1459
                                }
nkeynes@359
  1460
                                RCL1_r32( R_EAX );
nkeynes@359
  1461
                                store_reg( R_EAX, Rn );
nkeynes@359
  1462
                                SETC_t();
nkeynes@417
  1463
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1464
                                }
nkeynes@359
  1465
                                break;
nkeynes@359
  1466
                            default:
nkeynes@359
  1467
                                UNDEF();
nkeynes@359
  1468
                                break;
nkeynes@359
  1469
                        }
nkeynes@359
  1470
                        break;
nkeynes@359
  1471
                    case 0x5:
nkeynes@359
  1472
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1473
                            case 0x0:
nkeynes@359
  1474
                                { /* ROTR Rn */
nkeynes@359
  1475
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1476
                                load_reg( R_EAX, Rn );
nkeynes@359
  1477
                                ROR1_r32( R_EAX );
nkeynes@359
  1478
                                store_reg( R_EAX, Rn );
nkeynes@359
  1479
                                SETC_t();
nkeynes@417
  1480
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1481
                                }
nkeynes@359
  1482
                                break;
nkeynes@359
  1483
                            case 0x1:
nkeynes@359
  1484
                                { /* CMP/PL Rn */
nkeynes@359
  1485
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1486
                                load_reg( R_EAX, Rn );
nkeynes@359
  1487
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1488
                                SETG_t();
nkeynes@417
  1489
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1490
                                }
nkeynes@359
  1491
                                break;
nkeynes@359
  1492
                            case 0x2:
nkeynes@359
  1493
                                { /* ROTCR Rn */
nkeynes@359
  1494
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1495
                                load_reg( R_EAX, Rn );
nkeynes@417
  1496
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1497
                            	LDC_t();
nkeynes@417
  1498
                                }
nkeynes@359
  1499
                                RCR1_r32( R_EAX );
nkeynes@359
  1500
                                store_reg( R_EAX, Rn );
nkeynes@359
  1501
                                SETC_t();
nkeynes@417
  1502
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1503
                                }
nkeynes@359
  1504
                                break;
nkeynes@359
  1505
                            default:
nkeynes@359
  1506
                                UNDEF();
nkeynes@359
  1507
                                break;
nkeynes@359
  1508
                        }
nkeynes@359
  1509
                        break;
nkeynes@359
  1510
                    case 0x6:
nkeynes@359
  1511
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1512
                            case 0x0:
nkeynes@359
  1513
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1514
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1515
                                load_reg( R_EAX, Rm );
nkeynes@395
  1516
                                check_ralign32( R_EAX );
nkeynes@359
  1517
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1518
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1519
                                store_reg( R_EAX, Rm );
nkeynes@359
  1520
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1521
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1522
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1523
                                }
nkeynes@359
  1524
                                break;
nkeynes@359
  1525
                            case 0x1:
nkeynes@359
  1526
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1527
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1528
                                load_reg( R_EAX, Rm );
nkeynes@395
  1529
                                check_ralign32( R_EAX );
nkeynes@359
  1530
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1531
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1532
                                store_reg( R_EAX, Rm );
nkeynes@359
  1533
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1534
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1535
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1536
                                }
nkeynes@359
  1537
                                break;
nkeynes@359
  1538
                            case 0x2:
nkeynes@359
  1539
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1540
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1541
                                load_reg( R_EAX, Rm );
nkeynes@395
  1542
                                check_ralign32( R_EAX );
nkeynes@359
  1543
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1544
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1545
                                store_reg( R_EAX, Rm );
nkeynes@359
  1546
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1547
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1548
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1549
                                }
nkeynes@359
  1550
                                break;
nkeynes@359
  1551
                            case 0x3:
nkeynes@359
  1552
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1553
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1554
                                check_priv();
nkeynes@359
  1555
                                load_reg( R_EAX, Rm );
nkeynes@395
  1556
                                check_ralign32( R_EAX );
nkeynes@359
  1557
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1558
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1559
                                store_reg( R_EAX, Rm );
nkeynes@359
  1560
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1561
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1562
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1563
                                }
nkeynes@359
  1564
                                break;
nkeynes@359
  1565
                            case 0x5:
nkeynes@359
  1566
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1567
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1568
                                load_reg( R_EAX, Rm );
nkeynes@395
  1569
                                check_ralign32( R_EAX );
nkeynes@359
  1570
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1571
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1572
                                store_reg( R_EAX, Rm );
nkeynes@359
  1573
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1574
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1575
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1576
                                }
nkeynes@359
  1577
                                break;
nkeynes@359
  1578
                            case 0x6:
nkeynes@359
  1579
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1580
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1581
                                load_reg( R_EAX, Rm );
nkeynes@395
  1582
                                check_ralign32( R_EAX );
nkeynes@359
  1583
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1584
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1585
                                store_reg( R_EAX, Rm );
nkeynes@359
  1586
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1587
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1588
                                update_fr_bank( R_EAX );
nkeynes@417
  1589
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1590
                                }
nkeynes@359
  1591
                                break;
nkeynes@359
  1592
                            case 0xF:
nkeynes@359
  1593
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1594
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1595
                                check_priv();
nkeynes@359
  1596
                                load_reg( R_EAX, Rm );
nkeynes@395
  1597
                                check_ralign32( R_EAX );
nkeynes@359
  1598
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1599
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1600
                                store_reg( R_EAX, Rm );
nkeynes@359
  1601
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1602
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1603
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1604
                                }
nkeynes@359
  1605
                                break;
nkeynes@359
  1606
                            default:
nkeynes@359
  1607
                                UNDEF();
nkeynes@359
  1608
                                break;
nkeynes@359
  1609
                        }
nkeynes@359
  1610
                        break;
nkeynes@359
  1611
                    case 0x7:
nkeynes@359
  1612
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1613
                            case 0x0:
nkeynes@359
  1614
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1615
                                    case 0x0:
nkeynes@359
  1616
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1617
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1618
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1619
                                    	SLOTILLEGAL();
nkeynes@386
  1620
                                        } else {
nkeynes@559
  1621
                                    	check_priv();
nkeynes@386
  1622
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1623
                                    	check_ralign32( R_EAX );
nkeynes@386
  1624
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1625
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1626
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1627
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1628
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1629
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1630
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1631
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1632
                                        }
nkeynes@359
  1633
                                        }
nkeynes@359
  1634
                                        break;
nkeynes@359
  1635
                                    case 0x1:
nkeynes@359
  1636
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1637
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1638
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1639
                                        check_ralign32( R_EAX );
nkeynes@359
  1640
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1641
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1642
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1643
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1644
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1645
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1646
                                        }
nkeynes@359
  1647
                                        break;
nkeynes@359
  1648
                                    case 0x2:
nkeynes@359
  1649
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1650
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1651
                                        check_priv();
nkeynes@359
  1652
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1653
                                        check_ralign32( R_EAX );
nkeynes@359
  1654
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1655
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1656
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1657
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1658
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1659
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1660
                                        }
nkeynes@359
  1661
                                        break;
nkeynes@359
  1662
                                    case 0x3:
nkeynes@359
  1663
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1664
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1665
                                        check_priv();
nkeynes@359
  1666
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1667
                                        check_ralign32( R_EAX );
nkeynes@359
  1668
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1669
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1670
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1671
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1672
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1673
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1674
                                        }
nkeynes@359
  1675
                                        break;
nkeynes@359
  1676
                                    case 0x4:
nkeynes@359
  1677
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1678
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@559
  1679
                                        check_priv();
nkeynes@359
  1680
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1681
                                        check_ralign32( R_EAX );
nkeynes@359
  1682
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1683
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1684
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1685
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1686
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1687
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1688
                                        }
nkeynes@359
  1689
                                        break;
nkeynes@359
  1690
                                    default:
nkeynes@359
  1691
                                        UNDEF();
nkeynes@359
  1692
                                        break;
nkeynes@359
  1693
                                }
nkeynes@359
  1694
                                break;
nkeynes@359
  1695
                            case 0x1:
nkeynes@359
  1696
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1697
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@559
  1698
                                check_priv();
nkeynes@374
  1699
                                load_reg( R_EAX, Rm );
nkeynes@395
  1700
                                check_ralign32( R_EAX );
nkeynes@374
  1701
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1702
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1703
                                store_reg( R_EAX, Rm );
nkeynes@374
  1704
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1705
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1706
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1707
                                }
nkeynes@359
  1708
                                break;
nkeynes@359
  1709
                        }
nkeynes@359
  1710
                        break;
nkeynes@359
  1711
                    case 0x8:
nkeynes@359
  1712
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1713
                            case 0x0:
nkeynes@359
  1714
                                { /* SHLL2 Rn */
nkeynes@359
  1715
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1716
                                load_reg( R_EAX, Rn );
nkeynes@359
  1717
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1718
                                store_reg( R_EAX, Rn );
nkeynes@417
  1719
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1720
                                }
nkeynes@359
  1721
                                break;
nkeynes@359
  1722
                            case 0x1:
nkeynes@359
  1723
                                { /* SHLL8 Rn */
nkeynes@359
  1724
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1725
                                load_reg( R_EAX, Rn );
nkeynes@359
  1726
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1727
                                store_reg( R_EAX, Rn );
nkeynes@417
  1728
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1729
                                }
nkeynes@359
  1730
                                break;
nkeynes@359
  1731
                            case 0x2:
nkeynes@359
  1732
                                { /* SHLL16 Rn */
nkeynes@359
  1733
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1734
                                load_reg( R_EAX, Rn );
nkeynes@359
  1735
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1736
                                store_reg( R_EAX, Rn );
nkeynes@417
  1737
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1738
                                }
nkeynes@359
  1739
                                break;
nkeynes@359
  1740
                            default:
nkeynes@359
  1741
                                UNDEF();
nkeynes@359
  1742
                                break;
nkeynes@359
  1743
                        }
nkeynes@359
  1744
                        break;
nkeynes@359
  1745
                    case 0x9:
nkeynes@359
  1746
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1747
                            case 0x0:
nkeynes@359
  1748
                                { /* SHLR2 Rn */
nkeynes@359
  1749
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1750
                                load_reg( R_EAX, Rn );
nkeynes@359
  1751
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1752
                                store_reg( R_EAX, Rn );
nkeynes@417
  1753
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1754
                                }
nkeynes@359
  1755
                                break;
nkeynes@359
  1756
                            case 0x1:
nkeynes@359
  1757
                                { /* SHLR8 Rn */
nkeynes@359
  1758
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1759
                                load_reg( R_EAX, Rn );
nkeynes@359
  1760
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1761
                                store_reg( R_EAX, Rn );
nkeynes@417
  1762
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1763
                                }
nkeynes@359
  1764
                                break;
nkeynes@359
  1765
                            case 0x2:
nkeynes@359
  1766
                                { /* SHLR16 Rn */
nkeynes@359
  1767
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1768
                                load_reg( R_EAX, Rn );
nkeynes@359
  1769
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1770
                                store_reg( R_EAX, Rn );
nkeynes@417
  1771
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1772
                                }
nkeynes@359
  1773
                                break;
nkeynes@359
  1774
                            default:
nkeynes@359
  1775
                                UNDEF();
nkeynes@359
  1776
                                break;
nkeynes@359
  1777
                        }
nkeynes@359
  1778
                        break;
nkeynes@359
  1779
                    case 0xA:
nkeynes@359
  1780
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1781
                            case 0x0:
nkeynes@359
  1782
                                { /* LDS Rm, MACH */
nkeynes@359
  1783
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1784
                                load_reg( R_EAX, Rm );
nkeynes@359
  1785
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1786
                                }
nkeynes@359
  1787
                                break;
nkeynes@359
  1788
                            case 0x1:
nkeynes@359
  1789
                                { /* LDS Rm, MACL */
nkeynes@359
  1790
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1791
                                load_reg( R_EAX, Rm );
nkeynes@359
  1792
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1793
                                }
nkeynes@359
  1794
                                break;
nkeynes@359
  1795
                            case 0x2:
nkeynes@359
  1796
                                { /* LDS Rm, PR */
nkeynes@359
  1797
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1798
                                load_reg( R_EAX, Rm );
nkeynes@359
  1799
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1800
                                }
nkeynes@359
  1801
                                break;
nkeynes@359
  1802
                            case 0x3:
nkeynes@359
  1803
                                { /* LDC Rm, SGR */
nkeynes@359
  1804
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1805
                                check_priv();
nkeynes@359
  1806
                                load_reg( R_EAX, Rm );
nkeynes@359
  1807
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1808
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1809
                                }
nkeynes@359
  1810
                                break;
nkeynes@359
  1811
                            case 0x5:
nkeynes@359
  1812
                                { /* LDS Rm, FPUL */
nkeynes@359
  1813
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1814
                                load_reg( R_EAX, Rm );
nkeynes@359
  1815
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1816
                                }
nkeynes@359
  1817
                                break;
nkeynes@359
  1818
                            case 0x6:
nkeynes@359
  1819
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1820
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1821
                                load_reg( R_EAX, Rm );
nkeynes@359
  1822
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1823
                                update_fr_bank( R_EAX );
nkeynes@417
  1824
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1825
                                }
nkeynes@359
  1826
                                break;
nkeynes@359
  1827
                            case 0xF:
nkeynes@359
  1828
                                { /* LDC Rm, DBR */
nkeynes@359
  1829
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1830
                                check_priv();
nkeynes@359
  1831
                                load_reg( R_EAX, Rm );
nkeynes@359
  1832
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1833
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1834
                                }
nkeynes@359
  1835
                                break;
nkeynes@359
  1836
                            default:
nkeynes@359
  1837
                                UNDEF();
nkeynes@359
  1838
                                break;
nkeynes@359
  1839
                        }
nkeynes@359
  1840
                        break;
nkeynes@359
  1841
                    case 0xB:
nkeynes@359
  1842
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1843
                            case 0x0:
nkeynes@359
  1844
                                { /* JSR @Rn */
nkeynes@359
  1845
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1846
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1847
                            	SLOTILLEGAL();
nkeynes@374
  1848
                                } else {
nkeynes@374
  1849
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1850
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1851
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1852
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1853
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1854
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1855
                            	exit_block_pcset(pc+2);
nkeynes@409
  1856
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1857
                            	return 4;
nkeynes@374
  1858
                                }
nkeynes@359
  1859
                                }
nkeynes@359
  1860
                                break;
nkeynes@359
  1861
                            case 0x1:
nkeynes@359
  1862
                                { /* TAS.B @Rn */
nkeynes@359
  1863
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1864
                                load_reg( R_ECX, Rn );
nkeynes@361
  1865
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1866
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1867
                                SETE_t();
nkeynes@361
  1868
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1869
                                load_reg( R_ECX, Rn );
nkeynes@361
  1870
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1871
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1872
                                }
nkeynes@359
  1873
                                break;
nkeynes@359
  1874
                            case 0x2:
nkeynes@359
  1875
                                { /* JMP @Rn */
nkeynes@359
  1876
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1877
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1878
                            	SLOTILLEGAL();
nkeynes@374
  1879
                                } else {
nkeynes@408
  1880
                            	load_reg( R_ECX, Rn );
nkeynes@408
  1881
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1882
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1883
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1884
                            	exit_block_pcset(pc+2);
nkeynes@409
  1885
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1886
                            	return 4;
nkeynes@374
  1887
                                }
nkeynes@359
  1888
                                }
nkeynes@359
  1889
                                break;
nkeynes@359
  1890
                            default:
nkeynes@359
  1891
                                UNDEF();
nkeynes@359
  1892
                                break;
nkeynes@359
  1893
                        }
nkeynes@359
  1894
                        break;
nkeynes@359
  1895
                    case 0xC:
nkeynes@359
  1896
                        { /* SHAD Rm, Rn */
nkeynes@359
  1897
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1898
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1899
                        load_reg( R_EAX, Rn );
nkeynes@361
  1900
                        load_reg( R_ECX, Rm );
nkeynes@361
  1901
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1902
                        JGE_rel8(16, doshl);
nkeynes@361
  1903
                                        
nkeynes@361
  1904
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1905
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1906
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1907
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1908
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1909
                    
nkeynes@386
  1910
                        JMP_TARGET(emptysar);
nkeynes@386
  1911
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1912
                        JMP_rel8(5, end2);
nkeynes@386
  1913
                    
nkeynes@380
  1914
                        JMP_TARGET(doshl);
nkeynes@361
  1915
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1916
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1917
                        JMP_TARGET(end);
nkeynes@386
  1918
                        JMP_TARGET(end2);
nkeynes@361
  1919
                        store_reg( R_EAX, Rn );
nkeynes@417
  1920
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1921
                        }
nkeynes@359
  1922
                        break;
nkeynes@359
  1923
                    case 0xD:
nkeynes@359
  1924
                        { /* SHLD Rm, Rn */
nkeynes@359
  1925
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1926
                        load_reg( R_EAX, Rn );
nkeynes@368
  1927
                        load_reg( R_ECX, Rm );
nkeynes@386
  1928
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1929
                        JGE_rel8(15, doshl);
nkeynes@368
  1930
                    
nkeynes@386
  1931
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1932
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1933
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1934
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1935
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1936
                    
nkeynes@386
  1937
                        JMP_TARGET(emptyshr);
nkeynes@386
  1938
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1939
                        JMP_rel8(5, end2);
nkeynes@386
  1940
                    
nkeynes@386
  1941
                        JMP_TARGET(doshl);
nkeynes@386
  1942
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1943
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1944
                        JMP_TARGET(end);
nkeynes@386
  1945
                        JMP_TARGET(end2);
nkeynes@368
  1946
                        store_reg( R_EAX, Rn );
nkeynes@417
  1947
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1948
                        }
nkeynes@359
  1949
                        break;
nkeynes@359
  1950
                    case 0xE:
nkeynes@359
  1951
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1952
                            case 0x0:
nkeynes@359
  1953
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1954
                                    case 0x0:
nkeynes@359
  1955
                                        { /* LDC Rm, SR */
nkeynes@359
  1956
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1957
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1958
                                    	SLOTILLEGAL();
nkeynes@386
  1959
                                        } else {
nkeynes@386
  1960
                                    	check_priv();
nkeynes@386
  1961
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1962
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1963
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1964
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1965
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1966
                                        }
nkeynes@359
  1967
                                        }
nkeynes@359
  1968
                                        break;
nkeynes@359
  1969
                                    case 0x1:
nkeynes@359
  1970
                                        { /* LDC Rm, GBR */
nkeynes@359
  1971
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1972
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1973
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1974
                                        }
nkeynes@359
  1975
                                        break;
nkeynes@359
  1976
                                    case 0x2:
nkeynes@359
  1977
                                        { /* LDC Rm, VBR */
nkeynes@359
  1978
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1979
                                        check_priv();
nkeynes@359
  1980
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1981
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1982
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1983
                                        }
nkeynes@359
  1984
                                        break;
nkeynes@359
  1985
                                    case 0x3:
nkeynes@359
  1986
                                        { /* LDC Rm, SSR */
nkeynes@359
  1987
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1988
                                        check_priv();
nkeynes@359
  1989
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1990
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1991
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1992
                                        }
nkeynes@359
  1993
                                        break;
nkeynes@359
  1994
                                    case 0x4:
nkeynes@359
  1995
                                        { /* LDC Rm, SPC */
nkeynes@359
  1996
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1997
                                        check_priv();
nkeynes@359
  1998
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1999
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2000
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2001
                                        }
nkeynes@359
  2002
                                        break;
nkeynes@359
  2003
                                    default:
nkeynes@359
  2004
                                        UNDEF();
nkeynes@359
  2005
                                        break;
nkeynes@359
  2006
                                }
nkeynes@359
  2007
                                break;
nkeynes@359
  2008
                            case 0x1:
nkeynes@359
  2009
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2010
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2011
                                check_priv();
nkeynes@374
  2012
                                load_reg( R_EAX, Rm );
nkeynes@374
  2013
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2014
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2015
                                }
nkeynes@359
  2016
                                break;
nkeynes@359
  2017
                        }
nkeynes@359
  2018
                        break;
nkeynes@359
  2019
                    case 0xF:
nkeynes@359
  2020
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2021
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  2022
                        load_reg( R_ECX, Rm );
nkeynes@386
  2023
                        check_ralign16( R_ECX );
nkeynes@386
  2024
                        load_reg( R_ECX, Rn );
nkeynes@386
  2025
                        check_ralign16( R_ECX );
nkeynes@386
  2026
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  2027
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2028
                        PUSH_realigned_r32( R_EAX );
nkeynes@386
  2029
                        load_reg( R_ECX, Rm );
nkeynes@386
  2030
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  2031
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2032
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2033
                        IMUL_r32( R_ECX );
nkeynes@386
  2034
                    
nkeynes@386
  2035
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2036
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2037
                        JE_rel8( 47, nosat );
nkeynes@386
  2038
                    
nkeynes@386
  2039
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2040
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2041
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2042
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2043
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2044
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2045
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2046
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2047
                    
nkeynes@386
  2048
                        JMP_TARGET(positive);
nkeynes@386
  2049
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2050
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2051
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2052
                    
nkeynes@386
  2053
                        JMP_TARGET(nosat);
nkeynes@386
  2054
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2055
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2056
                        JMP_TARGET(end);
nkeynes@386
  2057
                        JMP_TARGET(end2);
nkeynes@386
  2058
                        JMP_TARGET(end3);
nkeynes@417
  2059
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2060
                        }
nkeynes@359
  2061
                        break;
nkeynes@359
  2062
                }
nkeynes@359
  2063
                break;
nkeynes@359
  2064
            case 0x5:
nkeynes@359
  2065
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2066
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2067
                load_reg( R_ECX, Rm );
nkeynes@361
  2068
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  2069
                check_ralign32( R_ECX );
nkeynes@361
  2070
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2071
                store_reg( R_EAX, Rn );
nkeynes@417
  2072
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2073
                }
nkeynes@359
  2074
                break;
nkeynes@359
  2075
            case 0x6:
nkeynes@359
  2076
                switch( ir&0xF ) {
nkeynes@359
  2077
                    case 0x0:
nkeynes@359
  2078
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2079
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2080
                        load_reg( R_ECX, Rm );
nkeynes@359
  2081
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2082
                        store_reg( R_EAX, Rn );
nkeynes@417
  2083
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2084
                        }
nkeynes@359
  2085
                        break;
nkeynes@359
  2086
                    case 0x1:
nkeynes@359
  2087
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2088
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2089
                        load_reg( R_ECX, Rm );
nkeynes@374
  2090
                        check_ralign16( R_ECX );
nkeynes@361
  2091
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2092
                        store_reg( R_EAX, Rn );
nkeynes@417
  2093
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2094
                        }
nkeynes@359
  2095
                        break;
nkeynes@359
  2096
                    case 0x2:
nkeynes@359
  2097
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2098
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2099
                        load_reg( R_ECX, Rm );
nkeynes@374
  2100
                        check_ralign32( R_ECX );
nkeynes@361
  2101
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2102
                        store_reg( R_EAX, Rn );
nkeynes@417
  2103
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2104
                        }
nkeynes@359
  2105
                        break;
nkeynes@359
  2106
                    case 0x3:
nkeynes@359
  2107
                        { /* MOV Rm, Rn */
nkeynes@359
  2108
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2109
                        load_reg( R_EAX, Rm );
nkeynes@359
  2110
                        store_reg( R_EAX, Rn );
nkeynes@359
  2111
                        }
nkeynes@359
  2112
                        break;
nkeynes@359
  2113
                    case 0x4:
nkeynes@359
  2114
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2115
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2116
                        load_reg( R_ECX, Rm );
nkeynes@359
  2117
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2118
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2119
                        store_reg( R_EAX, Rm );
nkeynes@359
  2120
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2121
                        store_reg( R_EAX, Rn );
nkeynes@417
  2122
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2123
                        }
nkeynes@359
  2124
                        break;
nkeynes@359
  2125
                    case 0x5:
nkeynes@359
  2126
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2127
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2128
                        load_reg( R_EAX, Rm );
nkeynes@374
  2129
                        check_ralign16( R_EAX );
nkeynes@361
  2130
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2131
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2132
                        store_reg( R_EAX, Rm );
nkeynes@361
  2133
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2134
                        store_reg( R_EAX, Rn );
nkeynes@417
  2135
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2136
                        }
nkeynes@359
  2137
                        break;
nkeynes@359
  2138
                    case 0x6:
nkeynes@359
  2139
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2140
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2141
                        load_reg( R_EAX, Rm );
nkeynes@386
  2142
                        check_ralign32( R_EAX );
nkeynes@361
  2143
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2144
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2145
                        store_reg( R_EAX, Rm );
nkeynes@361
  2146
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2147
                        store_reg( R_EAX, Rn );
nkeynes@417
  2148
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2149
                        }
nkeynes@359
  2150
                        break;
nkeynes@359
  2151
                    case 0x7:
nkeynes@359
  2152
                        { /* NOT Rm, Rn */
nkeynes@359
  2153
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2154
                        load_reg( R_EAX, Rm );
nkeynes@359
  2155
                        NOT_r32( R_EAX );
nkeynes@359
  2156
                        store_reg( R_EAX, Rn );
nkeynes@417
  2157
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2158
                        }
nkeynes@359
  2159
                        break;
nkeynes@359
  2160
                    case 0x8:
nkeynes@359
  2161
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2162
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2163
                        load_reg( R_EAX, Rm );
nkeynes@359
  2164
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2165
                        store_reg( R_EAX, Rn );
nkeynes@359
  2166
                        }
nkeynes@359
  2167
                        break;
nkeynes@359
  2168
                    case 0x9:
nkeynes@359
  2169
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2170
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2171
                        load_reg( R_EAX, Rm );
nkeynes@359
  2172
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2173
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2174
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2175
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2176
                        store_reg( R_ECX, Rn );
nkeynes@417
  2177
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2178
                        }
nkeynes@359
  2179
                        break;
nkeynes@359
  2180
                    case 0xA:
nkeynes@359
  2181
                        { /* NEGC Rm, Rn */
nkeynes@359
  2182
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2183
                        load_reg( R_EAX, Rm );
nkeynes@359
  2184
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2185
                        LDC_t();
nkeynes@359
  2186
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2187
                        store_reg( R_ECX, Rn );
nkeynes@359
  2188
                        SETC_t();
nkeynes@417
  2189
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2190
                        }
nkeynes@359
  2191
                        break;
nkeynes@359
  2192
                    case 0xB:
nkeynes@359
  2193
                        { /* NEG Rm, Rn */
nkeynes@359
  2194
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2195
                        load_reg( R_EAX, Rm );
nkeynes@359
  2196
                        NEG_r32( R_EAX );
nkeynes@359
  2197
                        store_reg( R_EAX, Rn );
nkeynes@417
  2198
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2199
                        }
nkeynes@359
  2200
                        break;
nkeynes@359
  2201
                    case 0xC:
nkeynes@359
  2202
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2203
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2204
                        load_reg( R_EAX, Rm );
nkeynes@361
  2205
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2206
                        store_reg( R_EAX, Rn );
nkeynes@359
  2207
                        }
nkeynes@359
  2208
                        break;
nkeynes@359
  2209
                    case 0xD:
nkeynes@359
  2210
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2211
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2212
                        load_reg( R_EAX, Rm );
nkeynes@361
  2213
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2214
                        store_reg( R_EAX, Rn );
nkeynes@359
  2215
                        }
nkeynes@359
  2216
                        break;
nkeynes@359
  2217
                    case 0xE:
nkeynes@359
  2218
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2219
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2220
                        load_reg( R_EAX, Rm );
nkeynes@359
  2221
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2222
                        store_reg( R_EAX, Rn );
nkeynes@359
  2223
                        }
nkeynes@359
  2224
                        break;
nkeynes@359
  2225
                    case 0xF:
nkeynes@359
  2226
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2227
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2228
                        load_reg( R_EAX, Rm );
nkeynes@361
  2229
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2230
                        store_reg( R_EAX, Rn );
nkeynes@359
  2231
                        }
nkeynes@359
  2232
                        break;
nkeynes@359
  2233
                }
nkeynes@359
  2234
                break;
nkeynes@359
  2235
            case 0x7:
nkeynes@359
  2236
                { /* ADD #imm, Rn */
nkeynes@359
  2237
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2238
                load_reg( R_EAX, Rn );
nkeynes@359
  2239
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2240
                store_reg( R_EAX, Rn );
nkeynes@417
  2241
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2242
                }
nkeynes@359
  2243
                break;
nkeynes@359
  2244
            case 0x8:
nkeynes@359
  2245
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2246
                    case 0x0:
nkeynes@359
  2247
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2248
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2249
                        load_reg( R_EAX, 0 );
nkeynes@359
  2250
                        load_reg( R_ECX, Rn );
nkeynes@359
  2251
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2252
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2253
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2254
                        }
nkeynes@359
  2255
                        break;
nkeynes@359
  2256
                    case 0x1:
nkeynes@359
  2257
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2258
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2259
                        load_reg( R_ECX, Rn );
nkeynes@361
  2260
                        load_reg( R_EAX, 0 );
nkeynes@361
  2261
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2262
                        check_walign16( R_ECX );
nkeynes@361
  2263
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2264
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2265
                        }
nkeynes@359
  2266
                        break;
nkeynes@359
  2267
                    case 0x4:
nkeynes@359
  2268
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2269
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2270
                        load_reg( R_ECX, Rm );
nkeynes@359
  2271
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2272
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2273
                        store_reg( R_EAX, 0 );
nkeynes@417
  2274
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2275
                        }
nkeynes@359
  2276
                        break;
nkeynes@359
  2277
                    case 0x5:
nkeynes@359
  2278
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2279
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2280
                        load_reg( R_ECX, Rm );
nkeynes@361
  2281
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2282
                        check_ralign16( R_ECX );
nkeynes@361
  2283
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2284
                        store_reg( R_EAX, 0 );
nkeynes@417
  2285
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2286
                        }
nkeynes@359
  2287
                        break;
nkeynes@359
  2288
                    case 0x8:
nkeynes@359
  2289
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2290
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2291
                        load_reg( R_EAX, 0 );
nkeynes@359
  2292
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2293
                        SETE_t();
nkeynes@417
  2294
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2295
                        }
nkeynes@359
  2296
                        break;
nkeynes@359
  2297
                    case 0x9:
nkeynes@359
  2298
                        { /* BT disp */
nkeynes@359
  2299
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2300
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2301
                    	SLOTILLEGAL();
nkeynes@374
  2302
                        } else {
nkeynes@527
  2303
                    	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2304
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2305
                    	JMP_TARGET(nottaken);
nkeynes@408
  2306
                    	return 2;
nkeynes@374
  2307
                        }
nkeynes@359
  2308
                        }
nkeynes@359
  2309
                        break;
nkeynes@359
  2310
                    case 0xB:
nkeynes@359
  2311
                        { /* BF disp */
nkeynes@359
  2312
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2313
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2314
                    	SLOTILLEGAL();
nkeynes@374
  2315
                        } else {
nkeynes@527
  2316
                    	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2317
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2318
                    	JMP_TARGET(nottaken);
nkeynes@408
  2319
                    	return 2;
nkeynes@374
  2320
                        }
nkeynes@359
  2321
                        }
nkeynes@359
  2322
                        break;
nkeynes@359
  2323
                    case 0xD:
nkeynes@359
  2324
                        { /* BT/S disp */
nkeynes@359
  2325
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2326
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2327
                    	SLOTILLEGAL();
nkeynes@374
  2328
                        } else {
nkeynes@408
  2329
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2330
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2331
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2332
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2333
                    	}
nkeynes@417
  2334
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2335
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2336
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2337
                    	// not taken
nkeynes@408
  2338
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2339
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2340
                    	return 4;
nkeynes@374
  2341
                        }
nkeynes@359
  2342
                        }
nkeynes@359
  2343
                        break;
nkeynes@359
  2344
                    case 0xF:
nkeynes@359
  2345
                        { /* BF/S disp */
nkeynes@359
  2346
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2347
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2348
                    	SLOTILLEGAL();
nkeynes@374
  2349
                        } else {
nkeynes@408
  2350
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2351
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2352
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2353
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2354
                    	}
nkeynes@417
  2355
                    	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  2356
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2357
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2358
                    	// not taken
nkeynes@408
  2359
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2360
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2361
                    	return 4;
nkeynes@374
  2362
                        }
nkeynes@359
  2363
                        }
nkeynes@359
  2364
                        break;
nkeynes@359
  2365
                    default:
nkeynes@359
  2366
                        UNDEF();
nkeynes@359
  2367
                        break;
nkeynes@359
  2368
                }
nkeynes@359
  2369
                break;
nkeynes@359
  2370
            case 0x9:
nkeynes@359
  2371
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2372
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2373
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2374
            	SLOTILLEGAL();
nkeynes@374
  2375
                } else {
nkeynes@569
  2376
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  2377
            	uint32_t target = pc + disp + 4;
nkeynes@569
  2378
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2379
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  2380
            	    MOV_moff32_EAX( ptr );
nkeynes@569
  2381
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  2382
            	} else {
nkeynes@569
  2383
            	    load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@569
  2384
            	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@569
  2385
            	    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@569
  2386
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  2387
            	}
nkeynes@374
  2388
            	store_reg( R_EAX, Rn );
nkeynes@374
  2389
                }
nkeynes@359
  2390
                }
nkeynes@359
  2391
                break;
nkeynes@359
  2392
            case 0xA:
nkeynes@359
  2393
                { /* BRA disp */
nkeynes@359
  2394
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2395
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2396
            	SLOTILLEGAL();
nkeynes@374
  2397
                } else {
nkeynes@374
  2398
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2399
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2400
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2401
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2402
            	return 4;
nkeynes@374
  2403
                }
nkeynes@359
  2404
                }
nkeynes@359
  2405
                break;
nkeynes@359
  2406
            case 0xB:
nkeynes@359
  2407
                { /* BSR disp */
nkeynes@359
  2408
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2409
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2410
            	SLOTILLEGAL();
nkeynes@374
  2411
                } else {
nkeynes@374
  2412
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2413
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2414
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2415
            	sh4_translate_instruction( pc + 2 );
nkeynes@408
  2416
            	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  2417
            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2418
            	return 4;
nkeynes@374
  2419
                }
nkeynes@359
  2420
                }
nkeynes@359
  2421
                break;
nkeynes@359
  2422
            case 0xC:
nkeynes@359
  2423
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2424
                    case 0x0:
nkeynes@359
  2425
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2426
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2427
                        load_reg( R_EAX, 0 );
nkeynes@359
  2428
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2429
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2430
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2431
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2432
                        }
nkeynes@359
  2433
                        break;
nkeynes@359
  2434
                    case 0x1:
nkeynes@359
  2435
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2436
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2437
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2438
                        load_reg( R_EAX, 0 );
nkeynes@361
  2439
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2440
                        check_walign16( R_ECX );
nkeynes@361
  2441
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2442
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2443
                        }
nkeynes@359
  2444
                        break;
nkeynes@359
  2445
                    case 0x2:
nkeynes@359
  2446
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2447
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2448
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2449
                        load_reg( R_EAX, 0 );
nkeynes@361
  2450
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2451
                        check_walign32( R_ECX );
nkeynes@361
  2452
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2453
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2454
                        }
nkeynes@359
  2455
                        break;
nkeynes@359
  2456
                    case 0x3:
nkeynes@359
  2457
                        { /* TRAPA #imm */
nkeynes@359
  2458
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2459
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2460
                    	SLOTILLEGAL();
nkeynes@374
  2461
                        } else {
nkeynes@533
  2462
                    	load_imm32( R_ECX, pc+2 );
nkeynes@533
  2463
                    	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  2464
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2465
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2466
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2467
                    	exit_block_pcset(pc);
nkeynes@409
  2468
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2469
                    	return 2;
nkeynes@374
  2470
                        }
nkeynes@359
  2471
                        }
nkeynes@359
  2472
                        break;
nkeynes@359
  2473
                    case 0x4:
nkeynes@359
  2474
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2475
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2476
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2477
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2478
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2479
                        store_reg( R_EAX, 0 );
nkeynes@417
  2480
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2481
                        }
nkeynes@359
  2482
                        break;
nkeynes@359
  2483
                    case 0x5:
nkeynes@359
  2484
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2485
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2486
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2487
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2488
                        check_ralign16( R_ECX );
nkeynes@361
  2489
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2490
                        store_reg( R_EAX, 0 );
nkeynes@417
  2491
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2492
                        }
nkeynes@359
  2493
                        break;
nkeynes@359
  2494
                    case 0x6:
nkeynes@359
  2495
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2496
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2497
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2498
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2499
                        check_ralign32( R_ECX );
nkeynes@361
  2500
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2501
                        store_reg( R_EAX, 0 );
nkeynes@417
  2502
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2503
                        }
nkeynes@359
  2504
                        break;
nkeynes@359
  2505
                    case 0x7:
nkeynes@359
  2506
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2507
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2508
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2509
                    	SLOTILLEGAL();
nkeynes@374
  2510
                        } else {
nkeynes@569
  2511
                    	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  2512
                    	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  2513
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2514
                        }
nkeynes@359
  2515
                        }
nkeynes@359
  2516
                        break;
nkeynes@359
  2517
                    case 0x8:
nkeynes@359
  2518
                        { /* TST #imm, R0 */
nkeynes@359
  2519
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2520
                        load_reg( R_EAX, 0 );
nkeynes@368
  2521
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2522
                        SETE_t();
nkeynes@417
  2523
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2524
                        }
nkeynes@359
  2525
                        break;
nkeynes@359
  2526
                    case 0x9:
nkeynes@359
  2527
                        { /* AND #imm, R0 */
nkeynes@359
  2528
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2529
                        load_reg( R_EAX, 0 );
nkeynes@359
  2530
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2531
                        store_reg( R_EAX, 0 );
nkeynes@417
  2532
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2533
                        }
nkeynes@359
  2534
                        break;
nkeynes@359
  2535
                    case 0xA:
nkeynes@359
  2536
                        { /* XOR #imm, R0 */
nkeynes@359
  2537
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2538
                        load_reg( R_EAX, 0 );
nkeynes@359
  2539
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2540
                        store_reg( R_EAX, 0 );
nkeynes@417
  2541
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2542
                        }
nkeynes@359
  2543
                        break;
nkeynes@359
  2544
                    case 0xB:
nkeynes@359
  2545
                        { /* OR #imm, R0 */
nkeynes@359
  2546
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2547
                        load_reg( R_EAX, 0 );
nkeynes@359
  2548
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2549
                        store_reg( R_EAX, 0 );
nkeynes@417
  2550
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2551
                        }
nkeynes@359
  2552
                        break;
nkeynes@359
  2553
                    case 0xC:
nkeynes@359
  2554
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2555
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2556
                        load_reg( R_EAX, 0);
nkeynes@368
  2557
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2558
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2559
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  2560
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2561
                        SETE_t();
nkeynes@417
  2562
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2563
                        }
nkeynes@359
  2564
                        break;
nkeynes@359
  2565
                    case 0xD:
nkeynes@359
  2566
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2567
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2568
                        load_reg( R_EAX, 0 );
nkeynes@359
  2569
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2570
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2571
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2572
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2573
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2574
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2575
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2576
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2577
                        }
nkeynes@359
  2578
                        break;
nkeynes@359
  2579
                    case 0xE:
nkeynes@359
  2580
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2581
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2582
                        load_reg( R_EAX, 0 );
nkeynes@359
  2583
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2584
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2585
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2586
                        MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
  2587
                        POP_realigned_r32(R_ECX);
nkeynes@359
  2588
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2589
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2590
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2591
                        }
nkeynes@359
  2592
                        break;
nkeynes@359
  2593
                    case 0xF:
nkeynes@359
  2594
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2595
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2596
                        load_reg( R_EAX, 0 );
nkeynes@374
  2597
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2598
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
  2599
                        PUSH_realigned_r32(R_ECX);
nkeynes@527
  2600
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
  2601
                        POP_realigned_r32(R_ECX);
nkeynes@386
  2602
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2603
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2604
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2605
                        }
nkeynes@359
  2606
                        break;
nkeynes@359
  2607
                }
nkeynes@359
  2608
                break;
nkeynes@359
  2609
            case 0xD:
nkeynes@359
  2610
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2611
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2612
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2613
            	SLOTILLEGAL();
nkeynes@374
  2614
                } else {
nkeynes@388
  2615
            	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  2616
            	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  2617
            	    // If the target address is in the same page as the code, it's
nkeynes@569
  2618
            	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  2619
            	    // memory subsystem. (this is a big performance win)
nkeynes@569
  2620
            
nkeynes@569
  2621
            	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  2622
            	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  2623
            	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  2624
            	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  2625
            	    // behaviour though.
nkeynes@569
  2626
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  2627
            	    MOV_moff32_EAX( ptr );
nkeynes@388
  2628
            	} else {
nkeynes@569
  2629
            	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  2630
            	    // different virtual address than the translation was done with,
nkeynes@569
  2631
            	    // but we can safely assume that the low bits are the same.
nkeynes@569
  2632
            	    load_imm32( R_ECX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  2633
            	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@388
  2634
            	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@569
  2635
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2636
            	}
nkeynes@386
  2637
            	store_reg( R_EAX, Rn );
nkeynes@374
  2638
                }
nkeynes@359
  2639
                }
nkeynes@359
  2640
                break;
nkeynes@359
  2641
            case 0xE:
nkeynes@359
  2642
                { /* MOV #imm, Rn */
nkeynes@359
  2643
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2644
                load_imm32( R_EAX, imm );
nkeynes@359
  2645
                store_reg( R_EAX, Rn );
nkeynes@359
  2646
                }
nkeynes@359
  2647
                break;
nkeynes@359
  2648
            case 0xF:
nkeynes@359
  2649
                switch( ir&0xF ) {
nkeynes@359
  2650
                    case 0x0:
nkeynes@359
  2651
                        { /* FADD FRm, FRn */
nkeynes@359
  2652
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2653
                        check_fpuen();
nkeynes@377
  2654
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2655
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2656
                        load_fr_bank( R_EDX );
nkeynes@380
  2657
                        JNE_rel8(13,doubleprec);
nkeynes@377
  2658
                        push_fr(R_EDX, FRm);
nkeynes@377
  2659
                        push_fr(R_EDX, FRn);
nkeynes@377
  2660
                        FADDP_st(1);
nkeynes@377
  2661
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2662
                        JMP_rel8(11,end);
nkeynes@380
  2663
                        JMP_TARGET(doubleprec);
nkeynes@377
  2664
                        push_dr(R_EDX, FRm);
nkeynes@377
  2665
                        push_dr(R_EDX, FRn);
nkeynes@377
  2666
                        FADDP_st(1);
nkeynes@377
  2667
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2668
                        JMP_TARGET(end);
nkeynes@417
  2669
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2670
                        }
nkeynes@359
  2671
                        break;
nkeynes@359
  2672
                    case 0x1:
nkeynes@359
  2673
                        { /* FSUB FRm, FRn */
nkeynes@359
  2674
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2675
                        check_fpuen();
nkeynes@377
  2676
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2677
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2678
                        load_fr_bank( R_EDX );
nkeynes@380
  2679
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2680
                        push_fr(R_EDX, FRn);
nkeynes@377
  2681
                        push_fr(R_EDX, FRm);
nkeynes@388
  2682
                        FSUBP_st(1);
nkeynes@377
  2683
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2684
                        JMP_rel8(11, end);
nkeynes@380
  2685
                        JMP_TARGET(doubleprec);
nkeynes@377
  2686
                        push_dr(R_EDX, FRn);
nkeynes@377
  2687
                        push_dr(R_EDX, FRm);
nkeynes@388
  2688
                        FSUBP_st(1);
nkeynes@377
  2689
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2690
                        JMP_TARGET(end);
nkeynes@417
  2691
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2692
                        }
nkeynes@359
  2693
                        break;
nkeynes@359
  2694
                    case 0x2:
nkeynes@359
  2695
                        { /* FMUL FRm, FRn */
nkeynes@359
  2696
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2697
                        check_fpuen();
nkeynes@377
  2698
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2699
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2700
                        load_fr_bank( R_EDX );
nkeynes@380
  2701
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2702
                        push_fr(R_EDX, FRm);
nkeynes@377
  2703
                        push_fr(R_ED